1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * sata_via.c - VIA Serial ATA controllers 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2003-2004 Red Hat, Inc. All rights reserved. 10 * Copyright 2003-2004 Jeff Garzik 11 * 12 * libata documentation is available via 'make {ps|pdf}docs', 13 * as Documentation/driver-api/libata.rst 14 * 15 * Hardware documentation available under NDA. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/blkdev.h> 22 #include <linux/delay.h> 23 #include <linux/device.h> 24 #include <scsi/scsi.h> 25 #include <scsi/scsi_cmnd.h> 26 #include <scsi/scsi_host.h> 27 #include <linux/libata.h> 28 #include <linux/string_choices.h> 29 30 #define DRV_NAME "sata_via" 31 #define DRV_VERSION "2.6" 32 33 /* 34 * vt8251 is different from other sata controllers of VIA. It has two 35 * channels, each channel has both Master and Slave slot. 36 */ 37 enum board_ids_enum { 38 vt6420, 39 vt6421, 40 vt8251, 41 }; 42 43 enum { 44 SATA_CHAN_ENAB = 0x40, /* SATA channel enable */ 45 SATA_INT_GATE = 0x41, /* SATA interrupt gating */ 46 SATA_NATIVE_MODE = 0x42, /* Native mode enable */ 47 SVIA_MISC_3 = 0x46, /* Miscellaneous Control III */ 48 PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */ 49 PATA_PIO_TIMING = 0xAB, /* PATA timing register */ 50 51 PORT0 = (1 << 1), 52 PORT1 = (1 << 0), 53 ALL_PORTS = PORT0 | PORT1, 54 55 NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4), 56 57 SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */ 58 59 SATA_HOTPLUG = (1 << 5), /* enable IRQ on hotplug */ 60 }; 61 62 struct svia_priv { 63 bool wd_workaround; 64 }; 65 66 static int vt6420_hotplug; 67 module_param_named(vt6420_hotplug, vt6420_hotplug, int, 0644); 68 MODULE_PARM_DESC(vt6420_hotplug, "Enable hot-plug support for VT6420 (0=Don't support, 1=support)"); 69 70 static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 71 #ifdef CONFIG_PM_SLEEP 72 static int svia_pci_device_resume(struct pci_dev *pdev); 73 #endif 74 static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 75 static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 76 static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val); 77 static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val); 78 static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf); 79 static void svia_noop_freeze(struct ata_port *ap); 80 static int vt6420_prereset(struct ata_link *link, unsigned long deadline); 81 static void vt6420_bmdma_start(struct ata_queued_cmd *qc); 82 static int vt6421_pata_cable_detect(struct ata_port *ap); 83 static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev); 84 static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev); 85 static void vt6421_error_handler(struct ata_port *ap); 86 87 static const struct pci_device_id svia_pci_tbl[] = { 88 { 89 PCI_VDEVICE(VIA, 0x5337), 90 .driver_data = vt6420, 91 }, { 92 /* 2 sata chnls (Master) */ 93 PCI_VDEVICE(VIA, 0x0591), 94 .driver_data = vt6420, 95 }, { 96 /* 2 sata chnls (Master) */ 97 PCI_VDEVICE(VIA, 0x3149), 98 .driver_data = vt6420, 99 }, { 100 /* 2 sata chnls, 1 pata chnl */ 101 PCI_VDEVICE(VIA, 0x3249), 102 .driver_data = vt6421, 103 }, { 104 PCI_VDEVICE(VIA, 0x5372), 105 .driver_data = vt6420, 106 }, { 107 PCI_VDEVICE(VIA, 0x7372), 108 .driver_data = vt6420, 109 }, { 110 /* 2 sata chnls (Master/Slave) */ 111 PCI_VDEVICE(VIA, 0x5287), 112 .driver_data = vt8251, 113 }, { 114 PCI_VDEVICE(VIA, 0x9000), 115 .driver_data = vt8251, 116 }, 117 { } /* terminate list */ 118 }; 119 120 static struct pci_driver svia_pci_driver = { 121 .name = DRV_NAME, 122 .id_table = svia_pci_tbl, 123 .probe = svia_init_one, 124 #ifdef CONFIG_PM_SLEEP 125 .suspend = ata_pci_device_suspend, 126 .resume = svia_pci_device_resume, 127 #endif 128 .remove = ata_pci_remove_one, 129 }; 130 131 static const struct scsi_host_template svia_sht = { 132 ATA_BMDMA_SHT(DRV_NAME), 133 }; 134 135 static struct ata_port_operations svia_base_ops = { 136 .inherits = &ata_bmdma_port_ops, 137 .sff_tf_load = svia_tf_load, 138 }; 139 140 static struct ata_port_operations vt6420_sata_ops = { 141 .inherits = &svia_base_ops, 142 .freeze = svia_noop_freeze, 143 .reset.prereset = vt6420_prereset, 144 .bmdma_start = vt6420_bmdma_start, 145 }; 146 147 static struct ata_port_operations vt6421_pata_ops = { 148 .inherits = &svia_base_ops, 149 .cable_detect = vt6421_pata_cable_detect, 150 .set_piomode = vt6421_set_pio_mode, 151 .set_dmamode = vt6421_set_dma_mode, 152 }; 153 154 static struct ata_port_operations vt6421_sata_ops = { 155 .inherits = &svia_base_ops, 156 .scr_read = svia_scr_read, 157 .scr_write = svia_scr_write, 158 .error_handler = vt6421_error_handler, 159 }; 160 161 static struct ata_port_operations vt8251_ops = { 162 .inherits = &svia_base_ops, 163 .reset.hardreset = sata_std_hardreset, 164 .scr_read = vt8251_scr_read, 165 .scr_write = vt8251_scr_write, 166 }; 167 168 static const struct ata_port_info vt6420_port_info = { 169 .flags = ATA_FLAG_SATA, 170 .pio_mask = ATA_PIO4, 171 .mwdma_mask = ATA_MWDMA2, 172 .udma_mask = ATA_UDMA6, 173 .port_ops = &vt6420_sata_ops, 174 }; 175 176 static const struct ata_port_info vt6421_sport_info = { 177 .flags = ATA_FLAG_SATA, 178 .pio_mask = ATA_PIO4, 179 .mwdma_mask = ATA_MWDMA2, 180 .udma_mask = ATA_UDMA6, 181 .port_ops = &vt6421_sata_ops, 182 }; 183 184 static const struct ata_port_info vt6421_pport_info = { 185 .flags = ATA_FLAG_SLAVE_POSS, 186 .pio_mask = ATA_PIO4, 187 /* No MWDMA */ 188 .udma_mask = ATA_UDMA6, 189 .port_ops = &vt6421_pata_ops, 190 }; 191 192 static const struct ata_port_info vt8251_port_info = { 193 .flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS, 194 .pio_mask = ATA_PIO4, 195 .mwdma_mask = ATA_MWDMA2, 196 .udma_mask = ATA_UDMA6, 197 .port_ops = &vt8251_ops, 198 }; 199 200 MODULE_AUTHOR("Jeff Garzik"); 201 MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers"); 202 MODULE_LICENSE("GPL"); 203 MODULE_DEVICE_TABLE(pci, svia_pci_tbl); 204 MODULE_VERSION(DRV_VERSION); 205 206 static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 207 { 208 if (sc_reg > SCR_CONTROL) 209 return -EINVAL; 210 *val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg)); 211 return 0; 212 } 213 214 static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 215 { 216 if (sc_reg > SCR_CONTROL) 217 return -EINVAL; 218 iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg)); 219 return 0; 220 } 221 222 static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val) 223 { 224 static const u8 ipm_tbl[] = { 1, 2, 6, 0 }; 225 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); 226 int slot = 2 * link->ap->port_no + link->pmp; 227 u32 v = 0; 228 u8 raw; 229 230 switch (scr) { 231 case SCR_STATUS: 232 pci_read_config_byte(pdev, 0xA0 + slot, &raw); 233 234 /* read the DET field, bit0 and 1 of the config byte */ 235 v |= raw & 0x03; 236 237 /* read the SPD field, bit4 of the configure byte */ 238 if (raw & (1 << 4)) 239 v |= 0x02 << 4; 240 else 241 v |= 0x01 << 4; 242 243 /* read the IPM field, bit2 and 3 of the config byte */ 244 v |= ipm_tbl[(raw >> 2) & 0x3]; 245 break; 246 247 case SCR_ERROR: 248 /* devices other than 5287 uses 0xA8 as base */ 249 WARN_ON(pdev->device != 0x5287); 250 pci_read_config_dword(pdev, 0xB0 + slot * 4, &v); 251 break; 252 253 case SCR_CONTROL: 254 pci_read_config_byte(pdev, 0xA4 + slot, &raw); 255 256 /* read the DET field, bit0 and bit1 */ 257 v |= ((raw & 0x02) << 1) | (raw & 0x01); 258 259 /* read the IPM field, bit2 and bit3 */ 260 v |= ((raw >> 2) & 0x03) << 8; 261 break; 262 263 default: 264 return -EINVAL; 265 } 266 267 *val = v; 268 return 0; 269 } 270 271 static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val) 272 { 273 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); 274 int slot = 2 * link->ap->port_no + link->pmp; 275 u32 v = 0; 276 277 switch (scr) { 278 case SCR_ERROR: 279 /* devices other than 5287 uses 0xA8 as base */ 280 WARN_ON(pdev->device != 0x5287); 281 pci_write_config_dword(pdev, 0xB0 + slot * 4, val); 282 return 0; 283 284 case SCR_CONTROL: 285 /* set the DET field */ 286 v |= ((val & 0x4) >> 1) | (val & 0x1); 287 288 /* set the IPM field */ 289 v |= ((val >> 8) & 0x3) << 2; 290 291 pci_write_config_byte(pdev, 0xA4 + slot, v); 292 return 0; 293 294 default: 295 return -EINVAL; 296 } 297 } 298 299 /** 300 * svia_tf_load - send taskfile registers to host controller 301 * @ap: Port to which output is sent 302 * @tf: ATA taskfile register set 303 * 304 * Outputs ATA taskfile to standard ATA host controller. 305 * 306 * This is to fix the internal bug of via chipsets, which will 307 * reset the device register after changing the IEN bit on ctl 308 * register. 309 */ 310 static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 311 { 312 struct ata_taskfile ttf; 313 314 if (tf->ctl != ap->last_ctl) { 315 ttf = *tf; 316 ttf.flags |= ATA_TFLAG_DEVICE; 317 tf = &ttf; 318 } 319 ata_sff_tf_load(ap, tf); 320 } 321 322 static void svia_noop_freeze(struct ata_port *ap) 323 { 324 /* Some VIA controllers choke if ATA_NIEN is manipulated in 325 * certain way. Leave it alone and just clear pending IRQ. 326 */ 327 ap->ops->sff_check_status(ap); 328 ata_bmdma_irq_clear(ap); 329 } 330 331 /** 332 * vt6420_prereset - prereset for vt6420 333 * @link: target ATA link 334 * @deadline: deadline jiffies for the operation 335 * 336 * SCR registers on vt6420 are pieces of shit and may hang the 337 * whole machine completely if accessed with the wrong timing. 338 * To avoid such catastrophe, vt6420 doesn't provide generic SCR 339 * access operations, but uses SStatus and SControl only during 340 * boot probing in controlled way. 341 * 342 * As the old (pre EH update) probing code is proven to work, we 343 * strictly follow the access pattern. 344 * 345 * LOCKING: 346 * Kernel thread context (may sleep) 347 * 348 * RETURNS: 349 * 0 on success, -errno otherwise. 350 */ 351 static int vt6420_prereset(struct ata_link *link, unsigned long deadline) 352 { 353 struct ata_port *ap = link->ap; 354 struct ata_eh_context *ehc = &ap->link.eh_context; 355 unsigned long timeout = jiffies + (HZ * 5); 356 u32 sstatus, scontrol; 357 int online; 358 359 /* don't do any SCR stuff if we're not loading */ 360 if (!(ap->pflags & ATA_PFLAG_LOADING)) 361 goto skip_scr; 362 363 /* Resume phy. This is the old SATA resume sequence */ 364 svia_scr_write(link, SCR_CONTROL, 0x300); 365 svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */ 366 367 /* wait for phy to become ready, if necessary */ 368 do { 369 ata_msleep(link->ap, 200); 370 svia_scr_read(link, SCR_STATUS, &sstatus); 371 if ((sstatus & 0xf) != 1) 372 break; 373 } while (time_before(jiffies, timeout)); 374 375 /* open code sata_print_link_status() */ 376 svia_scr_read(link, SCR_STATUS, &sstatus); 377 svia_scr_read(link, SCR_CONTROL, &scontrol); 378 379 online = (sstatus & 0xf) == 0x3; 380 381 ata_port_info(ap, 382 "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n", 383 str_up_down(online), sstatus, scontrol); 384 385 /* SStatus is read one more time */ 386 svia_scr_read(link, SCR_STATUS, &sstatus); 387 388 if (!online) { 389 /* tell EH to bail */ 390 ehc->i.action &= ~ATA_EH_RESET; 391 return 0; 392 } 393 394 skip_scr: 395 /* wait for !BSY */ 396 ata_sff_wait_ready(link, deadline); 397 398 return 0; 399 } 400 401 static void vt6420_bmdma_start(struct ata_queued_cmd *qc) 402 { 403 struct ata_port *ap = qc->ap; 404 if ((qc->tf.command == ATA_CMD_PACKET) && 405 (qc->scsicmd->sc_data_direction == DMA_TO_DEVICE)) { 406 /* Prevents corruption on some ATAPI burners */ 407 ata_sff_pause(ap); 408 } 409 ata_bmdma_start(qc); 410 } 411 412 static int vt6421_pata_cable_detect(struct ata_port *ap) 413 { 414 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 415 u8 tmp; 416 417 pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp); 418 if (tmp & 0x10) 419 return ATA_CBL_PATA40; 420 return ATA_CBL_PATA80; 421 } 422 423 static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev) 424 { 425 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 426 static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 }; 427 pci_write_config_byte(pdev, PATA_PIO_TIMING - adev->devno, 428 pio_bits[adev->pio_mode - XFER_PIO_0]); 429 } 430 431 static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev) 432 { 433 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 434 static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 }; 435 pci_write_config_byte(pdev, PATA_UDMA_TIMING - adev->devno, 436 udma_bits[adev->dma_mode - XFER_UDMA_0]); 437 } 438 439 static const unsigned int svia_bar_sizes[] = { 440 8, 4, 8, 4, 16, 256 441 }; 442 443 static const unsigned int vt6421_bar_sizes[] = { 444 16, 16, 16, 16, 32, 128 445 }; 446 447 static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port) 448 { 449 return addr + (port * 128); 450 } 451 452 static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port) 453 { 454 return addr + (port * 64); 455 } 456 457 static void vt6421_init_addrs(struct ata_port *ap) 458 { 459 void __iomem * const * iomap = ap->host->iomap; 460 void __iomem *reg_addr = iomap[ap->port_no]; 461 void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8); 462 struct ata_ioports *ioaddr = &ap->ioaddr; 463 464 ioaddr->cmd_addr = reg_addr; 465 ioaddr->altstatus_addr = 466 ioaddr->ctl_addr = (void __iomem *) 467 ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS); 468 ioaddr->bmdma_addr = bmdma_addr; 469 ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no); 470 471 ata_sff_std_ports(ioaddr); 472 473 ata_port_pbar_desc(ap, ap->port_no, -1, "port"); 474 ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma"); 475 } 476 477 static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) 478 { 479 const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL }; 480 struct ata_host *host; 481 int rc; 482 483 if (vt6420_hotplug) { 484 ppi[0]->port_ops->scr_read = svia_scr_read; 485 ppi[0]->port_ops->scr_write = svia_scr_write; 486 } 487 488 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); 489 if (rc) 490 return rc; 491 *r_host = host; 492 493 rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); 494 if (rc) { 495 dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n"); 496 return rc; 497 } 498 499 host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0); 500 host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1); 501 502 return 0; 503 } 504 505 static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) 506 { 507 const struct ata_port_info *ppi[] = 508 { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info }; 509 struct ata_host *host; 510 int i, rc; 511 512 *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi)); 513 if (!host) { 514 dev_err(&pdev->dev, "failed to allocate host\n"); 515 return -ENOMEM; 516 } 517 518 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); 519 if (rc) { 520 dev_err(&pdev->dev, "failed to request/iomap PCI BARs (errno=%d)\n", 521 rc); 522 return rc; 523 } 524 host->iomap = pcim_iomap_table(pdev); 525 526 for (i = 0; i < host->n_ports; i++) 527 vt6421_init_addrs(host->ports[i]); 528 529 return dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); 530 } 531 532 static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) 533 { 534 const struct ata_port_info *ppi[] = { &vt8251_port_info, NULL }; 535 struct ata_host *host; 536 int i, rc; 537 538 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); 539 if (rc) 540 return rc; 541 *r_host = host; 542 543 rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); 544 if (rc) { 545 dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n"); 546 return rc; 547 } 548 549 /* 8251 hosts four sata ports as M/S of the two channels */ 550 for (i = 0; i < host->n_ports; i++) 551 ata_slave_link_init(host->ports[i]); 552 553 return 0; 554 } 555 556 static void svia_wd_fix(struct pci_dev *pdev) 557 { 558 u8 tmp8; 559 560 pci_read_config_byte(pdev, 0x52, &tmp8); 561 pci_write_config_byte(pdev, 0x52, tmp8 | BIT(2)); 562 } 563 564 static irqreturn_t vt642x_interrupt(int irq, void *dev_instance) 565 { 566 struct ata_host *host = dev_instance; 567 irqreturn_t rc = ata_bmdma_interrupt(irq, dev_instance); 568 569 /* if the IRQ was not handled, it might be a hotplug IRQ */ 570 if (rc != IRQ_HANDLED) { 571 u32 serror; 572 unsigned long flags; 573 574 spin_lock_irqsave(&host->lock, flags); 575 /* check for hotplug on port 0 */ 576 svia_scr_read(&host->ports[0]->link, SCR_ERROR, &serror); 577 if (serror & SERR_PHYRDY_CHG) { 578 ata_ehi_hotplugged(&host->ports[0]->link.eh_info); 579 ata_port_freeze(host->ports[0]); 580 rc = IRQ_HANDLED; 581 } 582 /* check for hotplug on port 1 */ 583 svia_scr_read(&host->ports[1]->link, SCR_ERROR, &serror); 584 if (serror & SERR_PHYRDY_CHG) { 585 ata_ehi_hotplugged(&host->ports[1]->link.eh_info); 586 ata_port_freeze(host->ports[1]); 587 rc = IRQ_HANDLED; 588 } 589 spin_unlock_irqrestore(&host->lock, flags); 590 } 591 592 return rc; 593 } 594 595 static void vt6421_error_handler(struct ata_port *ap) 596 __must_hold(&ap->host->eh_mutex) 597 { 598 struct svia_priv *hpriv = ap->host->private_data; 599 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 600 u32 serror; 601 602 /* see svia_configure() for description */ 603 if (!hpriv->wd_workaround) { 604 svia_scr_read(&ap->link, SCR_ERROR, &serror); 605 if (serror == 0x1000500) { 606 ata_port_warn(ap, "Incompatible drive: enabling workaround. This slows down transfer rate to ~60 MB/s"); 607 svia_wd_fix(pdev); 608 hpriv->wd_workaround = true; 609 ap->link.eh_context.i.flags |= ATA_EHI_QUIET; 610 } 611 } 612 613 ata_sff_error_handler(ap); 614 } 615 616 static void svia_configure(struct pci_dev *pdev, int board_id, 617 struct svia_priv *hpriv) 618 { 619 u8 tmp8; 620 621 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8); 622 dev_info(&pdev->dev, "routed to hard irq line %d\n", 623 (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f); 624 625 /* make sure SATA channels are enabled */ 626 pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8); 627 if ((tmp8 & ALL_PORTS) != ALL_PORTS) { 628 dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n", 629 (int)tmp8); 630 tmp8 |= ALL_PORTS; 631 pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8); 632 } 633 634 /* make sure interrupts for each channel sent to us */ 635 pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8); 636 if ((tmp8 & ALL_PORTS) != ALL_PORTS) { 637 dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n", 638 (int) tmp8); 639 tmp8 |= ALL_PORTS; 640 pci_write_config_byte(pdev, SATA_INT_GATE, tmp8); 641 } 642 643 /* make sure native mode is enabled */ 644 pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8); 645 if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) { 646 dev_dbg(&pdev->dev, 647 "enabling SATA channel native mode (0x%x)\n", 648 (int) tmp8); 649 tmp8 |= NATIVE_MODE_ALL; 650 pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8); 651 } 652 653 if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421) { 654 /* enable IRQ on hotplug */ 655 pci_read_config_byte(pdev, SVIA_MISC_3, &tmp8); 656 if ((tmp8 & SATA_HOTPLUG) != SATA_HOTPLUG) { 657 dev_dbg(&pdev->dev, 658 "enabling SATA hotplug (0x%x)\n", 659 (int) tmp8); 660 tmp8 |= SATA_HOTPLUG; 661 pci_write_config_byte(pdev, SVIA_MISC_3, tmp8); 662 } 663 } 664 665 /* 666 * vt6420/1 has problems talking to some drives. The following 667 * is the fix from Joseph Chan <JosephChan@via.com.tw>. 668 * 669 * When host issues HOLD, device may send up to 20DW of data 670 * before acknowledging it with HOLDA and the host should be 671 * able to buffer them in FIFO. Unfortunately, some WD drives 672 * send up to 40DW before acknowledging HOLD and, in the 673 * default configuration, this ends up overflowing vt6421's 674 * FIFO, making the controller abort the transaction with 675 * R_ERR. 676 * 677 * Rx52[2] is the internal 128DW FIFO Flow control watermark 678 * adjusting mechanism enable bit and the default value 0 679 * means host will issue HOLD to device when the left FIFO 680 * size goes below 32DW. Setting it to 1 makes the watermark 681 * 64DW. 682 * 683 * https://bugzilla.kernel.org/show_bug.cgi?id=15173 684 * http://article.gmane.org/gmane.linux.ide/46352 685 * http://thread.gmane.org/gmane.linux.kernel/1062139 686 * 687 * As the fix slows down data transfer, apply it only if the error 688 * actually appears - see vt6421_error_handler() 689 * Apply the fix always on vt6420 as we don't know if SCR_ERROR can be 690 * read safely. 691 */ 692 if (board_id == vt6420) { 693 svia_wd_fix(pdev); 694 hpriv->wd_workaround = true; 695 } 696 } 697 698 static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 699 { 700 unsigned int i; 701 int rc; 702 struct ata_host *host = NULL; 703 int board_id = (int) ent->driver_data; 704 const unsigned *bar_sizes; 705 struct svia_priv *hpriv; 706 707 ata_print_version_once(&pdev->dev, DRV_VERSION); 708 709 rc = pcim_enable_device(pdev); 710 if (rc) 711 return rc; 712 713 if (board_id == vt6421) 714 bar_sizes = &vt6421_bar_sizes[0]; 715 else 716 bar_sizes = &svia_bar_sizes[0]; 717 718 for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++) 719 if ((pci_resource_start(pdev, i) == 0) || 720 (pci_resource_len(pdev, i) < bar_sizes[i])) { 721 dev_err(&pdev->dev, 722 "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n", 723 i, 724 (unsigned long long)pci_resource_start(pdev, i), 725 (unsigned long long)pci_resource_len(pdev, i)); 726 return -ENODEV; 727 } 728 729 switch (board_id) { 730 case vt6420: 731 rc = vt6420_prepare_host(pdev, &host); 732 break; 733 case vt6421: 734 rc = vt6421_prepare_host(pdev, &host); 735 break; 736 case vt8251: 737 rc = vt8251_prepare_host(pdev, &host); 738 break; 739 default: 740 rc = -EINVAL; 741 } 742 if (rc) 743 return rc; 744 745 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 746 if (!hpriv) 747 return -ENOMEM; 748 host->private_data = hpriv; 749 750 svia_configure(pdev, board_id, hpriv); 751 752 pci_set_master(pdev); 753 if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421) 754 return ata_host_activate(host, pdev->irq, vt642x_interrupt, 755 IRQF_SHARED, &svia_sht); 756 else 757 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 758 IRQF_SHARED, &svia_sht); 759 } 760 761 #ifdef CONFIG_PM_SLEEP 762 static int svia_pci_device_resume(struct pci_dev *pdev) 763 { 764 struct ata_host *host = pci_get_drvdata(pdev); 765 struct svia_priv *hpriv = host->private_data; 766 int rc; 767 768 rc = ata_pci_device_do_resume(pdev); 769 if (rc) 770 return rc; 771 772 if (hpriv->wd_workaround) 773 svia_wd_fix(pdev); 774 ata_host_resume(host); 775 776 return 0; 777 } 778 #endif 779 780 module_pci_driver(svia_pci_driver); 781