1c82ee6d3SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2c6fd2807SJeff Garzik /*
3c6fd2807SJeff Garzik * sata_via.c - VIA Serial ATA controllers
4c6fd2807SJeff Garzik *
58c3d3d4bSTejun Heo * Maintained by: Tejun Heo <tj@kernel.org>
6c6fd2807SJeff Garzik * Please ALWAYS copy linux-ide@vger.kernel.org
75796d1c4SJeff Garzik * on emails.
8c6fd2807SJeff Garzik *
9c6fd2807SJeff Garzik * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
10c6fd2807SJeff Garzik * Copyright 2003-2004 Jeff Garzik
11c6fd2807SJeff Garzik *
12c6fd2807SJeff Garzik * libata documentation is available via 'make {ps|pdf}docs',
139bb9a39cSMauro Carvalho Chehab * as Documentation/driver-api/libata.rst
14c6fd2807SJeff Garzik *
15c6fd2807SJeff Garzik * Hardware documentation available under NDA.
16c6fd2807SJeff Garzik */
17c6fd2807SJeff Garzik
18c6fd2807SJeff Garzik #include <linux/kernel.h>
19c6fd2807SJeff Garzik #include <linux/module.h>
20c6fd2807SJeff Garzik #include <linux/pci.h>
21c6fd2807SJeff Garzik #include <linux/blkdev.h>
22c6fd2807SJeff Garzik #include <linux/delay.h>
23c6fd2807SJeff Garzik #include <linux/device.h>
24a55ab496SBart Hartgers #include <scsi/scsi.h>
25a55ab496SBart Hartgers #include <scsi/scsi_cmnd.h>
26c6fd2807SJeff Garzik #include <scsi/scsi_host.h>
27c6fd2807SJeff Garzik #include <linux/libata.h>
28c6fd2807SJeff Garzik
29c6fd2807SJeff Garzik #define DRV_NAME "sata_via"
30a55ab496SBart Hartgers #define DRV_VERSION "2.6"
31c6fd2807SJeff Garzik
32b9d5b89bSTejun Heo /*
33b9d5b89bSTejun Heo * vt8251 is different from other sata controllers of VIA. It has two
34b9d5b89bSTejun Heo * channels, each channel has both Master and Slave slot.
35b9d5b89bSTejun Heo */
36c6fd2807SJeff Garzik enum board_ids_enum {
37c6fd2807SJeff Garzik vt6420,
38c6fd2807SJeff Garzik vt6421,
39b9d5b89bSTejun Heo vt8251,
40c6fd2807SJeff Garzik };
41c6fd2807SJeff Garzik
42c6fd2807SJeff Garzik enum {
43c6fd2807SJeff Garzik SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
44c6fd2807SJeff Garzik SATA_INT_GATE = 0x41, /* SATA interrupt gating */
45c6fd2807SJeff Garzik SATA_NATIVE_MODE = 0x42, /* Native mode enable */
4657e5568fSOndrej Zary SVIA_MISC_3 = 0x46, /* Miscellaneous Control III */
47d73f30e1SAlan PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
48d73f30e1SAlan PATA_PIO_TIMING = 0xAB, /* PATA timing register */
49c6fd2807SJeff Garzik
50c6fd2807SJeff Garzik PORT0 = (1 << 1),
51c6fd2807SJeff Garzik PORT1 = (1 << 0),
52c6fd2807SJeff Garzik ALL_PORTS = PORT0 | PORT1,
53c6fd2807SJeff Garzik
54c6fd2807SJeff Garzik NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),
55c6fd2807SJeff Garzik
56c6fd2807SJeff Garzik SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
5757e5568fSOndrej Zary
5857e5568fSOndrej Zary SATA_HOTPLUG = (1 << 5), /* enable IRQ on hotplug */
59c6fd2807SJeff Garzik };
60c6fd2807SJeff Garzik
6144a9b494SOndrej Zary struct svia_priv {
6244a9b494SOndrej Zary bool wd_workaround;
6344a9b494SOndrej Zary };
6444a9b494SOndrej Zary
6598633258SOndrej Zary static int vt6420_hotplug;
6698633258SOndrej Zary module_param_named(vt6420_hotplug, vt6420_hotplug, int, 0644);
6798633258SOndrej Zary MODULE_PARM_DESC(vt6420_hotplug, "Enable hot-plug support for VT6420 (0=Don't support, 1=support)");
6898633258SOndrej Zary
69c6fd2807SJeff Garzik static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
7044a9b494SOndrej Zary #ifdef CONFIG_PM_SLEEP
7144a9b494SOndrej Zary static int svia_pci_device_resume(struct pci_dev *pdev);
7244a9b494SOndrej Zary #endif
7382ef04fbSTejun Heo static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
7482ef04fbSTejun Heo static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
75b9d5b89bSTejun Heo static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val);
76b9d5b89bSTejun Heo static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val);
77b78152e9STejun Heo static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf);
7817234246STejun Heo static void svia_noop_freeze(struct ata_port *ap);
79a1efdabaSTejun Heo static int vt6420_prereset(struct ata_link *link, unsigned long deadline);
80a55ab496SBart Hartgers static void vt6420_bmdma_start(struct ata_queued_cmd *qc);
81a0fcdc02SJeff Garzik static int vt6421_pata_cable_detect(struct ata_port *ap);
82d73f30e1SAlan static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
83d73f30e1SAlan static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);
8444a9b494SOndrej Zary static void vt6421_error_handler(struct ata_port *ap);
85c6fd2807SJeff Garzik
86c6fd2807SJeff Garzik static const struct pci_device_id svia_pci_tbl[] = {
8796bc103fSLuca Pedrielli { PCI_VDEVICE(VIA, 0x5337), vt6420 },
88b9d5b89bSTejun Heo { PCI_VDEVICE(VIA, 0x0591), vt6420 }, /* 2 sata chnls (Master) */
89b9d5b89bSTejun Heo { PCI_VDEVICE(VIA, 0x3149), vt6420 }, /* 2 sata chnls (Master) */
90b9d5b89bSTejun Heo { PCI_VDEVICE(VIA, 0x3249), vt6421 }, /* 2 sata chnls, 1 pata chnl */
9152df0ee0SJeff Garzik { PCI_VDEVICE(VIA, 0x5372), vt6420 },
9252df0ee0SJeff Garzik { PCI_VDEVICE(VIA, 0x7372), vt6420 },
93b9d5b89bSTejun Heo { PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */
9468139520SJosephChan@via.com.tw { PCI_VDEVICE(VIA, 0x9000), vt8251 },
95c6fd2807SJeff Garzik
96c6fd2807SJeff Garzik { } /* terminate list */
97c6fd2807SJeff Garzik };
98c6fd2807SJeff Garzik
99c6fd2807SJeff Garzik static struct pci_driver svia_pci_driver = {
100c6fd2807SJeff Garzik .name = DRV_NAME,
101c6fd2807SJeff Garzik .id_table = svia_pci_tbl,
102c6fd2807SJeff Garzik .probe = svia_init_one,
10358eb8cd5SBartlomiej Zolnierkiewicz #ifdef CONFIG_PM_SLEEP
104e1e143cfSTejun Heo .suspend = ata_pci_device_suspend,
10544a9b494SOndrej Zary .resume = svia_pci_device_resume,
106e1e143cfSTejun Heo #endif
107c6fd2807SJeff Garzik .remove = ata_pci_remove_one,
108c6fd2807SJeff Garzik };
109c6fd2807SJeff Garzik
110*25df73d9SBart Van Assche static const struct scsi_host_template svia_sht = {
11168d1d07bSTejun Heo ATA_BMDMA_SHT(DRV_NAME),
112c6fd2807SJeff Garzik };
113c6fd2807SJeff Garzik
114b78152e9STejun Heo static struct ata_port_operations svia_base_ops = {
115029cfd6bSTejun Heo .inherits = &ata_bmdma_port_ops,
116b78152e9STejun Heo .sff_tf_load = svia_tf_load,
117b78152e9STejun Heo };
118b78152e9STejun Heo
119b78152e9STejun Heo static struct ata_port_operations vt6420_sata_ops = {
120b78152e9STejun Heo .inherits = &svia_base_ops,
12117234246STejun Heo .freeze = svia_noop_freeze,
122a1efdabaSTejun Heo .prereset = vt6420_prereset,
123a55ab496SBart Hartgers .bmdma_start = vt6420_bmdma_start,
12454a86bfcSJeff Garzik };
12554a86bfcSJeff Garzik
126029cfd6bSTejun Heo static struct ata_port_operations vt6421_pata_ops = {
127b78152e9STejun Heo .inherits = &svia_base_ops,
128029cfd6bSTejun Heo .cable_detect = vt6421_pata_cable_detect,
129d73f30e1SAlan .set_piomode = vt6421_set_pio_mode,
130d73f30e1SAlan .set_dmamode = vt6421_set_dma_mode,
131d73f30e1SAlan };
132d73f30e1SAlan
133029cfd6bSTejun Heo static struct ata_port_operations vt6421_sata_ops = {
134b78152e9STejun Heo .inherits = &svia_base_ops,
135c6fd2807SJeff Garzik .scr_read = svia_scr_read,
136c6fd2807SJeff Garzik .scr_write = svia_scr_write,
13744a9b494SOndrej Zary .error_handler = vt6421_error_handler,
138c6fd2807SJeff Garzik };
139c6fd2807SJeff Garzik
140b9d5b89bSTejun Heo static struct ata_port_operations vt8251_ops = {
141b9d5b89bSTejun Heo .inherits = &svia_base_ops,
142b9d5b89bSTejun Heo .hardreset = sata_std_hardreset,
143b9d5b89bSTejun Heo .scr_read = vt8251_scr_read,
144b9d5b89bSTejun Heo .scr_write = vt8251_scr_write,
145b9d5b89bSTejun Heo };
146b9d5b89bSTejun Heo
147eca25dcaSTejun Heo static const struct ata_port_info vt6420_port_info = {
1489cbe056fSSergei Shtylyov .flags = ATA_FLAG_SATA,
14914bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4,
15014bdef98SErik Inge Bolsø .mwdma_mask = ATA_MWDMA2,
151bf6263a8SJeff Garzik .udma_mask = ATA_UDMA6,
15254a86bfcSJeff Garzik .port_ops = &vt6420_sata_ops,
153c6fd2807SJeff Garzik };
154c6fd2807SJeff Garzik
155f356b082SBhumika Goyal static const struct ata_port_info vt6421_sport_info = {
1569cbe056fSSergei Shtylyov .flags = ATA_FLAG_SATA,
15714bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4,
15814bdef98SErik Inge Bolsø .mwdma_mask = ATA_MWDMA2,
159bf6263a8SJeff Garzik .udma_mask = ATA_UDMA6,
160eca25dcaSTejun Heo .port_ops = &vt6421_sata_ops,
161eca25dcaSTejun Heo };
162eca25dcaSTejun Heo
163f356b082SBhumika Goyal static const struct ata_port_info vt6421_pport_info = {
1649cbe056fSSergei Shtylyov .flags = ATA_FLAG_SLAVE_POSS,
16514bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4,
16614bdef98SErik Inge Bolsø /* No MWDMA */
167bf6263a8SJeff Garzik .udma_mask = ATA_UDMA6,
168eca25dcaSTejun Heo .port_ops = &vt6421_pata_ops,
169eca25dcaSTejun Heo };
170eca25dcaSTejun Heo
171f356b082SBhumika Goyal static const struct ata_port_info vt8251_port_info = {
1729cbe056fSSergei Shtylyov .flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS,
17314bdef98SErik Inge Bolsø .pio_mask = ATA_PIO4,
17414bdef98SErik Inge Bolsø .mwdma_mask = ATA_MWDMA2,
175b9d5b89bSTejun Heo .udma_mask = ATA_UDMA6,
176b9d5b89bSTejun Heo .port_ops = &vt8251_ops,
177b9d5b89bSTejun Heo };
178b9d5b89bSTejun Heo
179c6fd2807SJeff Garzik MODULE_AUTHOR("Jeff Garzik");
180c6fd2807SJeff Garzik MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
181c6fd2807SJeff Garzik MODULE_LICENSE("GPL");
182c6fd2807SJeff Garzik MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
183c6fd2807SJeff Garzik MODULE_VERSION(DRV_VERSION);
184c6fd2807SJeff Garzik
svia_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)18582ef04fbSTejun Heo static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
186c6fd2807SJeff Garzik {
187c6fd2807SJeff Garzik if (sc_reg > SCR_CONTROL)
188da3dbb17STejun Heo return -EINVAL;
18982ef04fbSTejun Heo *val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg));
190da3dbb17STejun Heo return 0;
191c6fd2807SJeff Garzik }
192c6fd2807SJeff Garzik
svia_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)19382ef04fbSTejun Heo static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
194c6fd2807SJeff Garzik {
195c6fd2807SJeff Garzik if (sc_reg > SCR_CONTROL)
196da3dbb17STejun Heo return -EINVAL;
19782ef04fbSTejun Heo iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg));
198da3dbb17STejun Heo return 0;
199c6fd2807SJeff Garzik }
200c6fd2807SJeff Garzik
vt8251_scr_read(struct ata_link * link,unsigned int scr,u32 * val)201b9d5b89bSTejun Heo static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
202b9d5b89bSTejun Heo {
203b9d5b89bSTejun Heo static const u8 ipm_tbl[] = { 1, 2, 6, 0 };
204b9d5b89bSTejun Heo struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
205b9d5b89bSTejun Heo int slot = 2 * link->ap->port_no + link->pmp;
206b9d5b89bSTejun Heo u32 v = 0;
207b9d5b89bSTejun Heo u8 raw;
208b9d5b89bSTejun Heo
209b9d5b89bSTejun Heo switch (scr) {
210b9d5b89bSTejun Heo case SCR_STATUS:
211b9d5b89bSTejun Heo pci_read_config_byte(pdev, 0xA0 + slot, &raw);
212b9d5b89bSTejun Heo
213b9d5b89bSTejun Heo /* read the DET field, bit0 and 1 of the config byte */
214b9d5b89bSTejun Heo v |= raw & 0x03;
215b9d5b89bSTejun Heo
216b9d5b89bSTejun Heo /* read the SPD field, bit4 of the configure byte */
217b9d5b89bSTejun Heo if (raw & (1 << 4))
218b9d5b89bSTejun Heo v |= 0x02 << 4;
219b9d5b89bSTejun Heo else
220b9d5b89bSTejun Heo v |= 0x01 << 4;
221b9d5b89bSTejun Heo
222b9d5b89bSTejun Heo /* read the IPM field, bit2 and 3 of the config byte */
223b9d5b89bSTejun Heo v |= ipm_tbl[(raw >> 2) & 0x3];
224b9d5b89bSTejun Heo break;
225b9d5b89bSTejun Heo
226b9d5b89bSTejun Heo case SCR_ERROR:
227b9d5b89bSTejun Heo /* devices other than 5287 uses 0xA8 as base */
228b9d5b89bSTejun Heo WARN_ON(pdev->device != 0x5287);
229b9d5b89bSTejun Heo pci_read_config_dword(pdev, 0xB0 + slot * 4, &v);
230b9d5b89bSTejun Heo break;
231b9d5b89bSTejun Heo
232b9d5b89bSTejun Heo case SCR_CONTROL:
233b9d5b89bSTejun Heo pci_read_config_byte(pdev, 0xA4 + slot, &raw);
234b9d5b89bSTejun Heo
235b9d5b89bSTejun Heo /* read the DET field, bit0 and bit1 */
236b9d5b89bSTejun Heo v |= ((raw & 0x02) << 1) | (raw & 0x01);
237b9d5b89bSTejun Heo
238b9d5b89bSTejun Heo /* read the IPM field, bit2 and bit3 */
239b9d5b89bSTejun Heo v |= ((raw >> 2) & 0x03) << 8;
240b9d5b89bSTejun Heo break;
241b9d5b89bSTejun Heo
242b9d5b89bSTejun Heo default:
243b9d5b89bSTejun Heo return -EINVAL;
244b9d5b89bSTejun Heo }
245b9d5b89bSTejun Heo
246b9d5b89bSTejun Heo *val = v;
247b9d5b89bSTejun Heo return 0;
248b9d5b89bSTejun Heo }
249b9d5b89bSTejun Heo
vt8251_scr_write(struct ata_link * link,unsigned int scr,u32 val)250b9d5b89bSTejun Heo static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val)
251b9d5b89bSTejun Heo {
252b9d5b89bSTejun Heo struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
253b9d5b89bSTejun Heo int slot = 2 * link->ap->port_no + link->pmp;
254b9d5b89bSTejun Heo u32 v = 0;
255b9d5b89bSTejun Heo
256b9d5b89bSTejun Heo switch (scr) {
257b9d5b89bSTejun Heo case SCR_ERROR:
258b9d5b89bSTejun Heo /* devices other than 5287 uses 0xA8 as base */
259b9d5b89bSTejun Heo WARN_ON(pdev->device != 0x5287);
260b9d5b89bSTejun Heo pci_write_config_dword(pdev, 0xB0 + slot * 4, val);
261b9d5b89bSTejun Heo return 0;
262b9d5b89bSTejun Heo
263b9d5b89bSTejun Heo case SCR_CONTROL:
264b9d5b89bSTejun Heo /* set the DET field */
265b9d5b89bSTejun Heo v |= ((val & 0x4) >> 1) | (val & 0x1);
266b9d5b89bSTejun Heo
267b9d5b89bSTejun Heo /* set the IPM field */
268b9d5b89bSTejun Heo v |= ((val >> 8) & 0x3) << 2;
269b9d5b89bSTejun Heo
270b9d5b89bSTejun Heo pci_write_config_byte(pdev, 0xA4 + slot, v);
271b9d5b89bSTejun Heo return 0;
272b9d5b89bSTejun Heo
273b9d5b89bSTejun Heo default:
274b9d5b89bSTejun Heo return -EINVAL;
275b9d5b89bSTejun Heo }
276b9d5b89bSTejun Heo }
277b9d5b89bSTejun Heo
278b78152e9STejun Heo /**
279b78152e9STejun Heo * svia_tf_load - send taskfile registers to host controller
280b78152e9STejun Heo * @ap: Port to which output is sent
281b78152e9STejun Heo * @tf: ATA taskfile register set
282b78152e9STejun Heo *
283b78152e9STejun Heo * Outputs ATA taskfile to standard ATA host controller.
284b78152e9STejun Heo *
285b78152e9STejun Heo * This is to fix the internal bug of via chipsets, which will
286b78152e9STejun Heo * reset the device register after changing the IEN bit on ctl
287b78152e9STejun Heo * register.
288b78152e9STejun Heo */
svia_tf_load(struct ata_port * ap,const struct ata_taskfile * tf)289b78152e9STejun Heo static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
290b78152e9STejun Heo {
291b78152e9STejun Heo struct ata_taskfile ttf;
292b78152e9STejun Heo
293b78152e9STejun Heo if (tf->ctl != ap->last_ctl) {
294b78152e9STejun Heo ttf = *tf;
295b78152e9STejun Heo ttf.flags |= ATA_TFLAG_DEVICE;
296b78152e9STejun Heo tf = &ttf;
297b78152e9STejun Heo }
298b78152e9STejun Heo ata_sff_tf_load(ap, tf);
299b78152e9STejun Heo }
300b78152e9STejun Heo
svia_noop_freeze(struct ata_port * ap)30117234246STejun Heo static void svia_noop_freeze(struct ata_port *ap)
30217234246STejun Heo {
30317234246STejun Heo /* Some VIA controllers choke if ATA_NIEN is manipulated in
30417234246STejun Heo * certain way. Leave it alone and just clear pending IRQ.
30517234246STejun Heo */
3065682ed33STejun Heo ap->ops->sff_check_status(ap);
30737f65b8bSTejun Heo ata_bmdma_irq_clear(ap);
30817234246STejun Heo }
30917234246STejun Heo
31054a86bfcSJeff Garzik /**
31154a86bfcSJeff Garzik * vt6420_prereset - prereset for vt6420
312cc0680a5STejun Heo * @link: target ATA link
313d4b2bab4STejun Heo * @deadline: deadline jiffies for the operation
31454a86bfcSJeff Garzik *
31554a86bfcSJeff Garzik * SCR registers on vt6420 are pieces of shit and may hang the
31654a86bfcSJeff Garzik * whole machine completely if accessed with the wrong timing.
31754a86bfcSJeff Garzik * To avoid such catastrophe, vt6420 doesn't provide generic SCR
31854a86bfcSJeff Garzik * access operations, but uses SStatus and SControl only during
31954a86bfcSJeff Garzik * boot probing in controlled way.
32054a86bfcSJeff Garzik *
32154a86bfcSJeff Garzik * As the old (pre EH update) probing code is proven to work, we
32254a86bfcSJeff Garzik * strictly follow the access pattern.
32354a86bfcSJeff Garzik *
32454a86bfcSJeff Garzik * LOCKING:
32554a86bfcSJeff Garzik * Kernel thread context (may sleep)
32654a86bfcSJeff Garzik *
32754a86bfcSJeff Garzik * RETURNS:
32854a86bfcSJeff Garzik * 0 on success, -errno otherwise.
32954a86bfcSJeff Garzik */
vt6420_prereset(struct ata_link * link,unsigned long deadline)330cc0680a5STejun Heo static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
33154a86bfcSJeff Garzik {
332cc0680a5STejun Heo struct ata_port *ap = link->ap;
3339af5c9c9STejun Heo struct ata_eh_context *ehc = &ap->link.eh_context;
33454a86bfcSJeff Garzik unsigned long timeout = jiffies + (HZ * 5);
33554a86bfcSJeff Garzik u32 sstatus, scontrol;
33654a86bfcSJeff Garzik int online;
33754a86bfcSJeff Garzik
33854a86bfcSJeff Garzik /* don't do any SCR stuff if we're not loading */
33968ff6e8eSJeff Garzik if (!(ap->pflags & ATA_PFLAG_LOADING))
34054a86bfcSJeff Garzik goto skip_scr;
34154a86bfcSJeff Garzik
342a09060ffSJeff Garzik /* Resume phy. This is the old SATA resume sequence */
34382ef04fbSTejun Heo svia_scr_write(link, SCR_CONTROL, 0x300);
34482ef04fbSTejun Heo svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */
34554a86bfcSJeff Garzik
34654a86bfcSJeff Garzik /* wait for phy to become ready, if necessary */
34754a86bfcSJeff Garzik do {
34897750cebSTejun Heo ata_msleep(link->ap, 200);
34982ef04fbSTejun Heo svia_scr_read(link, SCR_STATUS, &sstatus);
350da3dbb17STejun Heo if ((sstatus & 0xf) != 1)
35154a86bfcSJeff Garzik break;
35254a86bfcSJeff Garzik } while (time_before(jiffies, timeout));
35354a86bfcSJeff Garzik
35454a86bfcSJeff Garzik /* open code sata_print_link_status() */
35582ef04fbSTejun Heo svia_scr_read(link, SCR_STATUS, &sstatus);
35682ef04fbSTejun Heo svia_scr_read(link, SCR_CONTROL, &scontrol);
35754a86bfcSJeff Garzik
35854a86bfcSJeff Garzik online = (sstatus & 0xf) == 0x3;
35954a86bfcSJeff Garzik
360a9a79dfeSJoe Perches ata_port_info(ap,
36154a86bfcSJeff Garzik "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
36254a86bfcSJeff Garzik online ? "up" : "down", sstatus, scontrol);
36354a86bfcSJeff Garzik
36454a86bfcSJeff Garzik /* SStatus is read one more time */
36582ef04fbSTejun Heo svia_scr_read(link, SCR_STATUS, &sstatus);
36654a86bfcSJeff Garzik
36754a86bfcSJeff Garzik if (!online) {
36854a86bfcSJeff Garzik /* tell EH to bail */
369cf480626STejun Heo ehc->i.action &= ~ATA_EH_RESET;
37054a86bfcSJeff Garzik return 0;
37154a86bfcSJeff Garzik }
37254a86bfcSJeff Garzik
37354a86bfcSJeff Garzik skip_scr:
37454a86bfcSJeff Garzik /* wait for !BSY */
375705e76beSTejun Heo ata_sff_wait_ready(link, deadline);
37654a86bfcSJeff Garzik
37754a86bfcSJeff Garzik return 0;
37854a86bfcSJeff Garzik }
37954a86bfcSJeff Garzik
vt6420_bmdma_start(struct ata_queued_cmd * qc)380a55ab496SBart Hartgers static void vt6420_bmdma_start(struct ata_queued_cmd *qc)
381a55ab496SBart Hartgers {
382a55ab496SBart Hartgers struct ata_port *ap = qc->ap;
383a55ab496SBart Hartgers if ((qc->tf.command == ATA_CMD_PACKET) &&
384a55ab496SBart Hartgers (qc->scsicmd->sc_data_direction == DMA_TO_DEVICE)) {
385a55ab496SBart Hartgers /* Prevents corruption on some ATAPI burners */
386a55ab496SBart Hartgers ata_sff_pause(ap);
387a55ab496SBart Hartgers }
388a55ab496SBart Hartgers ata_bmdma_start(qc);
389a55ab496SBart Hartgers }
390a55ab496SBart Hartgers
vt6421_pata_cable_detect(struct ata_port * ap)391a0fcdc02SJeff Garzik static int vt6421_pata_cable_detect(struct ata_port *ap)
392d73f30e1SAlan {
393d73f30e1SAlan struct pci_dev *pdev = to_pci_dev(ap->host->dev);
394d73f30e1SAlan u8 tmp;
395d73f30e1SAlan
396d73f30e1SAlan pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
397d73f30e1SAlan if (tmp & 0x10)
398a0fcdc02SJeff Garzik return ATA_CBL_PATA40;
399a0fcdc02SJeff Garzik return ATA_CBL_PATA80;
400d73f30e1SAlan }
401d73f30e1SAlan
vt6421_set_pio_mode(struct ata_port * ap,struct ata_device * adev)402d73f30e1SAlan static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
403d73f30e1SAlan {
404d73f30e1SAlan struct pci_dev *pdev = to_pci_dev(ap->host->dev);
405d73f30e1SAlan static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
40602d1d616SBart Hartgers pci_write_config_byte(pdev, PATA_PIO_TIMING - adev->devno,
40702d1d616SBart Hartgers pio_bits[adev->pio_mode - XFER_PIO_0]);
408d73f30e1SAlan }
409d73f30e1SAlan
vt6421_set_dma_mode(struct ata_port * ap,struct ata_device * adev)410d73f30e1SAlan static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
411d73f30e1SAlan {
412d73f30e1SAlan struct pci_dev *pdev = to_pci_dev(ap->host->dev);
413d73f30e1SAlan static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
41402d1d616SBart Hartgers pci_write_config_byte(pdev, PATA_UDMA_TIMING - adev->devno,
41502d1d616SBart Hartgers udma_bits[adev->dma_mode - XFER_UDMA_0]);
416d73f30e1SAlan }
417d73f30e1SAlan
418c6fd2807SJeff Garzik static const unsigned int svia_bar_sizes[] = {
419c6fd2807SJeff Garzik 8, 4, 8, 4, 16, 256
420c6fd2807SJeff Garzik };
421c6fd2807SJeff Garzik
422c6fd2807SJeff Garzik static const unsigned int vt6421_bar_sizes[] = {
423c6fd2807SJeff Garzik 16, 16, 16, 16, 32, 128
424c6fd2807SJeff Garzik };
425c6fd2807SJeff Garzik
svia_scr_addr(void __iomem * addr,unsigned int port)4260d5ff566STejun Heo static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
427c6fd2807SJeff Garzik {
428c6fd2807SJeff Garzik return addr + (port * 128);
429c6fd2807SJeff Garzik }
430c6fd2807SJeff Garzik
vt6421_scr_addr(void __iomem * addr,unsigned int port)4310d5ff566STejun Heo static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
432c6fd2807SJeff Garzik {
433c6fd2807SJeff Garzik return addr + (port * 64);
434c6fd2807SJeff Garzik }
435c6fd2807SJeff Garzik
vt6421_init_addrs(struct ata_port * ap)436eca25dcaSTejun Heo static void vt6421_init_addrs(struct ata_port *ap)
437c6fd2807SJeff Garzik {
438eca25dcaSTejun Heo void __iomem * const * iomap = ap->host->iomap;
439eca25dcaSTejun Heo void __iomem *reg_addr = iomap[ap->port_no];
440eca25dcaSTejun Heo void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
441eca25dcaSTejun Heo struct ata_ioports *ioaddr = &ap->ioaddr;
442c6fd2807SJeff Garzik
443eca25dcaSTejun Heo ioaddr->cmd_addr = reg_addr;
444eca25dcaSTejun Heo ioaddr->altstatus_addr =
445eca25dcaSTejun Heo ioaddr->ctl_addr = (void __iomem *)
4460d5ff566STejun Heo ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
447eca25dcaSTejun Heo ioaddr->bmdma_addr = bmdma_addr;
448eca25dcaSTejun Heo ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
449c6fd2807SJeff Garzik
4509363c382STejun Heo ata_sff_std_ports(ioaddr);
451cbcdd875STejun Heo
452cbcdd875STejun Heo ata_port_pbar_desc(ap, ap->port_no, -1, "port");
453cbcdd875STejun Heo ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
454c6fd2807SJeff Garzik }
455c6fd2807SJeff Garzik
vt6420_prepare_host(struct pci_dev * pdev,struct ata_host ** r_host)456eca25dcaSTejun Heo static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
457c6fd2807SJeff Garzik {
458eca25dcaSTejun Heo const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
459eca25dcaSTejun Heo struct ata_host *host;
460eca25dcaSTejun Heo int rc;
461c6fd2807SJeff Garzik
46298633258SOndrej Zary if (vt6420_hotplug) {
46398633258SOndrej Zary ppi[0]->port_ops->scr_read = svia_scr_read;
46498633258SOndrej Zary ppi[0]->port_ops->scr_write = svia_scr_write;
46598633258SOndrej Zary }
46698633258SOndrej Zary
4671c5afdf7STejun Heo rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
468eca25dcaSTejun Heo if (rc)
469eca25dcaSTejun Heo return rc;
470eca25dcaSTejun Heo *r_host = host;
471c6fd2807SJeff Garzik
472eca25dcaSTejun Heo rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
473eca25dcaSTejun Heo if (rc) {
474a44fec1fSJoe Perches dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
475eca25dcaSTejun Heo return rc;
476e1be5d73STejun Heo }
477e1be5d73STejun Heo
478eca25dcaSTejun Heo host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
479eca25dcaSTejun Heo host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
480c6fd2807SJeff Garzik
481eca25dcaSTejun Heo return 0;
482c6fd2807SJeff Garzik }
483c6fd2807SJeff Garzik
vt6421_prepare_host(struct pci_dev * pdev,struct ata_host ** r_host)484eca25dcaSTejun Heo static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
485c6fd2807SJeff Garzik {
486eca25dcaSTejun Heo const struct ata_port_info *ppi[] =
487eca25dcaSTejun Heo { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
488eca25dcaSTejun Heo struct ata_host *host;
489eca25dcaSTejun Heo int i, rc;
490c6fd2807SJeff Garzik
491eca25dcaSTejun Heo *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
492eca25dcaSTejun Heo if (!host) {
493a44fec1fSJoe Perches dev_err(&pdev->dev, "failed to allocate host\n");
494eca25dcaSTejun Heo return -ENOMEM;
495e1be5d73STejun Heo }
496e1be5d73STejun Heo
4978fd7d1b1STejun Heo rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
498eca25dcaSTejun Heo if (rc) {
499a44fec1fSJoe Perches dev_err(&pdev->dev, "failed to request/iomap PCI BARs (errno=%d)\n",
500a44fec1fSJoe Perches rc);
501eca25dcaSTejun Heo return rc;
502eca25dcaSTejun Heo }
503eca25dcaSTejun Heo host->iomap = pcim_iomap_table(pdev);
504c6fd2807SJeff Garzik
505eca25dcaSTejun Heo for (i = 0; i < host->n_ports; i++)
506eca25dcaSTejun Heo vt6421_init_addrs(host->ports[i]);
507eca25dcaSTejun Heo
508b5e55556SChristoph Hellwig return dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
509c6fd2807SJeff Garzik }
510c6fd2807SJeff Garzik
vt8251_prepare_host(struct pci_dev * pdev,struct ata_host ** r_host)511b9d5b89bSTejun Heo static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
512b9d5b89bSTejun Heo {
513b9d5b89bSTejun Heo const struct ata_port_info *ppi[] = { &vt8251_port_info, NULL };
514b9d5b89bSTejun Heo struct ata_host *host;
515b9d5b89bSTejun Heo int i, rc;
516b9d5b89bSTejun Heo
5171c5afdf7STejun Heo rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
518b9d5b89bSTejun Heo if (rc)
519b9d5b89bSTejun Heo return rc;
520b9d5b89bSTejun Heo *r_host = host;
521b9d5b89bSTejun Heo
522b9d5b89bSTejun Heo rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
523b9d5b89bSTejun Heo if (rc) {
524a44fec1fSJoe Perches dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n");
525b9d5b89bSTejun Heo return rc;
526b9d5b89bSTejun Heo }
527b9d5b89bSTejun Heo
528b9d5b89bSTejun Heo /* 8251 hosts four sata ports as M/S of the two channels */
529b9d5b89bSTejun Heo for (i = 0; i < host->n_ports; i++)
530b9d5b89bSTejun Heo ata_slave_link_init(host->ports[i]);
531b9d5b89bSTejun Heo
532b9d5b89bSTejun Heo return 0;
533b9d5b89bSTejun Heo }
534b9d5b89bSTejun Heo
svia_wd_fix(struct pci_dev * pdev)53544a9b494SOndrej Zary static void svia_wd_fix(struct pci_dev *pdev)
53644a9b494SOndrej Zary {
53744a9b494SOndrej Zary u8 tmp8;
53844a9b494SOndrej Zary
53944a9b494SOndrej Zary pci_read_config_byte(pdev, 0x52, &tmp8);
54044a9b494SOndrej Zary pci_write_config_byte(pdev, 0x52, tmp8 | BIT(2));
54144a9b494SOndrej Zary }
54244a9b494SOndrej Zary
vt642x_interrupt(int irq,void * dev_instance)54398633258SOndrej Zary static irqreturn_t vt642x_interrupt(int irq, void *dev_instance)
54457e5568fSOndrej Zary {
54557e5568fSOndrej Zary struct ata_host *host = dev_instance;
54657e5568fSOndrej Zary irqreturn_t rc = ata_bmdma_interrupt(irq, dev_instance);
54757e5568fSOndrej Zary
54857e5568fSOndrej Zary /* if the IRQ was not handled, it might be a hotplug IRQ */
54957e5568fSOndrej Zary if (rc != IRQ_HANDLED) {
55057e5568fSOndrej Zary u32 serror;
55157e5568fSOndrej Zary unsigned long flags;
55257e5568fSOndrej Zary
55357e5568fSOndrej Zary spin_lock_irqsave(&host->lock, flags);
55457e5568fSOndrej Zary /* check for hotplug on port 0 */
55557e5568fSOndrej Zary svia_scr_read(&host->ports[0]->link, SCR_ERROR, &serror);
55657e5568fSOndrej Zary if (serror & SERR_PHYRDY_CHG) {
55757e5568fSOndrej Zary ata_ehi_hotplugged(&host->ports[0]->link.eh_info);
55857e5568fSOndrej Zary ata_port_freeze(host->ports[0]);
55957e5568fSOndrej Zary rc = IRQ_HANDLED;
56057e5568fSOndrej Zary }
56157e5568fSOndrej Zary /* check for hotplug on port 1 */
56257e5568fSOndrej Zary svia_scr_read(&host->ports[1]->link, SCR_ERROR, &serror);
56357e5568fSOndrej Zary if (serror & SERR_PHYRDY_CHG) {
56457e5568fSOndrej Zary ata_ehi_hotplugged(&host->ports[1]->link.eh_info);
56557e5568fSOndrej Zary ata_port_freeze(host->ports[1]);
56657e5568fSOndrej Zary rc = IRQ_HANDLED;
56757e5568fSOndrej Zary }
56857e5568fSOndrej Zary spin_unlock_irqrestore(&host->lock, flags);
56957e5568fSOndrej Zary }
57057e5568fSOndrej Zary
57157e5568fSOndrej Zary return rc;
57257e5568fSOndrej Zary }
57357e5568fSOndrej Zary
vt6421_error_handler(struct ata_port * ap)57444a9b494SOndrej Zary static void vt6421_error_handler(struct ata_port *ap)
57544a9b494SOndrej Zary {
57644a9b494SOndrej Zary struct svia_priv *hpriv = ap->host->private_data;
57744a9b494SOndrej Zary struct pci_dev *pdev = to_pci_dev(ap->host->dev);
57844a9b494SOndrej Zary u32 serror;
57944a9b494SOndrej Zary
58044a9b494SOndrej Zary /* see svia_configure() for description */
58144a9b494SOndrej Zary if (!hpriv->wd_workaround) {
58244a9b494SOndrej Zary svia_scr_read(&ap->link, SCR_ERROR, &serror);
58344a9b494SOndrej Zary if (serror == 0x1000500) {
58444a9b494SOndrej Zary ata_port_warn(ap, "Incompatible drive: enabling workaround. This slows down transfer rate to ~60 MB/s");
58544a9b494SOndrej Zary svia_wd_fix(pdev);
58644a9b494SOndrej Zary hpriv->wd_workaround = true;
58744a9b494SOndrej Zary ap->link.eh_context.i.flags |= ATA_EHI_QUIET;
58844a9b494SOndrej Zary }
58944a9b494SOndrej Zary }
59044a9b494SOndrej Zary
59144a9b494SOndrej Zary ata_sff_error_handler(ap);
59244a9b494SOndrej Zary }
59344a9b494SOndrej Zary
svia_configure(struct pci_dev * pdev,int board_id,struct svia_priv * hpriv)59444a9b494SOndrej Zary static void svia_configure(struct pci_dev *pdev, int board_id,
59544a9b494SOndrej Zary struct svia_priv *hpriv)
596c6fd2807SJeff Garzik {
597c6fd2807SJeff Garzik u8 tmp8;
598c6fd2807SJeff Garzik
599c6fd2807SJeff Garzik pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
600a44fec1fSJoe Perches dev_info(&pdev->dev, "routed to hard irq line %d\n",
601c6fd2807SJeff Garzik (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
602c6fd2807SJeff Garzik
603c6fd2807SJeff Garzik /* make sure SATA channels are enabled */
604c6fd2807SJeff Garzik pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
605c6fd2807SJeff Garzik if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
6065b933e63SJoe Perches dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n",
607c6fd2807SJeff Garzik (int)tmp8);
608c6fd2807SJeff Garzik tmp8 |= ALL_PORTS;
609c6fd2807SJeff Garzik pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
610c6fd2807SJeff Garzik }
611c6fd2807SJeff Garzik
612c6fd2807SJeff Garzik /* make sure interrupts for each channel sent to us */
613c6fd2807SJeff Garzik pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
614c6fd2807SJeff Garzik if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
6155b933e63SJoe Perches dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n",
616c6fd2807SJeff Garzik (int) tmp8);
617c6fd2807SJeff Garzik tmp8 |= ALL_PORTS;
618c6fd2807SJeff Garzik pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
619c6fd2807SJeff Garzik }
620c6fd2807SJeff Garzik
621c6fd2807SJeff Garzik /* make sure native mode is enabled */
622c6fd2807SJeff Garzik pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
623c6fd2807SJeff Garzik if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
6245b933e63SJoe Perches dev_dbg(&pdev->dev,
625c6fd2807SJeff Garzik "enabling SATA channel native mode (0x%x)\n",
626c6fd2807SJeff Garzik (int) tmp8);
627c6fd2807SJeff Garzik tmp8 |= NATIVE_MODE_ALL;
628c6fd2807SJeff Garzik pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
629c6fd2807SJeff Garzik }
6308b27ff4cSTejun Heo
63198633258SOndrej Zary if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421) {
63257e5568fSOndrej Zary /* enable IRQ on hotplug */
63357e5568fSOndrej Zary pci_read_config_byte(pdev, SVIA_MISC_3, &tmp8);
63457e5568fSOndrej Zary if ((tmp8 & SATA_HOTPLUG) != SATA_HOTPLUG) {
63557e5568fSOndrej Zary dev_dbg(&pdev->dev,
63657e5568fSOndrej Zary "enabling SATA hotplug (0x%x)\n",
63757e5568fSOndrej Zary (int) tmp8);
63857e5568fSOndrej Zary tmp8 |= SATA_HOTPLUG;
63957e5568fSOndrej Zary pci_write_config_byte(pdev, SVIA_MISC_3, tmp8);
64057e5568fSOndrej Zary }
6413cf86452SOndrej Zary }
64257e5568fSOndrej Zary
6438b27ff4cSTejun Heo /*
644b1353e4fSTejun Heo * vt6420/1 has problems talking to some drives. The following
645b475a3b8STejun Heo * is the fix from Joseph Chan <JosephChan@via.com.tw>.
646b475a3b8STejun Heo *
647b475a3b8STejun Heo * When host issues HOLD, device may send up to 20DW of data
648b475a3b8STejun Heo * before acknowledging it with HOLDA and the host should be
649b475a3b8STejun Heo * able to buffer them in FIFO. Unfortunately, some WD drives
650b475a3b8STejun Heo * send up to 40DW before acknowledging HOLD and, in the
651b475a3b8STejun Heo * default configuration, this ends up overflowing vt6421's
652b475a3b8STejun Heo * FIFO, making the controller abort the transaction with
653b475a3b8STejun Heo * R_ERR.
654b475a3b8STejun Heo *
655b475a3b8STejun Heo * Rx52[2] is the internal 128DW FIFO Flow control watermark
656b475a3b8STejun Heo * adjusting mechanism enable bit and the default value 0
657b475a3b8STejun Heo * means host will issue HOLD to device when the left FIFO
658b475a3b8STejun Heo * size goes below 32DW. Setting it to 1 makes the watermark
659b475a3b8STejun Heo * 64DW.
6608b27ff4cSTejun Heo *
6618b27ff4cSTejun Heo * https://bugzilla.kernel.org/show_bug.cgi?id=15173
662b475a3b8STejun Heo * http://article.gmane.org/gmane.linux.ide/46352
663b1353e4fSTejun Heo * http://thread.gmane.org/gmane.linux.kernel/1062139
66444a9b494SOndrej Zary *
66544a9b494SOndrej Zary * As the fix slows down data transfer, apply it only if the error
66644a9b494SOndrej Zary * actually appears - see vt6421_error_handler()
66744a9b494SOndrej Zary * Apply the fix always on vt6420 as we don't know if SCR_ERROR can be
66844a9b494SOndrej Zary * read safely.
6698b27ff4cSTejun Heo */
67044a9b494SOndrej Zary if (board_id == vt6420) {
67144a9b494SOndrej Zary svia_wd_fix(pdev);
67244a9b494SOndrej Zary hpriv->wd_workaround = true;
6738b27ff4cSTejun Heo }
674c6fd2807SJeff Garzik }
675c6fd2807SJeff Garzik
svia_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)676c6fd2807SJeff Garzik static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
677c6fd2807SJeff Garzik {
678c6fd2807SJeff Garzik unsigned int i;
679c6fd2807SJeff Garzik int rc;
680f1c22943SJeff Garzik struct ata_host *host = NULL;
681c6fd2807SJeff Garzik int board_id = (int) ent->driver_data;
682b4482a4bSAl Viro const unsigned *bar_sizes;
68344a9b494SOndrej Zary struct svia_priv *hpriv;
684c6fd2807SJeff Garzik
68506296a1eSJoe Perches ata_print_version_once(&pdev->dev, DRV_VERSION);
686c6fd2807SJeff Garzik
68724dc5f33STejun Heo rc = pcim_enable_device(pdev);
688c6fd2807SJeff Garzik if (rc)
689c6fd2807SJeff Garzik return rc;
690c6fd2807SJeff Garzik
691b9d5b89bSTejun Heo if (board_id == vt6421)
692c6fd2807SJeff Garzik bar_sizes = &vt6421_bar_sizes[0];
693b9d5b89bSTejun Heo else
694b9d5b89bSTejun Heo bar_sizes = &svia_bar_sizes[0];
695c6fd2807SJeff Garzik
696c6fd2807SJeff Garzik for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
697c6fd2807SJeff Garzik if ((pci_resource_start(pdev, i) == 0) ||
698c6fd2807SJeff Garzik (pci_resource_len(pdev, i) < bar_sizes[i])) {
699a44fec1fSJoe Perches dev_err(&pdev->dev,
700c6fd2807SJeff Garzik "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
701c6fd2807SJeff Garzik i,
702c6fd2807SJeff Garzik (unsigned long long)pci_resource_start(pdev, i),
703c6fd2807SJeff Garzik (unsigned long long)pci_resource_len(pdev, i));
70424dc5f33STejun Heo return -ENODEV;
705c6fd2807SJeff Garzik }
706c6fd2807SJeff Garzik
707b9d5b89bSTejun Heo switch (board_id) {
708b9d5b89bSTejun Heo case vt6420:
709eca25dcaSTejun Heo rc = vt6420_prepare_host(pdev, &host);
710b9d5b89bSTejun Heo break;
711b9d5b89bSTejun Heo case vt6421:
712eca25dcaSTejun Heo rc = vt6421_prepare_host(pdev, &host);
713b9d5b89bSTejun Heo break;
714b9d5b89bSTejun Heo case vt8251:
715b9d5b89bSTejun Heo rc = vt8251_prepare_host(pdev, &host);
716b9d5b89bSTejun Heo break;
717b9d5b89bSTejun Heo default:
718554d491dSMarcin Slusarz rc = -EINVAL;
719b9d5b89bSTejun Heo }
720554d491dSMarcin Slusarz if (rc)
721554d491dSMarcin Slusarz return rc;
722c6fd2807SJeff Garzik
72344a9b494SOndrej Zary hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
72444a9b494SOndrej Zary if (!hpriv)
72544a9b494SOndrej Zary return -ENOMEM;
72644a9b494SOndrej Zary host->private_data = hpriv;
72744a9b494SOndrej Zary
72844a9b494SOndrej Zary svia_configure(pdev, board_id, hpriv);
729c6fd2807SJeff Garzik
730c6fd2807SJeff Garzik pci_set_master(pdev);
73198633258SOndrej Zary if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421)
73298633258SOndrej Zary return ata_host_activate(host, pdev->irq, vt642x_interrupt,
73357e5568fSOndrej Zary IRQF_SHARED, &svia_sht);
73457e5568fSOndrej Zary else
735c3b28894STejun Heo return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
7369363c382STejun Heo IRQF_SHARED, &svia_sht);
737c6fd2807SJeff Garzik }
738c6fd2807SJeff Garzik
73944a9b494SOndrej Zary #ifdef CONFIG_PM_SLEEP
svia_pci_device_resume(struct pci_dev * pdev)74044a9b494SOndrej Zary static int svia_pci_device_resume(struct pci_dev *pdev)
74144a9b494SOndrej Zary {
74244a9b494SOndrej Zary struct ata_host *host = pci_get_drvdata(pdev);
74344a9b494SOndrej Zary struct svia_priv *hpriv = host->private_data;
74444a9b494SOndrej Zary int rc;
74544a9b494SOndrej Zary
74644a9b494SOndrej Zary rc = ata_pci_device_do_resume(pdev);
74744a9b494SOndrej Zary if (rc)
74844a9b494SOndrej Zary return rc;
74944a9b494SOndrej Zary
75044a9b494SOndrej Zary if (hpriv->wd_workaround)
75144a9b494SOndrej Zary svia_wd_fix(pdev);
75244a9b494SOndrej Zary ata_host_resume(host);
75344a9b494SOndrej Zary
75444a9b494SOndrej Zary return 0;
75544a9b494SOndrej Zary }
75644a9b494SOndrej Zary #endif
75744a9b494SOndrej Zary
7582fc75da0SAxel Lin module_pci_driver(svia_pci_driver);
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