1 /* 2 * sata_uli.c - ULi Electronics SATA 3 * 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; see the file COPYING. If not, write to 17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * 20 * libata documentation is available via 'make {ps|pdf}docs', 21 * as Documentation/DocBook/libata.* 22 * 23 * Hardware documentation available under NDA. 24 * 25 */ 26 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/blkdev.h> 32 #include <linux/delay.h> 33 #include <linux/interrupt.h> 34 #include <linux/device.h> 35 #include <scsi/scsi_host.h> 36 #include <linux/libata.h> 37 38 #define DRV_NAME "sata_uli" 39 #define DRV_VERSION "1.1" 40 41 enum { 42 uli_5289 = 0, 43 uli_5287 = 1, 44 uli_5281 = 2, 45 46 uli_max_ports = 4, 47 48 /* PCI configuration registers */ 49 ULI5287_BASE = 0x90, /* sata0 phy SCR registers */ 50 ULI5287_OFFS = 0x10, /* offset from sata0->sata1 phy regs */ 51 ULI5281_BASE = 0x60, /* sata0 phy SCR registers */ 52 ULI5281_OFFS = 0x60, /* offset from sata0->sata1 phy regs */ 53 }; 54 55 struct uli_priv { 56 unsigned int scr_cfg_addr[uli_max_ports]; 57 }; 58 59 static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 60 static u32 uli_scr_read (struct ata_port *ap, unsigned int sc_reg); 61 static void uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 62 63 static const struct pci_device_id uli_pci_tbl[] = { 64 { PCI_VDEVICE(AL, 0x5289), uli_5289 }, 65 { PCI_VDEVICE(AL, 0x5287), uli_5287 }, 66 { PCI_VDEVICE(AL, 0x5281), uli_5281 }, 67 68 { } /* terminate list */ 69 }; 70 71 static struct pci_driver uli_pci_driver = { 72 .name = DRV_NAME, 73 .id_table = uli_pci_tbl, 74 .probe = uli_init_one, 75 .remove = ata_pci_remove_one, 76 }; 77 78 static struct scsi_host_template uli_sht = { 79 .module = THIS_MODULE, 80 .name = DRV_NAME, 81 .ioctl = ata_scsi_ioctl, 82 .queuecommand = ata_scsi_queuecmd, 83 .can_queue = ATA_DEF_QUEUE, 84 .this_id = ATA_SHT_THIS_ID, 85 .sg_tablesize = LIBATA_MAX_PRD, 86 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 87 .emulated = ATA_SHT_EMULATED, 88 .use_clustering = ATA_SHT_USE_CLUSTERING, 89 .proc_name = DRV_NAME, 90 .dma_boundary = ATA_DMA_BOUNDARY, 91 .slave_configure = ata_scsi_slave_config, 92 .slave_destroy = ata_scsi_slave_destroy, 93 .bios_param = ata_std_bios_param, 94 }; 95 96 static const struct ata_port_operations uli_ops = { 97 .port_disable = ata_port_disable, 98 99 .tf_load = ata_tf_load, 100 .tf_read = ata_tf_read, 101 .check_status = ata_check_status, 102 .exec_command = ata_exec_command, 103 .dev_select = ata_std_dev_select, 104 105 .bmdma_setup = ata_bmdma_setup, 106 .bmdma_start = ata_bmdma_start, 107 .bmdma_stop = ata_bmdma_stop, 108 .bmdma_status = ata_bmdma_status, 109 .qc_prep = ata_qc_prep, 110 .qc_issue = ata_qc_issue_prot, 111 .data_xfer = ata_data_xfer, 112 113 .freeze = ata_bmdma_freeze, 114 .thaw = ata_bmdma_thaw, 115 .error_handler = ata_bmdma_error_handler, 116 .post_internal_cmd = ata_bmdma_post_internal_cmd, 117 118 .irq_clear = ata_bmdma_irq_clear, 119 .irq_on = ata_irq_on, 120 .irq_ack = ata_irq_ack, 121 122 .scr_read = uli_scr_read, 123 .scr_write = uli_scr_write, 124 125 .port_start = ata_port_start, 126 }; 127 128 static struct ata_port_info uli_port_info = { 129 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 130 ATA_FLAG_IGN_SIMPLEX, 131 .pio_mask = 0x1f, /* pio0-4 */ 132 .udma_mask = 0x7f, /* udma0-6 */ 133 .port_ops = &uli_ops, 134 }; 135 136 137 MODULE_AUTHOR("Peer Chen"); 138 MODULE_DESCRIPTION("low-level driver for ULi Electronics SATA controller"); 139 MODULE_LICENSE("GPL"); 140 MODULE_DEVICE_TABLE(pci, uli_pci_tbl); 141 MODULE_VERSION(DRV_VERSION); 142 143 static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg) 144 { 145 struct uli_priv *hpriv = ap->host->private_data; 146 return hpriv->scr_cfg_addr[ap->port_no] + (4 * sc_reg); 147 } 148 149 static u32 uli_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg) 150 { 151 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 152 unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg); 153 u32 val; 154 155 pci_read_config_dword(pdev, cfg_addr, &val); 156 return val; 157 } 158 159 static void uli_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val) 160 { 161 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 162 unsigned int cfg_addr = get_scr_cfg_addr(ap, scr); 163 164 pci_write_config_dword(pdev, cfg_addr, val); 165 } 166 167 static u32 uli_scr_read (struct ata_port *ap, unsigned int sc_reg) 168 { 169 if (sc_reg > SCR_CONTROL) 170 return 0xffffffffU; 171 172 return uli_scr_cfg_read(ap, sc_reg); 173 } 174 175 static void uli_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) 176 { 177 if (sc_reg > SCR_CONTROL) //SCR_CONTROL=2, SCR_ERROR=1, SCR_STATUS=0 178 return; 179 180 uli_scr_cfg_write(ap, sc_reg, val); 181 } 182 183 static int uli_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 184 { 185 static int printed_version; 186 const struct ata_port_info *ppi[] = { &uli_port_info, NULL }; 187 unsigned int board_idx = (unsigned int) ent->driver_data; 188 struct ata_host *host; 189 struct uli_priv *hpriv; 190 void __iomem * const *iomap; 191 struct ata_ioports *ioaddr; 192 int n_ports, rc; 193 194 if (!printed_version++) 195 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 196 197 rc = pcim_enable_device(pdev); 198 if (rc) 199 return rc; 200 201 n_ports = 2; 202 if (board_idx == uli_5287) 203 n_ports = 4; 204 rc = ata_pci_prepare_native_host(pdev, ppi, n_ports, &host); 205 if (rc) 206 return rc; 207 208 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 209 if (!hpriv) 210 return -ENOMEM; 211 host->private_data = hpriv; 212 213 iomap = host->iomap; 214 215 switch (board_idx) { 216 case uli_5287: 217 hpriv->scr_cfg_addr[0] = ULI5287_BASE; 218 hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS; 219 220 ioaddr = &host->ports[2]->ioaddr; 221 ioaddr->cmd_addr = iomap[0] + 8; 222 ioaddr->altstatus_addr = 223 ioaddr->ctl_addr = (void __iomem *) 224 ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS) + 4; 225 ioaddr->bmdma_addr = iomap[4] + 16; 226 hpriv->scr_cfg_addr[2] = ULI5287_BASE + ULI5287_OFFS*4; 227 ata_std_ports(ioaddr); 228 229 ioaddr = &host->ports[3]->ioaddr; 230 ioaddr->cmd_addr = iomap[2] + 8; 231 ioaddr->altstatus_addr = 232 ioaddr->ctl_addr = (void __iomem *) 233 ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS) + 4; 234 ioaddr->bmdma_addr = iomap[4] + 24; 235 hpriv->scr_cfg_addr[3] = ULI5287_BASE + ULI5287_OFFS*5; 236 ata_std_ports(ioaddr); 237 break; 238 239 case uli_5289: 240 hpriv->scr_cfg_addr[0] = ULI5287_BASE; 241 hpriv->scr_cfg_addr[1] = ULI5287_BASE + ULI5287_OFFS; 242 break; 243 244 case uli_5281: 245 hpriv->scr_cfg_addr[0] = ULI5281_BASE; 246 hpriv->scr_cfg_addr[1] = ULI5281_BASE + ULI5281_OFFS; 247 break; 248 249 default: 250 BUG(); 251 break; 252 } 253 254 pci_set_master(pdev); 255 pci_intx(pdev, 1); 256 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED, 257 &uli_sht); 258 } 259 260 static int __init uli_init(void) 261 { 262 return pci_register_driver(&uli_pci_driver); 263 } 264 265 static void __exit uli_exit(void) 266 { 267 pci_unregister_driver(&uli_pci_driver); 268 } 269 270 271 module_init(uli_init); 272 module_exit(uli_exit); 273