1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * sata_svw.c - ServerWorks / Apple K2 SATA 4 * 5 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and 6 * Jeff Garzik <jgarzik@pobox.com> 7 * Please ALWAYS copy linux-ide@vger.kernel.org 8 * on emails. 9 * 10 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> 11 * 12 * Bits from Jeff Garzik, Copyright RedHat, Inc. 13 * 14 * This driver probably works with non-Apple versions of the 15 * Broadcom chipset... 16 * 17 * libata documentation is available via 'make {ps|pdf}docs', 18 * as Documentation/driver-api/libata.rst 19 * 20 * Hardware documentation available under NDA. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 #include <linux/blkdev.h> 27 #include <linux/delay.h> 28 #include <linux/interrupt.h> 29 #include <linux/device.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_cmnd.h> 32 #include <scsi/scsi.h> 33 #include <linux/libata.h> 34 #include <linux/of.h> 35 36 #define DRV_NAME "sata_svw" 37 #define DRV_VERSION "2.3" 38 39 enum { 40 /* ap->flags bits */ 41 K2_FLAG_SATA_8_PORTS = (1 << 24), 42 K2_FLAG_NO_ATAPI_DMA = (1 << 25), 43 K2_FLAG_BAR_POS_3 = (1 << 26), 44 45 /* Taskfile registers offsets */ 46 K2_SATA_TF_CMD_OFFSET = 0x00, 47 K2_SATA_TF_DATA_OFFSET = 0x00, 48 K2_SATA_TF_ERROR_OFFSET = 0x04, 49 K2_SATA_TF_NSECT_OFFSET = 0x08, 50 K2_SATA_TF_LBAL_OFFSET = 0x0c, 51 K2_SATA_TF_LBAM_OFFSET = 0x10, 52 K2_SATA_TF_LBAH_OFFSET = 0x14, 53 K2_SATA_TF_DEVICE_OFFSET = 0x18, 54 K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, 55 K2_SATA_TF_CTL_OFFSET = 0x20, 56 57 /* DMA base */ 58 K2_SATA_DMA_CMD_OFFSET = 0x30, 59 60 /* SCRs base */ 61 K2_SATA_SCR_STATUS_OFFSET = 0x40, 62 K2_SATA_SCR_ERROR_OFFSET = 0x44, 63 K2_SATA_SCR_CONTROL_OFFSET = 0x48, 64 65 /* Others */ 66 K2_SATA_SICR1_OFFSET = 0x80, 67 K2_SATA_SICR2_OFFSET = 0x84, 68 K2_SATA_SIM_OFFSET = 0x88, 69 70 /* Port stride */ 71 K2_SATA_PORT_OFFSET = 0x100, 72 73 chip_svw4 = 0, 74 chip_svw8 = 1, 75 chip_svw42 = 2, /* bar 3 */ 76 chip_svw43 = 3, /* bar 5 */ 77 }; 78 79 static u8 k2_stat_check_status(struct ata_port *ap); 80 81 82 static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc) 83 { 84 u8 cmnd = qc->scsicmd->cmnd[0]; 85 86 if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA) 87 return -1; /* ATAPI DMA not supported */ 88 else { 89 switch (cmnd) { 90 case READ_10: 91 case READ_12: 92 case READ_16: 93 case WRITE_10: 94 case WRITE_12: 95 case WRITE_16: 96 return 0; 97 98 default: 99 return -1; 100 } 101 102 } 103 } 104 105 static int k2_sata_scr_read(struct ata_link *link, 106 unsigned int sc_reg, u32 *val) 107 { 108 if (sc_reg > SCR_CONTROL) 109 return -EINVAL; 110 *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); 111 return 0; 112 } 113 114 115 static int k2_sata_scr_write(struct ata_link *link, 116 unsigned int sc_reg, u32 val) 117 { 118 if (sc_reg > SCR_CONTROL) 119 return -EINVAL; 120 writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); 121 return 0; 122 } 123 124 static int k2_sata_softreset(struct ata_link *link, 125 unsigned int *class, unsigned long deadline) 126 { 127 u8 dmactl; 128 void __iomem *mmio = link->ap->ioaddr.bmdma_addr; 129 130 dmactl = readb(mmio + ATA_DMA_CMD); 131 132 /* Clear the start bit */ 133 if (dmactl & ATA_DMA_START) { 134 dmactl &= ~ATA_DMA_START; 135 writeb(dmactl, mmio + ATA_DMA_CMD); 136 } 137 138 return ata_sff_softreset(link, class, deadline); 139 } 140 141 static int k2_sata_hardreset(struct ata_link *link, 142 unsigned int *class, unsigned long deadline) 143 { 144 u8 dmactl; 145 void __iomem *mmio = link->ap->ioaddr.bmdma_addr; 146 147 dmactl = readb(mmio + ATA_DMA_CMD); 148 149 /* Clear the start bit */ 150 if (dmactl & ATA_DMA_START) { 151 dmactl &= ~ATA_DMA_START; 152 writeb(dmactl, mmio + ATA_DMA_CMD); 153 } 154 155 return sata_sff_hardreset(link, class, deadline); 156 } 157 158 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 159 { 160 struct ata_ioports *ioaddr = &ap->ioaddr; 161 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 162 163 if (tf->ctl != ap->last_ctl) { 164 writeb(tf->ctl, ioaddr->ctl_addr); 165 ap->last_ctl = tf->ctl; 166 ata_wait_idle(ap); 167 } 168 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 169 writew(tf->feature | (((u16)tf->hob_feature) << 8), 170 ioaddr->feature_addr); 171 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), 172 ioaddr->nsect_addr); 173 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), 174 ioaddr->lbal_addr); 175 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), 176 ioaddr->lbam_addr); 177 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), 178 ioaddr->lbah_addr); 179 } else if (is_addr) { 180 writew(tf->feature, ioaddr->feature_addr); 181 writew(tf->nsect, ioaddr->nsect_addr); 182 writew(tf->lbal, ioaddr->lbal_addr); 183 writew(tf->lbam, ioaddr->lbam_addr); 184 writew(tf->lbah, ioaddr->lbah_addr); 185 } 186 187 if (tf->flags & ATA_TFLAG_DEVICE) 188 writeb(tf->device, ioaddr->device_addr); 189 190 ata_wait_idle(ap); 191 } 192 193 194 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 195 { 196 struct ata_ioports *ioaddr = &ap->ioaddr; 197 u16 nsect, lbal, lbam, lbah, error; 198 199 tf->status = k2_stat_check_status(ap); 200 tf->device = readw(ioaddr->device_addr); 201 error = readw(ioaddr->error_addr); 202 nsect = readw(ioaddr->nsect_addr); 203 lbal = readw(ioaddr->lbal_addr); 204 lbam = readw(ioaddr->lbam_addr); 205 lbah = readw(ioaddr->lbah_addr); 206 207 tf->error = error; 208 tf->nsect = nsect; 209 tf->lbal = lbal; 210 tf->lbam = lbam; 211 tf->lbah = lbah; 212 213 if (tf->flags & ATA_TFLAG_LBA48) { 214 tf->hob_feature = error >> 8; 215 tf->hob_nsect = nsect >> 8; 216 tf->hob_lbal = lbal >> 8; 217 tf->hob_lbam = lbam >> 8; 218 tf->hob_lbah = lbah >> 8; 219 } 220 } 221 222 /** 223 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) 224 * @qc: Info associated with this ATA transaction. 225 * 226 * LOCKING: 227 * spin_lock_irqsave(host lock) 228 */ 229 230 static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc) 231 { 232 struct ata_port *ap = qc->ap; 233 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 234 u8 dmactl; 235 void __iomem *mmio = ap->ioaddr.bmdma_addr; 236 237 /* load PRD table addr. */ 238 mb(); /* make sure PRD table writes are visible to controller */ 239 writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS); 240 241 /* specify data direction, triple-check start bit is clear */ 242 dmactl = readb(mmio + ATA_DMA_CMD); 243 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); 244 if (!rw) 245 dmactl |= ATA_DMA_WR; 246 writeb(dmactl, mmio + ATA_DMA_CMD); 247 248 /* issue r/w command if this is not a ATA DMA command*/ 249 if (qc->tf.protocol != ATA_PROT_DMA) 250 ap->ops->sff_exec_command(ap, &qc->tf); 251 } 252 253 /** 254 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) 255 * @qc: Info associated with this ATA transaction. 256 * 257 * LOCKING: 258 * spin_lock_irqsave(host lock) 259 */ 260 261 static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc) 262 { 263 struct ata_port *ap = qc->ap; 264 void __iomem *mmio = ap->ioaddr.bmdma_addr; 265 u8 dmactl; 266 267 /* start host DMA transaction */ 268 dmactl = readb(mmio + ATA_DMA_CMD); 269 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); 270 /* This works around possible data corruption. 271 272 On certain SATA controllers that can be seen when the r/w 273 command is given to the controller before the host DMA is 274 started. 275 276 On a Read command, the controller would initiate the 277 command to the drive even before it sees the DMA 278 start. When there are very fast drives connected to the 279 controller, or when the data request hits in the drive 280 cache, there is the possibility that the drive returns a 281 part or all of the requested data to the controller before 282 the DMA start is issued. In this case, the controller 283 would become confused as to what to do with the data. In 284 the worst case when all the data is returned back to the 285 controller, the controller could hang. In other cases it 286 could return partial data returning in data 287 corruption. This problem has been seen in PPC systems and 288 can also appear on an system with very fast disks, where 289 the SATA controller is sitting behind a number of bridges, 290 and hence there is significant latency between the r/w 291 command and the start command. */ 292 /* issue r/w command if the access is to ATA */ 293 if (qc->tf.protocol == ATA_PROT_DMA) 294 ap->ops->sff_exec_command(ap, &qc->tf); 295 } 296 297 298 static u8 k2_stat_check_status(struct ata_port *ap) 299 { 300 return readl(ap->ioaddr.status_addr); 301 } 302 303 static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost) 304 { 305 struct ata_port *ap; 306 struct device_node *np; 307 int index; 308 309 /* Find the ata_port */ 310 ap = ata_shost_to_port(shost); 311 if (ap == NULL) 312 return 0; 313 314 /* Find the OF node for the PCI device proper */ 315 np = pci_device_to_OF_node(to_pci_dev(ap->host->dev)); 316 if (np == NULL) 317 return 0; 318 319 /* Match it to a port node */ 320 index = (ap == ap->host->ports[0]) ? 0 : 1; 321 for (np = np->child; np != NULL; np = np->sibling) { 322 const u32 *reg = of_get_property(np, "reg", NULL); 323 if (!reg) 324 continue; 325 if (index == *reg) { 326 seq_printf(m, "devspec: %pOF\n", np); 327 break; 328 } 329 } 330 return 0; 331 } 332 333 static const struct scsi_host_template k2_sata_sht = { 334 ATA_BMDMA_SHT(DRV_NAME), 335 .show_info = k2_sata_show_info, 336 }; 337 338 339 static struct ata_port_operations k2_sata_ops = { 340 .inherits = &ata_bmdma_port_ops, 341 .softreset = k2_sata_softreset, 342 .hardreset = k2_sata_hardreset, 343 .sff_tf_load = k2_sata_tf_load, 344 .sff_tf_read = k2_sata_tf_read, 345 .sff_check_status = k2_stat_check_status, 346 .check_atapi_dma = k2_sata_check_atapi_dma, 347 .bmdma_setup = k2_bmdma_setup_mmio, 348 .bmdma_start = k2_bmdma_start_mmio, 349 .scr_read = k2_sata_scr_read, 350 .scr_write = k2_sata_scr_write, 351 }; 352 353 static const struct ata_port_info k2_port_info[] = { 354 /* chip_svw4 */ 355 { 356 .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA, 357 .pio_mask = ATA_PIO4, 358 .mwdma_mask = ATA_MWDMA2, 359 .udma_mask = ATA_UDMA6, 360 .port_ops = &k2_sata_ops, 361 }, 362 /* chip_svw8 */ 363 { 364 .flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA | 365 K2_FLAG_SATA_8_PORTS, 366 .pio_mask = ATA_PIO4, 367 .mwdma_mask = ATA_MWDMA2, 368 .udma_mask = ATA_UDMA6, 369 .port_ops = &k2_sata_ops, 370 }, 371 /* chip_svw42 */ 372 { 373 .flags = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3, 374 .pio_mask = ATA_PIO4, 375 .mwdma_mask = ATA_MWDMA2, 376 .udma_mask = ATA_UDMA6, 377 .port_ops = &k2_sata_ops, 378 }, 379 /* chip_svw43 */ 380 { 381 .flags = ATA_FLAG_SATA, 382 .pio_mask = ATA_PIO4, 383 .mwdma_mask = ATA_MWDMA2, 384 .udma_mask = ATA_UDMA6, 385 .port_ops = &k2_sata_ops, 386 }, 387 }; 388 389 static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) 390 { 391 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; 392 port->data_addr = base + K2_SATA_TF_DATA_OFFSET; 393 port->feature_addr = 394 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; 395 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; 396 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; 397 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; 398 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; 399 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; 400 port->command_addr = 401 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; 402 port->altstatus_addr = 403 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; 404 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; 405 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; 406 } 407 408 409 static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 410 { 411 const struct ata_port_info *ppi[] = 412 { &k2_port_info[ent->driver_data], NULL }; 413 struct ata_host *host; 414 void __iomem *mmio_base; 415 int n_ports, i, rc, bar_pos; 416 417 ata_print_version_once(&pdev->dev, DRV_VERSION); 418 419 /* allocate host */ 420 n_ports = 4; 421 if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS) 422 n_ports = 8; 423 424 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 425 if (!host) 426 return -ENOMEM; 427 428 bar_pos = 5; 429 if (ppi[0]->flags & K2_FLAG_BAR_POS_3) 430 bar_pos = 3; 431 /* 432 * If this driver happens to only be useful on Apple's K2, then 433 * we should check that here as it has a normal Serverworks ID 434 */ 435 rc = pcim_enable_device(pdev); 436 if (rc) 437 return rc; 438 439 /* 440 * Check if we have resources mapped at all (second function may 441 * have been disabled by firmware) 442 */ 443 if (pci_resource_len(pdev, bar_pos) == 0) { 444 /* In IDE mode we need to pin the device to ensure that 445 pcim_release does not clear the busmaster bit in config 446 space, clearing causes busmaster DMA to fail on 447 ports 3 & 4 */ 448 pcim_pin_device(pdev); 449 return -ENODEV; 450 } 451 452 /* Request and iomap PCI regions */ 453 rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME); 454 if (rc == -EBUSY) 455 pcim_pin_device(pdev); 456 if (rc) 457 return rc; 458 host->iomap = pcim_iomap_table(pdev); 459 mmio_base = host->iomap[bar_pos]; 460 461 /* different controllers have different number of ports - currently 4 or 8 */ 462 /* All ports are on the same function. Multi-function device is no 463 * longer available. This should not be seen in any system. */ 464 for (i = 0; i < host->n_ports; i++) { 465 struct ata_port *ap = host->ports[i]; 466 unsigned int offset = i * K2_SATA_PORT_OFFSET; 467 468 k2_sata_setup_port(&ap->ioaddr, mmio_base + offset); 469 470 ata_port_pbar_desc(ap, 5, -1, "mmio"); 471 ata_port_pbar_desc(ap, 5, offset, "port"); 472 } 473 474 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); 475 if (rc) 476 return rc; 477 478 /* Clear a magic bit in SCR1 according to Darwin, those help 479 * some funky seagate drives (though so far, those were already 480 * set by the firmware on the machines I had access to) 481 */ 482 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, 483 mmio_base + K2_SATA_SICR1_OFFSET); 484 485 /* Clear SATA error & interrupts we don't use */ 486 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); 487 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); 488 489 pci_set_master(pdev); 490 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 491 IRQF_SHARED, &k2_sata_sht); 492 } 493 494 /* 0x240 is device ID for Apple K2 device 495 * 0x241 is device ID for Serverworks Frodo4 496 * 0x242 is device ID for Serverworks Frodo8 497 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA 498 * controller 499 * */ 500 static const struct pci_device_id k2_sata_pci_tbl[] = { 501 { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 }, 502 { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 }, 503 { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 }, 504 { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 }, 505 { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 }, 506 { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 }, 507 { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 }, 508 509 { } 510 }; 511 512 static struct pci_driver k2_sata_pci_driver = { 513 .name = DRV_NAME, 514 .id_table = k2_sata_pci_tbl, 515 .probe = k2_sata_init_one, 516 .remove = ata_pci_remove_one, 517 }; 518 519 module_pci_driver(k2_sata_pci_driver); 520 521 MODULE_AUTHOR("Benjamin Herrenschmidt"); 522 MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); 523 MODULE_LICENSE("GPL"); 524 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); 525 MODULE_VERSION(DRV_VERSION); 526