1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * sata_sis.c - Silicon Integrated Systems SATA 4 * 5 * Maintained by: Uwe Koziolek 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004 Uwe Koziolek 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * Hardware documentation available under NDA. 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/blkdev.h> 21 #include <linux/delay.h> 22 #include <linux/interrupt.h> 23 #include <linux/device.h> 24 #include <scsi/scsi_host.h> 25 #include <linux/libata.h> 26 #include "sis.h" 27 28 #define DRV_NAME "sata_sis" 29 #define DRV_VERSION "1.0" 30 31 enum { 32 sis_180 = 0, 33 SIS_SCR_PCI_BAR = 5, 34 35 /* PCI configuration registers */ 36 SIS_GENCTL = 0x54, /* IDE General Control register */ 37 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ 38 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ 39 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ 40 SIS_PMR = 0x90, /* port mapping register */ 41 SIS_PMR_COMBINED = 0x30, 42 43 /* random bits */ 44 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ 45 46 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ 47 }; 48 49 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 50 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 51 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 52 53 static const struct pci_device_id sis_pci_tbl[] = { 54 { 55 /* SiS 964/180 */ 56 PCI_VDEVICE(SI, 0x0180), 57 .driver_data = sis_180, 58 }, { 59 /* SiS 964/180 */ 60 PCI_VDEVICE(SI, 0x0181), 61 .driver_data = sis_180, 62 }, { 63 /* SiS 965/965L */ 64 PCI_VDEVICE(SI, 0x0182), 65 .driver_data = sis_180, 66 }, { 67 /* SiS 965/965L */ 68 PCI_VDEVICE(SI, 0x0183), 69 .driver_data = sis_180, 70 }, { 71 /* SiS 966/680 */ 72 PCI_VDEVICE(SI, 0x1182), 73 .driver_data = sis_180, 74 }, { 75 /* SiS 966/966L/968/680 */ 76 PCI_VDEVICE(SI, 0x1183), 77 .driver_data = sis_180, 78 }, 79 { } /* terminate list */ 80 }; 81 82 static struct pci_driver sis_pci_driver = { 83 .name = DRV_NAME, 84 .id_table = sis_pci_tbl, 85 .probe = sis_init_one, 86 .remove = ata_pci_remove_one, 87 #ifdef CONFIG_PM_SLEEP 88 .suspend = ata_pci_device_suspend, 89 .resume = ata_pci_device_resume, 90 #endif 91 }; 92 93 static const struct scsi_host_template sis_sht = { 94 ATA_BMDMA_SHT(DRV_NAME), 95 }; 96 97 static struct ata_port_operations sis_ops = { 98 .inherits = &ata_bmdma_port_ops, 99 .scr_read = sis_scr_read, 100 .scr_write = sis_scr_write, 101 }; 102 103 static const struct ata_port_info sis_port_info = { 104 .flags = ATA_FLAG_SATA, 105 .pio_mask = ATA_PIO4, 106 .mwdma_mask = ATA_MWDMA2, 107 .udma_mask = ATA_UDMA6, 108 .port_ops = &sis_ops, 109 }; 110 111 MODULE_AUTHOR("Uwe Koziolek"); 112 MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller"); 113 MODULE_LICENSE("GPL"); 114 MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 115 MODULE_VERSION(DRV_VERSION); 116 117 static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg) 118 { 119 struct ata_port *ap = link->ap; 120 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 121 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); 122 u8 pmr; 123 124 if (ap->port_no) { 125 switch (pdev->device) { 126 case 0x0180: 127 case 0x0181: 128 pci_read_config_byte(pdev, SIS_PMR, &pmr); 129 if ((pmr & SIS_PMR_COMBINED) == 0) 130 addr += SIS180_SATA1_OFS; 131 break; 132 133 case 0x0182: 134 case 0x0183: 135 case 0x1182: 136 addr += SIS182_SATA1_OFS; 137 break; 138 } 139 } 140 if (link->pmp) 141 addr += 0x10; 142 143 return addr; 144 } 145 146 static u32 sis_scr_cfg_read(struct ata_link *link, 147 unsigned int sc_reg, u32 *val) 148 { 149 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); 150 unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); 151 152 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ 153 return -EINVAL; 154 155 pci_read_config_dword(pdev, cfg_addr, val); 156 return 0; 157 } 158 159 static int sis_scr_cfg_write(struct ata_link *link, 160 unsigned int sc_reg, u32 val) 161 { 162 struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); 163 unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg); 164 165 pci_write_config_dword(pdev, cfg_addr, val); 166 return 0; 167 } 168 169 static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 170 { 171 struct ata_port *ap = link->ap; 172 void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; 173 174 if (sc_reg > SCR_CONTROL) 175 return -EINVAL; 176 177 if (ap->flags & SIS_FLAG_CFGSCR) 178 return sis_scr_cfg_read(link, sc_reg, val); 179 180 *val = ioread32(base + sc_reg * 4); 181 return 0; 182 } 183 184 static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 185 { 186 struct ata_port *ap = link->ap; 187 void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10; 188 189 if (sc_reg > SCR_CONTROL) 190 return -EINVAL; 191 192 if (ap->flags & SIS_FLAG_CFGSCR) 193 return sis_scr_cfg_write(link, sc_reg, val); 194 195 iowrite32(val, base + (sc_reg * 4)); 196 return 0; 197 } 198 199 static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 200 { 201 struct ata_port_info pi = sis_port_info; 202 const struct ata_port_info *ppi[] = { &pi, &pi }; 203 struct ata_host *host; 204 u32 genctl, val; 205 u8 pmr; 206 u8 port2_start = 0x20; 207 int i, rc; 208 209 ata_print_version_once(&pdev->dev, DRV_VERSION); 210 211 rc = pcim_enable_device(pdev); 212 if (rc) 213 return rc; 214 215 /* check and see if the SCRs are in IO space or PCI cfg space */ 216 pci_read_config_dword(pdev, SIS_GENCTL, &genctl); 217 if ((genctl & GENCTL_IOMAPPED_SCR) == 0) 218 pi.flags |= SIS_FLAG_CFGSCR; 219 220 /* if hardware thinks SCRs are in IO space, but there are 221 * no IO resources assigned, change to PCI cfg space. 222 */ 223 if ((!(pi.flags & SIS_FLAG_CFGSCR)) && 224 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || 225 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { 226 genctl &= ~GENCTL_IOMAPPED_SCR; 227 pci_write_config_dword(pdev, SIS_GENCTL, genctl); 228 pi.flags |= SIS_FLAG_CFGSCR; 229 } 230 231 pci_read_config_byte(pdev, SIS_PMR, &pmr); 232 switch (ent->device) { 233 case 0x0180: 234 case 0x0181: 235 236 /* The PATA-handling is provided by pata_sis */ 237 switch (pmr & 0x30) { 238 case 0x10: 239 ppi[1] = &sis_info133_for_sata; 240 break; 241 242 case 0x30: 243 ppi[0] = &sis_info133_for_sata; 244 break; 245 } 246 if ((pmr & SIS_PMR_COMBINED) == 0) { 247 dev_info(&pdev->dev, 248 "Detected SiS 180/181/964 chipset in SATA mode\n"); 249 port2_start = 64; 250 } else { 251 dev_info(&pdev->dev, 252 "Detected SiS 180/181 chipset in combined mode\n"); 253 port2_start = 0; 254 pi.flags |= ATA_FLAG_SLAVE_POSS; 255 } 256 break; 257 258 case 0x0182: 259 case 0x0183: 260 pci_read_config_dword(pdev, 0x6C, &val); 261 if (val & (1L << 31)) { 262 dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n"); 263 pi.flags |= ATA_FLAG_SLAVE_POSS; 264 } else { 265 dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n"); 266 } 267 break; 268 269 case 0x1182: 270 dev_info(&pdev->dev, 271 "Detected SiS 1182/966/680 SATA controller\n"); 272 pi.flags |= ATA_FLAG_SLAVE_POSS; 273 break; 274 275 case 0x1183: 276 dev_info(&pdev->dev, 277 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n"); 278 ppi[0] = &sis_info133_for_sata; 279 ppi[1] = &sis_info133_for_sata; 280 break; 281 } 282 283 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); 284 if (rc) 285 return rc; 286 287 for (i = 0; i < 2; i++) { 288 struct ata_port *ap = host->ports[i]; 289 290 if (ap->flags & ATA_FLAG_SATA && 291 ap->flags & ATA_FLAG_SLAVE_POSS) { 292 rc = ata_slave_link_init(ap); 293 if (rc) 294 return rc; 295 } 296 } 297 298 if (!(pi.flags & SIS_FLAG_CFGSCR)) { 299 void __iomem *mmio; 300 301 rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME); 302 if (rc) 303 return rc; 304 mmio = host->iomap[SIS_SCR_PCI_BAR]; 305 306 host->ports[0]->ioaddr.scr_addr = mmio; 307 host->ports[1]->ioaddr.scr_addr = mmio + port2_start; 308 } 309 310 pci_set_master(pdev); 311 pcim_intx(pdev, 1); 312 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 313 IRQF_SHARED, &sis_sht); 314 } 315 316 module_pci_driver(sis_pci_driver); 317