1 /* 2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers 3 * 4 * Copyright 2005 Tejun Heo 5 * 6 * Based on preview driver from Silicon Image. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/device.h> 28 #include <scsi/scsi_host.h> 29 #include <scsi/scsi_cmnd.h> 30 #include <linux/libata.h> 31 32 #define DRV_NAME "sata_sil24" 33 #define DRV_VERSION "0.8" 34 35 /* 36 * Port request block (PRB) 32 bytes 37 */ 38 struct sil24_prb { 39 __le16 ctrl; 40 __le16 prot; 41 __le32 rx_cnt; 42 u8 fis[6 * 4]; 43 }; 44 45 /* 46 * Scatter gather entry (SGE) 16 bytes 47 */ 48 struct sil24_sge { 49 __le64 addr; 50 __le32 cnt; 51 __le32 flags; 52 }; 53 54 /* 55 * Port multiplier 56 */ 57 struct sil24_port_multiplier { 58 __le32 diag; 59 __le32 sactive; 60 }; 61 62 enum { 63 SIL24_HOST_BAR = 0, 64 SIL24_PORT_BAR = 2, 65 66 /* 67 * Global controller registers (128 bytes @ BAR0) 68 */ 69 /* 32 bit regs */ 70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ 71 HOST_CTRL = 0x40, 72 HOST_IRQ_STAT = 0x44, 73 HOST_PHY_CFG = 0x48, 74 HOST_BIST_CTRL = 0x50, 75 HOST_BIST_PTRN = 0x54, 76 HOST_BIST_STAT = 0x58, 77 HOST_MEM_BIST_STAT = 0x5c, 78 HOST_FLASH_CMD = 0x70, 79 /* 8 bit regs */ 80 HOST_FLASH_DATA = 0x74, 81 HOST_TRANSITION_DETECT = 0x75, 82 HOST_GPIO_CTRL = 0x76, 83 HOST_I2C_ADDR = 0x78, /* 32 bit */ 84 HOST_I2C_DATA = 0x7c, 85 HOST_I2C_XFER_CNT = 0x7e, 86 HOST_I2C_CTRL = 0x7f, 87 88 /* HOST_SLOT_STAT bits */ 89 HOST_SSTAT_ATTN = (1 << 31), 90 91 /* HOST_CTRL bits */ 92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ 93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ 94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ 95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ 96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ 97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ 98 99 /* 100 * Port registers 101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) 102 */ 103 PORT_REGS_SIZE = 0x2000, 104 105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ 106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 107 108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ 109 PORT_PMP_STATUS = 0x0000, /* port device status offset */ 110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ 111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ 112 113 /* 32 bit regs */ 114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ 117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ 118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ 119 PORT_ACTIVATE_UPPER_ADDR= 0x101c, 120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ 121 PORT_CMD_ERR = 0x1024, /* command error number */ 122 PORT_FIS_CFG = 0x1028, 123 PORT_FIFO_THRES = 0x102c, 124 /* 16 bit regs */ 125 PORT_DECODE_ERR_CNT = 0x1040, 126 PORT_DECODE_ERR_THRESH = 0x1042, 127 PORT_CRC_ERR_CNT = 0x1044, 128 PORT_CRC_ERR_THRESH = 0x1046, 129 PORT_HSHK_ERR_CNT = 0x1048, 130 PORT_HSHK_ERR_THRESH = 0x104a, 131 /* 32 bit regs */ 132 PORT_PHY_CFG = 0x1050, 133 PORT_SLOT_STAT = 0x1800, 134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ 135 PORT_CONTEXT = 0x1e04, 136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ 137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ 138 PORT_SCONTROL = 0x1f00, 139 PORT_SSTATUS = 0x1f04, 140 PORT_SERROR = 0x1f08, 141 PORT_SACTIVE = 0x1f0c, 142 143 /* PORT_CTRL_STAT bits */ 144 PORT_CS_PORT_RST = (1 << 0), /* port reset */ 145 PORT_CS_DEV_RST = (1 << 1), /* device reset */ 146 PORT_CS_INIT = (1 << 2), /* port initialize */ 147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ 150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ 152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 153 154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 155 /* bits[11:0] are masked */ 156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ 157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */ 158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ 159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ 160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ 161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ 162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ 163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ 164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ 165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ 166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ 167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ 168 169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | 170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | 171 PORT_IRQ_UNK_FIS, 172 173 /* bits[27:16] are unmasked (raw) */ 174 PORT_IRQ_RAW_SHIFT = 16, 175 PORT_IRQ_MASKED_MASK = 0x7ff, 176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), 177 178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ 179 PORT_IRQ_STEER_SHIFT = 30, 180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), 181 182 /* PORT_CMD_ERR constants */ 183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ 184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ 185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ 186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ 187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ 188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ 189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ 190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ 191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ 192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ 193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ 194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ 195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ 196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ 197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ 198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ 199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ 200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ 201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ 202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ 203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ 204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ 205 206 /* bits of PRB control field */ 207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ 208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ 209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ 210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ 211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ 212 213 /* PRB protocol field */ 214 PRB_PROT_PACKET = (1 << 0), 215 PRB_PROT_TCQ = (1 << 1), 216 PRB_PROT_NCQ = (1 << 2), 217 PRB_PROT_READ = (1 << 3), 218 PRB_PROT_WRITE = (1 << 4), 219 PRB_PROT_TRANSPARENT = (1 << 5), 220 221 /* 222 * Other constants 223 */ 224 SGE_TRM = (1 << 31), /* Last SGE in chain */ 225 SGE_LNK = (1 << 30), /* linked list 226 Points to SGT, not SGE */ 227 SGE_DRD = (1 << 29), /* discard data read (/dev/null) 228 data address ignored */ 229 230 SIL24_MAX_CMDS = 31, 231 232 /* board id */ 233 BID_SIL3124 = 0, 234 BID_SIL3132 = 1, 235 BID_SIL3131 = 2, 236 237 /* host flags */ 238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 240 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY, 241 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ 242 243 IRQ_STAT_4PORTS = 0xf, 244 }; 245 246 struct sil24_ata_block { 247 struct sil24_prb prb; 248 struct sil24_sge sge[LIBATA_MAX_PRD]; 249 }; 250 251 struct sil24_atapi_block { 252 struct sil24_prb prb; 253 u8 cdb[16]; 254 struct sil24_sge sge[LIBATA_MAX_PRD - 1]; 255 }; 256 257 union sil24_cmd_block { 258 struct sil24_ata_block ata; 259 struct sil24_atapi_block atapi; 260 }; 261 262 static struct sil24_cerr_info { 263 unsigned int err_mask, action; 264 const char *desc; 265 } sil24_cerr_db[] = { 266 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 267 "device error" }, 268 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 269 "device error via D2H FIS" }, 270 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 271 "device error via SDB FIS" }, 272 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 273 "error in data FIS" }, 274 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 275 "failed to transmit command FIS" }, 276 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 277 "protocol mismatch" }, 278 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 279 "data directon mismatch" }, 280 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 281 "ran out of SGEs while writing" }, 282 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 283 "ran out of SGEs while reading" }, 284 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 285 "invalid data directon for ATAPI CDB" }, 286 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 287 "SGT no on qword boundary" }, 288 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 289 "PCI target abort while fetching SGT" }, 290 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 291 "PCI master abort while fetching SGT" }, 292 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 293 "PCI parity error while fetching SGT" }, 294 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 295 "PRB not on qword boundary" }, 296 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 297 "PCI target abort while fetching PRB" }, 298 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 299 "PCI master abort while fetching PRB" }, 300 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 301 "PCI parity error while fetching PRB" }, 302 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 303 "undefined error while transferring data" }, 304 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 305 "PCI target abort while transferring data" }, 306 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 307 "PCI master abort while transferring data" }, 308 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 309 "PCI parity error while transferring data" }, 310 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 311 "FIS received while sending service FIS" }, 312 }; 313 314 /* 315 * ap->private_data 316 * 317 * The preview driver always returned 0 for status. We emulate it 318 * here from the previous interrupt. 319 */ 320 struct sil24_port_priv { 321 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ 322 dma_addr_t cmd_block_dma; /* DMA base addr for them */ 323 struct ata_taskfile tf; /* Cached taskfile registers */ 324 }; 325 326 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); 327 static u8 sil24_check_status(struct ata_port *ap); 328 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); 329 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); 330 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); 331 static void sil24_qc_prep(struct ata_queued_cmd *qc); 332 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); 333 static void sil24_irq_clear(struct ata_port *ap); 334 static irqreturn_t sil24_interrupt(int irq, void *dev_instance); 335 static void sil24_freeze(struct ata_port *ap); 336 static void sil24_thaw(struct ata_port *ap); 337 static void sil24_error_handler(struct ata_port *ap); 338 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); 339 static int sil24_port_start(struct ata_port *ap); 340 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 341 #ifdef CONFIG_PM 342 static int sil24_pci_device_resume(struct pci_dev *pdev); 343 #endif 344 345 static const struct pci_device_id sil24_pci_tbl[] = { 346 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, 347 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, 348 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, 349 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, 350 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, 351 352 { } /* terminate list */ 353 }; 354 355 static struct pci_driver sil24_pci_driver = { 356 .name = DRV_NAME, 357 .id_table = sil24_pci_tbl, 358 .probe = sil24_init_one, 359 .remove = ata_pci_remove_one, 360 #ifdef CONFIG_PM 361 .suspend = ata_pci_device_suspend, 362 .resume = sil24_pci_device_resume, 363 #endif 364 }; 365 366 static struct scsi_host_template sil24_sht = { 367 .module = THIS_MODULE, 368 .name = DRV_NAME, 369 .ioctl = ata_scsi_ioctl, 370 .queuecommand = ata_scsi_queuecmd, 371 .change_queue_depth = ata_scsi_change_queue_depth, 372 .can_queue = SIL24_MAX_CMDS, 373 .this_id = ATA_SHT_THIS_ID, 374 .sg_tablesize = LIBATA_MAX_PRD, 375 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 376 .emulated = ATA_SHT_EMULATED, 377 .use_clustering = ATA_SHT_USE_CLUSTERING, 378 .proc_name = DRV_NAME, 379 .dma_boundary = ATA_DMA_BOUNDARY, 380 .slave_configure = ata_scsi_slave_config, 381 .slave_destroy = ata_scsi_slave_destroy, 382 .bios_param = ata_std_bios_param, 383 #ifdef CONFIG_PM 384 .suspend = ata_scsi_device_suspend, 385 .resume = ata_scsi_device_resume, 386 #endif 387 }; 388 389 static const struct ata_port_operations sil24_ops = { 390 .port_disable = ata_port_disable, 391 392 .dev_config = sil24_dev_config, 393 394 .check_status = sil24_check_status, 395 .check_altstatus = sil24_check_status, 396 .dev_select = ata_noop_dev_select, 397 398 .tf_read = sil24_tf_read, 399 400 .qc_prep = sil24_qc_prep, 401 .qc_issue = sil24_qc_issue, 402 403 .irq_handler = sil24_interrupt, 404 .irq_clear = sil24_irq_clear, 405 .irq_on = ata_dummy_irq_on, 406 .irq_ack = ata_dummy_irq_ack, 407 408 .scr_read = sil24_scr_read, 409 .scr_write = sil24_scr_write, 410 411 .freeze = sil24_freeze, 412 .thaw = sil24_thaw, 413 .error_handler = sil24_error_handler, 414 .post_internal_cmd = sil24_post_internal_cmd, 415 416 .port_start = sil24_port_start, 417 }; 418 419 /* 420 * Use bits 30-31 of port_flags to encode available port numbers. 421 * Current maxium is 4. 422 */ 423 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) 424 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) 425 426 static struct ata_port_info sil24_port_info[] = { 427 /* sil_3124 */ 428 { 429 .sht = &sil24_sht, 430 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | 431 SIL24_FLAG_PCIX_IRQ_WOC, 432 .pio_mask = 0x1f, /* pio0-4 */ 433 .mwdma_mask = 0x07, /* mwdma0-2 */ 434 .udma_mask = 0x3f, /* udma0-5 */ 435 .port_ops = &sil24_ops, 436 }, 437 /* sil_3132 */ 438 { 439 .sht = &sil24_sht, 440 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), 441 .pio_mask = 0x1f, /* pio0-4 */ 442 .mwdma_mask = 0x07, /* mwdma0-2 */ 443 .udma_mask = 0x3f, /* udma0-5 */ 444 .port_ops = &sil24_ops, 445 }, 446 /* sil_3131/sil_3531 */ 447 { 448 .sht = &sil24_sht, 449 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), 450 .pio_mask = 0x1f, /* pio0-4 */ 451 .mwdma_mask = 0x07, /* mwdma0-2 */ 452 .udma_mask = 0x3f, /* udma0-5 */ 453 .port_ops = &sil24_ops, 454 }, 455 }; 456 457 static int sil24_tag(int tag) 458 { 459 if (unlikely(ata_tag_internal(tag))) 460 return 0; 461 return tag; 462 } 463 464 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) 465 { 466 void __iomem *port = ap->ioaddr.cmd_addr; 467 468 if (dev->cdb_len == 16) 469 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); 470 else 471 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); 472 } 473 474 static inline void sil24_update_tf(struct ata_port *ap) 475 { 476 struct sil24_port_priv *pp = ap->private_data; 477 void __iomem *port = ap->ioaddr.cmd_addr; 478 struct sil24_prb __iomem *prb = port; 479 u8 fis[6 * 4]; 480 481 memcpy_fromio(fis, prb->fis, 6 * 4); 482 ata_tf_from_fis(fis, &pp->tf); 483 } 484 485 static u8 sil24_check_status(struct ata_port *ap) 486 { 487 struct sil24_port_priv *pp = ap->private_data; 488 return pp->tf.command; 489 } 490 491 static int sil24_scr_map[] = { 492 [SCR_CONTROL] = 0, 493 [SCR_STATUS] = 1, 494 [SCR_ERROR] = 2, 495 [SCR_ACTIVE] = 3, 496 }; 497 498 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) 499 { 500 void __iomem *scr_addr = ap->ioaddr.scr_addr; 501 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 502 void __iomem *addr; 503 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 504 return readl(scr_addr + sil24_scr_map[sc_reg] * 4); 505 } 506 return 0xffffffffU; 507 } 508 509 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) 510 { 511 void __iomem *scr_addr = ap->ioaddr.scr_addr; 512 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 513 void __iomem *addr; 514 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 515 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); 516 } 517 } 518 519 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 520 { 521 struct sil24_port_priv *pp = ap->private_data; 522 *tf = pp->tf; 523 } 524 525 static int sil24_init_port(struct ata_port *ap) 526 { 527 void __iomem *port = ap->ioaddr.cmd_addr; 528 u32 tmp; 529 530 writel(PORT_CS_INIT, port + PORT_CTRL_STAT); 531 ata_wait_register(port + PORT_CTRL_STAT, 532 PORT_CS_INIT, PORT_CS_INIT, 10, 100); 533 tmp = ata_wait_register(port + PORT_CTRL_STAT, 534 PORT_CS_RDY, 0, 10, 100); 535 536 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) 537 return -EIO; 538 return 0; 539 } 540 541 static int sil24_softreset(struct ata_port *ap, unsigned int *class) 542 { 543 void __iomem *port = ap->ioaddr.cmd_addr; 544 struct sil24_port_priv *pp = ap->private_data; 545 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; 546 dma_addr_t paddr = pp->cmd_block_dma; 547 u32 mask, irq_stat; 548 const char *reason; 549 550 DPRINTK("ENTER\n"); 551 552 if (ata_port_offline(ap)) { 553 DPRINTK("PHY reports no device\n"); 554 *class = ATA_DEV_NONE; 555 goto out; 556 } 557 558 /* put the port into known state */ 559 if (sil24_init_port(ap)) { 560 reason ="port not ready"; 561 goto err; 562 } 563 564 /* do SRST */ 565 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST); 566 prb->fis[1] = 0; /* no PMP yet */ 567 568 writel((u32)paddr, port + PORT_CMD_ACTIVATE); 569 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); 570 571 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; 572 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0, 573 100, ATA_TMOUT_BOOT / HZ * 1000); 574 575 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */ 576 irq_stat >>= PORT_IRQ_RAW_SHIFT; 577 578 if (!(irq_stat & PORT_IRQ_COMPLETE)) { 579 if (irq_stat & PORT_IRQ_ERROR) 580 reason = "SRST command error"; 581 else 582 reason = "timeout"; 583 goto err; 584 } 585 586 sil24_update_tf(ap); 587 *class = ata_dev_classify(&pp->tf); 588 589 if (*class == ATA_DEV_UNKNOWN) 590 *class = ATA_DEV_NONE; 591 592 out: 593 DPRINTK("EXIT, class=%u\n", *class); 594 return 0; 595 596 err: 597 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); 598 return -EIO; 599 } 600 601 static int sil24_hardreset(struct ata_port *ap, unsigned int *class) 602 { 603 void __iomem *port = ap->ioaddr.cmd_addr; 604 const char *reason; 605 int tout_msec, rc; 606 u32 tmp; 607 608 /* sil24 does the right thing(tm) without any protection */ 609 sata_set_spd(ap); 610 611 tout_msec = 100; 612 if (ata_port_online(ap)) 613 tout_msec = 5000; 614 615 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); 616 tmp = ata_wait_register(port + PORT_CTRL_STAT, 617 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec); 618 619 /* SStatus oscillates between zero and valid status after 620 * DEV_RST, debounce it. 621 */ 622 rc = sata_phy_debounce(ap, sata_deb_timing_long); 623 if (rc) { 624 reason = "PHY debouncing failed"; 625 goto err; 626 } 627 628 if (tmp & PORT_CS_DEV_RST) { 629 if (ata_port_offline(ap)) 630 return 0; 631 reason = "link not ready"; 632 goto err; 633 } 634 635 /* Sil24 doesn't store signature FIS after hardreset, so we 636 * can't wait for BSY to clear. Some devices take a long time 637 * to get ready and those devices will choke if we don't wait 638 * for BSY clearance here. Tell libata to perform follow-up 639 * softreset. 640 */ 641 return -EAGAIN; 642 643 err: 644 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason); 645 return -EIO; 646 } 647 648 static inline void sil24_fill_sg(struct ata_queued_cmd *qc, 649 struct sil24_sge *sge) 650 { 651 struct scatterlist *sg; 652 653 ata_for_each_sg(sg, qc) { 654 sge->addr = cpu_to_le64(sg_dma_address(sg)); 655 sge->cnt = cpu_to_le32(sg_dma_len(sg)); 656 if (ata_sg_is_last(sg, qc)) 657 sge->flags = cpu_to_le32(SGE_TRM); 658 else 659 sge->flags = 0; 660 sge++; 661 } 662 } 663 664 static void sil24_qc_prep(struct ata_queued_cmd *qc) 665 { 666 struct ata_port *ap = qc->ap; 667 struct sil24_port_priv *pp = ap->private_data; 668 union sil24_cmd_block *cb; 669 struct sil24_prb *prb; 670 struct sil24_sge *sge; 671 u16 ctrl = 0; 672 673 cb = &pp->cmd_block[sil24_tag(qc->tag)]; 674 675 switch (qc->tf.protocol) { 676 case ATA_PROT_PIO: 677 case ATA_PROT_DMA: 678 case ATA_PROT_NCQ: 679 case ATA_PROT_NODATA: 680 prb = &cb->ata.prb; 681 sge = cb->ata.sge; 682 break; 683 684 case ATA_PROT_ATAPI: 685 case ATA_PROT_ATAPI_DMA: 686 case ATA_PROT_ATAPI_NODATA: 687 prb = &cb->atapi.prb; 688 sge = cb->atapi.sge; 689 memset(cb->atapi.cdb, 0, 32); 690 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); 691 692 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { 693 if (qc->tf.flags & ATA_TFLAG_WRITE) 694 ctrl = PRB_CTRL_PACKET_WRITE; 695 else 696 ctrl = PRB_CTRL_PACKET_READ; 697 } 698 break; 699 700 default: 701 prb = NULL; /* shut up, gcc */ 702 sge = NULL; 703 BUG(); 704 } 705 706 prb->ctrl = cpu_to_le16(ctrl); 707 ata_tf_to_fis(&qc->tf, prb->fis, 0); 708 709 if (qc->flags & ATA_QCFLAG_DMAMAP) 710 sil24_fill_sg(qc, sge); 711 } 712 713 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) 714 { 715 struct ata_port *ap = qc->ap; 716 struct sil24_port_priv *pp = ap->private_data; 717 void __iomem *port = ap->ioaddr.cmd_addr; 718 unsigned int tag = sil24_tag(qc->tag); 719 dma_addr_t paddr; 720 void __iomem *activate; 721 722 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); 723 activate = port + PORT_CMD_ACTIVATE + tag * 8; 724 725 writel((u32)paddr, activate); 726 writel((u64)paddr >> 32, activate + 4); 727 728 return 0; 729 } 730 731 static void sil24_irq_clear(struct ata_port *ap) 732 { 733 /* unused */ 734 } 735 736 static void sil24_freeze(struct ata_port *ap) 737 { 738 void __iomem *port = ap->ioaddr.cmd_addr; 739 740 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear 741 * PORT_IRQ_ENABLE instead. 742 */ 743 writel(0xffff, port + PORT_IRQ_ENABLE_CLR); 744 } 745 746 static void sil24_thaw(struct ata_port *ap) 747 { 748 void __iomem *port = ap->ioaddr.cmd_addr; 749 u32 tmp; 750 751 /* clear IRQ */ 752 tmp = readl(port + PORT_IRQ_STAT); 753 writel(tmp, port + PORT_IRQ_STAT); 754 755 /* turn IRQ back on */ 756 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); 757 } 758 759 static void sil24_error_intr(struct ata_port *ap) 760 { 761 void __iomem *port = ap->ioaddr.cmd_addr; 762 struct ata_eh_info *ehi = &ap->eh_info; 763 int freeze = 0; 764 u32 irq_stat; 765 766 /* on error, we need to clear IRQ explicitly */ 767 irq_stat = readl(port + PORT_IRQ_STAT); 768 writel(irq_stat, port + PORT_IRQ_STAT); 769 770 /* first, analyze and record host port events */ 771 ata_ehi_clear_desc(ehi); 772 773 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); 774 775 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { 776 ata_ehi_hotplugged(ehi); 777 ata_ehi_push_desc(ehi, ", %s", 778 irq_stat & PORT_IRQ_PHYRDY_CHG ? 779 "PHY RDY changed" : "device exchanged"); 780 freeze = 1; 781 } 782 783 if (irq_stat & PORT_IRQ_UNK_FIS) { 784 ehi->err_mask |= AC_ERR_HSM; 785 ehi->action |= ATA_EH_SOFTRESET; 786 ata_ehi_push_desc(ehi , ", unknown FIS"); 787 freeze = 1; 788 } 789 790 /* deal with command error */ 791 if (irq_stat & PORT_IRQ_ERROR) { 792 struct sil24_cerr_info *ci = NULL; 793 unsigned int err_mask = 0, action = 0; 794 struct ata_queued_cmd *qc; 795 u32 cerr; 796 797 /* analyze CMD_ERR */ 798 cerr = readl(port + PORT_CMD_ERR); 799 if (cerr < ARRAY_SIZE(sil24_cerr_db)) 800 ci = &sil24_cerr_db[cerr]; 801 802 if (ci && ci->desc) { 803 err_mask |= ci->err_mask; 804 action |= ci->action; 805 ata_ehi_push_desc(ehi, ", %s", ci->desc); 806 } else { 807 err_mask |= AC_ERR_OTHER; 808 action |= ATA_EH_SOFTRESET; 809 ata_ehi_push_desc(ehi, ", unknown command error %d", 810 cerr); 811 } 812 813 /* record error info */ 814 qc = ata_qc_from_tag(ap, ap->active_tag); 815 if (qc) { 816 sil24_update_tf(ap); 817 qc->err_mask |= err_mask; 818 } else 819 ehi->err_mask |= err_mask; 820 821 ehi->action |= action; 822 } 823 824 /* freeze or abort */ 825 if (freeze) 826 ata_port_freeze(ap); 827 else 828 ata_port_abort(ap); 829 } 830 831 static void sil24_finish_qc(struct ata_queued_cmd *qc) 832 { 833 if (qc->flags & ATA_QCFLAG_RESULT_TF) 834 sil24_update_tf(qc->ap); 835 } 836 837 static inline void sil24_host_intr(struct ata_port *ap) 838 { 839 void __iomem *port = ap->ioaddr.cmd_addr; 840 u32 slot_stat, qc_active; 841 int rc; 842 843 slot_stat = readl(port + PORT_SLOT_STAT); 844 845 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { 846 sil24_error_intr(ap); 847 return; 848 } 849 850 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) 851 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); 852 853 qc_active = slot_stat & ~HOST_SSTAT_ATTN; 854 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc); 855 if (rc > 0) 856 return; 857 if (rc < 0) { 858 struct ata_eh_info *ehi = &ap->eh_info; 859 ehi->err_mask |= AC_ERR_HSM; 860 ehi->action |= ATA_EH_SOFTRESET; 861 ata_port_freeze(ap); 862 return; 863 } 864 865 if (ata_ratelimit()) 866 ata_port_printk(ap, KERN_INFO, "spurious interrupt " 867 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", 868 slot_stat, ap->active_tag, ap->sactive); 869 } 870 871 static irqreturn_t sil24_interrupt(int irq, void *dev_instance) 872 { 873 struct ata_host *host = dev_instance; 874 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 875 unsigned handled = 0; 876 u32 status; 877 int i; 878 879 status = readl(host_base + HOST_IRQ_STAT); 880 881 if (status == 0xffffffff) { 882 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " 883 "PCI fault or device removal?\n"); 884 goto out; 885 } 886 887 if (!(status & IRQ_STAT_4PORTS)) 888 goto out; 889 890 spin_lock(&host->lock); 891 892 for (i = 0; i < host->n_ports; i++) 893 if (status & (1 << i)) { 894 struct ata_port *ap = host->ports[i]; 895 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { 896 sil24_host_intr(host->ports[i]); 897 handled++; 898 } else 899 printk(KERN_ERR DRV_NAME 900 ": interrupt from disabled port %d\n", i); 901 } 902 903 spin_unlock(&host->lock); 904 out: 905 return IRQ_RETVAL(handled); 906 } 907 908 static void sil24_error_handler(struct ata_port *ap) 909 { 910 struct ata_eh_context *ehc = &ap->eh_context; 911 912 if (sil24_init_port(ap)) { 913 ata_eh_freeze_port(ap); 914 ehc->i.action |= ATA_EH_HARDRESET; 915 } 916 917 /* perform recovery */ 918 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset, 919 ata_std_postreset); 920 } 921 922 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) 923 { 924 struct ata_port *ap = qc->ap; 925 926 if (qc->flags & ATA_QCFLAG_FAILED) 927 qc->err_mask |= AC_ERR_OTHER; 928 929 /* make DMA engine forget about the failed command */ 930 if (qc->err_mask) 931 sil24_init_port(ap); 932 } 933 934 static int sil24_port_start(struct ata_port *ap) 935 { 936 struct device *dev = ap->host->dev; 937 struct sil24_port_priv *pp; 938 union sil24_cmd_block *cb; 939 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; 940 dma_addr_t cb_dma; 941 int rc; 942 943 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 944 if (!pp) 945 return -ENOMEM; 946 947 pp->tf.command = ATA_DRDY; 948 949 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); 950 if (!cb) 951 return -ENOMEM; 952 memset(cb, 0, cb_size); 953 954 rc = ata_pad_alloc(ap, dev); 955 if (rc) 956 return rc; 957 958 pp->cmd_block = cb; 959 pp->cmd_block_dma = cb_dma; 960 961 ap->private_data = pp; 962 963 return 0; 964 } 965 966 static void sil24_init_controller(struct pci_dev *pdev, int n_ports, 967 unsigned long port_flags, 968 void __iomem *host_base, 969 void __iomem *port_base) 970 { 971 u32 tmp; 972 int i; 973 974 /* GPIO off */ 975 writel(0, host_base + HOST_FLASH_CMD); 976 977 /* clear global reset & mask interrupts during initialization */ 978 writel(0, host_base + HOST_CTRL); 979 980 /* init ports */ 981 for (i = 0; i < n_ports; i++) { 982 void __iomem *port = port_base + i * PORT_REGS_SIZE; 983 984 /* Initial PHY setting */ 985 writel(0x20c, port + PORT_PHY_CFG); 986 987 /* Clear port RST */ 988 tmp = readl(port + PORT_CTRL_STAT); 989 if (tmp & PORT_CS_PORT_RST) { 990 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); 991 tmp = ata_wait_register(port + PORT_CTRL_STAT, 992 PORT_CS_PORT_RST, 993 PORT_CS_PORT_RST, 10, 100); 994 if (tmp & PORT_CS_PORT_RST) 995 dev_printk(KERN_ERR, &pdev->dev, 996 "failed to clear port RST\n"); 997 } 998 999 /* Configure IRQ WoC */ 1000 if (port_flags & SIL24_FLAG_PCIX_IRQ_WOC) 1001 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); 1002 else 1003 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); 1004 1005 /* Zero error counters. */ 1006 writel(0x8000, port + PORT_DECODE_ERR_THRESH); 1007 writel(0x8000, port + PORT_CRC_ERR_THRESH); 1008 writel(0x8000, port + PORT_HSHK_ERR_THRESH); 1009 writel(0x0000, port + PORT_DECODE_ERR_CNT); 1010 writel(0x0000, port + PORT_CRC_ERR_CNT); 1011 writel(0x0000, port + PORT_HSHK_ERR_CNT); 1012 1013 /* Always use 64bit activation */ 1014 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); 1015 1016 /* Clear port multiplier enable and resume bits */ 1017 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, 1018 port + PORT_CTRL_CLR); 1019 } 1020 1021 /* Turn on interrupts */ 1022 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); 1023 } 1024 1025 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1026 { 1027 static int printed_version = 0; 1028 struct device *dev = &pdev->dev; 1029 unsigned int board_id = (unsigned int)ent->driver_data; 1030 struct ata_port_info *pinfo = &sil24_port_info[board_id]; 1031 struct ata_probe_ent *probe_ent; 1032 void __iomem *host_base; 1033 void __iomem *port_base; 1034 int i, rc; 1035 u32 tmp; 1036 1037 if (!printed_version++) 1038 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1039 1040 rc = pcim_enable_device(pdev); 1041 if (rc) 1042 return rc; 1043 1044 rc = pcim_iomap_regions(pdev, 1045 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), 1046 DRV_NAME); 1047 if (rc) 1048 return rc; 1049 1050 /* allocate & init probe_ent */ 1051 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); 1052 if (!probe_ent) 1053 return -ENOMEM; 1054 1055 probe_ent->dev = pci_dev_to_dev(pdev); 1056 INIT_LIST_HEAD(&probe_ent->node); 1057 1058 probe_ent->sht = pinfo->sht; 1059 probe_ent->port_flags = pinfo->flags; 1060 probe_ent->pio_mask = pinfo->pio_mask; 1061 probe_ent->mwdma_mask = pinfo->mwdma_mask; 1062 probe_ent->udma_mask = pinfo->udma_mask; 1063 probe_ent->port_ops = pinfo->port_ops; 1064 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->flags); 1065 1066 probe_ent->irq = pdev->irq; 1067 probe_ent->irq_flags = IRQF_SHARED; 1068 probe_ent->iomap = pcim_iomap_table(pdev); 1069 1070 host_base = probe_ent->iomap[SIL24_HOST_BAR]; 1071 port_base = probe_ent->iomap[SIL24_PORT_BAR]; 1072 1073 /* 1074 * Configure the device 1075 */ 1076 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 1077 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1078 if (rc) { 1079 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1080 if (rc) { 1081 dev_printk(KERN_ERR, &pdev->dev, 1082 "64-bit DMA enable failed\n"); 1083 return rc; 1084 } 1085 } 1086 } else { 1087 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1088 if (rc) { 1089 dev_printk(KERN_ERR, &pdev->dev, 1090 "32-bit DMA enable failed\n"); 1091 return rc; 1092 } 1093 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1094 if (rc) { 1095 dev_printk(KERN_ERR, &pdev->dev, 1096 "32-bit consistent DMA enable failed\n"); 1097 return rc; 1098 } 1099 } 1100 1101 /* Apply workaround for completion IRQ loss on PCI-X errata */ 1102 if (probe_ent->port_flags & SIL24_FLAG_PCIX_IRQ_WOC) { 1103 tmp = readl(host_base + HOST_CTRL); 1104 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) 1105 dev_printk(KERN_INFO, &pdev->dev, 1106 "Applying completion IRQ loss on PCI-X " 1107 "errata fix\n"); 1108 else 1109 probe_ent->port_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; 1110 } 1111 1112 for (i = 0; i < probe_ent->n_ports; i++) { 1113 void __iomem *port = port_base + i * PORT_REGS_SIZE; 1114 1115 probe_ent->port[i].cmd_addr = port; 1116 probe_ent->port[i].scr_addr = port + PORT_SCONTROL; 1117 1118 ata_std_ports(&probe_ent->port[i]); 1119 } 1120 1121 sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags, 1122 host_base, port_base); 1123 1124 pci_set_master(pdev); 1125 1126 if (!ata_device_add(probe_ent)) 1127 return -ENODEV; 1128 1129 devm_kfree(dev, probe_ent); 1130 return 0; 1131 } 1132 1133 #ifdef CONFIG_PM 1134 static int sil24_pci_device_resume(struct pci_dev *pdev) 1135 { 1136 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1137 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1138 void __iomem *port_base = host->iomap[SIL24_PORT_BAR]; 1139 int rc; 1140 1141 rc = ata_pci_device_do_resume(pdev); 1142 if (rc) 1143 return rc; 1144 1145 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) 1146 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); 1147 1148 sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags, 1149 host_base, port_base); 1150 1151 ata_host_resume(host); 1152 1153 return 0; 1154 } 1155 #endif 1156 1157 static int __init sil24_init(void) 1158 { 1159 return pci_register_driver(&sil24_pci_driver); 1160 } 1161 1162 static void __exit sil24_exit(void) 1163 { 1164 pci_unregister_driver(&sil24_pci_driver); 1165 } 1166 1167 MODULE_AUTHOR("Tejun Heo"); 1168 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); 1169 MODULE_LICENSE("GPL"); 1170 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); 1171 1172 module_init(sil24_init); 1173 module_exit(sil24_exit); 1174