1 /* 2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers 3 * 4 * Copyright 2005 Tejun Heo 5 * 6 * Based on preview driver from Silicon Image. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/device.h> 28 #include <scsi/scsi_host.h> 29 #include <scsi/scsi_cmnd.h> 30 #include <linux/libata.h> 31 32 #define DRV_NAME "sata_sil24" 33 #define DRV_VERSION "0.8" 34 35 /* 36 * Port request block (PRB) 32 bytes 37 */ 38 struct sil24_prb { 39 __le16 ctrl; 40 __le16 prot; 41 __le32 rx_cnt; 42 u8 fis[6 * 4]; 43 }; 44 45 /* 46 * Scatter gather entry (SGE) 16 bytes 47 */ 48 struct sil24_sge { 49 __le64 addr; 50 __le32 cnt; 51 __le32 flags; 52 }; 53 54 /* 55 * Port multiplier 56 */ 57 struct sil24_port_multiplier { 58 __le32 diag; 59 __le32 sactive; 60 }; 61 62 enum { 63 SIL24_HOST_BAR = 0, 64 SIL24_PORT_BAR = 2, 65 66 /* 67 * Global controller registers (128 bytes @ BAR0) 68 */ 69 /* 32 bit regs */ 70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ 71 HOST_CTRL = 0x40, 72 HOST_IRQ_STAT = 0x44, 73 HOST_PHY_CFG = 0x48, 74 HOST_BIST_CTRL = 0x50, 75 HOST_BIST_PTRN = 0x54, 76 HOST_BIST_STAT = 0x58, 77 HOST_MEM_BIST_STAT = 0x5c, 78 HOST_FLASH_CMD = 0x70, 79 /* 8 bit regs */ 80 HOST_FLASH_DATA = 0x74, 81 HOST_TRANSITION_DETECT = 0x75, 82 HOST_GPIO_CTRL = 0x76, 83 HOST_I2C_ADDR = 0x78, /* 32 bit */ 84 HOST_I2C_DATA = 0x7c, 85 HOST_I2C_XFER_CNT = 0x7e, 86 HOST_I2C_CTRL = 0x7f, 87 88 /* HOST_SLOT_STAT bits */ 89 HOST_SSTAT_ATTN = (1 << 31), 90 91 /* HOST_CTRL bits */ 92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ 93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ 94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ 95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ 96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ 97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ 98 99 /* 100 * Port registers 101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) 102 */ 103 PORT_REGS_SIZE = 0x2000, 104 105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ 106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 107 108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ 109 PORT_PMP_STATUS = 0x0000, /* port device status offset */ 110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ 111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ 112 113 /* 32 bit regs */ 114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ 117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ 118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ 119 PORT_ACTIVATE_UPPER_ADDR= 0x101c, 120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ 121 PORT_CMD_ERR = 0x1024, /* command error number */ 122 PORT_FIS_CFG = 0x1028, 123 PORT_FIFO_THRES = 0x102c, 124 /* 16 bit regs */ 125 PORT_DECODE_ERR_CNT = 0x1040, 126 PORT_DECODE_ERR_THRESH = 0x1042, 127 PORT_CRC_ERR_CNT = 0x1044, 128 PORT_CRC_ERR_THRESH = 0x1046, 129 PORT_HSHK_ERR_CNT = 0x1048, 130 PORT_HSHK_ERR_THRESH = 0x104a, 131 /* 32 bit regs */ 132 PORT_PHY_CFG = 0x1050, 133 PORT_SLOT_STAT = 0x1800, 134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ 135 PORT_CONTEXT = 0x1e04, 136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ 137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ 138 PORT_SCONTROL = 0x1f00, 139 PORT_SSTATUS = 0x1f04, 140 PORT_SERROR = 0x1f08, 141 PORT_SACTIVE = 0x1f0c, 142 143 /* PORT_CTRL_STAT bits */ 144 PORT_CS_PORT_RST = (1 << 0), /* port reset */ 145 PORT_CS_DEV_RST = (1 << 1), /* device reset */ 146 PORT_CS_INIT = (1 << 2), /* port initialize */ 147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ 150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ 152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 153 154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 155 /* bits[11:0] are masked */ 156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ 157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */ 158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ 159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ 160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ 161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ 162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ 163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ 164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ 165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ 166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ 167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ 168 169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | 170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | 171 PORT_IRQ_UNK_FIS, 172 173 /* bits[27:16] are unmasked (raw) */ 174 PORT_IRQ_RAW_SHIFT = 16, 175 PORT_IRQ_MASKED_MASK = 0x7ff, 176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), 177 178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ 179 PORT_IRQ_STEER_SHIFT = 30, 180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), 181 182 /* PORT_CMD_ERR constants */ 183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ 184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ 185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ 186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ 187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ 188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ 189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ 190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ 191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ 192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ 193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ 194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ 195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ 196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ 197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ 198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ 199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ 200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ 201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ 202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ 203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ 204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ 205 206 /* bits of PRB control field */ 207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ 208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ 209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ 210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ 211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ 212 213 /* PRB protocol field */ 214 PRB_PROT_PACKET = (1 << 0), 215 PRB_PROT_TCQ = (1 << 1), 216 PRB_PROT_NCQ = (1 << 2), 217 PRB_PROT_READ = (1 << 3), 218 PRB_PROT_WRITE = (1 << 4), 219 PRB_PROT_TRANSPARENT = (1 << 5), 220 221 /* 222 * Other constants 223 */ 224 SGE_TRM = (1 << 31), /* Last SGE in chain */ 225 SGE_LNK = (1 << 30), /* linked list 226 Points to SGT, not SGE */ 227 SGE_DRD = (1 << 29), /* discard data read (/dev/null) 228 data address ignored */ 229 230 SIL24_MAX_CMDS = 31, 231 232 /* board id */ 233 BID_SIL3124 = 0, 234 BID_SIL3132 = 1, 235 BID_SIL3131 = 2, 236 237 /* host flags */ 238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 240 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY, 241 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ 242 243 IRQ_STAT_4PORTS = 0xf, 244 }; 245 246 struct sil24_ata_block { 247 struct sil24_prb prb; 248 struct sil24_sge sge[LIBATA_MAX_PRD]; 249 }; 250 251 struct sil24_atapi_block { 252 struct sil24_prb prb; 253 u8 cdb[16]; 254 struct sil24_sge sge[LIBATA_MAX_PRD - 1]; 255 }; 256 257 union sil24_cmd_block { 258 struct sil24_ata_block ata; 259 struct sil24_atapi_block atapi; 260 }; 261 262 static struct sil24_cerr_info { 263 unsigned int err_mask, action; 264 const char *desc; 265 } sil24_cerr_db[] = { 266 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 267 "device error" }, 268 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 269 "device error via D2H FIS" }, 270 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 271 "device error via SDB FIS" }, 272 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 273 "error in data FIS" }, 274 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 275 "failed to transmit command FIS" }, 276 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 277 "protocol mismatch" }, 278 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 279 "data directon mismatch" }, 280 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 281 "ran out of SGEs while writing" }, 282 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 283 "ran out of SGEs while reading" }, 284 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 285 "invalid data directon for ATAPI CDB" }, 286 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 287 "SGT no on qword boundary" }, 288 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 289 "PCI target abort while fetching SGT" }, 290 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 291 "PCI master abort while fetching SGT" }, 292 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 293 "PCI parity error while fetching SGT" }, 294 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 295 "PRB not on qword boundary" }, 296 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 297 "PCI target abort while fetching PRB" }, 298 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 299 "PCI master abort while fetching PRB" }, 300 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 301 "PCI parity error while fetching PRB" }, 302 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 303 "undefined error while transferring data" }, 304 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 305 "PCI target abort while transferring data" }, 306 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 307 "PCI master abort while transferring data" }, 308 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 309 "PCI parity error while transferring data" }, 310 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 311 "FIS received while sending service FIS" }, 312 }; 313 314 /* 315 * ap->private_data 316 * 317 * The preview driver always returned 0 for status. We emulate it 318 * here from the previous interrupt. 319 */ 320 struct sil24_port_priv { 321 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ 322 dma_addr_t cmd_block_dma; /* DMA base addr for them */ 323 struct ata_taskfile tf; /* Cached taskfile registers */ 324 }; 325 326 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); 327 static u8 sil24_check_status(struct ata_port *ap); 328 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); 329 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); 330 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); 331 static void sil24_qc_prep(struct ata_queued_cmd *qc); 332 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); 333 static void sil24_irq_clear(struct ata_port *ap); 334 static irqreturn_t sil24_interrupt(int irq, void *dev_instance); 335 static void sil24_freeze(struct ata_port *ap); 336 static void sil24_thaw(struct ata_port *ap); 337 static void sil24_error_handler(struct ata_port *ap); 338 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); 339 static int sil24_port_start(struct ata_port *ap); 340 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 341 #ifdef CONFIG_PM 342 static int sil24_pci_device_resume(struct pci_dev *pdev); 343 #endif 344 345 static const struct pci_device_id sil24_pci_tbl[] = { 346 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, 347 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, 348 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, 349 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, 350 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, 351 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, 352 353 { } /* terminate list */ 354 }; 355 356 static struct pci_driver sil24_pci_driver = { 357 .name = DRV_NAME, 358 .id_table = sil24_pci_tbl, 359 .probe = sil24_init_one, 360 .remove = ata_pci_remove_one, 361 #ifdef CONFIG_PM 362 .suspend = ata_pci_device_suspend, 363 .resume = sil24_pci_device_resume, 364 #endif 365 }; 366 367 static struct scsi_host_template sil24_sht = { 368 .module = THIS_MODULE, 369 .name = DRV_NAME, 370 .ioctl = ata_scsi_ioctl, 371 .queuecommand = ata_scsi_queuecmd, 372 .change_queue_depth = ata_scsi_change_queue_depth, 373 .can_queue = SIL24_MAX_CMDS, 374 .this_id = ATA_SHT_THIS_ID, 375 .sg_tablesize = LIBATA_MAX_PRD, 376 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 377 .emulated = ATA_SHT_EMULATED, 378 .use_clustering = ATA_SHT_USE_CLUSTERING, 379 .proc_name = DRV_NAME, 380 .dma_boundary = ATA_DMA_BOUNDARY, 381 .slave_configure = ata_scsi_slave_config, 382 .slave_destroy = ata_scsi_slave_destroy, 383 .bios_param = ata_std_bios_param, 384 #ifdef CONFIG_PM 385 .suspend = ata_scsi_device_suspend, 386 .resume = ata_scsi_device_resume, 387 #endif 388 }; 389 390 static const struct ata_port_operations sil24_ops = { 391 .port_disable = ata_port_disable, 392 393 .dev_config = sil24_dev_config, 394 395 .check_status = sil24_check_status, 396 .check_altstatus = sil24_check_status, 397 .dev_select = ata_noop_dev_select, 398 399 .tf_read = sil24_tf_read, 400 401 .qc_prep = sil24_qc_prep, 402 .qc_issue = sil24_qc_issue, 403 404 .irq_handler = sil24_interrupt, 405 .irq_clear = sil24_irq_clear, 406 .irq_on = ata_dummy_irq_on, 407 .irq_ack = ata_dummy_irq_ack, 408 409 .scr_read = sil24_scr_read, 410 .scr_write = sil24_scr_write, 411 412 .freeze = sil24_freeze, 413 .thaw = sil24_thaw, 414 .error_handler = sil24_error_handler, 415 .post_internal_cmd = sil24_post_internal_cmd, 416 417 .port_start = sil24_port_start, 418 }; 419 420 /* 421 * Use bits 30-31 of port_flags to encode available port numbers. 422 * Current maxium is 4. 423 */ 424 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) 425 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) 426 427 static struct ata_port_info sil24_port_info[] = { 428 /* sil_3124 */ 429 { 430 .sht = &sil24_sht, 431 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | 432 SIL24_FLAG_PCIX_IRQ_WOC, 433 .pio_mask = 0x1f, /* pio0-4 */ 434 .mwdma_mask = 0x07, /* mwdma0-2 */ 435 .udma_mask = 0x3f, /* udma0-5 */ 436 .port_ops = &sil24_ops, 437 }, 438 /* sil_3132 */ 439 { 440 .sht = &sil24_sht, 441 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), 442 .pio_mask = 0x1f, /* pio0-4 */ 443 .mwdma_mask = 0x07, /* mwdma0-2 */ 444 .udma_mask = 0x3f, /* udma0-5 */ 445 .port_ops = &sil24_ops, 446 }, 447 /* sil_3131/sil_3531 */ 448 { 449 .sht = &sil24_sht, 450 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), 451 .pio_mask = 0x1f, /* pio0-4 */ 452 .mwdma_mask = 0x07, /* mwdma0-2 */ 453 .udma_mask = 0x3f, /* udma0-5 */ 454 .port_ops = &sil24_ops, 455 }, 456 }; 457 458 static int sil24_tag(int tag) 459 { 460 if (unlikely(ata_tag_internal(tag))) 461 return 0; 462 return tag; 463 } 464 465 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) 466 { 467 void __iomem *port = ap->ioaddr.cmd_addr; 468 469 if (dev->cdb_len == 16) 470 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); 471 else 472 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); 473 } 474 475 static inline void sil24_update_tf(struct ata_port *ap) 476 { 477 struct sil24_port_priv *pp = ap->private_data; 478 void __iomem *port = ap->ioaddr.cmd_addr; 479 struct sil24_prb __iomem *prb = port; 480 u8 fis[6 * 4]; 481 482 memcpy_fromio(fis, prb->fis, 6 * 4); 483 ata_tf_from_fis(fis, &pp->tf); 484 } 485 486 static u8 sil24_check_status(struct ata_port *ap) 487 { 488 struct sil24_port_priv *pp = ap->private_data; 489 return pp->tf.command; 490 } 491 492 static int sil24_scr_map[] = { 493 [SCR_CONTROL] = 0, 494 [SCR_STATUS] = 1, 495 [SCR_ERROR] = 2, 496 [SCR_ACTIVE] = 3, 497 }; 498 499 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) 500 { 501 void __iomem *scr_addr = ap->ioaddr.scr_addr; 502 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 503 void __iomem *addr; 504 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 505 return readl(scr_addr + sil24_scr_map[sc_reg] * 4); 506 } 507 return 0xffffffffU; 508 } 509 510 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) 511 { 512 void __iomem *scr_addr = ap->ioaddr.scr_addr; 513 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 514 void __iomem *addr; 515 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 516 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); 517 } 518 } 519 520 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 521 { 522 struct sil24_port_priv *pp = ap->private_data; 523 *tf = pp->tf; 524 } 525 526 static int sil24_init_port(struct ata_port *ap) 527 { 528 void __iomem *port = ap->ioaddr.cmd_addr; 529 u32 tmp; 530 531 writel(PORT_CS_INIT, port + PORT_CTRL_STAT); 532 ata_wait_register(port + PORT_CTRL_STAT, 533 PORT_CS_INIT, PORT_CS_INIT, 10, 100); 534 tmp = ata_wait_register(port + PORT_CTRL_STAT, 535 PORT_CS_RDY, 0, 10, 100); 536 537 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) 538 return -EIO; 539 return 0; 540 } 541 542 static int sil24_softreset(struct ata_port *ap, unsigned int *class) 543 { 544 void __iomem *port = ap->ioaddr.cmd_addr; 545 struct sil24_port_priv *pp = ap->private_data; 546 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; 547 dma_addr_t paddr = pp->cmd_block_dma; 548 u32 mask, irq_stat; 549 const char *reason; 550 551 DPRINTK("ENTER\n"); 552 553 if (ata_port_offline(ap)) { 554 DPRINTK("PHY reports no device\n"); 555 *class = ATA_DEV_NONE; 556 goto out; 557 } 558 559 /* put the port into known state */ 560 if (sil24_init_port(ap)) { 561 reason ="port not ready"; 562 goto err; 563 } 564 565 /* do SRST */ 566 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST); 567 prb->fis[1] = 0; /* no PMP yet */ 568 569 writel((u32)paddr, port + PORT_CMD_ACTIVATE); 570 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); 571 572 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; 573 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0, 574 100, ATA_TMOUT_BOOT / HZ * 1000); 575 576 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */ 577 irq_stat >>= PORT_IRQ_RAW_SHIFT; 578 579 if (!(irq_stat & PORT_IRQ_COMPLETE)) { 580 if (irq_stat & PORT_IRQ_ERROR) 581 reason = "SRST command error"; 582 else 583 reason = "timeout"; 584 goto err; 585 } 586 587 sil24_update_tf(ap); 588 *class = ata_dev_classify(&pp->tf); 589 590 if (*class == ATA_DEV_UNKNOWN) 591 *class = ATA_DEV_NONE; 592 593 out: 594 DPRINTK("EXIT, class=%u\n", *class); 595 return 0; 596 597 err: 598 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); 599 return -EIO; 600 } 601 602 static int sil24_hardreset(struct ata_port *ap, unsigned int *class) 603 { 604 void __iomem *port = ap->ioaddr.cmd_addr; 605 const char *reason; 606 int tout_msec, rc; 607 u32 tmp; 608 609 /* sil24 does the right thing(tm) without any protection */ 610 sata_set_spd(ap); 611 612 tout_msec = 100; 613 if (ata_port_online(ap)) 614 tout_msec = 5000; 615 616 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); 617 tmp = ata_wait_register(port + PORT_CTRL_STAT, 618 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec); 619 620 /* SStatus oscillates between zero and valid status after 621 * DEV_RST, debounce it. 622 */ 623 rc = sata_phy_debounce(ap, sata_deb_timing_long); 624 if (rc) { 625 reason = "PHY debouncing failed"; 626 goto err; 627 } 628 629 if (tmp & PORT_CS_DEV_RST) { 630 if (ata_port_offline(ap)) 631 return 0; 632 reason = "link not ready"; 633 goto err; 634 } 635 636 /* Sil24 doesn't store signature FIS after hardreset, so we 637 * can't wait for BSY to clear. Some devices take a long time 638 * to get ready and those devices will choke if we don't wait 639 * for BSY clearance here. Tell libata to perform follow-up 640 * softreset. 641 */ 642 return -EAGAIN; 643 644 err: 645 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason); 646 return -EIO; 647 } 648 649 static inline void sil24_fill_sg(struct ata_queued_cmd *qc, 650 struct sil24_sge *sge) 651 { 652 struct scatterlist *sg; 653 654 ata_for_each_sg(sg, qc) { 655 sge->addr = cpu_to_le64(sg_dma_address(sg)); 656 sge->cnt = cpu_to_le32(sg_dma_len(sg)); 657 if (ata_sg_is_last(sg, qc)) 658 sge->flags = cpu_to_le32(SGE_TRM); 659 else 660 sge->flags = 0; 661 sge++; 662 } 663 } 664 665 static void sil24_qc_prep(struct ata_queued_cmd *qc) 666 { 667 struct ata_port *ap = qc->ap; 668 struct sil24_port_priv *pp = ap->private_data; 669 union sil24_cmd_block *cb; 670 struct sil24_prb *prb; 671 struct sil24_sge *sge; 672 u16 ctrl = 0; 673 674 cb = &pp->cmd_block[sil24_tag(qc->tag)]; 675 676 switch (qc->tf.protocol) { 677 case ATA_PROT_PIO: 678 case ATA_PROT_DMA: 679 case ATA_PROT_NCQ: 680 case ATA_PROT_NODATA: 681 prb = &cb->ata.prb; 682 sge = cb->ata.sge; 683 break; 684 685 case ATA_PROT_ATAPI: 686 case ATA_PROT_ATAPI_DMA: 687 case ATA_PROT_ATAPI_NODATA: 688 prb = &cb->atapi.prb; 689 sge = cb->atapi.sge; 690 memset(cb->atapi.cdb, 0, 32); 691 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); 692 693 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { 694 if (qc->tf.flags & ATA_TFLAG_WRITE) 695 ctrl = PRB_CTRL_PACKET_WRITE; 696 else 697 ctrl = PRB_CTRL_PACKET_READ; 698 } 699 break; 700 701 default: 702 prb = NULL; /* shut up, gcc */ 703 sge = NULL; 704 BUG(); 705 } 706 707 prb->ctrl = cpu_to_le16(ctrl); 708 ata_tf_to_fis(&qc->tf, prb->fis, 0); 709 710 if (qc->flags & ATA_QCFLAG_DMAMAP) 711 sil24_fill_sg(qc, sge); 712 } 713 714 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) 715 { 716 struct ata_port *ap = qc->ap; 717 struct sil24_port_priv *pp = ap->private_data; 718 void __iomem *port = ap->ioaddr.cmd_addr; 719 unsigned int tag = sil24_tag(qc->tag); 720 dma_addr_t paddr; 721 void __iomem *activate; 722 723 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); 724 activate = port + PORT_CMD_ACTIVATE + tag * 8; 725 726 writel((u32)paddr, activate); 727 writel((u64)paddr >> 32, activate + 4); 728 729 return 0; 730 } 731 732 static void sil24_irq_clear(struct ata_port *ap) 733 { 734 /* unused */ 735 } 736 737 static void sil24_freeze(struct ata_port *ap) 738 { 739 void __iomem *port = ap->ioaddr.cmd_addr; 740 741 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear 742 * PORT_IRQ_ENABLE instead. 743 */ 744 writel(0xffff, port + PORT_IRQ_ENABLE_CLR); 745 } 746 747 static void sil24_thaw(struct ata_port *ap) 748 { 749 void __iomem *port = ap->ioaddr.cmd_addr; 750 u32 tmp; 751 752 /* clear IRQ */ 753 tmp = readl(port + PORT_IRQ_STAT); 754 writel(tmp, port + PORT_IRQ_STAT); 755 756 /* turn IRQ back on */ 757 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); 758 } 759 760 static void sil24_error_intr(struct ata_port *ap) 761 { 762 void __iomem *port = ap->ioaddr.cmd_addr; 763 struct ata_eh_info *ehi = &ap->eh_info; 764 int freeze = 0; 765 u32 irq_stat; 766 767 /* on error, we need to clear IRQ explicitly */ 768 irq_stat = readl(port + PORT_IRQ_STAT); 769 writel(irq_stat, port + PORT_IRQ_STAT); 770 771 /* first, analyze and record host port events */ 772 ata_ehi_clear_desc(ehi); 773 774 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); 775 776 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { 777 ata_ehi_hotplugged(ehi); 778 ata_ehi_push_desc(ehi, ", %s", 779 irq_stat & PORT_IRQ_PHYRDY_CHG ? 780 "PHY RDY changed" : "device exchanged"); 781 freeze = 1; 782 } 783 784 if (irq_stat & PORT_IRQ_UNK_FIS) { 785 ehi->err_mask |= AC_ERR_HSM; 786 ehi->action |= ATA_EH_SOFTRESET; 787 ata_ehi_push_desc(ehi , ", unknown FIS"); 788 freeze = 1; 789 } 790 791 /* deal with command error */ 792 if (irq_stat & PORT_IRQ_ERROR) { 793 struct sil24_cerr_info *ci = NULL; 794 unsigned int err_mask = 0, action = 0; 795 struct ata_queued_cmd *qc; 796 u32 cerr; 797 798 /* analyze CMD_ERR */ 799 cerr = readl(port + PORT_CMD_ERR); 800 if (cerr < ARRAY_SIZE(sil24_cerr_db)) 801 ci = &sil24_cerr_db[cerr]; 802 803 if (ci && ci->desc) { 804 err_mask |= ci->err_mask; 805 action |= ci->action; 806 ata_ehi_push_desc(ehi, ", %s", ci->desc); 807 } else { 808 err_mask |= AC_ERR_OTHER; 809 action |= ATA_EH_SOFTRESET; 810 ata_ehi_push_desc(ehi, ", unknown command error %d", 811 cerr); 812 } 813 814 /* record error info */ 815 qc = ata_qc_from_tag(ap, ap->active_tag); 816 if (qc) { 817 sil24_update_tf(ap); 818 qc->err_mask |= err_mask; 819 } else 820 ehi->err_mask |= err_mask; 821 822 ehi->action |= action; 823 } 824 825 /* freeze or abort */ 826 if (freeze) 827 ata_port_freeze(ap); 828 else 829 ata_port_abort(ap); 830 } 831 832 static void sil24_finish_qc(struct ata_queued_cmd *qc) 833 { 834 if (qc->flags & ATA_QCFLAG_RESULT_TF) 835 sil24_update_tf(qc->ap); 836 } 837 838 static inline void sil24_host_intr(struct ata_port *ap) 839 { 840 void __iomem *port = ap->ioaddr.cmd_addr; 841 u32 slot_stat, qc_active; 842 int rc; 843 844 slot_stat = readl(port + PORT_SLOT_STAT); 845 846 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { 847 sil24_error_intr(ap); 848 return; 849 } 850 851 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) 852 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); 853 854 qc_active = slot_stat & ~HOST_SSTAT_ATTN; 855 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc); 856 if (rc > 0) 857 return; 858 if (rc < 0) { 859 struct ata_eh_info *ehi = &ap->eh_info; 860 ehi->err_mask |= AC_ERR_HSM; 861 ehi->action |= ATA_EH_SOFTRESET; 862 ata_port_freeze(ap); 863 return; 864 } 865 866 if (ata_ratelimit()) 867 ata_port_printk(ap, KERN_INFO, "spurious interrupt " 868 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", 869 slot_stat, ap->active_tag, ap->sactive); 870 } 871 872 static irqreturn_t sil24_interrupt(int irq, void *dev_instance) 873 { 874 struct ata_host *host = dev_instance; 875 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 876 unsigned handled = 0; 877 u32 status; 878 int i; 879 880 status = readl(host_base + HOST_IRQ_STAT); 881 882 if (status == 0xffffffff) { 883 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " 884 "PCI fault or device removal?\n"); 885 goto out; 886 } 887 888 if (!(status & IRQ_STAT_4PORTS)) 889 goto out; 890 891 spin_lock(&host->lock); 892 893 for (i = 0; i < host->n_ports; i++) 894 if (status & (1 << i)) { 895 struct ata_port *ap = host->ports[i]; 896 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { 897 sil24_host_intr(host->ports[i]); 898 handled++; 899 } else 900 printk(KERN_ERR DRV_NAME 901 ": interrupt from disabled port %d\n", i); 902 } 903 904 spin_unlock(&host->lock); 905 out: 906 return IRQ_RETVAL(handled); 907 } 908 909 static void sil24_error_handler(struct ata_port *ap) 910 { 911 struct ata_eh_context *ehc = &ap->eh_context; 912 913 if (sil24_init_port(ap)) { 914 ata_eh_freeze_port(ap); 915 ehc->i.action |= ATA_EH_HARDRESET; 916 } 917 918 /* perform recovery */ 919 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset, 920 ata_std_postreset); 921 } 922 923 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) 924 { 925 struct ata_port *ap = qc->ap; 926 927 if (qc->flags & ATA_QCFLAG_FAILED) 928 qc->err_mask |= AC_ERR_OTHER; 929 930 /* make DMA engine forget about the failed command */ 931 if (qc->err_mask) 932 sil24_init_port(ap); 933 } 934 935 static int sil24_port_start(struct ata_port *ap) 936 { 937 struct device *dev = ap->host->dev; 938 struct sil24_port_priv *pp; 939 union sil24_cmd_block *cb; 940 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; 941 dma_addr_t cb_dma; 942 int rc; 943 944 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 945 if (!pp) 946 return -ENOMEM; 947 948 pp->tf.command = ATA_DRDY; 949 950 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); 951 if (!cb) 952 return -ENOMEM; 953 memset(cb, 0, cb_size); 954 955 rc = ata_pad_alloc(ap, dev); 956 if (rc) 957 return rc; 958 959 pp->cmd_block = cb; 960 pp->cmd_block_dma = cb_dma; 961 962 ap->private_data = pp; 963 964 return 0; 965 } 966 967 static void sil24_init_controller(struct pci_dev *pdev, int n_ports, 968 unsigned long port_flags, 969 void __iomem *host_base, 970 void __iomem *port_base) 971 { 972 u32 tmp; 973 int i; 974 975 /* GPIO off */ 976 writel(0, host_base + HOST_FLASH_CMD); 977 978 /* clear global reset & mask interrupts during initialization */ 979 writel(0, host_base + HOST_CTRL); 980 981 /* init ports */ 982 for (i = 0; i < n_ports; i++) { 983 void __iomem *port = port_base + i * PORT_REGS_SIZE; 984 985 /* Initial PHY setting */ 986 writel(0x20c, port + PORT_PHY_CFG); 987 988 /* Clear port RST */ 989 tmp = readl(port + PORT_CTRL_STAT); 990 if (tmp & PORT_CS_PORT_RST) { 991 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); 992 tmp = ata_wait_register(port + PORT_CTRL_STAT, 993 PORT_CS_PORT_RST, 994 PORT_CS_PORT_RST, 10, 100); 995 if (tmp & PORT_CS_PORT_RST) 996 dev_printk(KERN_ERR, &pdev->dev, 997 "failed to clear port RST\n"); 998 } 999 1000 /* Configure IRQ WoC */ 1001 if (port_flags & SIL24_FLAG_PCIX_IRQ_WOC) 1002 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); 1003 else 1004 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); 1005 1006 /* Zero error counters. */ 1007 writel(0x8000, port + PORT_DECODE_ERR_THRESH); 1008 writel(0x8000, port + PORT_CRC_ERR_THRESH); 1009 writel(0x8000, port + PORT_HSHK_ERR_THRESH); 1010 writel(0x0000, port + PORT_DECODE_ERR_CNT); 1011 writel(0x0000, port + PORT_CRC_ERR_CNT); 1012 writel(0x0000, port + PORT_HSHK_ERR_CNT); 1013 1014 /* Always use 64bit activation */ 1015 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); 1016 1017 /* Clear port multiplier enable and resume bits */ 1018 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, 1019 port + PORT_CTRL_CLR); 1020 } 1021 1022 /* Turn on interrupts */ 1023 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); 1024 } 1025 1026 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1027 { 1028 static int printed_version = 0; 1029 struct device *dev = &pdev->dev; 1030 unsigned int board_id = (unsigned int)ent->driver_data; 1031 struct ata_port_info *pinfo = &sil24_port_info[board_id]; 1032 struct ata_probe_ent *probe_ent; 1033 void __iomem *host_base; 1034 void __iomem *port_base; 1035 int i, rc; 1036 u32 tmp; 1037 1038 if (!printed_version++) 1039 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1040 1041 rc = pcim_enable_device(pdev); 1042 if (rc) 1043 return rc; 1044 1045 rc = pcim_iomap_regions(pdev, 1046 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), 1047 DRV_NAME); 1048 if (rc) 1049 return rc; 1050 1051 /* allocate & init probe_ent */ 1052 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); 1053 if (!probe_ent) 1054 return -ENOMEM; 1055 1056 probe_ent->dev = pci_dev_to_dev(pdev); 1057 INIT_LIST_HEAD(&probe_ent->node); 1058 1059 probe_ent->sht = pinfo->sht; 1060 probe_ent->port_flags = pinfo->flags; 1061 probe_ent->pio_mask = pinfo->pio_mask; 1062 probe_ent->mwdma_mask = pinfo->mwdma_mask; 1063 probe_ent->udma_mask = pinfo->udma_mask; 1064 probe_ent->port_ops = pinfo->port_ops; 1065 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->flags); 1066 1067 probe_ent->irq = pdev->irq; 1068 probe_ent->irq_flags = IRQF_SHARED; 1069 probe_ent->iomap = pcim_iomap_table(pdev); 1070 1071 host_base = probe_ent->iomap[SIL24_HOST_BAR]; 1072 port_base = probe_ent->iomap[SIL24_PORT_BAR]; 1073 1074 /* 1075 * Configure the device 1076 */ 1077 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 1078 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1079 if (rc) { 1080 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1081 if (rc) { 1082 dev_printk(KERN_ERR, &pdev->dev, 1083 "64-bit DMA enable failed\n"); 1084 return rc; 1085 } 1086 } 1087 } else { 1088 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1089 if (rc) { 1090 dev_printk(KERN_ERR, &pdev->dev, 1091 "32-bit DMA enable failed\n"); 1092 return rc; 1093 } 1094 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1095 if (rc) { 1096 dev_printk(KERN_ERR, &pdev->dev, 1097 "32-bit consistent DMA enable failed\n"); 1098 return rc; 1099 } 1100 } 1101 1102 /* Apply workaround for completion IRQ loss on PCI-X errata */ 1103 if (probe_ent->port_flags & SIL24_FLAG_PCIX_IRQ_WOC) { 1104 tmp = readl(host_base + HOST_CTRL); 1105 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) 1106 dev_printk(KERN_INFO, &pdev->dev, 1107 "Applying completion IRQ loss on PCI-X " 1108 "errata fix\n"); 1109 else 1110 probe_ent->port_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; 1111 } 1112 1113 for (i = 0; i < probe_ent->n_ports; i++) { 1114 void __iomem *port = port_base + i * PORT_REGS_SIZE; 1115 1116 probe_ent->port[i].cmd_addr = port; 1117 probe_ent->port[i].scr_addr = port + PORT_SCONTROL; 1118 1119 ata_std_ports(&probe_ent->port[i]); 1120 } 1121 1122 sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags, 1123 host_base, port_base); 1124 1125 pci_set_master(pdev); 1126 1127 if (!ata_device_add(probe_ent)) 1128 return -ENODEV; 1129 1130 devm_kfree(dev, probe_ent); 1131 return 0; 1132 } 1133 1134 #ifdef CONFIG_PM 1135 static int sil24_pci_device_resume(struct pci_dev *pdev) 1136 { 1137 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1138 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1139 void __iomem *port_base = host->iomap[SIL24_PORT_BAR]; 1140 int rc; 1141 1142 rc = ata_pci_device_do_resume(pdev); 1143 if (rc) 1144 return rc; 1145 1146 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) 1147 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); 1148 1149 sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags, 1150 host_base, port_base); 1151 1152 ata_host_resume(host); 1153 1154 return 0; 1155 } 1156 #endif 1157 1158 static int __init sil24_init(void) 1159 { 1160 return pci_register_driver(&sil24_pci_driver); 1161 } 1162 1163 static void __exit sil24_exit(void) 1164 { 1165 pci_unregister_driver(&sil24_pci_driver); 1166 } 1167 1168 MODULE_AUTHOR("Tejun Heo"); 1169 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); 1170 MODULE_LICENSE("GPL"); 1171 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); 1172 1173 module_init(sil24_init); 1174 module_exit(sil24_exit); 1175