1 /* 2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers 3 * 4 * Copyright 2005 Tejun Heo 5 * 6 * Based on preview driver from Silicon Image. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/device.h> 28 #include <scsi/scsi_host.h> 29 #include <scsi/scsi_cmnd.h> 30 #include <linux/libata.h> 31 32 #define DRV_NAME "sata_sil24" 33 #define DRV_VERSION "1.1" 34 35 /* 36 * Port request block (PRB) 32 bytes 37 */ 38 struct sil24_prb { 39 __le16 ctrl; 40 __le16 prot; 41 __le32 rx_cnt; 42 u8 fis[6 * 4]; 43 }; 44 45 /* 46 * Scatter gather entry (SGE) 16 bytes 47 */ 48 struct sil24_sge { 49 __le64 addr; 50 __le32 cnt; 51 __le32 flags; 52 }; 53 54 /* 55 * Port multiplier 56 */ 57 struct sil24_port_multiplier { 58 __le32 diag; 59 __le32 sactive; 60 }; 61 62 enum { 63 SIL24_HOST_BAR = 0, 64 SIL24_PORT_BAR = 2, 65 66 /* 67 * Global controller registers (128 bytes @ BAR0) 68 */ 69 /* 32 bit regs */ 70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ 71 HOST_CTRL = 0x40, 72 HOST_IRQ_STAT = 0x44, 73 HOST_PHY_CFG = 0x48, 74 HOST_BIST_CTRL = 0x50, 75 HOST_BIST_PTRN = 0x54, 76 HOST_BIST_STAT = 0x58, 77 HOST_MEM_BIST_STAT = 0x5c, 78 HOST_FLASH_CMD = 0x70, 79 /* 8 bit regs */ 80 HOST_FLASH_DATA = 0x74, 81 HOST_TRANSITION_DETECT = 0x75, 82 HOST_GPIO_CTRL = 0x76, 83 HOST_I2C_ADDR = 0x78, /* 32 bit */ 84 HOST_I2C_DATA = 0x7c, 85 HOST_I2C_XFER_CNT = 0x7e, 86 HOST_I2C_CTRL = 0x7f, 87 88 /* HOST_SLOT_STAT bits */ 89 HOST_SSTAT_ATTN = (1 << 31), 90 91 /* HOST_CTRL bits */ 92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ 93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ 94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ 95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ 96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ 97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ 98 99 /* 100 * Port registers 101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) 102 */ 103 PORT_REGS_SIZE = 0x2000, 104 105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ 106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 107 108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ 109 PORT_PMP_STATUS = 0x0000, /* port device status offset */ 110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ 111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ 112 113 /* 32 bit regs */ 114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ 117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ 118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ 119 PORT_ACTIVATE_UPPER_ADDR= 0x101c, 120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ 121 PORT_CMD_ERR = 0x1024, /* command error number */ 122 PORT_FIS_CFG = 0x1028, 123 PORT_FIFO_THRES = 0x102c, 124 /* 16 bit regs */ 125 PORT_DECODE_ERR_CNT = 0x1040, 126 PORT_DECODE_ERR_THRESH = 0x1042, 127 PORT_CRC_ERR_CNT = 0x1044, 128 PORT_CRC_ERR_THRESH = 0x1046, 129 PORT_HSHK_ERR_CNT = 0x1048, 130 PORT_HSHK_ERR_THRESH = 0x104a, 131 /* 32 bit regs */ 132 PORT_PHY_CFG = 0x1050, 133 PORT_SLOT_STAT = 0x1800, 134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ 135 PORT_CONTEXT = 0x1e04, 136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ 137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ 138 PORT_SCONTROL = 0x1f00, 139 PORT_SSTATUS = 0x1f04, 140 PORT_SERROR = 0x1f08, 141 PORT_SACTIVE = 0x1f0c, 142 143 /* PORT_CTRL_STAT bits */ 144 PORT_CS_PORT_RST = (1 << 0), /* port reset */ 145 PORT_CS_DEV_RST = (1 << 1), /* device reset */ 146 PORT_CS_INIT = (1 << 2), /* port initialize */ 147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ 150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ 152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 153 154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 155 /* bits[11:0] are masked */ 156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ 157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */ 158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ 159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ 160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ 161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ 162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ 163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ 164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ 165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ 166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ 167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ 168 169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | 170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | 171 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, 172 173 /* bits[27:16] are unmasked (raw) */ 174 PORT_IRQ_RAW_SHIFT = 16, 175 PORT_IRQ_MASKED_MASK = 0x7ff, 176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), 177 178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ 179 PORT_IRQ_STEER_SHIFT = 30, 180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), 181 182 /* PORT_CMD_ERR constants */ 183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ 184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ 185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ 186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ 187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ 188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ 189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ 190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ 191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ 192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ 193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ 194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ 195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ 196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ 197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ 198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ 199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ 200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ 201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ 202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ 203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ 204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ 205 206 /* bits of PRB control field */ 207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ 208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ 209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ 210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ 211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ 212 213 /* PRB protocol field */ 214 PRB_PROT_PACKET = (1 << 0), 215 PRB_PROT_TCQ = (1 << 1), 216 PRB_PROT_NCQ = (1 << 2), 217 PRB_PROT_READ = (1 << 3), 218 PRB_PROT_WRITE = (1 << 4), 219 PRB_PROT_TRANSPARENT = (1 << 5), 220 221 /* 222 * Other constants 223 */ 224 SGE_TRM = (1 << 31), /* Last SGE in chain */ 225 SGE_LNK = (1 << 30), /* linked list 226 Points to SGT, not SGE */ 227 SGE_DRD = (1 << 29), /* discard data read (/dev/null) 228 data address ignored */ 229 230 SIL24_MAX_CMDS = 31, 231 232 /* board id */ 233 BID_SIL3124 = 0, 234 BID_SIL3132 = 1, 235 BID_SIL3131 = 2, 236 237 /* host flags */ 238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 240 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA | 241 ATA_FLAG_AN | ATA_FLAG_PMP, 242 SIL24_COMMON_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY, 243 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ 244 245 IRQ_STAT_4PORTS = 0xf, 246 }; 247 248 struct sil24_ata_block { 249 struct sil24_prb prb; 250 struct sil24_sge sge[LIBATA_MAX_PRD]; 251 }; 252 253 struct sil24_atapi_block { 254 struct sil24_prb prb; 255 u8 cdb[16]; 256 struct sil24_sge sge[LIBATA_MAX_PRD - 1]; 257 }; 258 259 union sil24_cmd_block { 260 struct sil24_ata_block ata; 261 struct sil24_atapi_block atapi; 262 }; 263 264 static struct sil24_cerr_info { 265 unsigned int err_mask, action; 266 const char *desc; 267 } sil24_cerr_db[] = { 268 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 269 "device error" }, 270 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 271 "device error via D2H FIS" }, 272 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 273 "device error via SDB FIS" }, 274 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 275 "error in data FIS" }, 276 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 277 "failed to transmit command FIS" }, 278 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 279 "protocol mismatch" }, 280 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 281 "data directon mismatch" }, 282 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 283 "ran out of SGEs while writing" }, 284 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 285 "ran out of SGEs while reading" }, 286 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 287 "invalid data directon for ATAPI CDB" }, 288 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 289 "SGT no on qword boundary" }, 290 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 291 "PCI target abort while fetching SGT" }, 292 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 293 "PCI master abort while fetching SGT" }, 294 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 295 "PCI parity error while fetching SGT" }, 296 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 297 "PRB not on qword boundary" }, 298 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 299 "PCI target abort while fetching PRB" }, 300 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 301 "PCI master abort while fetching PRB" }, 302 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 303 "PCI parity error while fetching PRB" }, 304 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 305 "undefined error while transferring data" }, 306 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 307 "PCI target abort while transferring data" }, 308 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 309 "PCI master abort while transferring data" }, 310 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 311 "PCI parity error while transferring data" }, 312 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 313 "FIS received while sending service FIS" }, 314 }; 315 316 /* 317 * ap->private_data 318 * 319 * The preview driver always returned 0 for status. We emulate it 320 * here from the previous interrupt. 321 */ 322 struct sil24_port_priv { 323 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ 324 dma_addr_t cmd_block_dma; /* DMA base addr for them */ 325 struct ata_taskfile tf; /* Cached taskfile registers */ 326 int do_port_rst; 327 }; 328 329 static void sil24_dev_config(struct ata_device *dev); 330 static u8 sil24_check_status(struct ata_port *ap); 331 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val); 332 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); 333 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); 334 static int sil24_qc_defer(struct ata_queued_cmd *qc); 335 static void sil24_qc_prep(struct ata_queued_cmd *qc); 336 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); 337 static void sil24_irq_clear(struct ata_port *ap); 338 static void sil24_pmp_attach(struct ata_port *ap); 339 static void sil24_pmp_detach(struct ata_port *ap); 340 static void sil24_freeze(struct ata_port *ap); 341 static void sil24_thaw(struct ata_port *ap); 342 static void sil24_error_handler(struct ata_port *ap); 343 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); 344 static int sil24_port_start(struct ata_port *ap); 345 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 346 #ifdef CONFIG_PM 347 static int sil24_pci_device_resume(struct pci_dev *pdev); 348 static int sil24_port_resume(struct ata_port *ap); 349 #endif 350 351 static const struct pci_device_id sil24_pci_tbl[] = { 352 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, 353 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, 354 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, 355 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, 356 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, 357 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, 358 359 { } /* terminate list */ 360 }; 361 362 static struct pci_driver sil24_pci_driver = { 363 .name = DRV_NAME, 364 .id_table = sil24_pci_tbl, 365 .probe = sil24_init_one, 366 .remove = ata_pci_remove_one, 367 #ifdef CONFIG_PM 368 .suspend = ata_pci_device_suspend, 369 .resume = sil24_pci_device_resume, 370 #endif 371 }; 372 373 static struct scsi_host_template sil24_sht = { 374 .module = THIS_MODULE, 375 .name = DRV_NAME, 376 .ioctl = ata_scsi_ioctl, 377 .queuecommand = ata_scsi_queuecmd, 378 .change_queue_depth = ata_scsi_change_queue_depth, 379 .can_queue = SIL24_MAX_CMDS, 380 .this_id = ATA_SHT_THIS_ID, 381 .sg_tablesize = LIBATA_MAX_PRD, 382 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 383 .emulated = ATA_SHT_EMULATED, 384 .use_clustering = ATA_SHT_USE_CLUSTERING, 385 .proc_name = DRV_NAME, 386 .dma_boundary = ATA_DMA_BOUNDARY, 387 .slave_configure = ata_scsi_slave_config, 388 .slave_destroy = ata_scsi_slave_destroy, 389 .bios_param = ata_std_bios_param, 390 }; 391 392 static const struct ata_port_operations sil24_ops = { 393 .dev_config = sil24_dev_config, 394 395 .check_status = sil24_check_status, 396 .check_altstatus = sil24_check_status, 397 .dev_select = ata_noop_dev_select, 398 399 .tf_read = sil24_tf_read, 400 401 .qc_defer = sil24_qc_defer, 402 .qc_prep = sil24_qc_prep, 403 .qc_issue = sil24_qc_issue, 404 405 .irq_clear = sil24_irq_clear, 406 407 .scr_read = sil24_scr_read, 408 .scr_write = sil24_scr_write, 409 410 .pmp_attach = sil24_pmp_attach, 411 .pmp_detach = sil24_pmp_detach, 412 413 .freeze = sil24_freeze, 414 .thaw = sil24_thaw, 415 .error_handler = sil24_error_handler, 416 .post_internal_cmd = sil24_post_internal_cmd, 417 418 .port_start = sil24_port_start, 419 420 #ifdef CONFIG_PM 421 .port_resume = sil24_port_resume, 422 #endif 423 }; 424 425 /* 426 * Use bits 30-31 of port_flags to encode available port numbers. 427 * Current maxium is 4. 428 */ 429 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) 430 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) 431 432 static const struct ata_port_info sil24_port_info[] = { 433 /* sil_3124 */ 434 { 435 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | 436 SIL24_FLAG_PCIX_IRQ_WOC, 437 .link_flags = SIL24_COMMON_LFLAGS, 438 .pio_mask = 0x1f, /* pio0-4 */ 439 .mwdma_mask = 0x07, /* mwdma0-2 */ 440 .udma_mask = ATA_UDMA5, /* udma0-5 */ 441 .port_ops = &sil24_ops, 442 }, 443 /* sil_3132 */ 444 { 445 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), 446 .link_flags = SIL24_COMMON_LFLAGS, 447 .pio_mask = 0x1f, /* pio0-4 */ 448 .mwdma_mask = 0x07, /* mwdma0-2 */ 449 .udma_mask = ATA_UDMA5, /* udma0-5 */ 450 .port_ops = &sil24_ops, 451 }, 452 /* sil_3131/sil_3531 */ 453 { 454 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), 455 .link_flags = SIL24_COMMON_LFLAGS, 456 .pio_mask = 0x1f, /* pio0-4 */ 457 .mwdma_mask = 0x07, /* mwdma0-2 */ 458 .udma_mask = ATA_UDMA5, /* udma0-5 */ 459 .port_ops = &sil24_ops, 460 }, 461 }; 462 463 static int sil24_tag(int tag) 464 { 465 if (unlikely(ata_tag_internal(tag))) 466 return 0; 467 return tag; 468 } 469 470 static void sil24_dev_config(struct ata_device *dev) 471 { 472 void __iomem *port = dev->link->ap->ioaddr.cmd_addr; 473 474 if (dev->cdb_len == 16) 475 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); 476 else 477 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); 478 } 479 480 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf) 481 { 482 void __iomem *port = ap->ioaddr.cmd_addr; 483 struct sil24_prb __iomem *prb; 484 u8 fis[6 * 4]; 485 486 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ; 487 memcpy_fromio(fis, prb->fis, sizeof(fis)); 488 ata_tf_from_fis(fis, tf); 489 } 490 491 static u8 sil24_check_status(struct ata_port *ap) 492 { 493 struct sil24_port_priv *pp = ap->private_data; 494 return pp->tf.command; 495 } 496 497 static int sil24_scr_map[] = { 498 [SCR_CONTROL] = 0, 499 [SCR_STATUS] = 1, 500 [SCR_ERROR] = 2, 501 [SCR_ACTIVE] = 3, 502 }; 503 504 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val) 505 { 506 void __iomem *scr_addr = ap->ioaddr.scr_addr; 507 508 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 509 void __iomem *addr; 510 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 511 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4); 512 return 0; 513 } 514 return -EINVAL; 515 } 516 517 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) 518 { 519 void __iomem *scr_addr = ap->ioaddr.scr_addr; 520 521 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 522 void __iomem *addr; 523 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 524 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); 525 return 0; 526 } 527 return -EINVAL; 528 } 529 530 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 531 { 532 struct sil24_port_priv *pp = ap->private_data; 533 *tf = pp->tf; 534 } 535 536 static void sil24_config_port(struct ata_port *ap) 537 { 538 void __iomem *port = ap->ioaddr.cmd_addr; 539 540 /* configure IRQ WoC */ 541 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) 542 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); 543 else 544 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); 545 546 /* zero error counters. */ 547 writel(0x8000, port + PORT_DECODE_ERR_THRESH); 548 writel(0x8000, port + PORT_CRC_ERR_THRESH); 549 writel(0x8000, port + PORT_HSHK_ERR_THRESH); 550 writel(0x0000, port + PORT_DECODE_ERR_CNT); 551 writel(0x0000, port + PORT_CRC_ERR_CNT); 552 writel(0x0000, port + PORT_HSHK_ERR_CNT); 553 554 /* always use 64bit activation */ 555 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); 556 557 /* clear port multiplier enable and resume bits */ 558 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); 559 } 560 561 static void sil24_config_pmp(struct ata_port *ap, int attached) 562 { 563 void __iomem *port = ap->ioaddr.cmd_addr; 564 565 if (attached) 566 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT); 567 else 568 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR); 569 } 570 571 static void sil24_clear_pmp(struct ata_port *ap) 572 { 573 void __iomem *port = ap->ioaddr.cmd_addr; 574 int i; 575 576 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); 577 578 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) { 579 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE; 580 581 writel(0, pmp_base + PORT_PMP_STATUS); 582 writel(0, pmp_base + PORT_PMP_QACTIVE); 583 } 584 } 585 586 static int sil24_init_port(struct ata_port *ap) 587 { 588 void __iomem *port = ap->ioaddr.cmd_addr; 589 struct sil24_port_priv *pp = ap->private_data; 590 u32 tmp; 591 592 /* clear PMP error status */ 593 if (ap->nr_pmp_links) 594 sil24_clear_pmp(ap); 595 596 writel(PORT_CS_INIT, port + PORT_CTRL_STAT); 597 ata_wait_register(port + PORT_CTRL_STAT, 598 PORT_CS_INIT, PORT_CS_INIT, 10, 100); 599 tmp = ata_wait_register(port + PORT_CTRL_STAT, 600 PORT_CS_RDY, 0, 10, 100); 601 602 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) { 603 pp->do_port_rst = 1; 604 ap->link.eh_context.i.action |= ATA_EH_HARDRESET; 605 return -EIO; 606 } 607 608 return 0; 609 } 610 611 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp, 612 const struct ata_taskfile *tf, 613 int is_cmd, u32 ctrl, 614 unsigned long timeout_msec) 615 { 616 void __iomem *port = ap->ioaddr.cmd_addr; 617 struct sil24_port_priv *pp = ap->private_data; 618 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; 619 dma_addr_t paddr = pp->cmd_block_dma; 620 u32 irq_enabled, irq_mask, irq_stat; 621 int rc; 622 623 prb->ctrl = cpu_to_le16(ctrl); 624 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis); 625 626 /* temporarily plug completion and error interrupts */ 627 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET); 628 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR); 629 630 writel((u32)paddr, port + PORT_CMD_ACTIVATE); 631 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); 632 633 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; 634 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0, 635 10, timeout_msec); 636 637 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */ 638 irq_stat >>= PORT_IRQ_RAW_SHIFT; 639 640 if (irq_stat & PORT_IRQ_COMPLETE) 641 rc = 0; 642 else { 643 /* force port into known state */ 644 sil24_init_port(ap); 645 646 if (irq_stat & PORT_IRQ_ERROR) 647 rc = -EIO; 648 else 649 rc = -EBUSY; 650 } 651 652 /* restore IRQ enabled */ 653 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET); 654 655 return rc; 656 } 657 658 static int sil24_do_softreset(struct ata_link *link, unsigned int *class, 659 int pmp, unsigned long deadline) 660 { 661 struct ata_port *ap = link->ap; 662 unsigned long timeout_msec = 0; 663 struct ata_taskfile tf; 664 const char *reason; 665 int rc; 666 667 DPRINTK("ENTER\n"); 668 669 if (ata_link_offline(link)) { 670 DPRINTK("PHY reports no device\n"); 671 *class = ATA_DEV_NONE; 672 goto out; 673 } 674 675 /* put the port into known state */ 676 if (sil24_init_port(ap)) { 677 reason ="port not ready"; 678 goto err; 679 } 680 681 /* do SRST */ 682 if (time_after(deadline, jiffies)) 683 timeout_msec = jiffies_to_msecs(deadline - jiffies); 684 685 ata_tf_init(link->device, &tf); /* doesn't really matter */ 686 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST, 687 timeout_msec); 688 if (rc == -EBUSY) { 689 reason = "timeout"; 690 goto err; 691 } else if (rc) { 692 reason = "SRST command error"; 693 goto err; 694 } 695 696 sil24_read_tf(ap, 0, &tf); 697 *class = ata_dev_classify(&tf); 698 699 if (*class == ATA_DEV_UNKNOWN) 700 *class = ATA_DEV_NONE; 701 702 out: 703 DPRINTK("EXIT, class=%u\n", *class); 704 return 0; 705 706 err: 707 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 708 return -EIO; 709 } 710 711 static int sil24_softreset(struct ata_link *link, unsigned int *class, 712 unsigned long deadline) 713 { 714 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline); 715 } 716 717 static int sil24_hardreset(struct ata_link *link, unsigned int *class, 718 unsigned long deadline) 719 { 720 struct ata_port *ap = link->ap; 721 void __iomem *port = ap->ioaddr.cmd_addr; 722 struct sil24_port_priv *pp = ap->private_data; 723 int did_port_rst = 0; 724 const char *reason; 725 int tout_msec, rc; 726 u32 tmp; 727 728 retry: 729 /* Sometimes, DEV_RST is not enough to recover the controller. 730 * This happens often after PM DMA CS errata. 731 */ 732 if (pp->do_port_rst) { 733 ata_port_printk(ap, KERN_WARNING, "controller in dubious " 734 "state, performing PORT_RST\n"); 735 736 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT); 737 msleep(10); 738 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); 739 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0, 740 10, 5000); 741 742 /* restore port configuration */ 743 sil24_config_port(ap); 744 sil24_config_pmp(ap, ap->nr_pmp_links); 745 746 pp->do_port_rst = 0; 747 did_port_rst = 1; 748 } 749 750 /* sil24 does the right thing(tm) without any protection */ 751 sata_set_spd(link); 752 753 tout_msec = 100; 754 if (ata_link_online(link)) 755 tout_msec = 5000; 756 757 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); 758 tmp = ata_wait_register(port + PORT_CTRL_STAT, 759 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec); 760 761 /* SStatus oscillates between zero and valid status after 762 * DEV_RST, debounce it. 763 */ 764 rc = sata_link_debounce(link, sata_deb_timing_long, deadline); 765 if (rc) { 766 reason = "PHY debouncing failed"; 767 goto err; 768 } 769 770 if (tmp & PORT_CS_DEV_RST) { 771 if (ata_link_offline(link)) 772 return 0; 773 reason = "link not ready"; 774 goto err; 775 } 776 777 /* Sil24 doesn't store signature FIS after hardreset, so we 778 * can't wait for BSY to clear. Some devices take a long time 779 * to get ready and those devices will choke if we don't wait 780 * for BSY clearance here. Tell libata to perform follow-up 781 * softreset. 782 */ 783 return -EAGAIN; 784 785 err: 786 if (!did_port_rst) { 787 pp->do_port_rst = 1; 788 goto retry; 789 } 790 791 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason); 792 return -EIO; 793 } 794 795 static inline void sil24_fill_sg(struct ata_queued_cmd *qc, 796 struct sil24_sge *sge) 797 { 798 struct scatterlist *sg; 799 800 ata_for_each_sg(sg, qc) { 801 sge->addr = cpu_to_le64(sg_dma_address(sg)); 802 sge->cnt = cpu_to_le32(sg_dma_len(sg)); 803 if (ata_sg_is_last(sg, qc)) 804 sge->flags = cpu_to_le32(SGE_TRM); 805 else 806 sge->flags = 0; 807 sge++; 808 } 809 } 810 811 static int sil24_qc_defer(struct ata_queued_cmd *qc) 812 { 813 struct ata_link *link = qc->dev->link; 814 struct ata_port *ap = link->ap; 815 u8 prot = qc->tf.protocol; 816 int is_atapi = (prot == ATA_PROT_ATAPI || 817 prot == ATA_PROT_ATAPI_NODATA || 818 prot == ATA_PROT_ATAPI_DMA); 819 820 /* ATAPI commands completing with CHECK_SENSE cause various 821 * weird problems if other commands are active. PMP DMA CS 822 * errata doesn't cover all and HSM violation occurs even with 823 * only one other device active. Always run an ATAPI command 824 * by itself. 825 */ 826 if (unlikely(ap->excl_link)) { 827 if (link == ap->excl_link) { 828 if (ap->nr_active_links) 829 return ATA_DEFER_PORT; 830 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 831 } else 832 return ATA_DEFER_PORT; 833 } else if (unlikely(is_atapi)) { 834 ap->excl_link = link; 835 if (ap->nr_active_links) 836 return ATA_DEFER_PORT; 837 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 838 } 839 840 return ata_std_qc_defer(qc); 841 } 842 843 static void sil24_qc_prep(struct ata_queued_cmd *qc) 844 { 845 struct ata_port *ap = qc->ap; 846 struct sil24_port_priv *pp = ap->private_data; 847 union sil24_cmd_block *cb; 848 struct sil24_prb *prb; 849 struct sil24_sge *sge; 850 u16 ctrl = 0; 851 852 cb = &pp->cmd_block[sil24_tag(qc->tag)]; 853 854 switch (qc->tf.protocol) { 855 case ATA_PROT_PIO: 856 case ATA_PROT_DMA: 857 case ATA_PROT_NCQ: 858 case ATA_PROT_NODATA: 859 prb = &cb->ata.prb; 860 sge = cb->ata.sge; 861 break; 862 863 case ATA_PROT_ATAPI: 864 case ATA_PROT_ATAPI_DMA: 865 case ATA_PROT_ATAPI_NODATA: 866 prb = &cb->atapi.prb; 867 sge = cb->atapi.sge; 868 memset(cb->atapi.cdb, 0, 32); 869 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); 870 871 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { 872 if (qc->tf.flags & ATA_TFLAG_WRITE) 873 ctrl = PRB_CTRL_PACKET_WRITE; 874 else 875 ctrl = PRB_CTRL_PACKET_READ; 876 } 877 break; 878 879 default: 880 prb = NULL; /* shut up, gcc */ 881 sge = NULL; 882 BUG(); 883 } 884 885 prb->ctrl = cpu_to_le16(ctrl); 886 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis); 887 888 if (qc->flags & ATA_QCFLAG_DMAMAP) 889 sil24_fill_sg(qc, sge); 890 } 891 892 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) 893 { 894 struct ata_port *ap = qc->ap; 895 struct sil24_port_priv *pp = ap->private_data; 896 void __iomem *port = ap->ioaddr.cmd_addr; 897 unsigned int tag = sil24_tag(qc->tag); 898 dma_addr_t paddr; 899 void __iomem *activate; 900 901 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); 902 activate = port + PORT_CMD_ACTIVATE + tag * 8; 903 904 writel((u32)paddr, activate); 905 writel((u64)paddr >> 32, activate + 4); 906 907 return 0; 908 } 909 910 static void sil24_irq_clear(struct ata_port *ap) 911 { 912 /* unused */ 913 } 914 915 static void sil24_pmp_attach(struct ata_port *ap) 916 { 917 sil24_config_pmp(ap, 1); 918 sil24_init_port(ap); 919 } 920 921 static void sil24_pmp_detach(struct ata_port *ap) 922 { 923 sil24_init_port(ap); 924 sil24_config_pmp(ap, 0); 925 } 926 927 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class, 928 unsigned long deadline) 929 { 930 return sil24_do_softreset(link, class, link->pmp, deadline); 931 } 932 933 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, 934 unsigned long deadline) 935 { 936 int rc; 937 938 rc = sil24_init_port(link->ap); 939 if (rc) { 940 ata_link_printk(link, KERN_ERR, 941 "hardreset failed (port not ready)\n"); 942 return rc; 943 } 944 945 return sata_pmp_std_hardreset(link, class, deadline); 946 } 947 948 static void sil24_freeze(struct ata_port *ap) 949 { 950 void __iomem *port = ap->ioaddr.cmd_addr; 951 952 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear 953 * PORT_IRQ_ENABLE instead. 954 */ 955 writel(0xffff, port + PORT_IRQ_ENABLE_CLR); 956 } 957 958 static void sil24_thaw(struct ata_port *ap) 959 { 960 void __iomem *port = ap->ioaddr.cmd_addr; 961 u32 tmp; 962 963 /* clear IRQ */ 964 tmp = readl(port + PORT_IRQ_STAT); 965 writel(tmp, port + PORT_IRQ_STAT); 966 967 /* turn IRQ back on */ 968 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); 969 } 970 971 static void sil24_error_intr(struct ata_port *ap) 972 { 973 void __iomem *port = ap->ioaddr.cmd_addr; 974 struct sil24_port_priv *pp = ap->private_data; 975 struct ata_queued_cmd *qc = NULL; 976 struct ata_link *link; 977 struct ata_eh_info *ehi; 978 int abort = 0, freeze = 0; 979 u32 irq_stat; 980 981 /* on error, we need to clear IRQ explicitly */ 982 irq_stat = readl(port + PORT_IRQ_STAT); 983 writel(irq_stat, port + PORT_IRQ_STAT); 984 985 /* first, analyze and record host port events */ 986 link = &ap->link; 987 ehi = &link->eh_info; 988 ata_ehi_clear_desc(ehi); 989 990 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); 991 992 if (irq_stat & PORT_IRQ_SDB_NOTIFY) { 993 ata_ehi_push_desc(ehi, "SDB notify"); 994 sata_async_notification(ap); 995 } 996 997 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { 998 ata_ehi_hotplugged(ehi); 999 ata_ehi_push_desc(ehi, "%s", 1000 irq_stat & PORT_IRQ_PHYRDY_CHG ? 1001 "PHY RDY changed" : "device exchanged"); 1002 freeze = 1; 1003 } 1004 1005 if (irq_stat & PORT_IRQ_UNK_FIS) { 1006 ehi->err_mask |= AC_ERR_HSM; 1007 ehi->action |= ATA_EH_SOFTRESET; 1008 ata_ehi_push_desc(ehi, "unknown FIS"); 1009 freeze = 1; 1010 } 1011 1012 /* deal with command error */ 1013 if (irq_stat & PORT_IRQ_ERROR) { 1014 struct sil24_cerr_info *ci = NULL; 1015 unsigned int err_mask = 0, action = 0; 1016 u32 context, cerr; 1017 int pmp; 1018 1019 abort = 1; 1020 1021 /* DMA Context Switch Failure in Port Multiplier Mode 1022 * errata. If we have active commands to 3 or more 1023 * devices, any error condition on active devices can 1024 * corrupt DMA context switching. 1025 */ 1026 if (ap->nr_active_links >= 3) { 1027 ehi->err_mask |= AC_ERR_OTHER; 1028 ehi->action |= ATA_EH_HARDRESET; 1029 ata_ehi_push_desc(ehi, "PMP DMA CS errata"); 1030 pp->do_port_rst = 1; 1031 freeze = 1; 1032 } 1033 1034 /* find out the offending link and qc */ 1035 if (ap->nr_pmp_links) { 1036 context = readl(port + PORT_CONTEXT); 1037 pmp = (context >> 5) & 0xf; 1038 1039 if (pmp < ap->nr_pmp_links) { 1040 link = &ap->pmp_link[pmp]; 1041 ehi = &link->eh_info; 1042 qc = ata_qc_from_tag(ap, link->active_tag); 1043 1044 ata_ehi_clear_desc(ehi); 1045 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", 1046 irq_stat); 1047 } else { 1048 err_mask |= AC_ERR_HSM; 1049 action |= ATA_EH_HARDRESET; 1050 freeze = 1; 1051 } 1052 } else 1053 qc = ata_qc_from_tag(ap, link->active_tag); 1054 1055 /* analyze CMD_ERR */ 1056 cerr = readl(port + PORT_CMD_ERR); 1057 if (cerr < ARRAY_SIZE(sil24_cerr_db)) 1058 ci = &sil24_cerr_db[cerr]; 1059 1060 if (ci && ci->desc) { 1061 err_mask |= ci->err_mask; 1062 action |= ci->action; 1063 ata_ehi_push_desc(ehi, "%s", ci->desc); 1064 } else { 1065 err_mask |= AC_ERR_OTHER; 1066 action |= ATA_EH_SOFTRESET; 1067 ata_ehi_push_desc(ehi, "unknown command error %d", 1068 cerr); 1069 } 1070 1071 /* record error info */ 1072 if (qc) { 1073 sil24_read_tf(ap, qc->tag, &pp->tf); 1074 qc->err_mask |= err_mask; 1075 } else 1076 ehi->err_mask |= err_mask; 1077 1078 ehi->action |= action; 1079 1080 /* if PMP, resume */ 1081 if (ap->nr_pmp_links) 1082 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT); 1083 } 1084 1085 /* freeze or abort */ 1086 if (freeze) 1087 ata_port_freeze(ap); 1088 else if (abort) { 1089 if (qc) 1090 ata_link_abort(qc->dev->link); 1091 else 1092 ata_port_abort(ap); 1093 } 1094 } 1095 1096 static void sil24_finish_qc(struct ata_queued_cmd *qc) 1097 { 1098 struct ata_port *ap = qc->ap; 1099 struct sil24_port_priv *pp = ap->private_data; 1100 1101 if (qc->flags & ATA_QCFLAG_RESULT_TF) 1102 sil24_read_tf(ap, qc->tag, &pp->tf); 1103 } 1104 1105 static inline void sil24_host_intr(struct ata_port *ap) 1106 { 1107 void __iomem *port = ap->ioaddr.cmd_addr; 1108 u32 slot_stat, qc_active; 1109 int rc; 1110 1111 /* If PCIX_IRQ_WOC, there's an inherent race window between 1112 * clearing IRQ pending status and reading PORT_SLOT_STAT 1113 * which may cause spurious interrupts afterwards. This is 1114 * unavoidable and much better than losing interrupts which 1115 * happens if IRQ pending is cleared after reading 1116 * PORT_SLOT_STAT. 1117 */ 1118 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) 1119 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); 1120 1121 slot_stat = readl(port + PORT_SLOT_STAT); 1122 1123 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { 1124 sil24_error_intr(ap); 1125 return; 1126 } 1127 1128 qc_active = slot_stat & ~HOST_SSTAT_ATTN; 1129 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc); 1130 if (rc > 0) 1131 return; 1132 if (rc < 0) { 1133 struct ata_eh_info *ehi = &ap->link.eh_info; 1134 ehi->err_mask |= AC_ERR_HSM; 1135 ehi->action |= ATA_EH_SOFTRESET; 1136 ata_port_freeze(ap); 1137 return; 1138 } 1139 1140 /* spurious interrupts are expected if PCIX_IRQ_WOC */ 1141 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit()) 1142 ata_port_printk(ap, KERN_INFO, "spurious interrupt " 1143 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", 1144 slot_stat, ap->link.active_tag, ap->link.sactive); 1145 } 1146 1147 static irqreturn_t sil24_interrupt(int irq, void *dev_instance) 1148 { 1149 struct ata_host *host = dev_instance; 1150 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1151 unsigned handled = 0; 1152 u32 status; 1153 int i; 1154 1155 status = readl(host_base + HOST_IRQ_STAT); 1156 1157 if (status == 0xffffffff) { 1158 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " 1159 "PCI fault or device removal?\n"); 1160 goto out; 1161 } 1162 1163 if (!(status & IRQ_STAT_4PORTS)) 1164 goto out; 1165 1166 spin_lock(&host->lock); 1167 1168 for (i = 0; i < host->n_ports; i++) 1169 if (status & (1 << i)) { 1170 struct ata_port *ap = host->ports[i]; 1171 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { 1172 sil24_host_intr(ap); 1173 handled++; 1174 } else 1175 printk(KERN_ERR DRV_NAME 1176 ": interrupt from disabled port %d\n", i); 1177 } 1178 1179 spin_unlock(&host->lock); 1180 out: 1181 return IRQ_RETVAL(handled); 1182 } 1183 1184 static void sil24_error_handler(struct ata_port *ap) 1185 { 1186 struct sil24_port_priv *pp = ap->private_data; 1187 1188 if (sil24_init_port(ap)) 1189 ata_eh_freeze_port(ap); 1190 1191 /* perform recovery */ 1192 sata_pmp_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset, 1193 ata_std_postreset, sata_pmp_std_prereset, 1194 sil24_pmp_softreset, sil24_pmp_hardreset, 1195 sata_pmp_std_postreset); 1196 1197 pp->do_port_rst = 0; 1198 } 1199 1200 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) 1201 { 1202 struct ata_port *ap = qc->ap; 1203 1204 /* make DMA engine forget about the failed command */ 1205 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap)) 1206 ata_eh_freeze_port(ap); 1207 } 1208 1209 static int sil24_port_start(struct ata_port *ap) 1210 { 1211 struct device *dev = ap->host->dev; 1212 struct sil24_port_priv *pp; 1213 union sil24_cmd_block *cb; 1214 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; 1215 dma_addr_t cb_dma; 1216 int rc; 1217 1218 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1219 if (!pp) 1220 return -ENOMEM; 1221 1222 pp->tf.command = ATA_DRDY; 1223 1224 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); 1225 if (!cb) 1226 return -ENOMEM; 1227 memset(cb, 0, cb_size); 1228 1229 rc = ata_pad_alloc(ap, dev); 1230 if (rc) 1231 return rc; 1232 1233 pp->cmd_block = cb; 1234 pp->cmd_block_dma = cb_dma; 1235 1236 ap->private_data = pp; 1237 1238 return 0; 1239 } 1240 1241 static void sil24_init_controller(struct ata_host *host) 1242 { 1243 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1244 u32 tmp; 1245 int i; 1246 1247 /* GPIO off */ 1248 writel(0, host_base + HOST_FLASH_CMD); 1249 1250 /* clear global reset & mask interrupts during initialization */ 1251 writel(0, host_base + HOST_CTRL); 1252 1253 /* init ports */ 1254 for (i = 0; i < host->n_ports; i++) { 1255 struct ata_port *ap = host->ports[i]; 1256 void __iomem *port = ap->ioaddr.cmd_addr; 1257 1258 /* Initial PHY setting */ 1259 writel(0x20c, port + PORT_PHY_CFG); 1260 1261 /* Clear port RST */ 1262 tmp = readl(port + PORT_CTRL_STAT); 1263 if (tmp & PORT_CS_PORT_RST) { 1264 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); 1265 tmp = ata_wait_register(port + PORT_CTRL_STAT, 1266 PORT_CS_PORT_RST, 1267 PORT_CS_PORT_RST, 10, 100); 1268 if (tmp & PORT_CS_PORT_RST) 1269 dev_printk(KERN_ERR, host->dev, 1270 "failed to clear port RST\n"); 1271 } 1272 1273 /* configure port */ 1274 sil24_config_port(ap); 1275 } 1276 1277 /* Turn on interrupts */ 1278 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); 1279 } 1280 1281 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1282 { 1283 static int printed_version = 0; 1284 struct ata_port_info pi = sil24_port_info[ent->driver_data]; 1285 const struct ata_port_info *ppi[] = { &pi, NULL }; 1286 void __iomem * const *iomap; 1287 struct ata_host *host; 1288 int i, rc; 1289 u32 tmp; 1290 1291 if (!printed_version++) 1292 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1293 1294 /* acquire resources */ 1295 rc = pcim_enable_device(pdev); 1296 if (rc) 1297 return rc; 1298 1299 rc = pcim_iomap_regions(pdev, 1300 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), 1301 DRV_NAME); 1302 if (rc) 1303 return rc; 1304 iomap = pcim_iomap_table(pdev); 1305 1306 /* apply workaround for completion IRQ loss on PCI-X errata */ 1307 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) { 1308 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL); 1309 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) 1310 dev_printk(KERN_INFO, &pdev->dev, 1311 "Applying completion IRQ loss on PCI-X " 1312 "errata fix\n"); 1313 else 1314 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; 1315 } 1316 1317 /* allocate and fill host */ 1318 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1319 SIL24_FLAG2NPORTS(ppi[0]->flags)); 1320 if (!host) 1321 return -ENOMEM; 1322 host->iomap = iomap; 1323 1324 for (i = 0; i < host->n_ports; i++) { 1325 struct ata_port *ap = host->ports[i]; 1326 size_t offset = ap->port_no * PORT_REGS_SIZE; 1327 void __iomem *port = iomap[SIL24_PORT_BAR] + offset; 1328 1329 host->ports[i]->ioaddr.cmd_addr = port; 1330 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL; 1331 1332 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host"); 1333 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port"); 1334 } 1335 1336 /* configure and activate the device */ 1337 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 1338 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1339 if (rc) { 1340 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1341 if (rc) { 1342 dev_printk(KERN_ERR, &pdev->dev, 1343 "64-bit DMA enable failed\n"); 1344 return rc; 1345 } 1346 } 1347 } else { 1348 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1349 if (rc) { 1350 dev_printk(KERN_ERR, &pdev->dev, 1351 "32-bit DMA enable failed\n"); 1352 return rc; 1353 } 1354 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1355 if (rc) { 1356 dev_printk(KERN_ERR, &pdev->dev, 1357 "32-bit consistent DMA enable failed\n"); 1358 return rc; 1359 } 1360 } 1361 1362 sil24_init_controller(host); 1363 1364 pci_set_master(pdev); 1365 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED, 1366 &sil24_sht); 1367 } 1368 1369 #ifdef CONFIG_PM 1370 static int sil24_pci_device_resume(struct pci_dev *pdev) 1371 { 1372 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1373 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1374 int rc; 1375 1376 rc = ata_pci_device_do_resume(pdev); 1377 if (rc) 1378 return rc; 1379 1380 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) 1381 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); 1382 1383 sil24_init_controller(host); 1384 1385 ata_host_resume(host); 1386 1387 return 0; 1388 } 1389 1390 static int sil24_port_resume(struct ata_port *ap) 1391 { 1392 sil24_config_pmp(ap, ap->nr_pmp_links); 1393 return 0; 1394 } 1395 #endif 1396 1397 static int __init sil24_init(void) 1398 { 1399 return pci_register_driver(&sil24_pci_driver); 1400 } 1401 1402 static void __exit sil24_exit(void) 1403 { 1404 pci_unregister_driver(&sil24_pci_driver); 1405 } 1406 1407 MODULE_AUTHOR("Tejun Heo"); 1408 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); 1409 MODULE_LICENSE("GPL"); 1410 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); 1411 1412 module_init(sil24_init); 1413 module_exit(sil24_exit); 1414