1 /* 2 * sata_promise.c - Promise SATA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Mikael Pettersson <mikpe@it.uu.se> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2003-2004 Red Hat, Inc. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * 27 * libata documentation is available via 'make {ps|pdf}docs', 28 * as Documentation/DocBook/libata.* 29 * 30 * Hardware information only available under NDA. 31 * 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/init.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/device.h> 42 #include <scsi/scsi.h> 43 #include <scsi/scsi_host.h> 44 #include <scsi/scsi_cmnd.h> 45 #include <linux/libata.h> 46 #include "sata_promise.h" 47 48 #define DRV_NAME "sata_promise" 49 #define DRV_VERSION "2.11" 50 51 enum { 52 PDC_MAX_PORTS = 4, 53 PDC_MMIO_BAR = 3, 54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ 55 56 /* register offsets */ 57 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ 58 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ 59 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ 60 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ 61 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ 62 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ 63 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ 64 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ 65 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ 66 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ 67 PDC_FLASH_CTL = 0x44, /* Flash control register */ 68 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ 69 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ 70 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ 71 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ 72 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ 73 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ 74 75 /* PDC_GLOBAL_CTL bit definitions */ 76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ 77 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ 78 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ 79 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ 80 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ 81 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ 82 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ 83 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ 84 PDC_DRIVE_ERR = (1 << 21), /* drive error */ 85 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ 86 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ 87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, 88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | 89 PDC2_ATA_DMA_CNT_ERR, 90 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | 91 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR | 92 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | 93 PDC1_ERR_MASK | PDC2_ERR_MASK, 94 95 board_2037x = 0, /* FastTrak S150 TX2plus */ 96 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ 97 board_20319 = 2, /* FastTrak S150 TX4 */ 98 board_20619 = 3, /* FastTrak TX4000 */ 99 board_2057x = 4, /* SATAII150 Tx2plus */ 100 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ 101 board_40518 = 6, /* SATAII150 Tx4 */ 102 103 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ 104 105 /* Sequence counter control registers bit definitions */ 106 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ 107 108 /* Feature register values */ 109 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ 110 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ 111 112 /* Device/Head register values */ 113 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ 114 115 /* PDC_CTLSTAT bit definitions */ 116 PDC_DMA_ENABLE = (1 << 7), 117 PDC_IRQ_DISABLE = (1 << 10), 118 PDC_RESET = (1 << 11), /* HDMA reset */ 119 120 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | 121 ATA_FLAG_MMIO | 122 ATA_FLAG_PIO_POLLING, 123 124 /* ap->flags bits */ 125 PDC_FLAG_GEN_II = (1 << 24), 126 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ 127 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ 128 }; 129 130 struct pdc_port_priv { 131 u8 *pkt; 132 dma_addr_t pkt_dma; 133 }; 134 135 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); 136 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); 137 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 138 static int pdc_common_port_start(struct ata_port *ap); 139 static int pdc_sata_port_start(struct ata_port *ap); 140 static void pdc_qc_prep(struct ata_queued_cmd *qc); 141 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 142 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 143 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); 144 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); 145 static void pdc_irq_clear(struct ata_port *ap); 146 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); 147 static void pdc_freeze(struct ata_port *ap); 148 static void pdc_thaw(struct ata_port *ap); 149 static void pdc_pata_error_handler(struct ata_port *ap); 150 static void pdc_sata_error_handler(struct ata_port *ap); 151 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); 152 static int pdc_pata_cable_detect(struct ata_port *ap); 153 static int pdc_sata_cable_detect(struct ata_port *ap); 154 155 static struct scsi_host_template pdc_ata_sht = { 156 .module = THIS_MODULE, 157 .name = DRV_NAME, 158 .ioctl = ata_scsi_ioctl, 159 .queuecommand = ata_scsi_queuecmd, 160 .can_queue = ATA_DEF_QUEUE, 161 .this_id = ATA_SHT_THIS_ID, 162 .sg_tablesize = PDC_MAX_PRD, 163 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 164 .emulated = ATA_SHT_EMULATED, 165 .use_clustering = ATA_SHT_USE_CLUSTERING, 166 .proc_name = DRV_NAME, 167 .dma_boundary = ATA_DMA_BOUNDARY, 168 .slave_configure = ata_scsi_slave_config, 169 .slave_destroy = ata_scsi_slave_destroy, 170 .bios_param = ata_std_bios_param, 171 }; 172 173 static const struct ata_port_operations pdc_sata_ops = { 174 .tf_load = pdc_tf_load_mmio, 175 .tf_read = ata_tf_read, 176 .check_status = ata_check_status, 177 .exec_command = pdc_exec_command_mmio, 178 .dev_select = ata_std_dev_select, 179 .check_atapi_dma = pdc_check_atapi_dma, 180 181 .qc_prep = pdc_qc_prep, 182 .qc_issue = pdc_qc_issue_prot, 183 .freeze = pdc_freeze, 184 .thaw = pdc_thaw, 185 .error_handler = pdc_sata_error_handler, 186 .post_internal_cmd = pdc_post_internal_cmd, 187 .cable_detect = pdc_sata_cable_detect, 188 .data_xfer = ata_data_xfer, 189 .irq_clear = pdc_irq_clear, 190 .irq_on = ata_irq_on, 191 192 .scr_read = pdc_sata_scr_read, 193 .scr_write = pdc_sata_scr_write, 194 .port_start = pdc_sata_port_start, 195 }; 196 197 /* First-generation chips need a more restrictive ->check_atapi_dma op */ 198 static const struct ata_port_operations pdc_old_sata_ops = { 199 .tf_load = pdc_tf_load_mmio, 200 .tf_read = ata_tf_read, 201 .check_status = ata_check_status, 202 .exec_command = pdc_exec_command_mmio, 203 .dev_select = ata_std_dev_select, 204 .check_atapi_dma = pdc_old_sata_check_atapi_dma, 205 206 .qc_prep = pdc_qc_prep, 207 .qc_issue = pdc_qc_issue_prot, 208 .freeze = pdc_freeze, 209 .thaw = pdc_thaw, 210 .error_handler = pdc_sata_error_handler, 211 .post_internal_cmd = pdc_post_internal_cmd, 212 .cable_detect = pdc_sata_cable_detect, 213 .data_xfer = ata_data_xfer, 214 .irq_clear = pdc_irq_clear, 215 .irq_on = ata_irq_on, 216 217 .scr_read = pdc_sata_scr_read, 218 .scr_write = pdc_sata_scr_write, 219 .port_start = pdc_sata_port_start, 220 }; 221 222 static const struct ata_port_operations pdc_pata_ops = { 223 .tf_load = pdc_tf_load_mmio, 224 .tf_read = ata_tf_read, 225 .check_status = ata_check_status, 226 .exec_command = pdc_exec_command_mmio, 227 .dev_select = ata_std_dev_select, 228 .check_atapi_dma = pdc_check_atapi_dma, 229 230 .qc_prep = pdc_qc_prep, 231 .qc_issue = pdc_qc_issue_prot, 232 .freeze = pdc_freeze, 233 .thaw = pdc_thaw, 234 .error_handler = pdc_pata_error_handler, 235 .post_internal_cmd = pdc_post_internal_cmd, 236 .cable_detect = pdc_pata_cable_detect, 237 .data_xfer = ata_data_xfer, 238 .irq_clear = pdc_irq_clear, 239 .irq_on = ata_irq_on, 240 241 .port_start = pdc_common_port_start, 242 }; 243 244 static const struct ata_port_info pdc_port_info[] = { 245 [board_2037x] = 246 { 247 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 248 PDC_FLAG_SATA_PATA, 249 .pio_mask = 0x1f, /* pio0-4 */ 250 .mwdma_mask = 0x07, /* mwdma0-2 */ 251 .udma_mask = ATA_UDMA6, 252 .port_ops = &pdc_old_sata_ops, 253 }, 254 255 [board_2037x_pata] = 256 { 257 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, 258 .pio_mask = 0x1f, /* pio0-4 */ 259 .mwdma_mask = 0x07, /* mwdma0-2 */ 260 .udma_mask = ATA_UDMA6, 261 .port_ops = &pdc_pata_ops, 262 }, 263 264 [board_20319] = 265 { 266 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 267 PDC_FLAG_4_PORTS, 268 .pio_mask = 0x1f, /* pio0-4 */ 269 .mwdma_mask = 0x07, /* mwdma0-2 */ 270 .udma_mask = ATA_UDMA6, 271 .port_ops = &pdc_old_sata_ops, 272 }, 273 274 [board_20619] = 275 { 276 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 277 PDC_FLAG_4_PORTS, 278 .pio_mask = 0x1f, /* pio0-4 */ 279 .mwdma_mask = 0x07, /* mwdma0-2 */ 280 .udma_mask = ATA_UDMA6, 281 .port_ops = &pdc_pata_ops, 282 }, 283 284 [board_2057x] = 285 { 286 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 287 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, 288 .pio_mask = 0x1f, /* pio0-4 */ 289 .mwdma_mask = 0x07, /* mwdma0-2 */ 290 .udma_mask = ATA_UDMA6, 291 .port_ops = &pdc_sata_ops, 292 }, 293 294 [board_2057x_pata] = 295 { 296 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | 297 PDC_FLAG_GEN_II, 298 .pio_mask = 0x1f, /* pio0-4 */ 299 .mwdma_mask = 0x07, /* mwdma0-2 */ 300 .udma_mask = ATA_UDMA6, 301 .port_ops = &pdc_pata_ops, 302 }, 303 304 [board_40518] = 305 { 306 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | 307 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, 308 .pio_mask = 0x1f, /* pio0-4 */ 309 .mwdma_mask = 0x07, /* mwdma0-2 */ 310 .udma_mask = ATA_UDMA6, 311 .port_ops = &pdc_sata_ops, 312 }, 313 }; 314 315 static const struct pci_device_id pdc_ata_pci_tbl[] = { 316 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, 317 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, 318 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, 319 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, 320 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, 321 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, 322 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, 323 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, 324 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, 325 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, 326 327 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, 328 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, 329 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, 330 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, 331 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, 332 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, 333 334 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, 335 336 { } /* terminate list */ 337 }; 338 339 static struct pci_driver pdc_ata_pci_driver = { 340 .name = DRV_NAME, 341 .id_table = pdc_ata_pci_tbl, 342 .probe = pdc_ata_init_one, 343 .remove = ata_pci_remove_one, 344 }; 345 346 static int pdc_common_port_start(struct ata_port *ap) 347 { 348 struct device *dev = ap->host->dev; 349 struct pdc_port_priv *pp; 350 int rc; 351 352 rc = ata_port_start(ap); 353 if (rc) 354 return rc; 355 356 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 357 if (!pp) 358 return -ENOMEM; 359 360 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); 361 if (!pp->pkt) 362 return -ENOMEM; 363 364 ap->private_data = pp; 365 366 return 0; 367 } 368 369 static int pdc_sata_port_start(struct ata_port *ap) 370 { 371 int rc; 372 373 rc = pdc_common_port_start(ap); 374 if (rc) 375 return rc; 376 377 /* fix up PHYMODE4 align timing */ 378 if (ap->flags & PDC_FLAG_GEN_II) { 379 void __iomem *mmio = ap->ioaddr.scr_addr; 380 unsigned int tmp; 381 382 tmp = readl(mmio + 0x014); 383 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ 384 writel(tmp, mmio + 0x014); 385 } 386 387 return 0; 388 } 389 390 static void pdc_reset_port(struct ata_port *ap) 391 { 392 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; 393 unsigned int i; 394 u32 tmp; 395 396 for (i = 11; i > 0; i--) { 397 tmp = readl(mmio); 398 if (tmp & PDC_RESET) 399 break; 400 401 udelay(100); 402 403 tmp |= PDC_RESET; 404 writel(tmp, mmio); 405 } 406 407 tmp &= ~PDC_RESET; 408 writel(tmp, mmio); 409 readl(mmio); /* flush */ 410 } 411 412 static int pdc_pata_cable_detect(struct ata_port *ap) 413 { 414 u8 tmp; 415 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; 416 417 tmp = readb(mmio); 418 if (tmp & 0x01) 419 return ATA_CBL_PATA40; 420 return ATA_CBL_PATA80; 421 } 422 423 static int pdc_sata_cable_detect(struct ata_port *ap) 424 { 425 return ATA_CBL_SATA; 426 } 427 428 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) 429 { 430 if (sc_reg > SCR_CONTROL) 431 return -EINVAL; 432 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4)); 433 return 0; 434 } 435 436 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) 437 { 438 if (sc_reg > SCR_CONTROL) 439 return -EINVAL; 440 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 441 return 0; 442 } 443 444 static void pdc_atapi_pkt(struct ata_queued_cmd *qc) 445 { 446 struct ata_port *ap = qc->ap; 447 dma_addr_t sg_table = ap->prd_dma; 448 unsigned int cdb_len = qc->dev->cdb_len; 449 u8 *cdb = qc->cdb; 450 struct pdc_port_priv *pp = ap->private_data; 451 u8 *buf = pp->pkt; 452 u32 *buf32 = (u32 *) buf; 453 unsigned int dev_sel, feature; 454 455 /* set control bits (byte 0), zero delay seq id (byte 3), 456 * and seq id (byte 2) 457 */ 458 switch (qc->tf.protocol) { 459 case ATAPI_PROT_DMA: 460 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 461 buf32[0] = cpu_to_le32(PDC_PKT_READ); 462 else 463 buf32[0] = 0; 464 break; 465 case ATAPI_PROT_NODATA: 466 buf32[0] = cpu_to_le32(PDC_PKT_NODATA); 467 break; 468 default: 469 BUG(); 470 break; 471 } 472 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ 473 buf32[2] = 0; /* no next-packet */ 474 475 /* select drive */ 476 if (sata_scr_valid(&ap->link)) 477 dev_sel = PDC_DEVICE_SATA; 478 else 479 dev_sel = qc->tf.device; 480 481 buf[12] = (1 << 5) | ATA_REG_DEVICE; 482 buf[13] = dev_sel; 483 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; 484 buf[15] = dev_sel; /* once more, waiting for BSY to clear */ 485 486 buf[16] = (1 << 5) | ATA_REG_NSECT; 487 buf[17] = qc->tf.nsect; 488 buf[18] = (1 << 5) | ATA_REG_LBAL; 489 buf[19] = qc->tf.lbal; 490 491 /* set feature and byte counter registers */ 492 if (qc->tf.protocol != ATAPI_PROT_DMA) 493 feature = PDC_FEATURE_ATAPI_PIO; 494 else 495 feature = PDC_FEATURE_ATAPI_DMA; 496 497 buf[20] = (1 << 5) | ATA_REG_FEATURE; 498 buf[21] = feature; 499 buf[22] = (1 << 5) | ATA_REG_BYTEL; 500 buf[23] = qc->tf.lbam; 501 buf[24] = (1 << 5) | ATA_REG_BYTEH; 502 buf[25] = qc->tf.lbah; 503 504 /* send ATAPI packet command 0xA0 */ 505 buf[26] = (1 << 5) | ATA_REG_CMD; 506 buf[27] = qc->tf.command; 507 508 /* select drive and check DRQ */ 509 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; 510 buf[29] = dev_sel; 511 512 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ 513 BUG_ON(cdb_len & ~0x1E); 514 515 /* append the CDB as the final part */ 516 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; 517 memcpy(buf+31, cdb, cdb_len); 518 } 519 520 /** 521 * pdc_fill_sg - Fill PCI IDE PRD table 522 * @qc: Metadata associated with taskfile to be transferred 523 * 524 * Fill PCI IDE PRD (scatter-gather) table with segments 525 * associated with the current disk command. 526 * Make sure hardware does not choke on it. 527 * 528 * LOCKING: 529 * spin_lock_irqsave(host lock) 530 * 531 */ 532 static void pdc_fill_sg(struct ata_queued_cmd *qc) 533 { 534 struct ata_port *ap = qc->ap; 535 struct scatterlist *sg; 536 const u32 SG_COUNT_ASIC_BUG = 41*4; 537 unsigned int si, idx; 538 u32 len; 539 540 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 541 return; 542 543 idx = 0; 544 for_each_sg(qc->sg, sg, qc->n_elem, si) { 545 u32 addr, offset; 546 u32 sg_len, len; 547 548 /* determine if physical DMA addr spans 64K boundary. 549 * Note h/w doesn't support 64-bit, so we unconditionally 550 * truncate dma_addr_t to u32. 551 */ 552 addr = (u32) sg_dma_address(sg); 553 sg_len = sg_dma_len(sg); 554 555 while (sg_len) { 556 offset = addr & 0xffff; 557 len = sg_len; 558 if ((offset + sg_len) > 0x10000) 559 len = 0x10000 - offset; 560 561 ap->prd[idx].addr = cpu_to_le32(addr); 562 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff); 563 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); 564 565 idx++; 566 sg_len -= len; 567 addr += len; 568 } 569 } 570 571 len = le32_to_cpu(ap->prd[idx - 1].flags_len); 572 573 if (len > SG_COUNT_ASIC_BUG) { 574 u32 addr; 575 576 VPRINTK("Splitting last PRD.\n"); 577 578 addr = le32_to_cpu(ap->prd[idx - 1].addr); 579 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG); 580 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG); 581 582 addr = addr + len - SG_COUNT_ASIC_BUG; 583 len = SG_COUNT_ASIC_BUG; 584 ap->prd[idx].addr = cpu_to_le32(addr); 585 ap->prd[idx].flags_len = cpu_to_le32(len); 586 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); 587 588 idx++; 589 } 590 591 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 592 } 593 594 static void pdc_qc_prep(struct ata_queued_cmd *qc) 595 { 596 struct pdc_port_priv *pp = qc->ap->private_data; 597 unsigned int i; 598 599 VPRINTK("ENTER\n"); 600 601 switch (qc->tf.protocol) { 602 case ATA_PROT_DMA: 603 pdc_fill_sg(qc); 604 /* fall through */ 605 606 case ATA_PROT_NODATA: 607 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, 608 qc->dev->devno, pp->pkt); 609 610 if (qc->tf.flags & ATA_TFLAG_LBA48) 611 i = pdc_prep_lba48(&qc->tf, pp->pkt, i); 612 else 613 i = pdc_prep_lba28(&qc->tf, pp->pkt, i); 614 615 pdc_pkt_footer(&qc->tf, pp->pkt, i); 616 break; 617 618 case ATAPI_PROT_PIO: 619 pdc_fill_sg(qc); 620 break; 621 622 case ATAPI_PROT_DMA: 623 pdc_fill_sg(qc); 624 /*FALLTHROUGH*/ 625 case ATAPI_PROT_NODATA: 626 pdc_atapi_pkt(qc); 627 break; 628 629 default: 630 break; 631 } 632 } 633 634 static void pdc_freeze(struct ata_port *ap) 635 { 636 void __iomem *mmio = ap->ioaddr.cmd_addr; 637 u32 tmp; 638 639 tmp = readl(mmio + PDC_CTLSTAT); 640 tmp |= PDC_IRQ_DISABLE; 641 tmp &= ~PDC_DMA_ENABLE; 642 writel(tmp, mmio + PDC_CTLSTAT); 643 readl(mmio + PDC_CTLSTAT); /* flush */ 644 } 645 646 static void pdc_thaw(struct ata_port *ap) 647 { 648 void __iomem *mmio = ap->ioaddr.cmd_addr; 649 u32 tmp; 650 651 /* clear IRQ */ 652 readl(mmio + PDC_INT_SEQMASK); 653 654 /* turn IRQ back on */ 655 tmp = readl(mmio + PDC_CTLSTAT); 656 tmp &= ~PDC_IRQ_DISABLE; 657 writel(tmp, mmio + PDC_CTLSTAT); 658 readl(mmio + PDC_CTLSTAT); /* flush */ 659 } 660 661 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset) 662 { 663 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 664 pdc_reset_port(ap); 665 666 /* perform recovery */ 667 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, 668 ata_std_postreset); 669 } 670 671 static void pdc_pata_error_handler(struct ata_port *ap) 672 { 673 pdc_common_error_handler(ap, NULL); 674 } 675 676 static void pdc_sata_error_handler(struct ata_port *ap) 677 { 678 pdc_common_error_handler(ap, sata_std_hardreset); 679 } 680 681 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) 682 { 683 struct ata_port *ap = qc->ap; 684 685 /* make DMA engine forget about the failed command */ 686 if (qc->flags & ATA_QCFLAG_FAILED) 687 pdc_reset_port(ap); 688 } 689 690 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, 691 u32 port_status, u32 err_mask) 692 { 693 struct ata_eh_info *ehi = &ap->link.eh_info; 694 unsigned int ac_err_mask = 0; 695 696 ata_ehi_clear_desc(ehi); 697 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); 698 port_status &= err_mask; 699 700 if (port_status & PDC_DRIVE_ERR) 701 ac_err_mask |= AC_ERR_DEV; 702 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) 703 ac_err_mask |= AC_ERR_HSM; 704 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) 705 ac_err_mask |= AC_ERR_ATA_BUS; 706 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR 707 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) 708 ac_err_mask |= AC_ERR_HOST_BUS; 709 710 if (sata_scr_valid(&ap->link)) { 711 u32 serror; 712 713 pdc_sata_scr_read(ap, SCR_ERROR, &serror); 714 ehi->serror |= serror; 715 } 716 717 qc->err_mask |= ac_err_mask; 718 719 pdc_reset_port(ap); 720 721 ata_port_abort(ap); 722 } 723 724 static inline unsigned int pdc_host_intr(struct ata_port *ap, 725 struct ata_queued_cmd *qc) 726 { 727 unsigned int handled = 0; 728 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 729 u32 port_status, err_mask; 730 731 err_mask = PDC_ERR_MASK; 732 if (ap->flags & PDC_FLAG_GEN_II) 733 err_mask &= ~PDC1_ERR_MASK; 734 else 735 err_mask &= ~PDC2_ERR_MASK; 736 port_status = readl(port_mmio + PDC_GLOBAL_CTL); 737 if (unlikely(port_status & err_mask)) { 738 pdc_error_intr(ap, qc, port_status, err_mask); 739 return 1; 740 } 741 742 switch (qc->tf.protocol) { 743 case ATA_PROT_DMA: 744 case ATA_PROT_NODATA: 745 case ATAPI_PROT_DMA: 746 case ATAPI_PROT_NODATA: 747 qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); 748 ata_qc_complete(qc); 749 handled = 1; 750 break; 751 752 default: 753 ap->stats.idle_irq++; 754 break; 755 } 756 757 return handled; 758 } 759 760 static void pdc_irq_clear(struct ata_port *ap) 761 { 762 struct ata_host *host = ap->host; 763 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 764 765 readl(mmio + PDC_INT_SEQMASK); 766 } 767 768 static int pdc_is_sataii_tx4(unsigned long flags) 769 { 770 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; 771 return (flags & mask) == mask; 772 } 773 774 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no, 775 int is_sataii_tx4) 776 { 777 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; 778 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; 779 } 780 781 static irqreturn_t pdc_interrupt(int irq, void *dev_instance) 782 { 783 struct ata_host *host = dev_instance; 784 struct ata_port *ap; 785 u32 mask = 0; 786 unsigned int i, tmp; 787 unsigned int handled = 0; 788 void __iomem *mmio_base; 789 unsigned int hotplug_offset, ata_no; 790 u32 hotplug_status; 791 int is_sataii_tx4; 792 793 VPRINTK("ENTER\n"); 794 795 if (!host || !host->iomap[PDC_MMIO_BAR]) { 796 VPRINTK("QUICK EXIT\n"); 797 return IRQ_NONE; 798 } 799 800 mmio_base = host->iomap[PDC_MMIO_BAR]; 801 802 /* read and clear hotplug flags for all ports */ 803 if (host->ports[0]->flags & PDC_FLAG_GEN_II) 804 hotplug_offset = PDC2_SATA_PLUG_CSR; 805 else 806 hotplug_offset = PDC_SATA_PLUG_CSR; 807 hotplug_status = readl(mmio_base + hotplug_offset); 808 if (hotplug_status & 0xff) 809 writel(hotplug_status | 0xff, mmio_base + hotplug_offset); 810 hotplug_status &= 0xff; /* clear uninteresting bits */ 811 812 /* reading should also clear interrupts */ 813 mask = readl(mmio_base + PDC_INT_SEQMASK); 814 815 if (mask == 0xffffffff && hotplug_status == 0) { 816 VPRINTK("QUICK EXIT 2\n"); 817 return IRQ_NONE; 818 } 819 820 spin_lock(&host->lock); 821 822 mask &= 0xffff; /* only 16 tags possible */ 823 if (mask == 0 && hotplug_status == 0) { 824 VPRINTK("QUICK EXIT 3\n"); 825 goto done_irq; 826 } 827 828 writel(mask, mmio_base + PDC_INT_SEQMASK); 829 830 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); 831 832 for (i = 0; i < host->n_ports; i++) { 833 VPRINTK("port %u\n", i); 834 ap = host->ports[i]; 835 836 /* check for a plug or unplug event */ 837 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 838 tmp = hotplug_status & (0x11 << ata_no); 839 if (tmp && ap && 840 !(ap->flags & ATA_FLAG_DISABLED)) { 841 struct ata_eh_info *ehi = &ap->link.eh_info; 842 ata_ehi_clear_desc(ehi); 843 ata_ehi_hotplugged(ehi); 844 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); 845 ata_port_freeze(ap); 846 ++handled; 847 continue; 848 } 849 850 /* check for a packet interrupt */ 851 tmp = mask & (1 << (i + 1)); 852 if (tmp && ap && 853 !(ap->flags & ATA_FLAG_DISABLED)) { 854 struct ata_queued_cmd *qc; 855 856 qc = ata_qc_from_tag(ap, ap->link.active_tag); 857 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 858 handled += pdc_host_intr(ap, qc); 859 } 860 } 861 862 VPRINTK("EXIT\n"); 863 864 done_irq: 865 spin_unlock(&host->lock); 866 return IRQ_RETVAL(handled); 867 } 868 869 static inline void pdc_packet_start(struct ata_queued_cmd *qc) 870 { 871 struct ata_port *ap = qc->ap; 872 struct pdc_port_priv *pp = ap->private_data; 873 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; 874 unsigned int port_no = ap->port_no; 875 u8 seq = (u8) (port_no + 1); 876 877 VPRINTK("ENTER, ap %p\n", ap); 878 879 writel(0x00000001, mmio + (seq * 4)); 880 readl(mmio + (seq * 4)); /* flush */ 881 882 pp->pkt[2] = seq; 883 wmb(); /* flush PRD, pkt writes */ 884 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); 885 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ 886 } 887 888 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) 889 { 890 switch (qc->tf.protocol) { 891 case ATAPI_PROT_NODATA: 892 if (qc->dev->flags & ATA_DFLAG_CDB_INTR) 893 break; 894 /*FALLTHROUGH*/ 895 case ATA_PROT_NODATA: 896 if (qc->tf.flags & ATA_TFLAG_POLLING) 897 break; 898 /*FALLTHROUGH*/ 899 case ATAPI_PROT_DMA: 900 case ATA_PROT_DMA: 901 pdc_packet_start(qc); 902 return 0; 903 904 default: 905 break; 906 } 907 908 return ata_qc_issue_prot(qc); 909 } 910 911 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) 912 { 913 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 914 ata_tf_load(ap, tf); 915 } 916 917 static void pdc_exec_command_mmio(struct ata_port *ap, 918 const struct ata_taskfile *tf) 919 { 920 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA); 921 ata_exec_command(ap, tf); 922 } 923 924 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) 925 { 926 u8 *scsicmd = qc->scsicmd->cmnd; 927 int pio = 1; /* atapi dma off by default */ 928 929 /* Whitelist commands that may use DMA. */ 930 switch (scsicmd[0]) { 931 case WRITE_12: 932 case WRITE_10: 933 case WRITE_6: 934 case READ_12: 935 case READ_10: 936 case READ_6: 937 case 0xad: /* READ_DVD_STRUCTURE */ 938 case 0xbe: /* READ_CD */ 939 pio = 0; 940 } 941 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ 942 if (scsicmd[0] == WRITE_10) { 943 unsigned int lba = 944 (scsicmd[2] << 24) | 945 (scsicmd[3] << 16) | 946 (scsicmd[4] << 8) | 947 scsicmd[5]; 948 if (lba >= 0xFFFF4FA2) 949 pio = 1; 950 } 951 return pio; 952 } 953 954 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) 955 { 956 /* First generation chips cannot use ATAPI DMA on SATA ports */ 957 return 1; 958 } 959 960 static void pdc_ata_setup_port(struct ata_port *ap, 961 void __iomem *base, void __iomem *scr_addr) 962 { 963 ap->ioaddr.cmd_addr = base; 964 ap->ioaddr.data_addr = base; 965 ap->ioaddr.feature_addr = 966 ap->ioaddr.error_addr = base + 0x4; 967 ap->ioaddr.nsect_addr = base + 0x8; 968 ap->ioaddr.lbal_addr = base + 0xc; 969 ap->ioaddr.lbam_addr = base + 0x10; 970 ap->ioaddr.lbah_addr = base + 0x14; 971 ap->ioaddr.device_addr = base + 0x18; 972 ap->ioaddr.command_addr = 973 ap->ioaddr.status_addr = base + 0x1c; 974 ap->ioaddr.altstatus_addr = 975 ap->ioaddr.ctl_addr = base + 0x38; 976 ap->ioaddr.scr_addr = scr_addr; 977 } 978 979 static void pdc_host_init(struct ata_host *host) 980 { 981 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; 982 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; 983 int hotplug_offset; 984 u32 tmp; 985 986 if (is_gen2) 987 hotplug_offset = PDC2_SATA_PLUG_CSR; 988 else 989 hotplug_offset = PDC_SATA_PLUG_CSR; 990 991 /* 992 * Except for the hotplug stuff, this is voodoo from the 993 * Promise driver. Label this entire section 994 * "TODO: figure out why we do this" 995 */ 996 997 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ 998 tmp = readl(mmio + PDC_FLASH_CTL); 999 tmp |= 0x02000; /* bit 13 (enable bmr burst) */ 1000 if (!is_gen2) 1001 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ 1002 writel(tmp, mmio + PDC_FLASH_CTL); 1003 1004 /* clear plug/unplug flags for all ports */ 1005 tmp = readl(mmio + hotplug_offset); 1006 writel(tmp | 0xff, mmio + hotplug_offset); 1007 1008 /* unmask plug/unplug ints */ 1009 tmp = readl(mmio + hotplug_offset); 1010 writel(tmp & ~0xff0000, mmio + hotplug_offset); 1011 1012 /* don't initialise TBG or SLEW on 2nd generation chips */ 1013 if (is_gen2) 1014 return; 1015 1016 /* reduce TBG clock to 133 Mhz. */ 1017 tmp = readl(mmio + PDC_TBG_MODE); 1018 tmp &= ~0x30000; /* clear bit 17, 16*/ 1019 tmp |= 0x10000; /* set bit 17:16 = 0:1 */ 1020 writel(tmp, mmio + PDC_TBG_MODE); 1021 1022 readl(mmio + PDC_TBG_MODE); /* flush */ 1023 msleep(10); 1024 1025 /* adjust slew rate control register. */ 1026 tmp = readl(mmio + PDC_SLEW_CTL); 1027 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ 1028 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ 1029 writel(tmp, mmio + PDC_SLEW_CTL); 1030 } 1031 1032 static int pdc_ata_init_one(struct pci_dev *pdev, 1033 const struct pci_device_id *ent) 1034 { 1035 static int printed_version; 1036 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; 1037 const struct ata_port_info *ppi[PDC_MAX_PORTS]; 1038 struct ata_host *host; 1039 void __iomem *base; 1040 int n_ports, i, rc; 1041 int is_sataii_tx4; 1042 1043 if (!printed_version++) 1044 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1045 1046 /* enable and acquire resources */ 1047 rc = pcim_enable_device(pdev); 1048 if (rc) 1049 return rc; 1050 1051 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 1052 if (rc == -EBUSY) 1053 pcim_pin_device(pdev); 1054 if (rc) 1055 return rc; 1056 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; 1057 1058 /* determine port configuration and setup host */ 1059 n_ports = 2; 1060 if (pi->flags & PDC_FLAG_4_PORTS) 1061 n_ports = 4; 1062 for (i = 0; i < n_ports; i++) 1063 ppi[i] = pi; 1064 1065 if (pi->flags & PDC_FLAG_SATA_PATA) { 1066 u8 tmp = readb(base + PDC_FLASH_CTL+1); 1067 if (!(tmp & 0x80)) 1068 ppi[n_ports++] = pi + 1; 1069 } 1070 1071 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 1072 if (!host) { 1073 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); 1074 return -ENOMEM; 1075 } 1076 host->iomap = pcim_iomap_table(pdev); 1077 1078 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); 1079 for (i = 0; i < host->n_ports; i++) { 1080 struct ata_port *ap = host->ports[i]; 1081 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); 1082 unsigned int port_offset = 0x200 + ata_no * 0x80; 1083 unsigned int scr_offset = 0x400 + ata_no * 0x100; 1084 1085 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset); 1086 1087 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 1088 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port"); 1089 } 1090 1091 /* initialize adapter */ 1092 pdc_host_init(host); 1093 1094 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 1095 if (rc) 1096 return rc; 1097 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 1098 if (rc) 1099 return rc; 1100 1101 /* start host, request IRQ and attach */ 1102 pci_set_master(pdev); 1103 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, 1104 &pdc_ata_sht); 1105 } 1106 1107 static int __init pdc_ata_init(void) 1108 { 1109 return pci_register_driver(&pdc_ata_pci_driver); 1110 } 1111 1112 static void __exit pdc_ata_exit(void) 1113 { 1114 pci_unregister_driver(&pdc_ata_pci_driver); 1115 } 1116 1117 MODULE_AUTHOR("Jeff Garzik"); 1118 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); 1119 MODULE_LICENSE("GPL"); 1120 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); 1121 MODULE_VERSION(DRV_VERSION); 1122 1123 module_init(pdc_ata_init); 1124 module_exit(pdc_ata_exit); 1125