1 /* 2 * sata_nv.c - NVIDIA nForce SATA 3 * 4 * Copyright 2004 NVIDIA Corp. All rights reserved. 5 * Copyright 2004 Andrew Chew 6 * 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * 23 * libata documentation is available via 'make {ps|pdf}docs', 24 * as Documentation/DocBook/libata.* 25 * 26 * No hardware documentation available outside of NVIDIA. 27 * This driver programs the NVIDIA SATA controller in a similar 28 * fashion as with other PCI IDE BMDMA controllers, with a few 29 * NV-specific details such as register offsets, SATA phy location, 30 * hotplug info, etc. 31 * 32 * CK804/MCP04 controllers support an alternate programming interface 33 * similar to the ADMA specification (with some modifications). 34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still 35 * sent through the legacy interface. 36 * 37 */ 38 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/gfp.h> 42 #include <linux/pci.h> 43 #include <linux/init.h> 44 #include <linux/blkdev.h> 45 #include <linux/delay.h> 46 #include <linux/interrupt.h> 47 #include <linux/device.h> 48 #include <scsi/scsi_host.h> 49 #include <scsi/scsi_device.h> 50 #include <linux/libata.h> 51 52 #define DRV_NAME "sata_nv" 53 #define DRV_VERSION "3.5" 54 55 #define NV_ADMA_DMA_BOUNDARY 0xffffffffUL 56 57 enum { 58 NV_MMIO_BAR = 5, 59 60 NV_PORTS = 2, 61 NV_PIO_MASK = ATA_PIO4, 62 NV_MWDMA_MASK = ATA_MWDMA2, 63 NV_UDMA_MASK = ATA_UDMA6, 64 NV_PORT0_SCR_REG_OFFSET = 0x00, 65 NV_PORT1_SCR_REG_OFFSET = 0x40, 66 67 /* INT_STATUS/ENABLE */ 68 NV_INT_STATUS = 0x10, 69 NV_INT_ENABLE = 0x11, 70 NV_INT_STATUS_CK804 = 0x440, 71 NV_INT_ENABLE_CK804 = 0x441, 72 73 /* INT_STATUS/ENABLE bits */ 74 NV_INT_DEV = 0x01, 75 NV_INT_PM = 0x02, 76 NV_INT_ADDED = 0x04, 77 NV_INT_REMOVED = 0x08, 78 79 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */ 80 81 NV_INT_ALL = 0x0f, 82 NV_INT_MASK = NV_INT_DEV | 83 NV_INT_ADDED | NV_INT_REMOVED, 84 85 /* INT_CONFIG */ 86 NV_INT_CONFIG = 0x12, 87 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI 88 89 // For PCI config register 20 90 NV_MCP_SATA_CFG_20 = 0x50, 91 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04, 92 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17), 93 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16), 94 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14), 95 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12), 96 97 NV_ADMA_MAX_CPBS = 32, 98 NV_ADMA_CPB_SZ = 128, 99 NV_ADMA_APRD_SZ = 16, 100 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) / 101 NV_ADMA_APRD_SZ, 102 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5, 103 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ, 104 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS * 105 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ), 106 107 /* BAR5 offset to ADMA general registers */ 108 NV_ADMA_GEN = 0x400, 109 NV_ADMA_GEN_CTL = 0x00, 110 NV_ADMA_NOTIFIER_CLEAR = 0x30, 111 112 /* BAR5 offset to ADMA ports */ 113 NV_ADMA_PORT = 0x480, 114 115 /* size of ADMA port register space */ 116 NV_ADMA_PORT_SIZE = 0x100, 117 118 /* ADMA port registers */ 119 NV_ADMA_CTL = 0x40, 120 NV_ADMA_CPB_COUNT = 0x42, 121 NV_ADMA_NEXT_CPB_IDX = 0x43, 122 NV_ADMA_STAT = 0x44, 123 NV_ADMA_CPB_BASE_LOW = 0x48, 124 NV_ADMA_CPB_BASE_HIGH = 0x4C, 125 NV_ADMA_APPEND = 0x50, 126 NV_ADMA_NOTIFIER = 0x68, 127 NV_ADMA_NOTIFIER_ERROR = 0x6C, 128 129 /* NV_ADMA_CTL register bits */ 130 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0), 131 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5), 132 NV_ADMA_CTL_GO = (1 << 7), 133 NV_ADMA_CTL_AIEN = (1 << 8), 134 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11), 135 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12), 136 137 /* CPB response flag bits */ 138 NV_CPB_RESP_DONE = (1 << 0), 139 NV_CPB_RESP_ATA_ERR = (1 << 3), 140 NV_CPB_RESP_CMD_ERR = (1 << 4), 141 NV_CPB_RESP_CPB_ERR = (1 << 7), 142 143 /* CPB control flag bits */ 144 NV_CPB_CTL_CPB_VALID = (1 << 0), 145 NV_CPB_CTL_QUEUE = (1 << 1), 146 NV_CPB_CTL_APRD_VALID = (1 << 2), 147 NV_CPB_CTL_IEN = (1 << 3), 148 NV_CPB_CTL_FPDMA = (1 << 4), 149 150 /* APRD flags */ 151 NV_APRD_WRITE = (1 << 1), 152 NV_APRD_END = (1 << 2), 153 NV_APRD_CONT = (1 << 3), 154 155 /* NV_ADMA_STAT flags */ 156 NV_ADMA_STAT_TIMEOUT = (1 << 0), 157 NV_ADMA_STAT_HOTUNPLUG = (1 << 1), 158 NV_ADMA_STAT_HOTPLUG = (1 << 2), 159 NV_ADMA_STAT_CPBERR = (1 << 4), 160 NV_ADMA_STAT_SERROR = (1 << 5), 161 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6), 162 NV_ADMA_STAT_IDLE = (1 << 8), 163 NV_ADMA_STAT_LEGACY = (1 << 9), 164 NV_ADMA_STAT_STOPPED = (1 << 10), 165 NV_ADMA_STAT_DONE = (1 << 12), 166 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR | 167 NV_ADMA_STAT_TIMEOUT, 168 169 /* port flags */ 170 NV_ADMA_PORT_REGISTER_MODE = (1 << 0), 171 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1), 172 173 /* MCP55 reg offset */ 174 NV_CTL_MCP55 = 0x400, 175 NV_INT_STATUS_MCP55 = 0x440, 176 NV_INT_ENABLE_MCP55 = 0x444, 177 NV_NCQ_REG_MCP55 = 0x448, 178 179 /* MCP55 */ 180 NV_INT_ALL_MCP55 = 0xffff, 181 NV_INT_PORT_SHIFT_MCP55 = 16, /* each port occupies 16 bits */ 182 NV_INT_MASK_MCP55 = NV_INT_ALL_MCP55 & 0xfffd, 183 184 /* SWNCQ ENABLE BITS*/ 185 NV_CTL_PRI_SWNCQ = 0x02, 186 NV_CTL_SEC_SWNCQ = 0x04, 187 188 /* SW NCQ status bits*/ 189 NV_SWNCQ_IRQ_DEV = (1 << 0), 190 NV_SWNCQ_IRQ_PM = (1 << 1), 191 NV_SWNCQ_IRQ_ADDED = (1 << 2), 192 NV_SWNCQ_IRQ_REMOVED = (1 << 3), 193 194 NV_SWNCQ_IRQ_BACKOUT = (1 << 4), 195 NV_SWNCQ_IRQ_SDBFIS = (1 << 5), 196 NV_SWNCQ_IRQ_DHREGFIS = (1 << 6), 197 NV_SWNCQ_IRQ_DMASETUP = (1 << 7), 198 199 NV_SWNCQ_IRQ_HOTPLUG = NV_SWNCQ_IRQ_ADDED | 200 NV_SWNCQ_IRQ_REMOVED, 201 202 }; 203 204 /* ADMA Physical Region Descriptor - one SG segment */ 205 struct nv_adma_prd { 206 __le64 addr; 207 __le32 len; 208 u8 flags; 209 u8 packet_len; 210 __le16 reserved; 211 }; 212 213 enum nv_adma_regbits { 214 CMDEND = (1 << 15), /* end of command list */ 215 WNB = (1 << 14), /* wait-not-BSY */ 216 IGN = (1 << 13), /* ignore this entry */ 217 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */ 218 DA2 = (1 << (2 + 8)), 219 DA1 = (1 << (1 + 8)), 220 DA0 = (1 << (0 + 8)), 221 }; 222 223 /* ADMA Command Parameter Block 224 The first 5 SG segments are stored inside the Command Parameter Block itself. 225 If there are more than 5 segments the remainder are stored in a separate 226 memory area indicated by next_aprd. */ 227 struct nv_adma_cpb { 228 u8 resp_flags; /* 0 */ 229 u8 reserved1; /* 1 */ 230 u8 ctl_flags; /* 2 */ 231 /* len is length of taskfile in 64 bit words */ 232 u8 len; /* 3 */ 233 u8 tag; /* 4 */ 234 u8 next_cpb_idx; /* 5 */ 235 __le16 reserved2; /* 6-7 */ 236 __le16 tf[12]; /* 8-31 */ 237 struct nv_adma_prd aprd[5]; /* 32-111 */ 238 __le64 next_aprd; /* 112-119 */ 239 __le64 reserved3; /* 120-127 */ 240 }; 241 242 243 struct nv_adma_port_priv { 244 struct nv_adma_cpb *cpb; 245 dma_addr_t cpb_dma; 246 struct nv_adma_prd *aprd; 247 dma_addr_t aprd_dma; 248 void __iomem *ctl_block; 249 void __iomem *gen_block; 250 void __iomem *notifier_clear_block; 251 u64 adma_dma_mask; 252 u8 flags; 253 int last_issue_ncq; 254 }; 255 256 struct nv_host_priv { 257 unsigned long type; 258 }; 259 260 struct defer_queue { 261 u32 defer_bits; 262 unsigned int head; 263 unsigned int tail; 264 unsigned int tag[ATA_MAX_QUEUE]; 265 }; 266 267 enum ncq_saw_flag_list { 268 ncq_saw_d2h = (1U << 0), 269 ncq_saw_dmas = (1U << 1), 270 ncq_saw_sdb = (1U << 2), 271 ncq_saw_backout = (1U << 3), 272 }; 273 274 struct nv_swncq_port_priv { 275 struct ata_prd *prd; /* our SG list */ 276 dma_addr_t prd_dma; /* and its DMA mapping */ 277 void __iomem *sactive_block; 278 void __iomem *irq_block; 279 void __iomem *tag_block; 280 u32 qc_active; 281 282 unsigned int last_issue_tag; 283 284 /* fifo circular queue to store deferral command */ 285 struct defer_queue defer_queue; 286 287 /* for NCQ interrupt analysis */ 288 u32 dhfis_bits; 289 u32 dmafis_bits; 290 u32 sdbfis_bits; 291 292 unsigned int ncq_flags; 293 }; 294 295 296 #define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT))))) 297 298 static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 299 #ifdef CONFIG_PM 300 static int nv_pci_device_resume(struct pci_dev *pdev); 301 #endif 302 static void nv_ck804_host_stop(struct ata_host *host); 303 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance); 304 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance); 305 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance); 306 static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 307 static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 308 309 static int nv_hardreset(struct ata_link *link, unsigned int *class, 310 unsigned long deadline); 311 static void nv_nf2_freeze(struct ata_port *ap); 312 static void nv_nf2_thaw(struct ata_port *ap); 313 static void nv_ck804_freeze(struct ata_port *ap); 314 static void nv_ck804_thaw(struct ata_port *ap); 315 static int nv_adma_slave_config(struct scsi_device *sdev); 316 static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc); 317 static void nv_adma_qc_prep(struct ata_queued_cmd *qc); 318 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc); 319 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance); 320 static void nv_adma_irq_clear(struct ata_port *ap); 321 static int nv_adma_port_start(struct ata_port *ap); 322 static void nv_adma_port_stop(struct ata_port *ap); 323 #ifdef CONFIG_PM 324 static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg); 325 static int nv_adma_port_resume(struct ata_port *ap); 326 #endif 327 static void nv_adma_freeze(struct ata_port *ap); 328 static void nv_adma_thaw(struct ata_port *ap); 329 static void nv_adma_error_handler(struct ata_port *ap); 330 static void nv_adma_host_stop(struct ata_host *host); 331 static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc); 332 static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf); 333 334 static void nv_mcp55_thaw(struct ata_port *ap); 335 static void nv_mcp55_freeze(struct ata_port *ap); 336 static void nv_swncq_error_handler(struct ata_port *ap); 337 static int nv_swncq_slave_config(struct scsi_device *sdev); 338 static int nv_swncq_port_start(struct ata_port *ap); 339 static void nv_swncq_qc_prep(struct ata_queued_cmd *qc); 340 static void nv_swncq_fill_sg(struct ata_queued_cmd *qc); 341 static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc); 342 static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis); 343 static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance); 344 #ifdef CONFIG_PM 345 static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg); 346 static int nv_swncq_port_resume(struct ata_port *ap); 347 #endif 348 349 enum nv_host_type 350 { 351 GENERIC, 352 NFORCE2, 353 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */ 354 CK804, 355 ADMA, 356 MCP5x, 357 SWNCQ, 358 }; 359 360 static const struct pci_device_id nv_pci_tbl[] = { 361 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 }, 362 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 }, 363 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 }, 364 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 }, 365 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 }, 366 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 }, 367 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 }, 368 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), MCP5x }, 369 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), MCP5x }, 370 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), MCP5x }, 371 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), MCP5x }, 372 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC }, 373 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC }, 374 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC }, 375 376 { } /* terminate list */ 377 }; 378 379 static struct pci_driver nv_pci_driver = { 380 .name = DRV_NAME, 381 .id_table = nv_pci_tbl, 382 .probe = nv_init_one, 383 #ifdef CONFIG_PM 384 .suspend = ata_pci_device_suspend, 385 .resume = nv_pci_device_resume, 386 #endif 387 .remove = ata_pci_remove_one, 388 }; 389 390 static struct scsi_host_template nv_sht = { 391 ATA_BMDMA_SHT(DRV_NAME), 392 }; 393 394 static struct scsi_host_template nv_adma_sht = { 395 ATA_NCQ_SHT(DRV_NAME), 396 .can_queue = NV_ADMA_MAX_CPBS, 397 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN, 398 .dma_boundary = NV_ADMA_DMA_BOUNDARY, 399 .slave_configure = nv_adma_slave_config, 400 }; 401 402 static struct scsi_host_template nv_swncq_sht = { 403 ATA_NCQ_SHT(DRV_NAME), 404 .can_queue = ATA_MAX_QUEUE, 405 .sg_tablesize = LIBATA_MAX_PRD, 406 .dma_boundary = ATA_DMA_BOUNDARY, 407 .slave_configure = nv_swncq_slave_config, 408 }; 409 410 /* 411 * NV SATA controllers have various different problems with hardreset 412 * protocol depending on the specific controller and device. 413 * 414 * GENERIC: 415 * 416 * bko11195 reports that link doesn't come online after hardreset on 417 * generic nv's and there have been several other similar reports on 418 * linux-ide. 419 * 420 * bko12351#c23 reports that warmplug on MCP61 doesn't work with 421 * softreset. 422 * 423 * NF2/3: 424 * 425 * bko3352 reports nf2/3 controllers can't determine device signature 426 * reliably after hardreset. The following thread reports detection 427 * failure on cold boot with the standard debouncing timing. 428 * 429 * http://thread.gmane.org/gmane.linux.ide/34098 430 * 431 * bko12176 reports that hardreset fails to bring up the link during 432 * boot on nf2. 433 * 434 * CK804: 435 * 436 * For initial probing after boot and hot plugging, hardreset mostly 437 * works fine on CK804 but curiously, reprobing on the initial port 438 * by rescanning or rmmod/insmod fails to acquire the initial D2H Reg 439 * FIS in somewhat undeterministic way. 440 * 441 * SWNCQ: 442 * 443 * bko12351 reports that when SWNCQ is enabled, for hotplug to work, 444 * hardreset should be used and hardreset can't report proper 445 * signature, which suggests that mcp5x is closer to nf2 as long as 446 * reset quirkiness is concerned. 447 * 448 * bko12703 reports that boot probing fails for intel SSD with 449 * hardreset. Link fails to come online. Softreset works fine. 450 * 451 * The failures are varied but the following patterns seem true for 452 * all flavors. 453 * 454 * - Softreset during boot always works. 455 * 456 * - Hardreset during boot sometimes fails to bring up the link on 457 * certain comibnations and device signature acquisition is 458 * unreliable. 459 * 460 * - Hardreset is often necessary after hotplug. 461 * 462 * So, preferring softreset for boot probing and error handling (as 463 * hardreset might bring down the link) but using hardreset for 464 * post-boot probing should work around the above issues in most 465 * cases. Define nv_hardreset() which only kicks in for post-boot 466 * probing and use it for all variants. 467 */ 468 static struct ata_port_operations nv_generic_ops = { 469 .inherits = &ata_bmdma_port_ops, 470 .lost_interrupt = ATA_OP_NULL, 471 .scr_read = nv_scr_read, 472 .scr_write = nv_scr_write, 473 .hardreset = nv_hardreset, 474 }; 475 476 static struct ata_port_operations nv_nf2_ops = { 477 .inherits = &nv_generic_ops, 478 .freeze = nv_nf2_freeze, 479 .thaw = nv_nf2_thaw, 480 }; 481 482 static struct ata_port_operations nv_ck804_ops = { 483 .inherits = &nv_generic_ops, 484 .freeze = nv_ck804_freeze, 485 .thaw = nv_ck804_thaw, 486 .host_stop = nv_ck804_host_stop, 487 }; 488 489 static struct ata_port_operations nv_adma_ops = { 490 .inherits = &nv_ck804_ops, 491 492 .check_atapi_dma = nv_adma_check_atapi_dma, 493 .sff_tf_read = nv_adma_tf_read, 494 .qc_defer = ata_std_qc_defer, 495 .qc_prep = nv_adma_qc_prep, 496 .qc_issue = nv_adma_qc_issue, 497 .sff_irq_clear = nv_adma_irq_clear, 498 499 .freeze = nv_adma_freeze, 500 .thaw = nv_adma_thaw, 501 .error_handler = nv_adma_error_handler, 502 .post_internal_cmd = nv_adma_post_internal_cmd, 503 504 .port_start = nv_adma_port_start, 505 .port_stop = nv_adma_port_stop, 506 #ifdef CONFIG_PM 507 .port_suspend = nv_adma_port_suspend, 508 .port_resume = nv_adma_port_resume, 509 #endif 510 .host_stop = nv_adma_host_stop, 511 }; 512 513 static struct ata_port_operations nv_swncq_ops = { 514 .inherits = &nv_generic_ops, 515 516 .qc_defer = ata_std_qc_defer, 517 .qc_prep = nv_swncq_qc_prep, 518 .qc_issue = nv_swncq_qc_issue, 519 520 .freeze = nv_mcp55_freeze, 521 .thaw = nv_mcp55_thaw, 522 .error_handler = nv_swncq_error_handler, 523 524 #ifdef CONFIG_PM 525 .port_suspend = nv_swncq_port_suspend, 526 .port_resume = nv_swncq_port_resume, 527 #endif 528 .port_start = nv_swncq_port_start, 529 }; 530 531 struct nv_pi_priv { 532 irq_handler_t irq_handler; 533 struct scsi_host_template *sht; 534 }; 535 536 #define NV_PI_PRIV(_irq_handler, _sht) \ 537 &(struct nv_pi_priv){ .irq_handler = _irq_handler, .sht = _sht } 538 539 static const struct ata_port_info nv_port_info[] = { 540 /* generic */ 541 { 542 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, 543 .pio_mask = NV_PIO_MASK, 544 .mwdma_mask = NV_MWDMA_MASK, 545 .udma_mask = NV_UDMA_MASK, 546 .port_ops = &nv_generic_ops, 547 .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht), 548 }, 549 /* nforce2/3 */ 550 { 551 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, 552 .pio_mask = NV_PIO_MASK, 553 .mwdma_mask = NV_MWDMA_MASK, 554 .udma_mask = NV_UDMA_MASK, 555 .port_ops = &nv_nf2_ops, 556 .private_data = NV_PI_PRIV(nv_nf2_interrupt, &nv_sht), 557 }, 558 /* ck804 */ 559 { 560 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, 561 .pio_mask = NV_PIO_MASK, 562 .mwdma_mask = NV_MWDMA_MASK, 563 .udma_mask = NV_UDMA_MASK, 564 .port_ops = &nv_ck804_ops, 565 .private_data = NV_PI_PRIV(nv_ck804_interrupt, &nv_sht), 566 }, 567 /* ADMA */ 568 { 569 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 570 ATA_FLAG_MMIO | ATA_FLAG_NCQ, 571 .pio_mask = NV_PIO_MASK, 572 .mwdma_mask = NV_MWDMA_MASK, 573 .udma_mask = NV_UDMA_MASK, 574 .port_ops = &nv_adma_ops, 575 .private_data = NV_PI_PRIV(nv_adma_interrupt, &nv_adma_sht), 576 }, 577 /* MCP5x */ 578 { 579 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, 580 .pio_mask = NV_PIO_MASK, 581 .mwdma_mask = NV_MWDMA_MASK, 582 .udma_mask = NV_UDMA_MASK, 583 .port_ops = &nv_generic_ops, 584 .private_data = NV_PI_PRIV(nv_generic_interrupt, &nv_sht), 585 }, 586 /* SWNCQ */ 587 { 588 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 589 ATA_FLAG_NCQ, 590 .pio_mask = NV_PIO_MASK, 591 .mwdma_mask = NV_MWDMA_MASK, 592 .udma_mask = NV_UDMA_MASK, 593 .port_ops = &nv_swncq_ops, 594 .private_data = NV_PI_PRIV(nv_swncq_interrupt, &nv_swncq_sht), 595 }, 596 }; 597 598 MODULE_AUTHOR("NVIDIA"); 599 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller"); 600 MODULE_LICENSE("GPL"); 601 MODULE_DEVICE_TABLE(pci, nv_pci_tbl); 602 MODULE_VERSION(DRV_VERSION); 603 604 static int adma_enabled; 605 static int swncq_enabled = 1; 606 static int msi_enabled; 607 608 static void nv_adma_register_mode(struct ata_port *ap) 609 { 610 struct nv_adma_port_priv *pp = ap->private_data; 611 void __iomem *mmio = pp->ctl_block; 612 u16 tmp, status; 613 int count = 0; 614 615 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) 616 return; 617 618 status = readw(mmio + NV_ADMA_STAT); 619 while (!(status & NV_ADMA_STAT_IDLE) && count < 20) { 620 ndelay(50); 621 status = readw(mmio + NV_ADMA_STAT); 622 count++; 623 } 624 if (count == 20) 625 ata_port_printk(ap, KERN_WARNING, 626 "timeout waiting for ADMA IDLE, stat=0x%hx\n", 627 status); 628 629 tmp = readw(mmio + NV_ADMA_CTL); 630 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); 631 632 count = 0; 633 status = readw(mmio + NV_ADMA_STAT); 634 while (!(status & NV_ADMA_STAT_LEGACY) && count < 20) { 635 ndelay(50); 636 status = readw(mmio + NV_ADMA_STAT); 637 count++; 638 } 639 if (count == 20) 640 ata_port_printk(ap, KERN_WARNING, 641 "timeout waiting for ADMA LEGACY, stat=0x%hx\n", 642 status); 643 644 pp->flags |= NV_ADMA_PORT_REGISTER_MODE; 645 } 646 647 static void nv_adma_mode(struct ata_port *ap) 648 { 649 struct nv_adma_port_priv *pp = ap->private_data; 650 void __iomem *mmio = pp->ctl_block; 651 u16 tmp, status; 652 int count = 0; 653 654 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) 655 return; 656 657 WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE); 658 659 tmp = readw(mmio + NV_ADMA_CTL); 660 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); 661 662 status = readw(mmio + NV_ADMA_STAT); 663 while (((status & NV_ADMA_STAT_LEGACY) || 664 !(status & NV_ADMA_STAT_IDLE)) && count < 20) { 665 ndelay(50); 666 status = readw(mmio + NV_ADMA_STAT); 667 count++; 668 } 669 if (count == 20) 670 ata_port_printk(ap, KERN_WARNING, 671 "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n", 672 status); 673 674 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE; 675 } 676 677 static int nv_adma_slave_config(struct scsi_device *sdev) 678 { 679 struct ata_port *ap = ata_shost_to_port(sdev->host); 680 struct nv_adma_port_priv *pp = ap->private_data; 681 struct nv_adma_port_priv *port0, *port1; 682 struct scsi_device *sdev0, *sdev1; 683 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 684 unsigned long segment_boundary, flags; 685 unsigned short sg_tablesize; 686 int rc; 687 int adma_enable; 688 u32 current_reg, new_reg, config_mask; 689 690 rc = ata_scsi_slave_config(sdev); 691 692 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun) 693 /* Not a proper libata device, ignore */ 694 return rc; 695 696 spin_lock_irqsave(ap->lock, flags); 697 698 if (ap->link.device[sdev->id].class == ATA_DEV_ATAPI) { 699 /* 700 * NVIDIA reports that ADMA mode does not support ATAPI commands. 701 * Therefore ATAPI commands are sent through the legacy interface. 702 * However, the legacy interface only supports 32-bit DMA. 703 * Restrict DMA parameters as required by the legacy interface 704 * when an ATAPI device is connected. 705 */ 706 segment_boundary = ATA_DMA_BOUNDARY; 707 /* Subtract 1 since an extra entry may be needed for padding, see 708 libata-scsi.c */ 709 sg_tablesize = LIBATA_MAX_PRD - 1; 710 711 /* Since the legacy DMA engine is in use, we need to disable ADMA 712 on the port. */ 713 adma_enable = 0; 714 nv_adma_register_mode(ap); 715 } else { 716 segment_boundary = NV_ADMA_DMA_BOUNDARY; 717 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN; 718 adma_enable = 1; 719 } 720 721 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, ¤t_reg); 722 723 if (ap->port_no == 1) 724 config_mask = NV_MCP_SATA_CFG_20_PORT1_EN | 725 NV_MCP_SATA_CFG_20_PORT1_PWB_EN; 726 else 727 config_mask = NV_MCP_SATA_CFG_20_PORT0_EN | 728 NV_MCP_SATA_CFG_20_PORT0_PWB_EN; 729 730 if (adma_enable) { 731 new_reg = current_reg | config_mask; 732 pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE; 733 } else { 734 new_reg = current_reg & ~config_mask; 735 pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE; 736 } 737 738 if (current_reg != new_reg) 739 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg); 740 741 port0 = ap->host->ports[0]->private_data; 742 port1 = ap->host->ports[1]->private_data; 743 sdev0 = ap->host->ports[0]->link.device[0].sdev; 744 sdev1 = ap->host->ports[1]->link.device[0].sdev; 745 if ((port0->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) || 746 (port1->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)) { 747 /** We have to set the DMA mask to 32-bit if either port is in 748 ATAPI mode, since they are on the same PCI device which is 749 used for DMA mapping. If we set the mask we also need to set 750 the bounce limit on both ports to ensure that the block 751 layer doesn't feed addresses that cause DMA mapping to 752 choke. If either SCSI device is not allocated yet, it's OK 753 since that port will discover its correct setting when it 754 does get allocated. 755 Note: Setting 32-bit mask should not fail. */ 756 if (sdev0) 757 blk_queue_bounce_limit(sdev0->request_queue, 758 ATA_DMA_MASK); 759 if (sdev1) 760 blk_queue_bounce_limit(sdev1->request_queue, 761 ATA_DMA_MASK); 762 763 pci_set_dma_mask(pdev, ATA_DMA_MASK); 764 } else { 765 /** This shouldn't fail as it was set to this value before */ 766 pci_set_dma_mask(pdev, pp->adma_dma_mask); 767 if (sdev0) 768 blk_queue_bounce_limit(sdev0->request_queue, 769 pp->adma_dma_mask); 770 if (sdev1) 771 blk_queue_bounce_limit(sdev1->request_queue, 772 pp->adma_dma_mask); 773 } 774 775 blk_queue_segment_boundary(sdev->request_queue, segment_boundary); 776 blk_queue_max_segments(sdev->request_queue, sg_tablesize); 777 ata_port_printk(ap, KERN_INFO, 778 "DMA mask 0x%llX, segment boundary 0x%lX, hw segs %hu\n", 779 (unsigned long long)*ap->host->dev->dma_mask, 780 segment_boundary, sg_tablesize); 781 782 spin_unlock_irqrestore(ap->lock, flags); 783 784 return rc; 785 } 786 787 static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc) 788 { 789 struct nv_adma_port_priv *pp = qc->ap->private_data; 790 return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE); 791 } 792 793 static void nv_adma_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 794 { 795 /* Other than when internal or pass-through commands are executed, 796 the only time this function will be called in ADMA mode will be 797 if a command fails. In the failure case we don't care about going 798 into register mode with ADMA commands pending, as the commands will 799 all shortly be aborted anyway. We assume that NCQ commands are not 800 issued via passthrough, which is the only way that switching into 801 ADMA mode could abort outstanding commands. */ 802 nv_adma_register_mode(ap); 803 804 ata_sff_tf_read(ap, tf); 805 } 806 807 static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb) 808 { 809 unsigned int idx = 0; 810 811 if (tf->flags & ATA_TFLAG_ISADDR) { 812 if (tf->flags & ATA_TFLAG_LBA48) { 813 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature | WNB); 814 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect); 815 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal); 816 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam); 817 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah); 818 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature); 819 } else 820 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature | WNB); 821 822 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect); 823 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal); 824 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam); 825 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah); 826 } 827 828 if (tf->flags & ATA_TFLAG_DEVICE) 829 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device); 830 831 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND); 832 833 while (idx < 12) 834 cpb[idx++] = cpu_to_le16(IGN); 835 836 return idx; 837 } 838 839 static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err) 840 { 841 struct nv_adma_port_priv *pp = ap->private_data; 842 u8 flags = pp->cpb[cpb_num].resp_flags; 843 844 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags); 845 846 if (unlikely((force_err || 847 flags & (NV_CPB_RESP_ATA_ERR | 848 NV_CPB_RESP_CMD_ERR | 849 NV_CPB_RESP_CPB_ERR)))) { 850 struct ata_eh_info *ehi = &ap->link.eh_info; 851 int freeze = 0; 852 853 ata_ehi_clear_desc(ehi); 854 __ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x: ", flags); 855 if (flags & NV_CPB_RESP_ATA_ERR) { 856 ata_ehi_push_desc(ehi, "ATA error"); 857 ehi->err_mask |= AC_ERR_DEV; 858 } else if (flags & NV_CPB_RESP_CMD_ERR) { 859 ata_ehi_push_desc(ehi, "CMD error"); 860 ehi->err_mask |= AC_ERR_DEV; 861 } else if (flags & NV_CPB_RESP_CPB_ERR) { 862 ata_ehi_push_desc(ehi, "CPB error"); 863 ehi->err_mask |= AC_ERR_SYSTEM; 864 freeze = 1; 865 } else { 866 /* notifier error, but no error in CPB flags? */ 867 ata_ehi_push_desc(ehi, "unknown"); 868 ehi->err_mask |= AC_ERR_OTHER; 869 freeze = 1; 870 } 871 /* Kill all commands. EH will determine what actually failed. */ 872 if (freeze) 873 ata_port_freeze(ap); 874 else 875 ata_port_abort(ap); 876 return 1; 877 } 878 879 if (likely(flags & NV_CPB_RESP_DONE)) { 880 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num); 881 VPRINTK("CPB flags done, flags=0x%x\n", flags); 882 if (likely(qc)) { 883 DPRINTK("Completing qc from tag %d\n", cpb_num); 884 ata_qc_complete(qc); 885 } else { 886 struct ata_eh_info *ehi = &ap->link.eh_info; 887 /* Notifier bits set without a command may indicate the drive 888 is misbehaving. Raise host state machine violation on this 889 condition. */ 890 ata_port_printk(ap, KERN_ERR, 891 "notifier for tag %d with no cmd?\n", 892 cpb_num); 893 ehi->err_mask |= AC_ERR_HSM; 894 ehi->action |= ATA_EH_RESET; 895 ata_port_freeze(ap); 896 return 1; 897 } 898 } 899 return 0; 900 } 901 902 static int nv_host_intr(struct ata_port *ap, u8 irq_stat) 903 { 904 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 905 906 /* freeze if hotplugged */ 907 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) { 908 ata_port_freeze(ap); 909 return 1; 910 } 911 912 /* bail out if not our interrupt */ 913 if (!(irq_stat & NV_INT_DEV)) 914 return 0; 915 916 /* DEV interrupt w/ no active qc? */ 917 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { 918 ata_sff_check_status(ap); 919 return 1; 920 } 921 922 /* handle interrupt */ 923 return ata_sff_host_intr(ap, qc); 924 } 925 926 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance) 927 { 928 struct ata_host *host = dev_instance; 929 int i, handled = 0; 930 u32 notifier_clears[2]; 931 932 spin_lock(&host->lock); 933 934 for (i = 0; i < host->n_ports; i++) { 935 struct ata_port *ap = host->ports[i]; 936 notifier_clears[i] = 0; 937 938 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { 939 struct nv_adma_port_priv *pp = ap->private_data; 940 void __iomem *mmio = pp->ctl_block; 941 u16 status; 942 u32 gen_ctl; 943 u32 notifier, notifier_error; 944 945 /* if ADMA is disabled, use standard ata interrupt handler */ 946 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) { 947 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804) 948 >> (NV_INT_PORT_SHIFT * i); 949 handled += nv_host_intr(ap, irq_stat); 950 continue; 951 } 952 953 /* if in ATA register mode, check for standard interrupts */ 954 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) { 955 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804) 956 >> (NV_INT_PORT_SHIFT * i); 957 if (ata_tag_valid(ap->link.active_tag)) 958 /** NV_INT_DEV indication seems unreliable at times 959 at least in ADMA mode. Force it on always when a 960 command is active, to prevent losing interrupts. */ 961 irq_stat |= NV_INT_DEV; 962 handled += nv_host_intr(ap, irq_stat); 963 } 964 965 notifier = readl(mmio + NV_ADMA_NOTIFIER); 966 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); 967 notifier_clears[i] = notifier | notifier_error; 968 969 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL); 970 971 if (!NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier && 972 !notifier_error) 973 /* Nothing to do */ 974 continue; 975 976 status = readw(mmio + NV_ADMA_STAT); 977 978 /* Clear status. Ensure the controller sees the clearing before we start 979 looking at any of the CPB statuses, so that any CPB completions after 980 this point in the handler will raise another interrupt. */ 981 writew(status, mmio + NV_ADMA_STAT); 982 readw(mmio + NV_ADMA_STAT); /* flush posted write */ 983 rmb(); 984 985 handled++; /* irq handled if we got here */ 986 987 /* freeze if hotplugged or controller error */ 988 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG | 989 NV_ADMA_STAT_HOTUNPLUG | 990 NV_ADMA_STAT_TIMEOUT | 991 NV_ADMA_STAT_SERROR))) { 992 struct ata_eh_info *ehi = &ap->link.eh_info; 993 994 ata_ehi_clear_desc(ehi); 995 __ata_ehi_push_desc(ehi, "ADMA status 0x%08x: ", status); 996 if (status & NV_ADMA_STAT_TIMEOUT) { 997 ehi->err_mask |= AC_ERR_SYSTEM; 998 ata_ehi_push_desc(ehi, "timeout"); 999 } else if (status & NV_ADMA_STAT_HOTPLUG) { 1000 ata_ehi_hotplugged(ehi); 1001 ata_ehi_push_desc(ehi, "hotplug"); 1002 } else if (status & NV_ADMA_STAT_HOTUNPLUG) { 1003 ata_ehi_hotplugged(ehi); 1004 ata_ehi_push_desc(ehi, "hot unplug"); 1005 } else if (status & NV_ADMA_STAT_SERROR) { 1006 /* let libata analyze SError and figure out the cause */ 1007 ata_ehi_push_desc(ehi, "SError"); 1008 } else 1009 ata_ehi_push_desc(ehi, "unknown"); 1010 ata_port_freeze(ap); 1011 continue; 1012 } 1013 1014 if (status & (NV_ADMA_STAT_DONE | 1015 NV_ADMA_STAT_CPBERR | 1016 NV_ADMA_STAT_CMD_COMPLETE)) { 1017 u32 check_commands = notifier_clears[i]; 1018 int pos, error = 0; 1019 1020 if (status & NV_ADMA_STAT_CPBERR) { 1021 /* Check all active commands */ 1022 if (ata_tag_valid(ap->link.active_tag)) 1023 check_commands = 1 << 1024 ap->link.active_tag; 1025 else 1026 check_commands = ap-> 1027 link.sactive; 1028 } 1029 1030 /** Check CPBs for completed commands */ 1031 while ((pos = ffs(check_commands)) && !error) { 1032 pos--; 1033 error = nv_adma_check_cpb(ap, pos, 1034 notifier_error & (1 << pos)); 1035 check_commands &= ~(1 << pos); 1036 } 1037 } 1038 } 1039 } 1040 1041 if (notifier_clears[0] || notifier_clears[1]) { 1042 /* Note: Both notifier clear registers must be written 1043 if either is set, even if one is zero, according to NVIDIA. */ 1044 struct nv_adma_port_priv *pp = host->ports[0]->private_data; 1045 writel(notifier_clears[0], pp->notifier_clear_block); 1046 pp = host->ports[1]->private_data; 1047 writel(notifier_clears[1], pp->notifier_clear_block); 1048 } 1049 1050 spin_unlock(&host->lock); 1051 1052 return IRQ_RETVAL(handled); 1053 } 1054 1055 static void nv_adma_freeze(struct ata_port *ap) 1056 { 1057 struct nv_adma_port_priv *pp = ap->private_data; 1058 void __iomem *mmio = pp->ctl_block; 1059 u16 tmp; 1060 1061 nv_ck804_freeze(ap); 1062 1063 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) 1064 return; 1065 1066 /* clear any outstanding CK804 notifications */ 1067 writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT), 1068 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); 1069 1070 /* Disable interrupt */ 1071 tmp = readw(mmio + NV_ADMA_CTL); 1072 writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN), 1073 mmio + NV_ADMA_CTL); 1074 readw(mmio + NV_ADMA_CTL); /* flush posted write */ 1075 } 1076 1077 static void nv_adma_thaw(struct ata_port *ap) 1078 { 1079 struct nv_adma_port_priv *pp = ap->private_data; 1080 void __iomem *mmio = pp->ctl_block; 1081 u16 tmp; 1082 1083 nv_ck804_thaw(ap); 1084 1085 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) 1086 return; 1087 1088 /* Enable interrupt */ 1089 tmp = readw(mmio + NV_ADMA_CTL); 1090 writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN), 1091 mmio + NV_ADMA_CTL); 1092 readw(mmio + NV_ADMA_CTL); /* flush posted write */ 1093 } 1094 1095 static void nv_adma_irq_clear(struct ata_port *ap) 1096 { 1097 struct nv_adma_port_priv *pp = ap->private_data; 1098 void __iomem *mmio = pp->ctl_block; 1099 u32 notifier_clears[2]; 1100 1101 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) { 1102 ata_sff_irq_clear(ap); 1103 return; 1104 } 1105 1106 /* clear any outstanding CK804 notifications */ 1107 writeb(NV_INT_ALL << (ap->port_no * NV_INT_PORT_SHIFT), 1108 ap->host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); 1109 1110 /* clear ADMA status */ 1111 writew(0xffff, mmio + NV_ADMA_STAT); 1112 1113 /* clear notifiers - note both ports need to be written with 1114 something even though we are only clearing on one */ 1115 if (ap->port_no == 0) { 1116 notifier_clears[0] = 0xFFFFFFFF; 1117 notifier_clears[1] = 0; 1118 } else { 1119 notifier_clears[0] = 0; 1120 notifier_clears[1] = 0xFFFFFFFF; 1121 } 1122 pp = ap->host->ports[0]->private_data; 1123 writel(notifier_clears[0], pp->notifier_clear_block); 1124 pp = ap->host->ports[1]->private_data; 1125 writel(notifier_clears[1], pp->notifier_clear_block); 1126 } 1127 1128 static void nv_adma_post_internal_cmd(struct ata_queued_cmd *qc) 1129 { 1130 struct nv_adma_port_priv *pp = qc->ap->private_data; 1131 1132 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) 1133 ata_sff_post_internal_cmd(qc); 1134 } 1135 1136 static int nv_adma_port_start(struct ata_port *ap) 1137 { 1138 struct device *dev = ap->host->dev; 1139 struct nv_adma_port_priv *pp; 1140 int rc; 1141 void *mem; 1142 dma_addr_t mem_dma; 1143 void __iomem *mmio; 1144 struct pci_dev *pdev = to_pci_dev(dev); 1145 u16 tmp; 1146 1147 VPRINTK("ENTER\n"); 1148 1149 /* Ensure DMA mask is set to 32-bit before allocating legacy PRD and 1150 pad buffers */ 1151 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1152 if (rc) 1153 return rc; 1154 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1155 if (rc) 1156 return rc; 1157 1158 rc = ata_port_start(ap); 1159 if (rc) 1160 return rc; 1161 1162 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1163 if (!pp) 1164 return -ENOMEM; 1165 1166 mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT + 1167 ap->port_no * NV_ADMA_PORT_SIZE; 1168 pp->ctl_block = mmio; 1169 pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN; 1170 pp->notifier_clear_block = pp->gen_block + 1171 NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no); 1172 1173 /* Now that the legacy PRD and padding buffer are allocated we can 1174 safely raise the DMA mask to allocate the CPB/APRD table. 1175 These are allowed to fail since we store the value that ends up 1176 being used to set as the bounce limit in slave_config later if 1177 needed. */ 1178 pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1179 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 1180 pp->adma_dma_mask = *dev->dma_mask; 1181 1182 mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ, 1183 &mem_dma, GFP_KERNEL); 1184 if (!mem) 1185 return -ENOMEM; 1186 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ); 1187 1188 /* 1189 * First item in chunk of DMA memory: 1190 * 128-byte command parameter block (CPB) 1191 * one for each command tag 1192 */ 1193 pp->cpb = mem; 1194 pp->cpb_dma = mem_dma; 1195 1196 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW); 1197 writel((mem_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH); 1198 1199 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ; 1200 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ; 1201 1202 /* 1203 * Second item: block of ADMA_SGTBL_LEN s/g entries 1204 */ 1205 pp->aprd = mem; 1206 pp->aprd_dma = mem_dma; 1207 1208 ap->private_data = pp; 1209 1210 /* clear any outstanding interrupt conditions */ 1211 writew(0xffff, mmio + NV_ADMA_STAT); 1212 1213 /* initialize port variables */ 1214 pp->flags = NV_ADMA_PORT_REGISTER_MODE; 1215 1216 /* clear CPB fetch count */ 1217 writew(0, mmio + NV_ADMA_CPB_COUNT); 1218 1219 /* clear GO for register mode, enable interrupt */ 1220 tmp = readw(mmio + NV_ADMA_CTL); 1221 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN | 1222 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL); 1223 1224 tmp = readw(mmio + NV_ADMA_CTL); 1225 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); 1226 readw(mmio + NV_ADMA_CTL); /* flush posted write */ 1227 udelay(1); 1228 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); 1229 readw(mmio + NV_ADMA_CTL); /* flush posted write */ 1230 1231 return 0; 1232 } 1233 1234 static void nv_adma_port_stop(struct ata_port *ap) 1235 { 1236 struct nv_adma_port_priv *pp = ap->private_data; 1237 void __iomem *mmio = pp->ctl_block; 1238 1239 VPRINTK("ENTER\n"); 1240 writew(0, mmio + NV_ADMA_CTL); 1241 } 1242 1243 #ifdef CONFIG_PM 1244 static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg) 1245 { 1246 struct nv_adma_port_priv *pp = ap->private_data; 1247 void __iomem *mmio = pp->ctl_block; 1248 1249 /* Go to register mode - clears GO */ 1250 nv_adma_register_mode(ap); 1251 1252 /* clear CPB fetch count */ 1253 writew(0, mmio + NV_ADMA_CPB_COUNT); 1254 1255 /* disable interrupt, shut down port */ 1256 writew(0, mmio + NV_ADMA_CTL); 1257 1258 return 0; 1259 } 1260 1261 static int nv_adma_port_resume(struct ata_port *ap) 1262 { 1263 struct nv_adma_port_priv *pp = ap->private_data; 1264 void __iomem *mmio = pp->ctl_block; 1265 u16 tmp; 1266 1267 /* set CPB block location */ 1268 writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW); 1269 writel((pp->cpb_dma >> 16) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH); 1270 1271 /* clear any outstanding interrupt conditions */ 1272 writew(0xffff, mmio + NV_ADMA_STAT); 1273 1274 /* initialize port variables */ 1275 pp->flags |= NV_ADMA_PORT_REGISTER_MODE; 1276 1277 /* clear CPB fetch count */ 1278 writew(0, mmio + NV_ADMA_CPB_COUNT); 1279 1280 /* clear GO for register mode, enable interrupt */ 1281 tmp = readw(mmio + NV_ADMA_CTL); 1282 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN | 1283 NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL); 1284 1285 tmp = readw(mmio + NV_ADMA_CTL); 1286 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); 1287 readw(mmio + NV_ADMA_CTL); /* flush posted write */ 1288 udelay(1); 1289 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); 1290 readw(mmio + NV_ADMA_CTL); /* flush posted write */ 1291 1292 return 0; 1293 } 1294 #endif 1295 1296 static void nv_adma_setup_port(struct ata_port *ap) 1297 { 1298 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; 1299 struct ata_ioports *ioport = &ap->ioaddr; 1300 1301 VPRINTK("ENTER\n"); 1302 1303 mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE; 1304 1305 ioport->cmd_addr = mmio; 1306 ioport->data_addr = mmio + (ATA_REG_DATA * 4); 1307 ioport->error_addr = 1308 ioport->feature_addr = mmio + (ATA_REG_ERR * 4); 1309 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4); 1310 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4); 1311 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4); 1312 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4); 1313 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4); 1314 ioport->status_addr = 1315 ioport->command_addr = mmio + (ATA_REG_STATUS * 4); 1316 ioport->altstatus_addr = 1317 ioport->ctl_addr = mmio + 0x20; 1318 } 1319 1320 static int nv_adma_host_init(struct ata_host *host) 1321 { 1322 struct pci_dev *pdev = to_pci_dev(host->dev); 1323 unsigned int i; 1324 u32 tmp32; 1325 1326 VPRINTK("ENTER\n"); 1327 1328 /* enable ADMA on the ports */ 1329 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); 1330 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN | 1331 NV_MCP_SATA_CFG_20_PORT0_PWB_EN | 1332 NV_MCP_SATA_CFG_20_PORT1_EN | 1333 NV_MCP_SATA_CFG_20_PORT1_PWB_EN; 1334 1335 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); 1336 1337 for (i = 0; i < host->n_ports; i++) 1338 nv_adma_setup_port(host->ports[i]); 1339 1340 return 0; 1341 } 1342 1343 static void nv_adma_fill_aprd(struct ata_queued_cmd *qc, 1344 struct scatterlist *sg, 1345 int idx, 1346 struct nv_adma_prd *aprd) 1347 { 1348 u8 flags = 0; 1349 if (qc->tf.flags & ATA_TFLAG_WRITE) 1350 flags |= NV_APRD_WRITE; 1351 if (idx == qc->n_elem - 1) 1352 flags |= NV_APRD_END; 1353 else if (idx != 4) 1354 flags |= NV_APRD_CONT; 1355 1356 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg))); 1357 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */ 1358 aprd->flags = flags; 1359 aprd->packet_len = 0; 1360 } 1361 1362 static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb) 1363 { 1364 struct nv_adma_port_priv *pp = qc->ap->private_data; 1365 struct nv_adma_prd *aprd; 1366 struct scatterlist *sg; 1367 unsigned int si; 1368 1369 VPRINTK("ENTER\n"); 1370 1371 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1372 aprd = (si < 5) ? &cpb->aprd[si] : 1373 &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (si-5)]; 1374 nv_adma_fill_aprd(qc, sg, si, aprd); 1375 } 1376 if (si > 5) 1377 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag))); 1378 else 1379 cpb->next_aprd = cpu_to_le64(0); 1380 } 1381 1382 static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc) 1383 { 1384 struct nv_adma_port_priv *pp = qc->ap->private_data; 1385 1386 /* ADMA engine can only be used for non-ATAPI DMA commands, 1387 or interrupt-driven no-data commands. */ 1388 if ((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) || 1389 (qc->tf.flags & ATA_TFLAG_POLLING)) 1390 return 1; 1391 1392 if ((qc->flags & ATA_QCFLAG_DMAMAP) || 1393 (qc->tf.protocol == ATA_PROT_NODATA)) 1394 return 0; 1395 1396 return 1; 1397 } 1398 1399 static void nv_adma_qc_prep(struct ata_queued_cmd *qc) 1400 { 1401 struct nv_adma_port_priv *pp = qc->ap->private_data; 1402 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag]; 1403 u8 ctl_flags = NV_CPB_CTL_CPB_VALID | 1404 NV_CPB_CTL_IEN; 1405 1406 if (nv_adma_use_reg_mode(qc)) { 1407 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) && 1408 (qc->flags & ATA_QCFLAG_DMAMAP)); 1409 nv_adma_register_mode(qc->ap); 1410 ata_sff_qc_prep(qc); 1411 return; 1412 } 1413 1414 cpb->resp_flags = NV_CPB_RESP_DONE; 1415 wmb(); 1416 cpb->ctl_flags = 0; 1417 wmb(); 1418 1419 cpb->len = 3; 1420 cpb->tag = qc->tag; 1421 cpb->next_cpb_idx = 0; 1422 1423 /* turn on NCQ flags for NCQ commands */ 1424 if (qc->tf.protocol == ATA_PROT_NCQ) 1425 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA; 1426 1427 VPRINTK("qc->flags = 0x%lx\n", qc->flags); 1428 1429 nv_adma_tf_to_cpb(&qc->tf, cpb->tf); 1430 1431 if (qc->flags & ATA_QCFLAG_DMAMAP) { 1432 nv_adma_fill_sg(qc, cpb); 1433 ctl_flags |= NV_CPB_CTL_APRD_VALID; 1434 } else 1435 memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5); 1436 1437 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID 1438 until we are finished filling in all of the contents */ 1439 wmb(); 1440 cpb->ctl_flags = ctl_flags; 1441 wmb(); 1442 cpb->resp_flags = 0; 1443 } 1444 1445 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc) 1446 { 1447 struct nv_adma_port_priv *pp = qc->ap->private_data; 1448 void __iomem *mmio = pp->ctl_block; 1449 int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ); 1450 1451 VPRINTK("ENTER\n"); 1452 1453 /* We can't handle result taskfile with NCQ commands, since 1454 retrieving the taskfile switches us out of ADMA mode and would abort 1455 existing commands. */ 1456 if (unlikely(qc->tf.protocol == ATA_PROT_NCQ && 1457 (qc->flags & ATA_QCFLAG_RESULT_TF))) { 1458 ata_dev_printk(qc->dev, KERN_ERR, 1459 "NCQ w/ RESULT_TF not allowed\n"); 1460 return AC_ERR_SYSTEM; 1461 } 1462 1463 if (nv_adma_use_reg_mode(qc)) { 1464 /* use ATA register mode */ 1465 VPRINTK("using ATA register mode: 0x%lx\n", qc->flags); 1466 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) && 1467 (qc->flags & ATA_QCFLAG_DMAMAP)); 1468 nv_adma_register_mode(qc->ap); 1469 return ata_sff_qc_issue(qc); 1470 } else 1471 nv_adma_mode(qc->ap); 1472 1473 /* write append register, command tag in lower 8 bits 1474 and (number of cpbs to append -1) in top 8 bits */ 1475 wmb(); 1476 1477 if (curr_ncq != pp->last_issue_ncq) { 1478 /* Seems to need some delay before switching between NCQ and 1479 non-NCQ commands, else we get command timeouts and such. */ 1480 udelay(20); 1481 pp->last_issue_ncq = curr_ncq; 1482 } 1483 1484 writew(qc->tag, mmio + NV_ADMA_APPEND); 1485 1486 DPRINTK("Issued tag %u\n", qc->tag); 1487 1488 return 0; 1489 } 1490 1491 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance) 1492 { 1493 struct ata_host *host = dev_instance; 1494 unsigned int i; 1495 unsigned int handled = 0; 1496 unsigned long flags; 1497 1498 spin_lock_irqsave(&host->lock, flags); 1499 1500 for (i = 0; i < host->n_ports; i++) { 1501 struct ata_port *ap; 1502 1503 ap = host->ports[i]; 1504 if (ap && 1505 !(ap->flags & ATA_FLAG_DISABLED)) { 1506 struct ata_queued_cmd *qc; 1507 1508 qc = ata_qc_from_tag(ap, ap->link.active_tag); 1509 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) 1510 handled += ata_sff_host_intr(ap, qc); 1511 else 1512 // No request pending? Clear interrupt status 1513 // anyway, in case there's one pending. 1514 ap->ops->sff_check_status(ap); 1515 } 1516 1517 } 1518 1519 spin_unlock_irqrestore(&host->lock, flags); 1520 1521 return IRQ_RETVAL(handled); 1522 } 1523 1524 static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat) 1525 { 1526 int i, handled = 0; 1527 1528 for (i = 0; i < host->n_ports; i++) { 1529 struct ata_port *ap = host->ports[i]; 1530 1531 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) 1532 handled += nv_host_intr(ap, irq_stat); 1533 1534 irq_stat >>= NV_INT_PORT_SHIFT; 1535 } 1536 1537 return IRQ_RETVAL(handled); 1538 } 1539 1540 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance) 1541 { 1542 struct ata_host *host = dev_instance; 1543 u8 irq_stat; 1544 irqreturn_t ret; 1545 1546 spin_lock(&host->lock); 1547 irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS); 1548 ret = nv_do_interrupt(host, irq_stat); 1549 spin_unlock(&host->lock); 1550 1551 return ret; 1552 } 1553 1554 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance) 1555 { 1556 struct ata_host *host = dev_instance; 1557 u8 irq_stat; 1558 irqreturn_t ret; 1559 1560 spin_lock(&host->lock); 1561 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804); 1562 ret = nv_do_interrupt(host, irq_stat); 1563 spin_unlock(&host->lock); 1564 1565 return ret; 1566 } 1567 1568 static int nv_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 1569 { 1570 if (sc_reg > SCR_CONTROL) 1571 return -EINVAL; 1572 1573 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg * 4)); 1574 return 0; 1575 } 1576 1577 static int nv_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 1578 { 1579 if (sc_reg > SCR_CONTROL) 1580 return -EINVAL; 1581 1582 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); 1583 return 0; 1584 } 1585 1586 static int nv_hardreset(struct ata_link *link, unsigned int *class, 1587 unsigned long deadline) 1588 { 1589 struct ata_eh_context *ehc = &link->eh_context; 1590 1591 /* Do hardreset iff it's post-boot probing, please read the 1592 * comment above port ops for details. 1593 */ 1594 if (!(link->ap->pflags & ATA_PFLAG_LOADING) && 1595 !ata_dev_enabled(link->device)) 1596 sata_link_hardreset(link, sata_deb_timing_hotplug, deadline, 1597 NULL, NULL); 1598 else { 1599 const unsigned long *timing = sata_ehc_deb_timing(ehc); 1600 int rc; 1601 1602 if (!(ehc->i.flags & ATA_EHI_QUIET)) 1603 ata_link_printk(link, KERN_INFO, "nv: skipping " 1604 "hardreset on occupied port\n"); 1605 1606 /* make sure the link is online */ 1607 rc = sata_link_resume(link, timing, deadline); 1608 /* whine about phy resume failure but proceed */ 1609 if (rc && rc != -EOPNOTSUPP) 1610 ata_link_printk(link, KERN_WARNING, "failed to resume " 1611 "link (errno=%d)\n", rc); 1612 } 1613 1614 /* device signature acquisition is unreliable */ 1615 return -EAGAIN; 1616 } 1617 1618 static void nv_nf2_freeze(struct ata_port *ap) 1619 { 1620 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr; 1621 int shift = ap->port_no * NV_INT_PORT_SHIFT; 1622 u8 mask; 1623 1624 mask = ioread8(scr_addr + NV_INT_ENABLE); 1625 mask &= ~(NV_INT_ALL << shift); 1626 iowrite8(mask, scr_addr + NV_INT_ENABLE); 1627 } 1628 1629 static void nv_nf2_thaw(struct ata_port *ap) 1630 { 1631 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr; 1632 int shift = ap->port_no * NV_INT_PORT_SHIFT; 1633 u8 mask; 1634 1635 iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS); 1636 1637 mask = ioread8(scr_addr + NV_INT_ENABLE); 1638 mask |= (NV_INT_MASK << shift); 1639 iowrite8(mask, scr_addr + NV_INT_ENABLE); 1640 } 1641 1642 static void nv_ck804_freeze(struct ata_port *ap) 1643 { 1644 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; 1645 int shift = ap->port_no * NV_INT_PORT_SHIFT; 1646 u8 mask; 1647 1648 mask = readb(mmio_base + NV_INT_ENABLE_CK804); 1649 mask &= ~(NV_INT_ALL << shift); 1650 writeb(mask, mmio_base + NV_INT_ENABLE_CK804); 1651 } 1652 1653 static void nv_ck804_thaw(struct ata_port *ap) 1654 { 1655 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; 1656 int shift = ap->port_no * NV_INT_PORT_SHIFT; 1657 u8 mask; 1658 1659 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804); 1660 1661 mask = readb(mmio_base + NV_INT_ENABLE_CK804); 1662 mask |= (NV_INT_MASK << shift); 1663 writeb(mask, mmio_base + NV_INT_ENABLE_CK804); 1664 } 1665 1666 static void nv_mcp55_freeze(struct ata_port *ap) 1667 { 1668 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; 1669 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55; 1670 u32 mask; 1671 1672 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55); 1673 1674 mask = readl(mmio_base + NV_INT_ENABLE_MCP55); 1675 mask &= ~(NV_INT_ALL_MCP55 << shift); 1676 writel(mask, mmio_base + NV_INT_ENABLE_MCP55); 1677 ata_sff_freeze(ap); 1678 } 1679 1680 static void nv_mcp55_thaw(struct ata_port *ap) 1681 { 1682 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR]; 1683 int shift = ap->port_no * NV_INT_PORT_SHIFT_MCP55; 1684 u32 mask; 1685 1686 writel(NV_INT_ALL_MCP55 << shift, mmio_base + NV_INT_STATUS_MCP55); 1687 1688 mask = readl(mmio_base + NV_INT_ENABLE_MCP55); 1689 mask |= (NV_INT_MASK_MCP55 << shift); 1690 writel(mask, mmio_base + NV_INT_ENABLE_MCP55); 1691 ata_sff_thaw(ap); 1692 } 1693 1694 static void nv_adma_error_handler(struct ata_port *ap) 1695 { 1696 struct nv_adma_port_priv *pp = ap->private_data; 1697 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) { 1698 void __iomem *mmio = pp->ctl_block; 1699 int i; 1700 u16 tmp; 1701 1702 if (ata_tag_valid(ap->link.active_tag) || ap->link.sactive) { 1703 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER); 1704 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR); 1705 u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL); 1706 u32 status = readw(mmio + NV_ADMA_STAT); 1707 u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT); 1708 u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX); 1709 1710 ata_port_printk(ap, KERN_ERR, 1711 "EH in ADMA mode, notifier 0x%X " 1712 "notifier_error 0x%X gen_ctl 0x%X status 0x%X " 1713 "next cpb count 0x%X next cpb idx 0x%x\n", 1714 notifier, notifier_error, gen_ctl, status, 1715 cpb_count, next_cpb_idx); 1716 1717 for (i = 0; i < NV_ADMA_MAX_CPBS; i++) { 1718 struct nv_adma_cpb *cpb = &pp->cpb[i]; 1719 if ((ata_tag_valid(ap->link.active_tag) && i == ap->link.active_tag) || 1720 ap->link.sactive & (1 << i)) 1721 ata_port_printk(ap, KERN_ERR, 1722 "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n", 1723 i, cpb->ctl_flags, cpb->resp_flags); 1724 } 1725 } 1726 1727 /* Push us back into port register mode for error handling. */ 1728 nv_adma_register_mode(ap); 1729 1730 /* Mark all of the CPBs as invalid to prevent them from 1731 being executed */ 1732 for (i = 0; i < NV_ADMA_MAX_CPBS; i++) 1733 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID; 1734 1735 /* clear CPB fetch count */ 1736 writew(0, mmio + NV_ADMA_CPB_COUNT); 1737 1738 /* Reset channel */ 1739 tmp = readw(mmio + NV_ADMA_CTL); 1740 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); 1741 readw(mmio + NV_ADMA_CTL); /* flush posted write */ 1742 udelay(1); 1743 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL); 1744 readw(mmio + NV_ADMA_CTL); /* flush posted write */ 1745 } 1746 1747 ata_sff_error_handler(ap); 1748 } 1749 1750 static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc) 1751 { 1752 struct nv_swncq_port_priv *pp = ap->private_data; 1753 struct defer_queue *dq = &pp->defer_queue; 1754 1755 /* queue is full */ 1756 WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE); 1757 dq->defer_bits |= (1 << qc->tag); 1758 dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->tag; 1759 } 1760 1761 static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap) 1762 { 1763 struct nv_swncq_port_priv *pp = ap->private_data; 1764 struct defer_queue *dq = &pp->defer_queue; 1765 unsigned int tag; 1766 1767 if (dq->head == dq->tail) /* null queue */ 1768 return NULL; 1769 1770 tag = dq->tag[dq->head & (ATA_MAX_QUEUE - 1)]; 1771 dq->tag[dq->head++ & (ATA_MAX_QUEUE - 1)] = ATA_TAG_POISON; 1772 WARN_ON(!(dq->defer_bits & (1 << tag))); 1773 dq->defer_bits &= ~(1 << tag); 1774 1775 return ata_qc_from_tag(ap, tag); 1776 } 1777 1778 static void nv_swncq_fis_reinit(struct ata_port *ap) 1779 { 1780 struct nv_swncq_port_priv *pp = ap->private_data; 1781 1782 pp->dhfis_bits = 0; 1783 pp->dmafis_bits = 0; 1784 pp->sdbfis_bits = 0; 1785 pp->ncq_flags = 0; 1786 } 1787 1788 static void nv_swncq_pp_reinit(struct ata_port *ap) 1789 { 1790 struct nv_swncq_port_priv *pp = ap->private_data; 1791 struct defer_queue *dq = &pp->defer_queue; 1792 1793 dq->head = 0; 1794 dq->tail = 0; 1795 dq->defer_bits = 0; 1796 pp->qc_active = 0; 1797 pp->last_issue_tag = ATA_TAG_POISON; 1798 nv_swncq_fis_reinit(ap); 1799 } 1800 1801 static void nv_swncq_irq_clear(struct ata_port *ap, u16 fis) 1802 { 1803 struct nv_swncq_port_priv *pp = ap->private_data; 1804 1805 writew(fis, pp->irq_block); 1806 } 1807 1808 static void __ata_bmdma_stop(struct ata_port *ap) 1809 { 1810 struct ata_queued_cmd qc; 1811 1812 qc.ap = ap; 1813 ata_bmdma_stop(&qc); 1814 } 1815 1816 static void nv_swncq_ncq_stop(struct ata_port *ap) 1817 { 1818 struct nv_swncq_port_priv *pp = ap->private_data; 1819 unsigned int i; 1820 u32 sactive; 1821 u32 done_mask; 1822 1823 ata_port_printk(ap, KERN_ERR, 1824 "EH in SWNCQ mode,QC:qc_active 0x%X sactive 0x%X\n", 1825 ap->qc_active, ap->link.sactive); 1826 ata_port_printk(ap, KERN_ERR, 1827 "SWNCQ:qc_active 0x%X defer_bits 0x%X last_issue_tag 0x%x\n " 1828 "dhfis 0x%X dmafis 0x%X sdbfis 0x%X\n", 1829 pp->qc_active, pp->defer_queue.defer_bits, pp->last_issue_tag, 1830 pp->dhfis_bits, pp->dmafis_bits, pp->sdbfis_bits); 1831 1832 ata_port_printk(ap, KERN_ERR, "ATA_REG 0x%X ERR_REG 0x%X\n", 1833 ap->ops->sff_check_status(ap), 1834 ioread8(ap->ioaddr.error_addr)); 1835 1836 sactive = readl(pp->sactive_block); 1837 done_mask = pp->qc_active ^ sactive; 1838 1839 ata_port_printk(ap, KERN_ERR, "tag : dhfis dmafis sdbfis sacitve\n"); 1840 for (i = 0; i < ATA_MAX_QUEUE; i++) { 1841 u8 err = 0; 1842 if (pp->qc_active & (1 << i)) 1843 err = 0; 1844 else if (done_mask & (1 << i)) 1845 err = 1; 1846 else 1847 continue; 1848 1849 ata_port_printk(ap, KERN_ERR, 1850 "tag 0x%x: %01x %01x %01x %01x %s\n", i, 1851 (pp->dhfis_bits >> i) & 0x1, 1852 (pp->dmafis_bits >> i) & 0x1, 1853 (pp->sdbfis_bits >> i) & 0x1, 1854 (sactive >> i) & 0x1, 1855 (err ? "error! tag doesn't exit" : " ")); 1856 } 1857 1858 nv_swncq_pp_reinit(ap); 1859 ap->ops->sff_irq_clear(ap); 1860 __ata_bmdma_stop(ap); 1861 nv_swncq_irq_clear(ap, 0xffff); 1862 } 1863 1864 static void nv_swncq_error_handler(struct ata_port *ap) 1865 { 1866 struct ata_eh_context *ehc = &ap->link.eh_context; 1867 1868 if (ap->link.sactive) { 1869 nv_swncq_ncq_stop(ap); 1870 ehc->i.action |= ATA_EH_RESET; 1871 } 1872 1873 ata_sff_error_handler(ap); 1874 } 1875 1876 #ifdef CONFIG_PM 1877 static int nv_swncq_port_suspend(struct ata_port *ap, pm_message_t mesg) 1878 { 1879 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; 1880 u32 tmp; 1881 1882 /* clear irq */ 1883 writel(~0, mmio + NV_INT_STATUS_MCP55); 1884 1885 /* disable irq */ 1886 writel(0, mmio + NV_INT_ENABLE_MCP55); 1887 1888 /* disable swncq */ 1889 tmp = readl(mmio + NV_CTL_MCP55); 1890 tmp &= ~(NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ); 1891 writel(tmp, mmio + NV_CTL_MCP55); 1892 1893 return 0; 1894 } 1895 1896 static int nv_swncq_port_resume(struct ata_port *ap) 1897 { 1898 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; 1899 u32 tmp; 1900 1901 /* clear irq */ 1902 writel(~0, mmio + NV_INT_STATUS_MCP55); 1903 1904 /* enable irq */ 1905 writel(0x00fd00fd, mmio + NV_INT_ENABLE_MCP55); 1906 1907 /* enable swncq */ 1908 tmp = readl(mmio + NV_CTL_MCP55); 1909 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55); 1910 1911 return 0; 1912 } 1913 #endif 1914 1915 static void nv_swncq_host_init(struct ata_host *host) 1916 { 1917 u32 tmp; 1918 void __iomem *mmio = host->iomap[NV_MMIO_BAR]; 1919 struct pci_dev *pdev = to_pci_dev(host->dev); 1920 u8 regval; 1921 1922 /* disable ECO 398 */ 1923 pci_read_config_byte(pdev, 0x7f, ®val); 1924 regval &= ~(1 << 7); 1925 pci_write_config_byte(pdev, 0x7f, regval); 1926 1927 /* enable swncq */ 1928 tmp = readl(mmio + NV_CTL_MCP55); 1929 VPRINTK("HOST_CTL:0x%X\n", tmp); 1930 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55); 1931 1932 /* enable irq intr */ 1933 tmp = readl(mmio + NV_INT_ENABLE_MCP55); 1934 VPRINTK("HOST_ENABLE:0x%X\n", tmp); 1935 writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55); 1936 1937 /* clear port irq */ 1938 writel(~0x0, mmio + NV_INT_STATUS_MCP55); 1939 } 1940 1941 static int nv_swncq_slave_config(struct scsi_device *sdev) 1942 { 1943 struct ata_port *ap = ata_shost_to_port(sdev->host); 1944 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 1945 struct ata_device *dev; 1946 int rc; 1947 u8 rev; 1948 u8 check_maxtor = 0; 1949 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 1950 1951 rc = ata_scsi_slave_config(sdev); 1952 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun) 1953 /* Not a proper libata device, ignore */ 1954 return rc; 1955 1956 dev = &ap->link.device[sdev->id]; 1957 if (!(ap->flags & ATA_FLAG_NCQ) || dev->class == ATA_DEV_ATAPI) 1958 return rc; 1959 1960 /* if MCP51 and Maxtor, then disable ncq */ 1961 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA || 1962 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2) 1963 check_maxtor = 1; 1964 1965 /* if MCP55 and rev <= a2 and Maxtor, then disable ncq */ 1966 if (pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA || 1967 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2) { 1968 pci_read_config_byte(pdev, 0x8, &rev); 1969 if (rev <= 0xa2) 1970 check_maxtor = 1; 1971 } 1972 1973 if (!check_maxtor) 1974 return rc; 1975 1976 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 1977 1978 if (strncmp(model_num, "Maxtor", 6) == 0) { 1979 ata_scsi_change_queue_depth(sdev, 1, SCSI_QDEPTH_DEFAULT); 1980 ata_dev_printk(dev, KERN_NOTICE, 1981 "Disabling SWNCQ mode (depth %x)\n", sdev->queue_depth); 1982 } 1983 1984 return rc; 1985 } 1986 1987 static int nv_swncq_port_start(struct ata_port *ap) 1988 { 1989 struct device *dev = ap->host->dev; 1990 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; 1991 struct nv_swncq_port_priv *pp; 1992 int rc; 1993 1994 rc = ata_port_start(ap); 1995 if (rc) 1996 return rc; 1997 1998 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1999 if (!pp) 2000 return -ENOMEM; 2001 2002 pp->prd = dmam_alloc_coherent(dev, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE, 2003 &pp->prd_dma, GFP_KERNEL); 2004 if (!pp->prd) 2005 return -ENOMEM; 2006 memset(pp->prd, 0, ATA_PRD_TBL_SZ * ATA_MAX_QUEUE); 2007 2008 ap->private_data = pp; 2009 pp->sactive_block = ap->ioaddr.scr_addr + 4 * SCR_ACTIVE; 2010 pp->irq_block = mmio + NV_INT_STATUS_MCP55 + ap->port_no * 2; 2011 pp->tag_block = mmio + NV_NCQ_REG_MCP55 + ap->port_no * 2; 2012 2013 return 0; 2014 } 2015 2016 static void nv_swncq_qc_prep(struct ata_queued_cmd *qc) 2017 { 2018 if (qc->tf.protocol != ATA_PROT_NCQ) { 2019 ata_sff_qc_prep(qc); 2020 return; 2021 } 2022 2023 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2024 return; 2025 2026 nv_swncq_fill_sg(qc); 2027 } 2028 2029 static void nv_swncq_fill_sg(struct ata_queued_cmd *qc) 2030 { 2031 struct ata_port *ap = qc->ap; 2032 struct scatterlist *sg; 2033 struct nv_swncq_port_priv *pp = ap->private_data; 2034 struct ata_prd *prd; 2035 unsigned int si, idx; 2036 2037 prd = pp->prd + ATA_MAX_PRD * qc->tag; 2038 2039 idx = 0; 2040 for_each_sg(qc->sg, sg, qc->n_elem, si) { 2041 u32 addr, offset; 2042 u32 sg_len, len; 2043 2044 addr = (u32)sg_dma_address(sg); 2045 sg_len = sg_dma_len(sg); 2046 2047 while (sg_len) { 2048 offset = addr & 0xffff; 2049 len = sg_len; 2050 if ((offset + sg_len) > 0x10000) 2051 len = 0x10000 - offset; 2052 2053 prd[idx].addr = cpu_to_le32(addr); 2054 prd[idx].flags_len = cpu_to_le32(len & 0xffff); 2055 2056 idx++; 2057 sg_len -= len; 2058 addr += len; 2059 } 2060 } 2061 2062 prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 2063 } 2064 2065 static unsigned int nv_swncq_issue_atacmd(struct ata_port *ap, 2066 struct ata_queued_cmd *qc) 2067 { 2068 struct nv_swncq_port_priv *pp = ap->private_data; 2069 2070 if (qc == NULL) 2071 return 0; 2072 2073 DPRINTK("Enter\n"); 2074 2075 writel((1 << qc->tag), pp->sactive_block); 2076 pp->last_issue_tag = qc->tag; 2077 pp->dhfis_bits &= ~(1 << qc->tag); 2078 pp->dmafis_bits &= ~(1 << qc->tag); 2079 pp->qc_active |= (0x1 << qc->tag); 2080 2081 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ 2082 ap->ops->sff_exec_command(ap, &qc->tf); 2083 2084 DPRINTK("Issued tag %u\n", qc->tag); 2085 2086 return 0; 2087 } 2088 2089 static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc) 2090 { 2091 struct ata_port *ap = qc->ap; 2092 struct nv_swncq_port_priv *pp = ap->private_data; 2093 2094 if (qc->tf.protocol != ATA_PROT_NCQ) 2095 return ata_sff_qc_issue(qc); 2096 2097 DPRINTK("Enter\n"); 2098 2099 if (!pp->qc_active) 2100 nv_swncq_issue_atacmd(ap, qc); 2101 else 2102 nv_swncq_qc_to_dq(ap, qc); /* add qc to defer queue */ 2103 2104 return 0; 2105 } 2106 2107 static void nv_swncq_hotplug(struct ata_port *ap, u32 fis) 2108 { 2109 u32 serror; 2110 struct ata_eh_info *ehi = &ap->link.eh_info; 2111 2112 ata_ehi_clear_desc(ehi); 2113 2114 /* AHCI needs SError cleared; otherwise, it might lock up */ 2115 sata_scr_read(&ap->link, SCR_ERROR, &serror); 2116 sata_scr_write(&ap->link, SCR_ERROR, serror); 2117 2118 /* analyze @irq_stat */ 2119 if (fis & NV_SWNCQ_IRQ_ADDED) 2120 ata_ehi_push_desc(ehi, "hot plug"); 2121 else if (fis & NV_SWNCQ_IRQ_REMOVED) 2122 ata_ehi_push_desc(ehi, "hot unplug"); 2123 2124 ata_ehi_hotplugged(ehi); 2125 2126 /* okay, let's hand over to EH */ 2127 ehi->serror |= serror; 2128 2129 ata_port_freeze(ap); 2130 } 2131 2132 static int nv_swncq_sdbfis(struct ata_port *ap) 2133 { 2134 struct ata_queued_cmd *qc; 2135 struct nv_swncq_port_priv *pp = ap->private_data; 2136 struct ata_eh_info *ehi = &ap->link.eh_info; 2137 u32 sactive; 2138 int nr_done = 0; 2139 u32 done_mask; 2140 int i; 2141 u8 host_stat; 2142 u8 lack_dhfis = 0; 2143 2144 host_stat = ap->ops->bmdma_status(ap); 2145 if (unlikely(host_stat & ATA_DMA_ERR)) { 2146 /* error when transfering data to/from memory */ 2147 ata_ehi_clear_desc(ehi); 2148 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); 2149 ehi->err_mask |= AC_ERR_HOST_BUS; 2150 ehi->action |= ATA_EH_RESET; 2151 return -EINVAL; 2152 } 2153 2154 ap->ops->sff_irq_clear(ap); 2155 __ata_bmdma_stop(ap); 2156 2157 sactive = readl(pp->sactive_block); 2158 done_mask = pp->qc_active ^ sactive; 2159 2160 if (unlikely(done_mask & sactive)) { 2161 ata_ehi_clear_desc(ehi); 2162 ata_ehi_push_desc(ehi, "illegal SWNCQ:qc_active transition" 2163 "(%08x->%08x)", pp->qc_active, sactive); 2164 ehi->err_mask |= AC_ERR_HSM; 2165 ehi->action |= ATA_EH_RESET; 2166 return -EINVAL; 2167 } 2168 for (i = 0; i < ATA_MAX_QUEUE; i++) { 2169 if (!(done_mask & (1 << i))) 2170 continue; 2171 2172 qc = ata_qc_from_tag(ap, i); 2173 if (qc) { 2174 ata_qc_complete(qc); 2175 pp->qc_active &= ~(1 << i); 2176 pp->dhfis_bits &= ~(1 << i); 2177 pp->dmafis_bits &= ~(1 << i); 2178 pp->sdbfis_bits |= (1 << i); 2179 nr_done++; 2180 } 2181 } 2182 2183 if (!ap->qc_active) { 2184 DPRINTK("over\n"); 2185 nv_swncq_pp_reinit(ap); 2186 return nr_done; 2187 } 2188 2189 if (pp->qc_active & pp->dhfis_bits) 2190 return nr_done; 2191 2192 if ((pp->ncq_flags & ncq_saw_backout) || 2193 (pp->qc_active ^ pp->dhfis_bits)) 2194 /* if the controller cann't get a device to host register FIS, 2195 * The driver needs to reissue the new command. 2196 */ 2197 lack_dhfis = 1; 2198 2199 DPRINTK("id 0x%x QC: qc_active 0x%x," 2200 "SWNCQ:qc_active 0x%X defer_bits %X " 2201 "dhfis 0x%X dmafis 0x%X last_issue_tag %x\n", 2202 ap->print_id, ap->qc_active, pp->qc_active, 2203 pp->defer_queue.defer_bits, pp->dhfis_bits, 2204 pp->dmafis_bits, pp->last_issue_tag); 2205 2206 nv_swncq_fis_reinit(ap); 2207 2208 if (lack_dhfis) { 2209 qc = ata_qc_from_tag(ap, pp->last_issue_tag); 2210 nv_swncq_issue_atacmd(ap, qc); 2211 return nr_done; 2212 } 2213 2214 if (pp->defer_queue.defer_bits) { 2215 /* send deferral queue command */ 2216 qc = nv_swncq_qc_from_dq(ap); 2217 WARN_ON(qc == NULL); 2218 nv_swncq_issue_atacmd(ap, qc); 2219 } 2220 2221 return nr_done; 2222 } 2223 2224 static inline u32 nv_swncq_tag(struct ata_port *ap) 2225 { 2226 struct nv_swncq_port_priv *pp = ap->private_data; 2227 u32 tag; 2228 2229 tag = readb(pp->tag_block) >> 2; 2230 return (tag & 0x1f); 2231 } 2232 2233 static int nv_swncq_dmafis(struct ata_port *ap) 2234 { 2235 struct ata_queued_cmd *qc; 2236 unsigned int rw; 2237 u8 dmactl; 2238 u32 tag; 2239 struct nv_swncq_port_priv *pp = ap->private_data; 2240 2241 __ata_bmdma_stop(ap); 2242 tag = nv_swncq_tag(ap); 2243 2244 DPRINTK("dma setup tag 0x%x\n", tag); 2245 qc = ata_qc_from_tag(ap, tag); 2246 2247 if (unlikely(!qc)) 2248 return 0; 2249 2250 rw = qc->tf.flags & ATA_TFLAG_WRITE; 2251 2252 /* load PRD table addr. */ 2253 iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->tag, 2254 ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); 2255 2256 /* specify data direction, triple-check start bit is clear */ 2257 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 2258 dmactl &= ~ATA_DMA_WR; 2259 if (!rw) 2260 dmactl |= ATA_DMA_WR; 2261 2262 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 2263 2264 return 1; 2265 } 2266 2267 static void nv_swncq_host_interrupt(struct ata_port *ap, u16 fis) 2268 { 2269 struct nv_swncq_port_priv *pp = ap->private_data; 2270 struct ata_queued_cmd *qc; 2271 struct ata_eh_info *ehi = &ap->link.eh_info; 2272 u32 serror; 2273 u8 ata_stat; 2274 int rc = 0; 2275 2276 ata_stat = ap->ops->sff_check_status(ap); 2277 nv_swncq_irq_clear(ap, fis); 2278 if (!fis) 2279 return; 2280 2281 if (ap->pflags & ATA_PFLAG_FROZEN) 2282 return; 2283 2284 if (fis & NV_SWNCQ_IRQ_HOTPLUG) { 2285 nv_swncq_hotplug(ap, fis); 2286 return; 2287 } 2288 2289 if (!pp->qc_active) 2290 return; 2291 2292 if (ap->ops->scr_read(&ap->link, SCR_ERROR, &serror)) 2293 return; 2294 ap->ops->scr_write(&ap->link, SCR_ERROR, serror); 2295 2296 if (ata_stat & ATA_ERR) { 2297 ata_ehi_clear_desc(ehi); 2298 ata_ehi_push_desc(ehi, "Ata error. fis:0x%X", fis); 2299 ehi->err_mask |= AC_ERR_DEV; 2300 ehi->serror |= serror; 2301 ehi->action |= ATA_EH_RESET; 2302 ata_port_freeze(ap); 2303 return; 2304 } 2305 2306 if (fis & NV_SWNCQ_IRQ_BACKOUT) { 2307 /* If the IRQ is backout, driver must issue 2308 * the new command again some time later. 2309 */ 2310 pp->ncq_flags |= ncq_saw_backout; 2311 } 2312 2313 if (fis & NV_SWNCQ_IRQ_SDBFIS) { 2314 pp->ncq_flags |= ncq_saw_sdb; 2315 DPRINTK("id 0x%x SWNCQ: qc_active 0x%X " 2316 "dhfis 0x%X dmafis 0x%X sactive 0x%X\n", 2317 ap->print_id, pp->qc_active, pp->dhfis_bits, 2318 pp->dmafis_bits, readl(pp->sactive_block)); 2319 rc = nv_swncq_sdbfis(ap); 2320 if (rc < 0) 2321 goto irq_error; 2322 } 2323 2324 if (fis & NV_SWNCQ_IRQ_DHREGFIS) { 2325 /* The interrupt indicates the new command 2326 * was transmitted correctly to the drive. 2327 */ 2328 pp->dhfis_bits |= (0x1 << pp->last_issue_tag); 2329 pp->ncq_flags |= ncq_saw_d2h; 2330 if (pp->ncq_flags & (ncq_saw_sdb | ncq_saw_backout)) { 2331 ata_ehi_push_desc(ehi, "illegal fis transaction"); 2332 ehi->err_mask |= AC_ERR_HSM; 2333 ehi->action |= ATA_EH_RESET; 2334 goto irq_error; 2335 } 2336 2337 if (!(fis & NV_SWNCQ_IRQ_DMASETUP) && 2338 !(pp->ncq_flags & ncq_saw_dmas)) { 2339 ata_stat = ap->ops->sff_check_status(ap); 2340 if (ata_stat & ATA_BUSY) 2341 goto irq_exit; 2342 2343 if (pp->defer_queue.defer_bits) { 2344 DPRINTK("send next command\n"); 2345 qc = nv_swncq_qc_from_dq(ap); 2346 nv_swncq_issue_atacmd(ap, qc); 2347 } 2348 } 2349 } 2350 2351 if (fis & NV_SWNCQ_IRQ_DMASETUP) { 2352 /* program the dma controller with appropriate PRD buffers 2353 * and start the DMA transfer for requested command. 2354 */ 2355 pp->dmafis_bits |= (0x1 << nv_swncq_tag(ap)); 2356 pp->ncq_flags |= ncq_saw_dmas; 2357 rc = nv_swncq_dmafis(ap); 2358 } 2359 2360 irq_exit: 2361 return; 2362 irq_error: 2363 ata_ehi_push_desc(ehi, "fis:0x%x", fis); 2364 ata_port_freeze(ap); 2365 return; 2366 } 2367 2368 static irqreturn_t nv_swncq_interrupt(int irq, void *dev_instance) 2369 { 2370 struct ata_host *host = dev_instance; 2371 unsigned int i; 2372 unsigned int handled = 0; 2373 unsigned long flags; 2374 u32 irq_stat; 2375 2376 spin_lock_irqsave(&host->lock, flags); 2377 2378 irq_stat = readl(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_MCP55); 2379 2380 for (i = 0; i < host->n_ports; i++) { 2381 struct ata_port *ap = host->ports[i]; 2382 2383 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { 2384 if (ap->link.sactive) { 2385 nv_swncq_host_interrupt(ap, (u16)irq_stat); 2386 handled = 1; 2387 } else { 2388 if (irq_stat) /* reserve Hotplug */ 2389 nv_swncq_irq_clear(ap, 0xfff0); 2390 2391 handled += nv_host_intr(ap, (u8)irq_stat); 2392 } 2393 } 2394 irq_stat >>= NV_INT_PORT_SHIFT_MCP55; 2395 } 2396 2397 spin_unlock_irqrestore(&host->lock, flags); 2398 2399 return IRQ_RETVAL(handled); 2400 } 2401 2402 static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2403 { 2404 static int printed_version; 2405 const struct ata_port_info *ppi[] = { NULL, NULL }; 2406 struct nv_pi_priv *ipriv; 2407 struct ata_host *host; 2408 struct nv_host_priv *hpriv; 2409 int rc; 2410 u32 bar; 2411 void __iomem *base; 2412 unsigned long type = ent->driver_data; 2413 2414 // Make sure this is a SATA controller by counting the number of bars 2415 // (NVIDIA SATA controllers will always have six bars). Otherwise, 2416 // it's an IDE controller and we ignore it. 2417 for (bar = 0; bar < 6; bar++) 2418 if (pci_resource_start(pdev, bar) == 0) 2419 return -ENODEV; 2420 2421 if (!printed_version++) 2422 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 2423 2424 rc = pcim_enable_device(pdev); 2425 if (rc) 2426 return rc; 2427 2428 /* determine type and allocate host */ 2429 if (type == CK804 && adma_enabled) { 2430 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n"); 2431 type = ADMA; 2432 } else if (type == MCP5x && swncq_enabled) { 2433 dev_printk(KERN_NOTICE, &pdev->dev, "Using SWNCQ mode\n"); 2434 type = SWNCQ; 2435 } 2436 2437 ppi[0] = &nv_port_info[type]; 2438 ipriv = ppi[0]->private_data; 2439 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 2440 if (rc) 2441 return rc; 2442 2443 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 2444 if (!hpriv) 2445 return -ENOMEM; 2446 hpriv->type = type; 2447 host->private_data = hpriv; 2448 2449 /* request and iomap NV_MMIO_BAR */ 2450 rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME); 2451 if (rc) 2452 return rc; 2453 2454 /* configure SCR access */ 2455 base = host->iomap[NV_MMIO_BAR]; 2456 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET; 2457 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET; 2458 2459 /* enable SATA space for CK804 */ 2460 if (type >= CK804) { 2461 u8 regval; 2462 2463 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); 2464 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; 2465 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); 2466 } 2467 2468 /* init ADMA */ 2469 if (type == ADMA) { 2470 rc = nv_adma_host_init(host); 2471 if (rc) 2472 return rc; 2473 } else if (type == SWNCQ) 2474 nv_swncq_host_init(host); 2475 2476 if (msi_enabled) { 2477 dev_printk(KERN_NOTICE, &pdev->dev, "Using MSI\n"); 2478 pci_enable_msi(pdev); 2479 } 2480 2481 pci_set_master(pdev); 2482 return ata_host_activate(host, pdev->irq, ipriv->irq_handler, 2483 IRQF_SHARED, ipriv->sht); 2484 } 2485 2486 #ifdef CONFIG_PM 2487 static int nv_pci_device_resume(struct pci_dev *pdev) 2488 { 2489 struct ata_host *host = dev_get_drvdata(&pdev->dev); 2490 struct nv_host_priv *hpriv = host->private_data; 2491 int rc; 2492 2493 rc = ata_pci_device_do_resume(pdev); 2494 if (rc) 2495 return rc; 2496 2497 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 2498 if (hpriv->type >= CK804) { 2499 u8 regval; 2500 2501 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); 2502 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; 2503 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); 2504 } 2505 if (hpriv->type == ADMA) { 2506 u32 tmp32; 2507 struct nv_adma_port_priv *pp; 2508 /* enable/disable ADMA on the ports appropriately */ 2509 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); 2510 2511 pp = host->ports[0]->private_data; 2512 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) 2513 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN | 2514 NV_MCP_SATA_CFG_20_PORT0_PWB_EN); 2515 else 2516 tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN | 2517 NV_MCP_SATA_CFG_20_PORT0_PWB_EN); 2518 pp = host->ports[1]->private_data; 2519 if (pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) 2520 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN | 2521 NV_MCP_SATA_CFG_20_PORT1_PWB_EN); 2522 else 2523 tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN | 2524 NV_MCP_SATA_CFG_20_PORT1_PWB_EN); 2525 2526 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); 2527 } 2528 } 2529 2530 ata_host_resume(host); 2531 2532 return 0; 2533 } 2534 #endif 2535 2536 static void nv_ck804_host_stop(struct ata_host *host) 2537 { 2538 struct pci_dev *pdev = to_pci_dev(host->dev); 2539 u8 regval; 2540 2541 /* disable SATA space for CK804 */ 2542 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); 2543 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN; 2544 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); 2545 } 2546 2547 static void nv_adma_host_stop(struct ata_host *host) 2548 { 2549 struct pci_dev *pdev = to_pci_dev(host->dev); 2550 u32 tmp32; 2551 2552 /* disable ADMA on the ports */ 2553 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32); 2554 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN | 2555 NV_MCP_SATA_CFG_20_PORT0_PWB_EN | 2556 NV_MCP_SATA_CFG_20_PORT1_EN | 2557 NV_MCP_SATA_CFG_20_PORT1_PWB_EN); 2558 2559 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32); 2560 2561 nv_ck804_host_stop(host); 2562 } 2563 2564 static int __init nv_init(void) 2565 { 2566 return pci_register_driver(&nv_pci_driver); 2567 } 2568 2569 static void __exit nv_exit(void) 2570 { 2571 pci_unregister_driver(&nv_pci_driver); 2572 } 2573 2574 module_init(nv_init); 2575 module_exit(nv_exit); 2576 module_param_named(adma, adma_enabled, bool, 0444); 2577 MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: false)"); 2578 module_param_named(swncq, swncq_enabled, bool, 0444); 2579 MODULE_PARM_DESC(swncq, "Enable use of SWNCQ (Default: true)"); 2580 module_param_named(msi, msi_enabled, bool, 0444); 2581 MODULE_PARM_DESC(msi, "Enable use of MSI (Default: false)"); 2582 2583