1 /* 2 * sata_mv.c - Marvell SATA support 3 * 4 * Copyright 2008-2009: Marvell Corporation, all rights reserved. 5 * Copyright 2005: EMC Corporation, all rights reserved. 6 * Copyright 2005 Red Hat, Inc. All rights reserved. 7 * 8 * Originally written by Brett Russ. 9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. 10 * 11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; version 2 of the License. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 /* 29 * sata_mv TODO list: 30 * 31 * --> Develop a low-power-consumption strategy, and implement it. 32 * 33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. 34 * 35 * --> [Experiment, Marvell value added] Is it possible to use target 36 * mode to cross-connect two Linux boxes with Marvell cards? If so, 37 * creating LibATA target mode support would be very interesting. 38 * 39 * Target mode, for those without docs, is the ability to directly 40 * connect two SATA ports. 41 */ 42 43 /* 44 * 80x1-B2 errata PCI#11: 45 * 46 * Users of the 6041/6081 Rev.B2 chips (current is C0) 47 * should be careful to insert those cards only onto PCI-X bus #0, 48 * and only in device slots 0..7, not higher. The chips may not 49 * work correctly otherwise (note: this is a pretty rare condition). 50 */ 51 52 #include <linux/kernel.h> 53 #include <linux/module.h> 54 #include <linux/pci.h> 55 #include <linux/init.h> 56 #include <linux/blkdev.h> 57 #include <linux/delay.h> 58 #include <linux/interrupt.h> 59 #include <linux/dmapool.h> 60 #include <linux/dma-mapping.h> 61 #include <linux/device.h> 62 #include <linux/clk.h> 63 #include <linux/phy/phy.h> 64 #include <linux/platform_device.h> 65 #include <linux/ata_platform.h> 66 #include <linux/mbus.h> 67 #include <linux/bitops.h> 68 #include <linux/gfp.h> 69 #include <linux/of.h> 70 #include <linux/of_irq.h> 71 #include <scsi/scsi_host.h> 72 #include <scsi/scsi_cmnd.h> 73 #include <scsi/scsi_device.h> 74 #include <linux/libata.h> 75 76 #define DRV_NAME "sata_mv" 77 #define DRV_VERSION "1.28" 78 79 /* 80 * module options 81 */ 82 83 #ifdef CONFIG_PCI 84 static int msi; 85 module_param(msi, int, S_IRUGO); 86 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 87 #endif 88 89 static int irq_coalescing_io_count; 90 module_param(irq_coalescing_io_count, int, S_IRUGO); 91 MODULE_PARM_DESC(irq_coalescing_io_count, 92 "IRQ coalescing I/O count threshold (0..255)"); 93 94 static int irq_coalescing_usecs; 95 module_param(irq_coalescing_usecs, int, S_IRUGO); 96 MODULE_PARM_DESC(irq_coalescing_usecs, 97 "IRQ coalescing time threshold in usecs"); 98 99 enum { 100 /* BAR's are enumerated in terms of pci_resource_start() terms */ 101 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 102 MV_IO_BAR = 2, /* offset 0x18: IO space */ 103 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 104 105 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 106 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 107 108 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ 109 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ 110 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ 111 MAX_COAL_IO_COUNT = 255, /* completed I/O count */ 112 113 MV_PCI_REG_BASE = 0, 114 115 /* 116 * Per-chip ("all ports") interrupt coalescing feature. 117 * This is only for GEN_II / GEN_IIE hardware. 118 * 119 * Coalescing defers the interrupt until either the IO_THRESHOLD 120 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 121 */ 122 COAL_REG_BASE = 0x18000, 123 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), 124 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ 125 126 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), 127 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), 128 129 /* 130 * Registers for the (unused here) transaction coalescing feature: 131 */ 132 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), 133 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), 134 135 SATAHC0_REG_BASE = 0x20000, 136 FLASH_CTL = 0x1046c, 137 GPIO_PORT_CTL = 0x104f0, 138 RESET_CFG = 0x180d8, 139 140 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 141 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 142 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 143 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 144 145 MV_MAX_Q_DEPTH = 32, 146 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 147 148 /* CRQB needs alignment on a 1KB boundary. Size == 1KB 149 * CRPB needs alignment on a 256B boundary. Size == 256B 150 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 151 */ 152 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 153 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 154 MV_MAX_SG_CT = 256, 155 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 156 157 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 158 MV_PORT_HC_SHIFT = 2, 159 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 160 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 161 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 162 163 /* Host Flags */ 164 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 165 166 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING, 167 168 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, 169 170 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | 171 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, 172 173 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, 174 175 CRQB_FLAG_READ = (1 << 0), 176 CRQB_TAG_SHIFT = 1, 177 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 178 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 179 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 180 CRQB_CMD_ADDR_SHIFT = 8, 181 CRQB_CMD_CS = (0x2 << 11), 182 CRQB_CMD_LAST = (1 << 15), 183 184 CRPB_FLAG_STATUS_SHIFT = 8, 185 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 186 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 187 188 EPRD_FLAG_END_OF_TBL = (1 << 31), 189 190 /* PCI interface registers */ 191 192 MV_PCI_COMMAND = 0xc00, 193 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ 194 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 195 196 PCI_MAIN_CMD_STS = 0xd30, 197 STOP_PCI_MASTER = (1 << 2), 198 PCI_MASTER_EMPTY = (1 << 3), 199 GLOB_SFT_RST = (1 << 4), 200 201 MV_PCI_MODE = 0xd00, 202 MV_PCI_MODE_MASK = 0x30, 203 204 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 205 MV_PCI_DISC_TIMER = 0xd04, 206 MV_PCI_MSI_TRIGGER = 0xc38, 207 MV_PCI_SERR_MASK = 0xc28, 208 MV_PCI_XBAR_TMOUT = 0x1d04, 209 MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 210 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 211 MV_PCI_ERR_ATTRIBUTE = 0x1d48, 212 MV_PCI_ERR_COMMAND = 0x1d50, 213 214 PCI_IRQ_CAUSE = 0x1d58, 215 PCI_IRQ_MASK = 0x1d5c, 216 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 217 218 PCIE_IRQ_CAUSE = 0x1900, 219 PCIE_IRQ_MASK = 0x1910, 220 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 221 222 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 223 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, 224 PCI_HC_MAIN_IRQ_MASK = 0x1d64, 225 SOC_HC_MAIN_IRQ_CAUSE = 0x20020, 226 SOC_HC_MAIN_IRQ_MASK = 0x20024, 227 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ 228 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ 229 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 230 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 231 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ 232 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ 233 PCI_ERR = (1 << 18), 234 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ 235 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ 236 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ 237 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ 238 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ 239 GPIO_INT = (1 << 22), 240 SELF_INT = (1 << 23), 241 TWSI_INT = (1 << 24), 242 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 243 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 244 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 245 246 /* SATAHC registers */ 247 HC_CFG = 0x00, 248 249 HC_IRQ_CAUSE = 0x14, 250 DMA_IRQ = (1 << 0), /* shift by port # */ 251 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 252 DEV_IRQ = (1 << 8), /* shift by port # */ 253 254 /* 255 * Per-HC (Host-Controller) interrupt coalescing feature. 256 * This is present on all chip generations. 257 * 258 * Coalescing defers the interrupt until either the IO_THRESHOLD 259 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. 260 */ 261 HC_IRQ_COAL_IO_THRESHOLD = 0x000c, 262 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, 263 264 SOC_LED_CTRL = 0x2c, 265 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ 266 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ 267 /* with dev activity LED */ 268 269 /* Shadow block registers */ 270 SHD_BLK = 0x100, 271 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ 272 273 /* SATA registers */ 274 SATA_STATUS = 0x300, /* ctrl, err regs follow status */ 275 SATA_ACTIVE = 0x350, 276 FIS_IRQ_CAUSE = 0x364, 277 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ 278 279 LTMODE = 0x30c, /* requires read-after-write */ 280 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 281 282 PHY_MODE2 = 0x330, 283 PHY_MODE3 = 0x310, 284 285 PHY_MODE4 = 0x314, /* requires read-after-write */ 286 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 287 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 288 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 289 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 290 291 SATA_IFCTL = 0x344, 292 SATA_TESTCTL = 0x348, 293 SATA_IFSTAT = 0x34c, 294 VENDOR_UNIQUE_FIS = 0x35c, 295 296 FISCFG = 0x360, 297 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 298 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 299 300 PHY_MODE9_GEN2 = 0x398, 301 PHY_MODE9_GEN1 = 0x39c, 302 PHYCFG_OFS = 0x3a0, /* only in 65n devices */ 303 304 MV5_PHY_MODE = 0x74, 305 MV5_LTMODE = 0x30, 306 MV5_PHY_CTL = 0x0C, 307 SATA_IFCFG = 0x050, 308 LP_PHY_CTL = 0x058, 309 310 MV_M2_PREAMP_MASK = 0x7e0, 311 312 /* Port registers */ 313 EDMA_CFG = 0, 314 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 315 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 316 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 317 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 318 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 319 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 320 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 321 322 EDMA_ERR_IRQ_CAUSE = 0x8, 323 EDMA_ERR_IRQ_MASK = 0xc, 324 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 325 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 326 EDMA_ERR_DEV = (1 << 2), /* device error */ 327 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 328 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 329 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 330 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 331 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 332 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 333 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 334 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 335 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 336 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 337 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 338 339 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 340 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 341 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 342 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 343 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 344 345 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 346 347 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 348 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 349 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 350 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 351 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 352 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 353 354 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 355 356 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 357 EDMA_ERR_OVERRUN_5 = (1 << 5), 358 EDMA_ERR_UNDERRUN_5 = (1 << 6), 359 360 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 361 EDMA_ERR_LNK_CTRL_RX_1 | 362 EDMA_ERR_LNK_CTRL_RX_3 | 363 EDMA_ERR_LNK_CTRL_TX, 364 365 EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 366 EDMA_ERR_PRD_PAR | 367 EDMA_ERR_DEV_DCON | 368 EDMA_ERR_DEV_CON | 369 EDMA_ERR_SERR | 370 EDMA_ERR_SELF_DIS | 371 EDMA_ERR_CRQB_PAR | 372 EDMA_ERR_CRPB_PAR | 373 EDMA_ERR_INTRL_PAR | 374 EDMA_ERR_IORDY | 375 EDMA_ERR_LNK_CTRL_RX_2 | 376 EDMA_ERR_LNK_DATA_RX | 377 EDMA_ERR_LNK_DATA_TX | 378 EDMA_ERR_TRANS_PROTO, 379 380 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 381 EDMA_ERR_PRD_PAR | 382 EDMA_ERR_DEV_DCON | 383 EDMA_ERR_DEV_CON | 384 EDMA_ERR_OVERRUN_5 | 385 EDMA_ERR_UNDERRUN_5 | 386 EDMA_ERR_SELF_DIS_5 | 387 EDMA_ERR_CRQB_PAR | 388 EDMA_ERR_CRPB_PAR | 389 EDMA_ERR_INTRL_PAR | 390 EDMA_ERR_IORDY, 391 392 EDMA_REQ_Q_BASE_HI = 0x10, 393 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ 394 395 EDMA_REQ_Q_OUT_PTR = 0x18, 396 EDMA_REQ_Q_PTR_SHIFT = 5, 397 398 EDMA_RSP_Q_BASE_HI = 0x1c, 399 EDMA_RSP_Q_IN_PTR = 0x20, 400 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ 401 EDMA_RSP_Q_PTR_SHIFT = 3, 402 403 EDMA_CMD = 0x28, /* EDMA command register */ 404 EDMA_EN = (1 << 0), /* enable EDMA */ 405 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 406 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 407 408 EDMA_STATUS = 0x30, /* EDMA engine status */ 409 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 410 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 411 412 EDMA_IORDY_TMOUT = 0x34, 413 EDMA_ARB_CFG = 0x38, 414 415 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ 416 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ 417 418 BMDMA_CMD = 0x224, /* bmdma command register */ 419 BMDMA_STATUS = 0x228, /* bmdma status register */ 420 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ 421 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ 422 423 /* Host private flags (hp_flags) */ 424 MV_HP_FLAG_MSI = (1 << 0), 425 MV_HP_ERRATA_50XXB0 = (1 << 1), 426 MV_HP_ERRATA_50XXB2 = (1 << 2), 427 MV_HP_ERRATA_60X1B2 = (1 << 3), 428 MV_HP_ERRATA_60X1C0 = (1 << 4), 429 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 430 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 431 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 432 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 433 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 434 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 435 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 436 MV_HP_FIX_LP_PHY_CTL = (1 << 13), /* fix speed in LP_PHY_CTL ? */ 437 438 /* Port private flags (pp_flags) */ 439 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 440 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 441 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 442 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 443 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ 444 }; 445 446 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 447 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 448 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 449 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 450 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 451 452 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 453 #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 454 455 enum { 456 /* DMA boundary 0xffff is required by the s/g splitting 457 * we need on /length/ in mv_fill-sg(). 458 */ 459 MV_DMA_BOUNDARY = 0xffffU, 460 461 /* mask of register bits containing lower 32 bits 462 * of EDMA request queue DMA address 463 */ 464 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 465 466 /* ditto, for response queue */ 467 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 468 }; 469 470 enum chip_type { 471 chip_504x, 472 chip_508x, 473 chip_5080, 474 chip_604x, 475 chip_608x, 476 chip_6042, 477 chip_7042, 478 chip_soc, 479 }; 480 481 /* Command ReQuest Block: 32B */ 482 struct mv_crqb { 483 __le32 sg_addr; 484 __le32 sg_addr_hi; 485 __le16 ctrl_flags; 486 __le16 ata_cmd[11]; 487 }; 488 489 struct mv_crqb_iie { 490 __le32 addr; 491 __le32 addr_hi; 492 __le32 flags; 493 __le32 len; 494 __le32 ata_cmd[4]; 495 }; 496 497 /* Command ResPonse Block: 8B */ 498 struct mv_crpb { 499 __le16 id; 500 __le16 flags; 501 __le32 tmstmp; 502 }; 503 504 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 505 struct mv_sg { 506 __le32 addr; 507 __le32 flags_size; 508 __le32 addr_hi; 509 __le32 reserved; 510 }; 511 512 /* 513 * We keep a local cache of a few frequently accessed port 514 * registers here, to avoid having to read them (very slow) 515 * when switching between EDMA and non-EDMA modes. 516 */ 517 struct mv_cached_regs { 518 u32 fiscfg; 519 u32 ltmode; 520 u32 haltcond; 521 u32 unknown_rsvd; 522 }; 523 524 struct mv_port_priv { 525 struct mv_crqb *crqb; 526 dma_addr_t crqb_dma; 527 struct mv_crpb *crpb; 528 dma_addr_t crpb_dma; 529 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 530 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 531 532 unsigned int req_idx; 533 unsigned int resp_idx; 534 535 u32 pp_flags; 536 struct mv_cached_regs cached; 537 unsigned int delayed_eh_pmp_map; 538 }; 539 540 struct mv_port_signal { 541 u32 amps; 542 u32 pre; 543 }; 544 545 struct mv_host_priv { 546 u32 hp_flags; 547 unsigned int board_idx; 548 u32 main_irq_mask; 549 struct mv_port_signal signal[8]; 550 const struct mv_hw_ops *ops; 551 int n_ports; 552 void __iomem *base; 553 void __iomem *main_irq_cause_addr; 554 void __iomem *main_irq_mask_addr; 555 u32 irq_cause_offset; 556 u32 irq_mask_offset; 557 u32 unmask_all_irqs; 558 559 /* 560 * Needed on some devices that require their clocks to be enabled. 561 * These are optional: if the platform device does not have any 562 * clocks, they won't be used. Also, if the underlying hardware 563 * does not support the common clock framework (CONFIG_HAVE_CLK=n), 564 * all the clock operations become no-ops (see clk.h). 565 */ 566 struct clk *clk; 567 struct clk **port_clks; 568 /* 569 * Some devices have a SATA PHY which can be enabled/disabled 570 * in order to save power. These are optional: if the platform 571 * devices does not have any phy, they won't be used. 572 */ 573 struct phy **port_phys; 574 /* 575 * These consistent DMA memory pools give us guaranteed 576 * alignment for hardware-accessed data structures, 577 * and less memory waste in accomplishing the alignment. 578 */ 579 struct dma_pool *crqb_pool; 580 struct dma_pool *crpb_pool; 581 struct dma_pool *sg_tbl_pool; 582 }; 583 584 struct mv_hw_ops { 585 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 586 unsigned int port); 587 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 588 void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 589 void __iomem *mmio); 590 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 591 unsigned int n_hc); 592 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 593 void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 594 }; 595 596 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 597 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 598 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 599 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 600 static int mv_port_start(struct ata_port *ap); 601 static void mv_port_stop(struct ata_port *ap); 602 static int mv_qc_defer(struct ata_queued_cmd *qc); 603 static void mv_qc_prep(struct ata_queued_cmd *qc); 604 static void mv_qc_prep_iie(struct ata_queued_cmd *qc); 605 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 606 static int mv_hardreset(struct ata_link *link, unsigned int *class, 607 unsigned long deadline); 608 static void mv_eh_freeze(struct ata_port *ap); 609 static void mv_eh_thaw(struct ata_port *ap); 610 static void mv6_dev_config(struct ata_device *dev); 611 612 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 613 unsigned int port); 614 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 615 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 616 void __iomem *mmio); 617 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 618 unsigned int n_hc); 619 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 620 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 621 622 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 623 unsigned int port); 624 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 625 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 626 void __iomem *mmio); 627 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 628 unsigned int n_hc); 629 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 630 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 631 void __iomem *mmio); 632 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 633 void __iomem *mmio); 634 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 635 void __iomem *mmio, unsigned int n_hc); 636 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 637 void __iomem *mmio); 638 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 639 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 640 void __iomem *mmio, unsigned int port); 641 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 642 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 643 unsigned int port_no); 644 static int mv_stop_edma(struct ata_port *ap); 645 static int mv_stop_edma_engine(void __iomem *port_mmio); 646 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); 647 648 static void mv_pmp_select(struct ata_port *ap, int pmp); 649 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 650 unsigned long deadline); 651 static int mv_softreset(struct ata_link *link, unsigned int *class, 652 unsigned long deadline); 653 static void mv_pmp_error_handler(struct ata_port *ap); 654 static void mv_process_crpb_entries(struct ata_port *ap, 655 struct mv_port_priv *pp); 656 657 static void mv_sff_irq_clear(struct ata_port *ap); 658 static int mv_check_atapi_dma(struct ata_queued_cmd *qc); 659 static void mv_bmdma_setup(struct ata_queued_cmd *qc); 660 static void mv_bmdma_start(struct ata_queued_cmd *qc); 661 static void mv_bmdma_stop(struct ata_queued_cmd *qc); 662 static u8 mv_bmdma_status(struct ata_port *ap); 663 static u8 mv_sff_check_status(struct ata_port *ap); 664 665 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 666 * because we have to allow room for worst case splitting of 667 * PRDs for 64K boundaries in mv_fill_sg(). 668 */ 669 #ifdef CONFIG_PCI 670 static struct scsi_host_template mv5_sht = { 671 ATA_BASE_SHT(DRV_NAME), 672 .sg_tablesize = MV_MAX_SG_CT / 2, 673 .dma_boundary = MV_DMA_BOUNDARY, 674 }; 675 #endif 676 static struct scsi_host_template mv6_sht = { 677 ATA_NCQ_SHT(DRV_NAME), 678 .can_queue = MV_MAX_Q_DEPTH - 1, 679 .sg_tablesize = MV_MAX_SG_CT / 2, 680 .dma_boundary = MV_DMA_BOUNDARY, 681 }; 682 683 static struct ata_port_operations mv5_ops = { 684 .inherits = &ata_sff_port_ops, 685 686 .lost_interrupt = ATA_OP_NULL, 687 688 .qc_defer = mv_qc_defer, 689 .qc_prep = mv_qc_prep, 690 .qc_issue = mv_qc_issue, 691 692 .freeze = mv_eh_freeze, 693 .thaw = mv_eh_thaw, 694 .hardreset = mv_hardreset, 695 696 .scr_read = mv5_scr_read, 697 .scr_write = mv5_scr_write, 698 699 .port_start = mv_port_start, 700 .port_stop = mv_port_stop, 701 }; 702 703 static struct ata_port_operations mv6_ops = { 704 .inherits = &ata_bmdma_port_ops, 705 706 .lost_interrupt = ATA_OP_NULL, 707 708 .qc_defer = mv_qc_defer, 709 .qc_prep = mv_qc_prep, 710 .qc_issue = mv_qc_issue, 711 712 .dev_config = mv6_dev_config, 713 714 .freeze = mv_eh_freeze, 715 .thaw = mv_eh_thaw, 716 .hardreset = mv_hardreset, 717 .softreset = mv_softreset, 718 .pmp_hardreset = mv_pmp_hardreset, 719 .pmp_softreset = mv_softreset, 720 .error_handler = mv_pmp_error_handler, 721 722 .scr_read = mv_scr_read, 723 .scr_write = mv_scr_write, 724 725 .sff_check_status = mv_sff_check_status, 726 .sff_irq_clear = mv_sff_irq_clear, 727 .check_atapi_dma = mv_check_atapi_dma, 728 .bmdma_setup = mv_bmdma_setup, 729 .bmdma_start = mv_bmdma_start, 730 .bmdma_stop = mv_bmdma_stop, 731 .bmdma_status = mv_bmdma_status, 732 733 .port_start = mv_port_start, 734 .port_stop = mv_port_stop, 735 }; 736 737 static struct ata_port_operations mv_iie_ops = { 738 .inherits = &mv6_ops, 739 .dev_config = ATA_OP_NULL, 740 .qc_prep = mv_qc_prep_iie, 741 }; 742 743 static const struct ata_port_info mv_port_info[] = { 744 { /* chip_504x */ 745 .flags = MV_GEN_I_FLAGS, 746 .pio_mask = ATA_PIO4, 747 .udma_mask = ATA_UDMA6, 748 .port_ops = &mv5_ops, 749 }, 750 { /* chip_508x */ 751 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 752 .pio_mask = ATA_PIO4, 753 .udma_mask = ATA_UDMA6, 754 .port_ops = &mv5_ops, 755 }, 756 { /* chip_5080 */ 757 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, 758 .pio_mask = ATA_PIO4, 759 .udma_mask = ATA_UDMA6, 760 .port_ops = &mv5_ops, 761 }, 762 { /* chip_604x */ 763 .flags = MV_GEN_II_FLAGS, 764 .pio_mask = ATA_PIO4, 765 .udma_mask = ATA_UDMA6, 766 .port_ops = &mv6_ops, 767 }, 768 { /* chip_608x */ 769 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, 770 .pio_mask = ATA_PIO4, 771 .udma_mask = ATA_UDMA6, 772 .port_ops = &mv6_ops, 773 }, 774 { /* chip_6042 */ 775 .flags = MV_GEN_IIE_FLAGS, 776 .pio_mask = ATA_PIO4, 777 .udma_mask = ATA_UDMA6, 778 .port_ops = &mv_iie_ops, 779 }, 780 { /* chip_7042 */ 781 .flags = MV_GEN_IIE_FLAGS, 782 .pio_mask = ATA_PIO4, 783 .udma_mask = ATA_UDMA6, 784 .port_ops = &mv_iie_ops, 785 }, 786 { /* chip_soc */ 787 .flags = MV_GEN_IIE_FLAGS, 788 .pio_mask = ATA_PIO4, 789 .udma_mask = ATA_UDMA6, 790 .port_ops = &mv_iie_ops, 791 }, 792 }; 793 794 static const struct pci_device_id mv_pci_tbl[] = { 795 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 796 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 797 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 798 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 799 /* RocketRAID 1720/174x have different identifiers */ 800 { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 801 { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, 802 { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, 803 804 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 805 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 806 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 807 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 808 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 809 810 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 811 812 /* Adaptec 1430SA */ 813 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 814 815 /* Marvell 7042 support */ 816 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 817 818 /* Highpoint RocketRAID PCIe series */ 819 { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 820 { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 821 822 { } /* terminate list */ 823 }; 824 825 static const struct mv_hw_ops mv5xxx_ops = { 826 .phy_errata = mv5_phy_errata, 827 .enable_leds = mv5_enable_leds, 828 .read_preamp = mv5_read_preamp, 829 .reset_hc = mv5_reset_hc, 830 .reset_flash = mv5_reset_flash, 831 .reset_bus = mv5_reset_bus, 832 }; 833 834 static const struct mv_hw_ops mv6xxx_ops = { 835 .phy_errata = mv6_phy_errata, 836 .enable_leds = mv6_enable_leds, 837 .read_preamp = mv6_read_preamp, 838 .reset_hc = mv6_reset_hc, 839 .reset_flash = mv6_reset_flash, 840 .reset_bus = mv_reset_pci_bus, 841 }; 842 843 static const struct mv_hw_ops mv_soc_ops = { 844 .phy_errata = mv6_phy_errata, 845 .enable_leds = mv_soc_enable_leds, 846 .read_preamp = mv_soc_read_preamp, 847 .reset_hc = mv_soc_reset_hc, 848 .reset_flash = mv_soc_reset_flash, 849 .reset_bus = mv_soc_reset_bus, 850 }; 851 852 static const struct mv_hw_ops mv_soc_65n_ops = { 853 .phy_errata = mv_soc_65n_phy_errata, 854 .enable_leds = mv_soc_enable_leds, 855 .reset_hc = mv_soc_reset_hc, 856 .reset_flash = mv_soc_reset_flash, 857 .reset_bus = mv_soc_reset_bus, 858 }; 859 860 /* 861 * Functions 862 */ 863 864 static inline void writelfl(unsigned long data, void __iomem *addr) 865 { 866 writel(data, addr); 867 (void) readl(addr); /* flush to avoid PCI posted write */ 868 } 869 870 static inline unsigned int mv_hc_from_port(unsigned int port) 871 { 872 return port >> MV_PORT_HC_SHIFT; 873 } 874 875 static inline unsigned int mv_hardport_from_port(unsigned int port) 876 { 877 return port & MV_PORT_MASK; 878 } 879 880 /* 881 * Consolidate some rather tricky bit shift calculations. 882 * This is hot-path stuff, so not a function. 883 * Simple code, with two return values, so macro rather than inline. 884 * 885 * port is the sole input, in range 0..7. 886 * shift is one output, for use with main_irq_cause / main_irq_mask registers. 887 * hardport is the other output, in range 0..3. 888 * 889 * Note that port and hardport may be the same variable in some cases. 890 */ 891 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 892 { \ 893 shift = mv_hc_from_port(port) * HC_SHIFT; \ 894 hardport = mv_hardport_from_port(port); \ 895 shift += hardport * 2; \ 896 } 897 898 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 899 { 900 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 901 } 902 903 static inline void __iomem *mv_hc_base_from_port(void __iomem *base, 904 unsigned int port) 905 { 906 return mv_hc_base(base, mv_hc_from_port(port)); 907 } 908 909 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 910 { 911 return mv_hc_base_from_port(base, port) + 912 MV_SATAHC_ARBTR_REG_SZ + 913 (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 914 } 915 916 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 917 { 918 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 919 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 920 921 return hc_mmio + ofs; 922 } 923 924 static inline void __iomem *mv_host_base(struct ata_host *host) 925 { 926 struct mv_host_priv *hpriv = host->private_data; 927 return hpriv->base; 928 } 929 930 static inline void __iomem *mv_ap_base(struct ata_port *ap) 931 { 932 return mv_port_base(mv_host_base(ap->host), ap->port_no); 933 } 934 935 static inline int mv_get_hc_count(unsigned long port_flags) 936 { 937 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 938 } 939 940 /** 941 * mv_save_cached_regs - (re-)initialize cached port registers 942 * @ap: the port whose registers we are caching 943 * 944 * Initialize the local cache of port registers, 945 * so that reading them over and over again can 946 * be avoided on the hotter paths of this driver. 947 * This saves a few microseconds each time we switch 948 * to/from EDMA mode to perform (eg.) a drive cache flush. 949 */ 950 static void mv_save_cached_regs(struct ata_port *ap) 951 { 952 void __iomem *port_mmio = mv_ap_base(ap); 953 struct mv_port_priv *pp = ap->private_data; 954 955 pp->cached.fiscfg = readl(port_mmio + FISCFG); 956 pp->cached.ltmode = readl(port_mmio + LTMODE); 957 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); 958 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); 959 } 960 961 /** 962 * mv_write_cached_reg - write to a cached port register 963 * @addr: hardware address of the register 964 * @old: pointer to cached value of the register 965 * @new: new value for the register 966 * 967 * Write a new value to a cached register, 968 * but only if the value is different from before. 969 */ 970 static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) 971 { 972 if (new != *old) { 973 unsigned long laddr; 974 *old = new; 975 /* 976 * Workaround for 88SX60x1-B2 FEr SATA#13: 977 * Read-after-write is needed to prevent generating 64-bit 978 * write cycles on the PCI bus for SATA interface registers 979 * at offsets ending in 0x4 or 0xc. 980 * 981 * Looks like a lot of fuss, but it avoids an unnecessary 982 * +1 usec read-after-write delay for unaffected registers. 983 */ 984 laddr = (long)addr & 0xffff; 985 if (laddr >= 0x300 && laddr <= 0x33c) { 986 laddr &= 0x000f; 987 if (laddr == 0x4 || laddr == 0xc) { 988 writelfl(new, addr); /* read after write */ 989 return; 990 } 991 } 992 writel(new, addr); /* unaffected by the errata */ 993 } 994 } 995 996 static void mv_set_edma_ptrs(void __iomem *port_mmio, 997 struct mv_host_priv *hpriv, 998 struct mv_port_priv *pp) 999 { 1000 u32 index; 1001 1002 /* 1003 * initialize request queue 1004 */ 1005 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 1006 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 1007 1008 WARN_ON(pp->crqb_dma & 0x3ff); 1009 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); 1010 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 1011 port_mmio + EDMA_REQ_Q_IN_PTR); 1012 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); 1013 1014 /* 1015 * initialize response queue 1016 */ 1017 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 1018 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 1019 1020 WARN_ON(pp->crpb_dma & 0xff); 1021 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); 1022 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); 1023 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 1024 port_mmio + EDMA_RSP_Q_OUT_PTR); 1025 } 1026 1027 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) 1028 { 1029 /* 1030 * When writing to the main_irq_mask in hardware, 1031 * we must ensure exclusivity between the interrupt coalescing bits 1032 * and the corresponding individual port DONE_IRQ bits. 1033 * 1034 * Note that this register is really an "IRQ enable" register, 1035 * not an "IRQ mask" register as Marvell's naming might suggest. 1036 */ 1037 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) 1038 mask &= ~DONE_IRQ_0_3; 1039 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) 1040 mask &= ~DONE_IRQ_4_7; 1041 writelfl(mask, hpriv->main_irq_mask_addr); 1042 } 1043 1044 static void mv_set_main_irq_mask(struct ata_host *host, 1045 u32 disable_bits, u32 enable_bits) 1046 { 1047 struct mv_host_priv *hpriv = host->private_data; 1048 u32 old_mask, new_mask; 1049 1050 old_mask = hpriv->main_irq_mask; 1051 new_mask = (old_mask & ~disable_bits) | enable_bits; 1052 if (new_mask != old_mask) { 1053 hpriv->main_irq_mask = new_mask; 1054 mv_write_main_irq_mask(new_mask, hpriv); 1055 } 1056 } 1057 1058 static void mv_enable_port_irqs(struct ata_port *ap, 1059 unsigned int port_bits) 1060 { 1061 unsigned int shift, hardport, port = ap->port_no; 1062 u32 disable_bits, enable_bits; 1063 1064 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 1065 1066 disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 1067 enable_bits = port_bits << shift; 1068 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 1069 } 1070 1071 static void mv_clear_and_enable_port_irqs(struct ata_port *ap, 1072 void __iomem *port_mmio, 1073 unsigned int port_irqs) 1074 { 1075 struct mv_host_priv *hpriv = ap->host->private_data; 1076 int hardport = mv_hardport_from_port(ap->port_no); 1077 void __iomem *hc_mmio = mv_hc_base_from_port( 1078 mv_host_base(ap->host), ap->port_no); 1079 u32 hc_irq_cause; 1080 1081 /* clear EDMA event indicators, if any */ 1082 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 1083 1084 /* clear pending irq events */ 1085 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 1086 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 1087 1088 /* clear FIS IRQ Cause */ 1089 if (IS_GEN_IIE(hpriv)) 1090 writelfl(0, port_mmio + FIS_IRQ_CAUSE); 1091 1092 mv_enable_port_irqs(ap, port_irqs); 1093 } 1094 1095 static void mv_set_irq_coalescing(struct ata_host *host, 1096 unsigned int count, unsigned int usecs) 1097 { 1098 struct mv_host_priv *hpriv = host->private_data; 1099 void __iomem *mmio = hpriv->base, *hc_mmio; 1100 u32 coal_enable = 0; 1101 unsigned long flags; 1102 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; 1103 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | 1104 ALL_PORTS_COAL_DONE; 1105 1106 /* Disable IRQ coalescing if either threshold is zero */ 1107 if (!usecs || !count) { 1108 clks = count = 0; 1109 } else { 1110 /* Respect maximum limits of the hardware */ 1111 clks = usecs * COAL_CLOCKS_PER_USEC; 1112 if (clks > MAX_COAL_TIME_THRESHOLD) 1113 clks = MAX_COAL_TIME_THRESHOLD; 1114 if (count > MAX_COAL_IO_COUNT) 1115 count = MAX_COAL_IO_COUNT; 1116 } 1117 1118 spin_lock_irqsave(&host->lock, flags); 1119 mv_set_main_irq_mask(host, coal_disable, 0); 1120 1121 if (is_dual_hc && !IS_GEN_I(hpriv)) { 1122 /* 1123 * GEN_II/GEN_IIE with dual host controllers: 1124 * one set of global thresholds for the entire chip. 1125 */ 1126 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); 1127 writel(count, mmio + IRQ_COAL_IO_THRESHOLD); 1128 /* clear leftover coal IRQ bit */ 1129 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 1130 if (count) 1131 coal_enable = ALL_PORTS_COAL_DONE; 1132 clks = count = 0; /* force clearing of regular regs below */ 1133 } 1134 1135 /* 1136 * All chips: independent thresholds for each HC on the chip. 1137 */ 1138 hc_mmio = mv_hc_base_from_port(mmio, 0); 1139 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1140 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1141 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 1142 if (count) 1143 coal_enable |= PORTS_0_3_COAL_DONE; 1144 if (is_dual_hc) { 1145 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); 1146 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); 1147 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); 1148 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); 1149 if (count) 1150 coal_enable |= PORTS_4_7_COAL_DONE; 1151 } 1152 1153 mv_set_main_irq_mask(host, 0, coal_enable); 1154 spin_unlock_irqrestore(&host->lock, flags); 1155 } 1156 1157 /** 1158 * mv_start_edma - Enable eDMA engine 1159 * @base: port base address 1160 * @pp: port private data 1161 * 1162 * Verify the local cache of the eDMA state is accurate with a 1163 * WARN_ON. 1164 * 1165 * LOCKING: 1166 * Inherited from caller. 1167 */ 1168 static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, 1169 struct mv_port_priv *pp, u8 protocol) 1170 { 1171 int want_ncq = (protocol == ATA_PROT_NCQ); 1172 1173 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 1174 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 1175 if (want_ncq != using_ncq) 1176 mv_stop_edma(ap); 1177 } 1178 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 1179 struct mv_host_priv *hpriv = ap->host->private_data; 1180 1181 mv_edma_cfg(ap, want_ncq, 1); 1182 1183 mv_set_edma_ptrs(port_mmio, hpriv, pp); 1184 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); 1185 1186 writelfl(EDMA_EN, port_mmio + EDMA_CMD); 1187 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 1188 } 1189 } 1190 1191 static void mv_wait_for_edma_empty_idle(struct ata_port *ap) 1192 { 1193 void __iomem *port_mmio = mv_ap_base(ap); 1194 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 1195 const int per_loop = 5, timeout = (15 * 1000 / per_loop); 1196 int i; 1197 1198 /* 1199 * Wait for the EDMA engine to finish transactions in progress. 1200 * No idea what a good "timeout" value might be, but measurements 1201 * indicate that it often requires hundreds of microseconds 1202 * with two drives in-use. So we use the 15msec value above 1203 * as a rough guess at what even more drives might require. 1204 */ 1205 for (i = 0; i < timeout; ++i) { 1206 u32 edma_stat = readl(port_mmio + EDMA_STATUS); 1207 if ((edma_stat & empty_idle) == empty_idle) 1208 break; 1209 udelay(per_loop); 1210 } 1211 /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */ 1212 } 1213 1214 /** 1215 * mv_stop_edma_engine - Disable eDMA engine 1216 * @port_mmio: io base address 1217 * 1218 * LOCKING: 1219 * Inherited from caller. 1220 */ 1221 static int mv_stop_edma_engine(void __iomem *port_mmio) 1222 { 1223 int i; 1224 1225 /* Disable eDMA. The disable bit auto clears. */ 1226 writelfl(EDMA_DS, port_mmio + EDMA_CMD); 1227 1228 /* Wait for the chip to confirm eDMA is off. */ 1229 for (i = 10000; i > 0; i--) { 1230 u32 reg = readl(port_mmio + EDMA_CMD); 1231 if (!(reg & EDMA_EN)) 1232 return 0; 1233 udelay(10); 1234 } 1235 return -EIO; 1236 } 1237 1238 static int mv_stop_edma(struct ata_port *ap) 1239 { 1240 void __iomem *port_mmio = mv_ap_base(ap); 1241 struct mv_port_priv *pp = ap->private_data; 1242 int err = 0; 1243 1244 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1245 return 0; 1246 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1247 mv_wait_for_edma_empty_idle(ap); 1248 if (mv_stop_edma_engine(port_mmio)) { 1249 ata_port_err(ap, "Unable to stop eDMA\n"); 1250 err = -EIO; 1251 } 1252 mv_edma_cfg(ap, 0, 0); 1253 return err; 1254 } 1255 1256 #ifdef ATA_DEBUG 1257 static void mv_dump_mem(void __iomem *start, unsigned bytes) 1258 { 1259 int b, w; 1260 for (b = 0; b < bytes; ) { 1261 DPRINTK("%p: ", start + b); 1262 for (w = 0; b < bytes && w < 4; w++) { 1263 printk("%08x ", readl(start + b)); 1264 b += sizeof(u32); 1265 } 1266 printk("\n"); 1267 } 1268 } 1269 #endif 1270 #if defined(ATA_DEBUG) || defined(CONFIG_PCI) 1271 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 1272 { 1273 #ifdef ATA_DEBUG 1274 int b, w; 1275 u32 dw; 1276 for (b = 0; b < bytes; ) { 1277 DPRINTK("%02x: ", b); 1278 for (w = 0; b < bytes && w < 4; w++) { 1279 (void) pci_read_config_dword(pdev, b, &dw); 1280 printk("%08x ", dw); 1281 b += sizeof(u32); 1282 } 1283 printk("\n"); 1284 } 1285 #endif 1286 } 1287 #endif 1288 static void mv_dump_all_regs(void __iomem *mmio_base, int port, 1289 struct pci_dev *pdev) 1290 { 1291 #ifdef ATA_DEBUG 1292 void __iomem *hc_base = mv_hc_base(mmio_base, 1293 port >> MV_PORT_HC_SHIFT); 1294 void __iomem *port_base; 1295 int start_port, num_ports, p, start_hc, num_hcs, hc; 1296 1297 if (0 > port) { 1298 start_hc = start_port = 0; 1299 num_ports = 8; /* shld be benign for 4 port devs */ 1300 num_hcs = 2; 1301 } else { 1302 start_hc = port >> MV_PORT_HC_SHIFT; 1303 start_port = port; 1304 num_ports = num_hcs = 1; 1305 } 1306 DPRINTK("All registers for port(s) %u-%u:\n", start_port, 1307 num_ports > 1 ? num_ports - 1 : start_port); 1308 1309 if (NULL != pdev) { 1310 DPRINTK("PCI config space regs:\n"); 1311 mv_dump_pci_cfg(pdev, 0x68); 1312 } 1313 DPRINTK("PCI regs:\n"); 1314 mv_dump_mem(mmio_base+0xc00, 0x3c); 1315 mv_dump_mem(mmio_base+0xd00, 0x34); 1316 mv_dump_mem(mmio_base+0xf00, 0x4); 1317 mv_dump_mem(mmio_base+0x1d00, 0x6c); 1318 for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1319 hc_base = mv_hc_base(mmio_base, hc); 1320 DPRINTK("HC regs (HC %i):\n", hc); 1321 mv_dump_mem(hc_base, 0x1c); 1322 } 1323 for (p = start_port; p < start_port + num_ports; p++) { 1324 port_base = mv_port_base(mmio_base, p); 1325 DPRINTK("EDMA regs (port %i):\n", p); 1326 mv_dump_mem(port_base, 0x54); 1327 DPRINTK("SATA regs (port %i):\n", p); 1328 mv_dump_mem(port_base+0x300, 0x60); 1329 } 1330 #endif 1331 } 1332 1333 static unsigned int mv_scr_offset(unsigned int sc_reg_in) 1334 { 1335 unsigned int ofs; 1336 1337 switch (sc_reg_in) { 1338 case SCR_STATUS: 1339 case SCR_CONTROL: 1340 case SCR_ERROR: 1341 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); 1342 break; 1343 case SCR_ACTIVE: 1344 ofs = SATA_ACTIVE; /* active is not with the others */ 1345 break; 1346 default: 1347 ofs = 0xffffffffU; 1348 break; 1349 } 1350 return ofs; 1351 } 1352 1353 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 1354 { 1355 unsigned int ofs = mv_scr_offset(sc_reg_in); 1356 1357 if (ofs != 0xffffffffU) { 1358 *val = readl(mv_ap_base(link->ap) + ofs); 1359 return 0; 1360 } else 1361 return -EINVAL; 1362 } 1363 1364 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 1365 { 1366 unsigned int ofs = mv_scr_offset(sc_reg_in); 1367 1368 if (ofs != 0xffffffffU) { 1369 void __iomem *addr = mv_ap_base(link->ap) + ofs; 1370 struct mv_host_priv *hpriv = link->ap->host->private_data; 1371 if (sc_reg_in == SCR_CONTROL) { 1372 /* 1373 * Workaround for 88SX60x1 FEr SATA#26: 1374 * 1375 * COMRESETs have to take care not to accidentally 1376 * put the drive to sleep when writing SCR_CONTROL. 1377 * Setting bits 12..15 prevents this problem. 1378 * 1379 * So if we see an outbound COMMRESET, set those bits. 1380 * Ditto for the followup write that clears the reset. 1381 * 1382 * The proprietary driver does this for 1383 * all chip versions, and so do we. 1384 */ 1385 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 1386 val |= 0xf000; 1387 1388 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { 1389 void __iomem *lp_phy_addr = 1390 mv_ap_base(link->ap) + LP_PHY_CTL; 1391 /* 1392 * Set PHY speed according to SControl speed. 1393 */ 1394 if ((val & 0xf0) == 0x10) 1395 writelfl(0x7, lp_phy_addr); 1396 else 1397 writelfl(0x227, lp_phy_addr); 1398 } 1399 } 1400 writelfl(val, addr); 1401 return 0; 1402 } else 1403 return -EINVAL; 1404 } 1405 1406 static void mv6_dev_config(struct ata_device *adev) 1407 { 1408 /* 1409 * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1410 * 1411 * Gen-II does not support NCQ over a port multiplier 1412 * (no FIS-based switching). 1413 */ 1414 if (adev->flags & ATA_DFLAG_NCQ) { 1415 if (sata_pmp_attached(adev->link->ap)) { 1416 adev->flags &= ~ATA_DFLAG_NCQ; 1417 ata_dev_info(adev, 1418 "NCQ disabled for command-based switching\n"); 1419 } 1420 } 1421 } 1422 1423 static int mv_qc_defer(struct ata_queued_cmd *qc) 1424 { 1425 struct ata_link *link = qc->dev->link; 1426 struct ata_port *ap = link->ap; 1427 struct mv_port_priv *pp = ap->private_data; 1428 1429 /* 1430 * Don't allow new commands if we're in a delayed EH state 1431 * for NCQ and/or FIS-based switching. 1432 */ 1433 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 1434 return ATA_DEFER_PORT; 1435 1436 /* PIO commands need exclusive link: no other commands [DMA or PIO] 1437 * can run concurrently. 1438 * set excl_link when we want to send a PIO command in DMA mode 1439 * or a non-NCQ command in NCQ mode. 1440 * When we receive a command from that link, and there are no 1441 * outstanding commands, mark a flag to clear excl_link and let 1442 * the command go through. 1443 */ 1444 if (unlikely(ap->excl_link)) { 1445 if (link == ap->excl_link) { 1446 if (ap->nr_active_links) 1447 return ATA_DEFER_PORT; 1448 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; 1449 return 0; 1450 } else 1451 return ATA_DEFER_PORT; 1452 } 1453 1454 /* 1455 * If the port is completely idle, then allow the new qc. 1456 */ 1457 if (ap->nr_active_links == 0) 1458 return 0; 1459 1460 /* 1461 * The port is operating in host queuing mode (EDMA) with NCQ 1462 * enabled, allow multiple NCQ commands. EDMA also allows 1463 * queueing multiple DMA commands but libata core currently 1464 * doesn't allow it. 1465 */ 1466 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 1467 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { 1468 if (ata_is_ncq(qc->tf.protocol)) 1469 return 0; 1470 else { 1471 ap->excl_link = link; 1472 return ATA_DEFER_PORT; 1473 } 1474 } 1475 1476 return ATA_DEFER_PORT; 1477 } 1478 1479 static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) 1480 { 1481 struct mv_port_priv *pp = ap->private_data; 1482 void __iomem *port_mmio; 1483 1484 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; 1485 u32 ltmode, *old_ltmode = &pp->cached.ltmode; 1486 u32 haltcond, *old_haltcond = &pp->cached.haltcond; 1487 1488 ltmode = *old_ltmode & ~LTMODE_BIT8; 1489 haltcond = *old_haltcond | EDMA_ERR_DEV; 1490 1491 if (want_fbs) { 1492 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; 1493 ltmode = *old_ltmode | LTMODE_BIT8; 1494 if (want_ncq) 1495 haltcond &= ~EDMA_ERR_DEV; 1496 else 1497 fiscfg |= FISCFG_WAIT_DEV_ERR; 1498 } else { 1499 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1500 } 1501 1502 port_mmio = mv_ap_base(ap); 1503 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); 1504 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); 1505 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); 1506 } 1507 1508 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1509 { 1510 struct mv_host_priv *hpriv = ap->host->private_data; 1511 u32 old, new; 1512 1513 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1514 old = readl(hpriv->base + GPIO_PORT_CTL); 1515 if (want_ncq) 1516 new = old | (1 << 22); 1517 else 1518 new = old & ~(1 << 22); 1519 if (new != old) 1520 writel(new, hpriv->base + GPIO_PORT_CTL); 1521 } 1522 1523 /** 1524 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma 1525 * @ap: Port being initialized 1526 * 1527 * There are two DMA modes on these chips: basic DMA, and EDMA. 1528 * 1529 * Bit-0 of the "EDMA RESERVED" register enables/disables use 1530 * of basic DMA on the GEN_IIE versions of the chips. 1531 * 1532 * This bit survives EDMA resets, and must be set for basic DMA 1533 * to function, and should be cleared when EDMA is active. 1534 */ 1535 static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) 1536 { 1537 struct mv_port_priv *pp = ap->private_data; 1538 u32 new, *old = &pp->cached.unknown_rsvd; 1539 1540 if (enable_bmdma) 1541 new = *old | 1; 1542 else 1543 new = *old & ~1; 1544 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); 1545 } 1546 1547 /* 1548 * SOC chips have an issue whereby the HDD LEDs don't always blink 1549 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode 1550 * of the SOC takes care of it, generating a steady blink rate when 1551 * any drive on the chip is active. 1552 * 1553 * Unfortunately, the blink mode is a global hardware setting for the SOC, 1554 * so we must use it whenever at least one port on the SOC has NCQ enabled. 1555 * 1556 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal 1557 * LED operation works then, and provides better (more accurate) feedback. 1558 * 1559 * Note that this code assumes that an SOC never has more than one HC onboard. 1560 */ 1561 static void mv_soc_led_blink_enable(struct ata_port *ap) 1562 { 1563 struct ata_host *host = ap->host; 1564 struct mv_host_priv *hpriv = host->private_data; 1565 void __iomem *hc_mmio; 1566 u32 led_ctrl; 1567 1568 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) 1569 return; 1570 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; 1571 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1572 led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1573 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1574 } 1575 1576 static void mv_soc_led_blink_disable(struct ata_port *ap) 1577 { 1578 struct ata_host *host = ap->host; 1579 struct mv_host_priv *hpriv = host->private_data; 1580 void __iomem *hc_mmio; 1581 u32 led_ctrl; 1582 unsigned int port; 1583 1584 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) 1585 return; 1586 1587 /* disable led-blink only if no ports are using NCQ */ 1588 for (port = 0; port < hpriv->n_ports; port++) { 1589 struct ata_port *this_ap = host->ports[port]; 1590 struct mv_port_priv *pp = this_ap->private_data; 1591 1592 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1593 return; 1594 } 1595 1596 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; 1597 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); 1598 led_ctrl = readl(hc_mmio + SOC_LED_CTRL); 1599 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); 1600 } 1601 1602 static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) 1603 { 1604 u32 cfg; 1605 struct mv_port_priv *pp = ap->private_data; 1606 struct mv_host_priv *hpriv = ap->host->private_data; 1607 void __iomem *port_mmio = mv_ap_base(ap); 1608 1609 /* set up non-NCQ EDMA configuration */ 1610 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1611 pp->pp_flags &= 1612 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 1613 1614 if (IS_GEN_I(hpriv)) 1615 cfg |= (1 << 8); /* enab config burst size mask */ 1616 1617 else if (IS_GEN_II(hpriv)) { 1618 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1619 mv_60x1_errata_sata25(ap, want_ncq); 1620 1621 } else if (IS_GEN_IIE(hpriv)) { 1622 int want_fbs = sata_pmp_attached(ap); 1623 /* 1624 * Possible future enhancement: 1625 * 1626 * The chip can use FBS with non-NCQ, if we allow it, 1627 * But first we need to have the error handling in place 1628 * for this mode (datasheet section 7.3.15.4.2.3). 1629 * So disallow non-NCQ FBS for now. 1630 */ 1631 want_fbs &= want_ncq; 1632 1633 mv_config_fbs(ap, want_ncq, want_fbs); 1634 1635 if (want_fbs) { 1636 pp->pp_flags |= MV_PP_FLAG_FBS_EN; 1637 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1638 } 1639 1640 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1641 if (want_edma) { 1642 cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1643 if (!IS_SOC(hpriv)) 1644 cfg |= (1 << 18); /* enab early completion */ 1645 } 1646 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1647 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1648 mv_bmdma_enable_iie(ap, !want_edma); 1649 1650 if (IS_SOC(hpriv)) { 1651 if (want_ncq) 1652 mv_soc_led_blink_enable(ap); 1653 else 1654 mv_soc_led_blink_disable(ap); 1655 } 1656 } 1657 1658 if (want_ncq) { 1659 cfg |= EDMA_CFG_NCQ; 1660 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1661 } 1662 1663 writelfl(cfg, port_mmio + EDMA_CFG); 1664 } 1665 1666 static void mv_port_free_dma_mem(struct ata_port *ap) 1667 { 1668 struct mv_host_priv *hpriv = ap->host->private_data; 1669 struct mv_port_priv *pp = ap->private_data; 1670 int tag; 1671 1672 if (pp->crqb) { 1673 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1674 pp->crqb = NULL; 1675 } 1676 if (pp->crpb) { 1677 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1678 pp->crpb = NULL; 1679 } 1680 /* 1681 * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1682 * For later hardware, we have one unique sg_tbl per NCQ tag. 1683 */ 1684 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1685 if (pp->sg_tbl[tag]) { 1686 if (tag == 0 || !IS_GEN_I(hpriv)) 1687 dma_pool_free(hpriv->sg_tbl_pool, 1688 pp->sg_tbl[tag], 1689 pp->sg_tbl_dma[tag]); 1690 pp->sg_tbl[tag] = NULL; 1691 } 1692 } 1693 } 1694 1695 /** 1696 * mv_port_start - Port specific init/start routine. 1697 * @ap: ATA channel to manipulate 1698 * 1699 * Allocate and point to DMA memory, init port private memory, 1700 * zero indices. 1701 * 1702 * LOCKING: 1703 * Inherited from caller. 1704 */ 1705 static int mv_port_start(struct ata_port *ap) 1706 { 1707 struct device *dev = ap->host->dev; 1708 struct mv_host_priv *hpriv = ap->host->private_data; 1709 struct mv_port_priv *pp; 1710 unsigned long flags; 1711 int tag; 1712 1713 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1714 if (!pp) 1715 return -ENOMEM; 1716 ap->private_data = pp; 1717 1718 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1719 if (!pp->crqb) 1720 return -ENOMEM; 1721 memset(pp->crqb, 0, MV_CRQB_Q_SZ); 1722 1723 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1724 if (!pp->crpb) 1725 goto out_port_free_dma_mem; 1726 memset(pp->crpb, 0, MV_CRPB_Q_SZ); 1727 1728 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 1729 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 1730 ap->flags |= ATA_FLAG_AN; 1731 /* 1732 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1733 * For later hardware, we need one unique sg_tbl per NCQ tag. 1734 */ 1735 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1736 if (tag == 0 || !IS_GEN_I(hpriv)) { 1737 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1738 GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1739 if (!pp->sg_tbl[tag]) 1740 goto out_port_free_dma_mem; 1741 } else { 1742 pp->sg_tbl[tag] = pp->sg_tbl[0]; 1743 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1744 } 1745 } 1746 1747 spin_lock_irqsave(ap->lock, flags); 1748 mv_save_cached_regs(ap); 1749 mv_edma_cfg(ap, 0, 0); 1750 spin_unlock_irqrestore(ap->lock, flags); 1751 1752 return 0; 1753 1754 out_port_free_dma_mem: 1755 mv_port_free_dma_mem(ap); 1756 return -ENOMEM; 1757 } 1758 1759 /** 1760 * mv_port_stop - Port specific cleanup/stop routine. 1761 * @ap: ATA channel to manipulate 1762 * 1763 * Stop DMA, cleanup port memory. 1764 * 1765 * LOCKING: 1766 * This routine uses the host lock to protect the DMA stop. 1767 */ 1768 static void mv_port_stop(struct ata_port *ap) 1769 { 1770 unsigned long flags; 1771 1772 spin_lock_irqsave(ap->lock, flags); 1773 mv_stop_edma(ap); 1774 mv_enable_port_irqs(ap, 0); 1775 spin_unlock_irqrestore(ap->lock, flags); 1776 mv_port_free_dma_mem(ap); 1777 } 1778 1779 /** 1780 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 1781 * @qc: queued command whose SG list to source from 1782 * 1783 * Populate the SG list and mark the last entry. 1784 * 1785 * LOCKING: 1786 * Inherited from caller. 1787 */ 1788 static void mv_fill_sg(struct ata_queued_cmd *qc) 1789 { 1790 struct mv_port_priv *pp = qc->ap->private_data; 1791 struct scatterlist *sg; 1792 struct mv_sg *mv_sg, *last_sg = NULL; 1793 unsigned int si; 1794 1795 mv_sg = pp->sg_tbl[qc->tag]; 1796 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1797 dma_addr_t addr = sg_dma_address(sg); 1798 u32 sg_len = sg_dma_len(sg); 1799 1800 while (sg_len) { 1801 u32 offset = addr & 0xffff; 1802 u32 len = sg_len; 1803 1804 if (offset + len > 0x10000) 1805 len = 0x10000 - offset; 1806 1807 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 1808 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 1809 mv_sg->flags_size = cpu_to_le32(len & 0xffff); 1810 mv_sg->reserved = 0; 1811 1812 sg_len -= len; 1813 addr += len; 1814 1815 last_sg = mv_sg; 1816 mv_sg++; 1817 } 1818 } 1819 1820 if (likely(last_sg)) 1821 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 1822 mb(); /* ensure data structure is visible to the chipset */ 1823 } 1824 1825 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 1826 { 1827 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 1828 (last ? CRQB_CMD_LAST : 0); 1829 *cmdw = cpu_to_le16(tmp); 1830 } 1831 1832 /** 1833 * mv_sff_irq_clear - Clear hardware interrupt after DMA. 1834 * @ap: Port associated with this ATA transaction. 1835 * 1836 * We need this only for ATAPI bmdma transactions, 1837 * as otherwise we experience spurious interrupts 1838 * after libata-sff handles the bmdma interrupts. 1839 */ 1840 static void mv_sff_irq_clear(struct ata_port *ap) 1841 { 1842 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); 1843 } 1844 1845 /** 1846 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. 1847 * @qc: queued command to check for chipset/DMA compatibility. 1848 * 1849 * The bmdma engines cannot handle speculative data sizes 1850 * (bytecount under/over flow). So only allow DMA for 1851 * data transfer commands with known data sizes. 1852 * 1853 * LOCKING: 1854 * Inherited from caller. 1855 */ 1856 static int mv_check_atapi_dma(struct ata_queued_cmd *qc) 1857 { 1858 struct scsi_cmnd *scmd = qc->scsicmd; 1859 1860 if (scmd) { 1861 switch (scmd->cmnd[0]) { 1862 case READ_6: 1863 case READ_10: 1864 case READ_12: 1865 case WRITE_6: 1866 case WRITE_10: 1867 case WRITE_12: 1868 case GPCMD_READ_CD: 1869 case GPCMD_SEND_DVD_STRUCTURE: 1870 case GPCMD_SEND_CUE_SHEET: 1871 return 0; /* DMA is safe */ 1872 } 1873 } 1874 return -EOPNOTSUPP; /* use PIO instead */ 1875 } 1876 1877 /** 1878 * mv_bmdma_setup - Set up BMDMA transaction 1879 * @qc: queued command to prepare DMA for. 1880 * 1881 * LOCKING: 1882 * Inherited from caller. 1883 */ 1884 static void mv_bmdma_setup(struct ata_queued_cmd *qc) 1885 { 1886 struct ata_port *ap = qc->ap; 1887 void __iomem *port_mmio = mv_ap_base(ap); 1888 struct mv_port_priv *pp = ap->private_data; 1889 1890 mv_fill_sg(qc); 1891 1892 /* clear all DMA cmd bits */ 1893 writel(0, port_mmio + BMDMA_CMD); 1894 1895 /* load PRD table addr. */ 1896 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, 1897 port_mmio + BMDMA_PRD_HIGH); 1898 writelfl(pp->sg_tbl_dma[qc->tag], 1899 port_mmio + BMDMA_PRD_LOW); 1900 1901 /* issue r/w command */ 1902 ap->ops->sff_exec_command(ap, &qc->tf); 1903 } 1904 1905 /** 1906 * mv_bmdma_start - Start a BMDMA transaction 1907 * @qc: queued command to start DMA on. 1908 * 1909 * LOCKING: 1910 * Inherited from caller. 1911 */ 1912 static void mv_bmdma_start(struct ata_queued_cmd *qc) 1913 { 1914 struct ata_port *ap = qc->ap; 1915 void __iomem *port_mmio = mv_ap_base(ap); 1916 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 1917 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; 1918 1919 /* start host DMA transaction */ 1920 writelfl(cmd, port_mmio + BMDMA_CMD); 1921 } 1922 1923 /** 1924 * mv_bmdma_stop - Stop BMDMA transfer 1925 * @qc: queued command to stop DMA on. 1926 * 1927 * Clears the ATA_DMA_START flag in the bmdma control register 1928 * 1929 * LOCKING: 1930 * Inherited from caller. 1931 */ 1932 static void mv_bmdma_stop_ap(struct ata_port *ap) 1933 { 1934 void __iomem *port_mmio = mv_ap_base(ap); 1935 u32 cmd; 1936 1937 /* clear start/stop bit */ 1938 cmd = readl(port_mmio + BMDMA_CMD); 1939 if (cmd & ATA_DMA_START) { 1940 cmd &= ~ATA_DMA_START; 1941 writelfl(cmd, port_mmio + BMDMA_CMD); 1942 1943 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 1944 ata_sff_dma_pause(ap); 1945 } 1946 } 1947 1948 static void mv_bmdma_stop(struct ata_queued_cmd *qc) 1949 { 1950 mv_bmdma_stop_ap(qc->ap); 1951 } 1952 1953 /** 1954 * mv_bmdma_status - Read BMDMA status 1955 * @ap: port for which to retrieve DMA status. 1956 * 1957 * Read and return equivalent of the sff BMDMA status register. 1958 * 1959 * LOCKING: 1960 * Inherited from caller. 1961 */ 1962 static u8 mv_bmdma_status(struct ata_port *ap) 1963 { 1964 void __iomem *port_mmio = mv_ap_base(ap); 1965 u32 reg, status; 1966 1967 /* 1968 * Other bits are valid only if ATA_DMA_ACTIVE==0, 1969 * and the ATA_DMA_INTR bit doesn't exist. 1970 */ 1971 reg = readl(port_mmio + BMDMA_STATUS); 1972 if (reg & ATA_DMA_ACTIVE) 1973 status = ATA_DMA_ACTIVE; 1974 else if (reg & ATA_DMA_ERR) 1975 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; 1976 else { 1977 /* 1978 * Just because DMA_ACTIVE is 0 (DMA completed), 1979 * this does _not_ mean the device is "done". 1980 * So we should not yet be signalling ATA_DMA_INTR 1981 * in some cases. Eg. DSM/TRIM, and perhaps others. 1982 */ 1983 mv_bmdma_stop_ap(ap); 1984 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) 1985 status = 0; 1986 else 1987 status = ATA_DMA_INTR; 1988 } 1989 return status; 1990 } 1991 1992 static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) 1993 { 1994 struct ata_taskfile *tf = &qc->tf; 1995 /* 1996 * Workaround for 88SX60x1 FEr SATA#24. 1997 * 1998 * Chip may corrupt WRITEs if multi_count >= 4kB. 1999 * Note that READs are unaffected. 2000 * 2001 * It's not clear if this errata really means "4K bytes", 2002 * or if it always happens for multi_count > 7 2003 * regardless of device sector_size. 2004 * 2005 * So, for safety, any write with multi_count > 7 2006 * gets converted here into a regular PIO write instead: 2007 */ 2008 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { 2009 if (qc->dev->multi_count > 7) { 2010 switch (tf->command) { 2011 case ATA_CMD_WRITE_MULTI: 2012 tf->command = ATA_CMD_PIO_WRITE; 2013 break; 2014 case ATA_CMD_WRITE_MULTI_FUA_EXT: 2015 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ 2016 /* fall through */ 2017 case ATA_CMD_WRITE_MULTI_EXT: 2018 tf->command = ATA_CMD_PIO_WRITE_EXT; 2019 break; 2020 } 2021 } 2022 } 2023 } 2024 2025 /** 2026 * mv_qc_prep - Host specific command preparation. 2027 * @qc: queued command to prepare 2028 * 2029 * This routine simply redirects to the general purpose routine 2030 * if command is not DMA. Else, it handles prep of the CRQB 2031 * (command request block), does some sanity checking, and calls 2032 * the SG load routine. 2033 * 2034 * LOCKING: 2035 * Inherited from caller. 2036 */ 2037 static void mv_qc_prep(struct ata_queued_cmd *qc) 2038 { 2039 struct ata_port *ap = qc->ap; 2040 struct mv_port_priv *pp = ap->private_data; 2041 __le16 *cw; 2042 struct ata_taskfile *tf = &qc->tf; 2043 u16 flags = 0; 2044 unsigned in_index; 2045 2046 switch (tf->protocol) { 2047 case ATA_PROT_DMA: 2048 if (tf->command == ATA_CMD_DSM) 2049 return; 2050 /* fall-thru */ 2051 case ATA_PROT_NCQ: 2052 break; /* continue below */ 2053 case ATA_PROT_PIO: 2054 mv_rw_multi_errata_sata24(qc); 2055 return; 2056 default: 2057 return; 2058 } 2059 2060 /* Fill in command request block 2061 */ 2062 if (!(tf->flags & ATA_TFLAG_WRITE)) 2063 flags |= CRQB_FLAG_READ; 2064 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2065 flags |= qc->tag << CRQB_TAG_SHIFT; 2066 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2067 2068 /* get current queue index from software */ 2069 in_index = pp->req_idx; 2070 2071 pp->crqb[in_index].sg_addr = 2072 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2073 pp->crqb[in_index].sg_addr_hi = 2074 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2075 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 2076 2077 cw = &pp->crqb[in_index].ata_cmd[0]; 2078 2079 /* Sadly, the CRQB cannot accommodate all registers--there are 2080 * only 11 bytes...so we must pick and choose required 2081 * registers based on the command. So, we drop feature and 2082 * hob_feature for [RW] DMA commands, but they are needed for 2083 * NCQ. NCQ will drop hob_nsect, which is not needed there 2084 * (nsect is used only for the tag; feat/hob_feat hold true nsect). 2085 */ 2086 switch (tf->command) { 2087 case ATA_CMD_READ: 2088 case ATA_CMD_READ_EXT: 2089 case ATA_CMD_WRITE: 2090 case ATA_CMD_WRITE_EXT: 2091 case ATA_CMD_WRITE_FUA_EXT: 2092 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 2093 break; 2094 case ATA_CMD_FPDMA_READ: 2095 case ATA_CMD_FPDMA_WRITE: 2096 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 2097 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 2098 break; 2099 default: 2100 /* The only other commands EDMA supports in non-queued and 2101 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 2102 * of which are defined/used by Linux. If we get here, this 2103 * driver needs work. 2104 * 2105 * FIXME: modify libata to give qc_prep a return value and 2106 * return error here. 2107 */ 2108 BUG_ON(tf->command); 2109 break; 2110 } 2111 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 2112 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 2113 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 2114 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 2115 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 2116 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 2117 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 2118 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 2119 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 2120 2121 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2122 return; 2123 mv_fill_sg(qc); 2124 } 2125 2126 /** 2127 * mv_qc_prep_iie - Host specific command preparation. 2128 * @qc: queued command to prepare 2129 * 2130 * This routine simply redirects to the general purpose routine 2131 * if command is not DMA. Else, it handles prep of the CRQB 2132 * (command request block), does some sanity checking, and calls 2133 * the SG load routine. 2134 * 2135 * LOCKING: 2136 * Inherited from caller. 2137 */ 2138 static void mv_qc_prep_iie(struct ata_queued_cmd *qc) 2139 { 2140 struct ata_port *ap = qc->ap; 2141 struct mv_port_priv *pp = ap->private_data; 2142 struct mv_crqb_iie *crqb; 2143 struct ata_taskfile *tf = &qc->tf; 2144 unsigned in_index; 2145 u32 flags = 0; 2146 2147 if ((tf->protocol != ATA_PROT_DMA) && 2148 (tf->protocol != ATA_PROT_NCQ)) 2149 return; 2150 if (tf->command == ATA_CMD_DSM) 2151 return; /* use bmdma for this */ 2152 2153 /* Fill in Gen IIE command request block */ 2154 if (!(tf->flags & ATA_TFLAG_WRITE)) 2155 flags |= CRQB_FLAG_READ; 2156 2157 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 2158 flags |= qc->tag << CRQB_TAG_SHIFT; 2159 flags |= qc->tag << CRQB_HOSTQ_SHIFT; 2160 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 2161 2162 /* get current queue index from software */ 2163 in_index = pp->req_idx; 2164 2165 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 2166 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 2167 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 2168 crqb->flags = cpu_to_le32(flags); 2169 2170 crqb->ata_cmd[0] = cpu_to_le32( 2171 (tf->command << 16) | 2172 (tf->feature << 24) 2173 ); 2174 crqb->ata_cmd[1] = cpu_to_le32( 2175 (tf->lbal << 0) | 2176 (tf->lbam << 8) | 2177 (tf->lbah << 16) | 2178 (tf->device << 24) 2179 ); 2180 crqb->ata_cmd[2] = cpu_to_le32( 2181 (tf->hob_lbal << 0) | 2182 (tf->hob_lbam << 8) | 2183 (tf->hob_lbah << 16) | 2184 (tf->hob_feature << 24) 2185 ); 2186 crqb->ata_cmd[3] = cpu_to_le32( 2187 (tf->nsect << 0) | 2188 (tf->hob_nsect << 8) 2189 ); 2190 2191 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2192 return; 2193 mv_fill_sg(qc); 2194 } 2195 2196 /** 2197 * mv_sff_check_status - fetch device status, if valid 2198 * @ap: ATA port to fetch status from 2199 * 2200 * When using command issue via mv_qc_issue_fis(), 2201 * the initial ATA_BUSY state does not show up in the 2202 * ATA status (shadow) register. This can confuse libata! 2203 * 2204 * So we have a hook here to fake ATA_BUSY for that situation, 2205 * until the first time a BUSY, DRQ, or ERR bit is seen. 2206 * 2207 * The rest of the time, it simply returns the ATA status register. 2208 */ 2209 static u8 mv_sff_check_status(struct ata_port *ap) 2210 { 2211 u8 stat = ioread8(ap->ioaddr.status_addr); 2212 struct mv_port_priv *pp = ap->private_data; 2213 2214 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { 2215 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) 2216 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; 2217 else 2218 stat = ATA_BUSY; 2219 } 2220 return stat; 2221 } 2222 2223 /** 2224 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register 2225 * @fis: fis to be sent 2226 * @nwords: number of 32-bit words in the fis 2227 */ 2228 static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) 2229 { 2230 void __iomem *port_mmio = mv_ap_base(ap); 2231 u32 ifctl, old_ifctl, ifstat; 2232 int i, timeout = 200, final_word = nwords - 1; 2233 2234 /* Initiate FIS transmission mode */ 2235 old_ifctl = readl(port_mmio + SATA_IFCTL); 2236 ifctl = 0x100 | (old_ifctl & 0xf); 2237 writelfl(ifctl, port_mmio + SATA_IFCTL); 2238 2239 /* Send all words of the FIS except for the final word */ 2240 for (i = 0; i < final_word; ++i) 2241 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); 2242 2243 /* Flag end-of-transmission, and then send the final word */ 2244 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); 2245 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); 2246 2247 /* 2248 * Wait for FIS transmission to complete. 2249 * This typically takes just a single iteration. 2250 */ 2251 do { 2252 ifstat = readl(port_mmio + SATA_IFSTAT); 2253 } while (!(ifstat & 0x1000) && --timeout); 2254 2255 /* Restore original port configuration */ 2256 writelfl(old_ifctl, port_mmio + SATA_IFCTL); 2257 2258 /* See if it worked */ 2259 if ((ifstat & 0x3000) != 0x1000) { 2260 ata_port_warn(ap, "%s transmission error, ifstat=%08x\n", 2261 __func__, ifstat); 2262 return AC_ERR_OTHER; 2263 } 2264 return 0; 2265 } 2266 2267 /** 2268 * mv_qc_issue_fis - Issue a command directly as a FIS 2269 * @qc: queued command to start 2270 * 2271 * Note that the ATA shadow registers are not updated 2272 * after command issue, so the device will appear "READY" 2273 * if polled, even while it is BUSY processing the command. 2274 * 2275 * So we use a status hook to fake ATA_BUSY until the drive changes state. 2276 * 2277 * Note: we don't get updated shadow regs on *completion* 2278 * of non-data commands. So avoid sending them via this function, 2279 * as they will appear to have completed immediately. 2280 * 2281 * GEN_IIE has special registers that we could get the result tf from, 2282 * but earlier chipsets do not. For now, we ignore those registers. 2283 */ 2284 static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) 2285 { 2286 struct ata_port *ap = qc->ap; 2287 struct mv_port_priv *pp = ap->private_data; 2288 struct ata_link *link = qc->dev->link; 2289 u32 fis[5]; 2290 int err = 0; 2291 2292 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); 2293 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis)); 2294 if (err) 2295 return err; 2296 2297 switch (qc->tf.protocol) { 2298 case ATAPI_PROT_PIO: 2299 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 2300 /* fall through */ 2301 case ATAPI_PROT_NODATA: 2302 ap->hsm_task_state = HSM_ST_FIRST; 2303 break; 2304 case ATA_PROT_PIO: 2305 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; 2306 if (qc->tf.flags & ATA_TFLAG_WRITE) 2307 ap->hsm_task_state = HSM_ST_FIRST; 2308 else 2309 ap->hsm_task_state = HSM_ST; 2310 break; 2311 default: 2312 ap->hsm_task_state = HSM_ST_LAST; 2313 break; 2314 } 2315 2316 if (qc->tf.flags & ATA_TFLAG_POLLING) 2317 ata_sff_queue_pio_task(link, 0); 2318 return 0; 2319 } 2320 2321 /** 2322 * mv_qc_issue - Initiate a command to the host 2323 * @qc: queued command to start 2324 * 2325 * This routine simply redirects to the general purpose routine 2326 * if command is not DMA. Else, it sanity checks our local 2327 * caches of the request producer/consumer indices then enables 2328 * DMA and bumps the request producer index. 2329 * 2330 * LOCKING: 2331 * Inherited from caller. 2332 */ 2333 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 2334 { 2335 static int limit_warnings = 10; 2336 struct ata_port *ap = qc->ap; 2337 void __iomem *port_mmio = mv_ap_base(ap); 2338 struct mv_port_priv *pp = ap->private_data; 2339 u32 in_index; 2340 unsigned int port_irqs; 2341 2342 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ 2343 2344 switch (qc->tf.protocol) { 2345 case ATA_PROT_DMA: 2346 if (qc->tf.command == ATA_CMD_DSM) { 2347 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ 2348 return AC_ERR_OTHER; 2349 break; /* use bmdma for this */ 2350 } 2351 /* fall thru */ 2352 case ATA_PROT_NCQ: 2353 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); 2354 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2355 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 2356 2357 /* Write the request in pointer to kick the EDMA to life */ 2358 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 2359 port_mmio + EDMA_REQ_Q_IN_PTR); 2360 return 0; 2361 2362 case ATA_PROT_PIO: 2363 /* 2364 * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 2365 * 2366 * Someday, we might implement special polling workarounds 2367 * for these, but it all seems rather unnecessary since we 2368 * normally use only DMA for commands which transfer more 2369 * than a single block of data. 2370 * 2371 * Much of the time, this could just work regardless. 2372 * So for now, just log the incident, and allow the attempt. 2373 */ 2374 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 2375 --limit_warnings; 2376 ata_link_warn(qc->dev->link, DRV_NAME 2377 ": attempting PIO w/multiple DRQ: " 2378 "this may fail due to h/w errata\n"); 2379 } 2380 /* drop through */ 2381 case ATA_PROT_NODATA: 2382 case ATAPI_PROT_PIO: 2383 case ATAPI_PROT_NODATA: 2384 if (ap->flags & ATA_FLAG_PIO_POLLING) 2385 qc->tf.flags |= ATA_TFLAG_POLLING; 2386 break; 2387 } 2388 2389 if (qc->tf.flags & ATA_TFLAG_POLLING) 2390 port_irqs = ERR_IRQ; /* mask device interrupt when polling */ 2391 else 2392 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ 2393 2394 /* 2395 * We're about to send a non-EDMA capable command to the 2396 * port. Turn off EDMA so there won't be problems accessing 2397 * shadow block, etc registers. 2398 */ 2399 mv_stop_edma(ap); 2400 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); 2401 mv_pmp_select(ap, qc->dev->link->pmp); 2402 2403 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { 2404 struct mv_host_priv *hpriv = ap->host->private_data; 2405 /* 2406 * Workaround for 88SX60x1 FEr SATA#25 (part 2). 2407 * 2408 * After any NCQ error, the READ_LOG_EXT command 2409 * from libata-eh *must* use mv_qc_issue_fis(). 2410 * Otherwise it might fail, due to chip errata. 2411 * 2412 * Rather than special-case it, we'll just *always* 2413 * use this method here for READ_LOG_EXT, making for 2414 * easier testing. 2415 */ 2416 if (IS_GEN_II(hpriv)) 2417 return mv_qc_issue_fis(qc); 2418 } 2419 return ata_bmdma_qc_issue(qc); 2420 } 2421 2422 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 2423 { 2424 struct mv_port_priv *pp = ap->private_data; 2425 struct ata_queued_cmd *qc; 2426 2427 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 2428 return NULL; 2429 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2430 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) 2431 return qc; 2432 return NULL; 2433 } 2434 2435 static void mv_pmp_error_handler(struct ata_port *ap) 2436 { 2437 unsigned int pmp, pmp_map; 2438 struct mv_port_priv *pp = ap->private_data; 2439 2440 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 2441 /* 2442 * Perform NCQ error analysis on failed PMPs 2443 * before we freeze the port entirely. 2444 * 2445 * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 2446 */ 2447 pmp_map = pp->delayed_eh_pmp_map; 2448 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 2449 for (pmp = 0; pmp_map != 0; pmp++) { 2450 unsigned int this_pmp = (1 << pmp); 2451 if (pmp_map & this_pmp) { 2452 struct ata_link *link = &ap->pmp_link[pmp]; 2453 pmp_map &= ~this_pmp; 2454 ata_eh_analyze_ncq_error(link); 2455 } 2456 } 2457 ata_port_freeze(ap); 2458 } 2459 sata_pmp_error_handler(ap); 2460 } 2461 2462 static unsigned int mv_get_err_pmp_map(struct ata_port *ap) 2463 { 2464 void __iomem *port_mmio = mv_ap_base(ap); 2465 2466 return readl(port_mmio + SATA_TESTCTL) >> 16; 2467 } 2468 2469 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 2470 { 2471 struct ata_eh_info *ehi; 2472 unsigned int pmp; 2473 2474 /* 2475 * Initialize EH info for PMPs which saw device errors 2476 */ 2477 ehi = &ap->link.eh_info; 2478 for (pmp = 0; pmp_map != 0; pmp++) { 2479 unsigned int this_pmp = (1 << pmp); 2480 if (pmp_map & this_pmp) { 2481 struct ata_link *link = &ap->pmp_link[pmp]; 2482 2483 pmp_map &= ~this_pmp; 2484 ehi = &link->eh_info; 2485 ata_ehi_clear_desc(ehi); 2486 ata_ehi_push_desc(ehi, "dev err"); 2487 ehi->err_mask |= AC_ERR_DEV; 2488 ehi->action |= ATA_EH_RESET; 2489 ata_link_abort(link); 2490 } 2491 } 2492 } 2493 2494 static int mv_req_q_empty(struct ata_port *ap) 2495 { 2496 void __iomem *port_mmio = mv_ap_base(ap); 2497 u32 in_ptr, out_ptr; 2498 2499 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) 2500 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2501 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) 2502 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2503 return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 2504 } 2505 2506 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 2507 { 2508 struct mv_port_priv *pp = ap->private_data; 2509 int failed_links; 2510 unsigned int old_map, new_map; 2511 2512 /* 2513 * Device error during FBS+NCQ operation: 2514 * 2515 * Set a port flag to prevent further I/O being enqueued. 2516 * Leave the EDMA running to drain outstanding commands from this port. 2517 * Perform the post-mortem/EH only when all responses are complete. 2518 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 2519 */ 2520 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 2521 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 2522 pp->delayed_eh_pmp_map = 0; 2523 } 2524 old_map = pp->delayed_eh_pmp_map; 2525 new_map = old_map | mv_get_err_pmp_map(ap); 2526 2527 if (old_map != new_map) { 2528 pp->delayed_eh_pmp_map = new_map; 2529 mv_pmp_eh_prep(ap, new_map & ~old_map); 2530 } 2531 failed_links = hweight16(new_map); 2532 2533 ata_port_info(ap, 2534 "%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n", 2535 __func__, pp->delayed_eh_pmp_map, 2536 ap->qc_active, failed_links, 2537 ap->nr_active_links); 2538 2539 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 2540 mv_process_crpb_entries(ap, pp); 2541 mv_stop_edma(ap); 2542 mv_eh_freeze(ap); 2543 ata_port_info(ap, "%s: done\n", __func__); 2544 return 1; /* handled */ 2545 } 2546 ata_port_info(ap, "%s: waiting\n", __func__); 2547 return 1; /* handled */ 2548 } 2549 2550 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 2551 { 2552 /* 2553 * Possible future enhancement: 2554 * 2555 * FBS+non-NCQ operation is not yet implemented. 2556 * See related notes in mv_edma_cfg(). 2557 * 2558 * Device error during FBS+non-NCQ operation: 2559 * 2560 * We need to snapshot the shadow registers for each failed command. 2561 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 2562 */ 2563 return 0; /* not handled */ 2564 } 2565 2566 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 2567 { 2568 struct mv_port_priv *pp = ap->private_data; 2569 2570 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 2571 return 0; /* EDMA was not active: not handled */ 2572 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 2573 return 0; /* FBS was not active: not handled */ 2574 2575 if (!(edma_err_cause & EDMA_ERR_DEV)) 2576 return 0; /* non DEV error: not handled */ 2577 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 2578 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 2579 return 0; /* other problems: not handled */ 2580 2581 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 2582 /* 2583 * EDMA should NOT have self-disabled for this case. 2584 * If it did, then something is wrong elsewhere, 2585 * and we cannot handle it here. 2586 */ 2587 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2588 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n", 2589 __func__, edma_err_cause, pp->pp_flags); 2590 return 0; /* not handled */ 2591 } 2592 return mv_handle_fbs_ncq_dev_err(ap); 2593 } else { 2594 /* 2595 * EDMA should have self-disabled for this case. 2596 * If it did not, then something is wrong elsewhere, 2597 * and we cannot handle it here. 2598 */ 2599 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 2600 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n", 2601 __func__, edma_err_cause, pp->pp_flags); 2602 return 0; /* not handled */ 2603 } 2604 return mv_handle_fbs_non_ncq_dev_err(ap); 2605 } 2606 return 0; /* not handled */ 2607 } 2608 2609 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 2610 { 2611 struct ata_eh_info *ehi = &ap->link.eh_info; 2612 char *when = "idle"; 2613 2614 ata_ehi_clear_desc(ehi); 2615 if (edma_was_enabled) { 2616 when = "EDMA enabled"; 2617 } else { 2618 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 2619 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 2620 when = "polling"; 2621 } 2622 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 2623 ehi->err_mask |= AC_ERR_OTHER; 2624 ehi->action |= ATA_EH_RESET; 2625 ata_port_freeze(ap); 2626 } 2627 2628 /** 2629 * mv_err_intr - Handle error interrupts on the port 2630 * @ap: ATA channel to manipulate 2631 * 2632 * Most cases require a full reset of the chip's state machine, 2633 * which also performs a COMRESET. 2634 * Also, if the port disabled DMA, update our cached copy to match. 2635 * 2636 * LOCKING: 2637 * Inherited from caller. 2638 */ 2639 static void mv_err_intr(struct ata_port *ap) 2640 { 2641 void __iomem *port_mmio = mv_ap_base(ap); 2642 u32 edma_err_cause, eh_freeze_mask, serr = 0; 2643 u32 fis_cause = 0; 2644 struct mv_port_priv *pp = ap->private_data; 2645 struct mv_host_priv *hpriv = ap->host->private_data; 2646 unsigned int action = 0, err_mask = 0; 2647 struct ata_eh_info *ehi = &ap->link.eh_info; 2648 struct ata_queued_cmd *qc; 2649 int abort = 0; 2650 2651 /* 2652 * Read and clear the SError and err_cause bits. 2653 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 2654 * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 2655 */ 2656 sata_scr_read(&ap->link, SCR_ERROR, &serr); 2657 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 2658 2659 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); 2660 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2661 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); 2662 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); 2663 } 2664 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); 2665 2666 if (edma_err_cause & EDMA_ERR_DEV) { 2667 /* 2668 * Device errors during FIS-based switching operation 2669 * require special handling. 2670 */ 2671 if (mv_handle_dev_err(ap, edma_err_cause)) 2672 return; 2673 } 2674 2675 qc = mv_get_active_qc(ap); 2676 ata_ehi_clear_desc(ehi); 2677 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 2678 edma_err_cause, pp->pp_flags); 2679 2680 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 2681 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 2682 if (fis_cause & FIS_IRQ_CAUSE_AN) { 2683 u32 ec = edma_err_cause & 2684 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 2685 sata_async_notification(ap); 2686 if (!ec) 2687 return; /* Just an AN; no need for the nukes */ 2688 ata_ehi_push_desc(ehi, "SDB notify"); 2689 } 2690 } 2691 /* 2692 * All generations share these EDMA error cause bits: 2693 */ 2694 if (edma_err_cause & EDMA_ERR_DEV) { 2695 err_mask |= AC_ERR_DEV; 2696 action |= ATA_EH_RESET; 2697 ata_ehi_push_desc(ehi, "dev error"); 2698 } 2699 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 2700 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 2701 EDMA_ERR_INTRL_PAR)) { 2702 err_mask |= AC_ERR_ATA_BUS; 2703 action |= ATA_EH_RESET; 2704 ata_ehi_push_desc(ehi, "parity error"); 2705 } 2706 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 2707 ata_ehi_hotplugged(ehi); 2708 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 2709 "dev disconnect" : "dev connect"); 2710 action |= ATA_EH_RESET; 2711 } 2712 2713 /* 2714 * Gen-I has a different SELF_DIS bit, 2715 * different FREEZE bits, and no SERR bit: 2716 */ 2717 if (IS_GEN_I(hpriv)) { 2718 eh_freeze_mask = EDMA_EH_FREEZE_5; 2719 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 2720 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2721 ata_ehi_push_desc(ehi, "EDMA self-disable"); 2722 } 2723 } else { 2724 eh_freeze_mask = EDMA_EH_FREEZE; 2725 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 2726 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2727 ata_ehi_push_desc(ehi, "EDMA self-disable"); 2728 } 2729 if (edma_err_cause & EDMA_ERR_SERR) { 2730 ata_ehi_push_desc(ehi, "SError=%08x", serr); 2731 err_mask |= AC_ERR_ATA_BUS; 2732 action |= ATA_EH_RESET; 2733 } 2734 } 2735 2736 if (!err_mask) { 2737 err_mask = AC_ERR_OTHER; 2738 action |= ATA_EH_RESET; 2739 } 2740 2741 ehi->serror |= serr; 2742 ehi->action |= action; 2743 2744 if (qc) 2745 qc->err_mask |= err_mask; 2746 else 2747 ehi->err_mask |= err_mask; 2748 2749 if (err_mask == AC_ERR_DEV) { 2750 /* 2751 * Cannot do ata_port_freeze() here, 2752 * because it would kill PIO access, 2753 * which is needed for further diagnosis. 2754 */ 2755 mv_eh_freeze(ap); 2756 abort = 1; 2757 } else if (edma_err_cause & eh_freeze_mask) { 2758 /* 2759 * Note to self: ata_port_freeze() calls ata_port_abort() 2760 */ 2761 ata_port_freeze(ap); 2762 } else { 2763 abort = 1; 2764 } 2765 2766 if (abort) { 2767 if (qc) 2768 ata_link_abort(qc->dev->link); 2769 else 2770 ata_port_abort(ap); 2771 } 2772 } 2773 2774 static bool mv_process_crpb_response(struct ata_port *ap, 2775 struct mv_crpb *response, unsigned int tag, int ncq_enabled) 2776 { 2777 u8 ata_status; 2778 u16 edma_status = le16_to_cpu(response->flags); 2779 2780 /* 2781 * edma_status from a response queue entry: 2782 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). 2783 * MSB is saved ATA status from command completion. 2784 */ 2785 if (!ncq_enabled) { 2786 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 2787 if (err_cause) { 2788 /* 2789 * Error will be seen/handled by 2790 * mv_err_intr(). So do nothing at all here. 2791 */ 2792 return false; 2793 } 2794 } 2795 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 2796 if (!ac_err_mask(ata_status)) 2797 return true; 2798 /* else: leave it for mv_err_intr() */ 2799 return false; 2800 } 2801 2802 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2803 { 2804 void __iomem *port_mmio = mv_ap_base(ap); 2805 struct mv_host_priv *hpriv = ap->host->private_data; 2806 u32 in_index; 2807 bool work_done = false; 2808 u32 done_mask = 0; 2809 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2810 2811 /* Get the hardware queue position index */ 2812 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) 2813 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2814 2815 /* Process new responses from since the last time we looked */ 2816 while (in_index != pp->resp_idx) { 2817 unsigned int tag; 2818 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2819 2820 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2821 2822 if (IS_GEN_I(hpriv)) { 2823 /* 50xx: no NCQ, only one command active at a time */ 2824 tag = ap->link.active_tag; 2825 } else { 2826 /* Gen II/IIE: get command tag from CRPB entry */ 2827 tag = le16_to_cpu(response->id) & 0x1f; 2828 } 2829 if (mv_process_crpb_response(ap, response, tag, ncq_enabled)) 2830 done_mask |= 1 << tag; 2831 work_done = true; 2832 } 2833 2834 if (work_done) { 2835 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); 2836 2837 /* Update the software queue position index in hardware */ 2838 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2839 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2840 port_mmio + EDMA_RSP_Q_OUT_PTR); 2841 } 2842 } 2843 2844 static void mv_port_intr(struct ata_port *ap, u32 port_cause) 2845 { 2846 struct mv_port_priv *pp; 2847 int edma_was_enabled; 2848 2849 /* 2850 * Grab a snapshot of the EDMA_EN flag setting, 2851 * so that we have a consistent view for this port, 2852 * even if something we call of our routines changes it. 2853 */ 2854 pp = ap->private_data; 2855 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2856 /* 2857 * Process completed CRPB response(s) before other events. 2858 */ 2859 if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2860 mv_process_crpb_entries(ap, pp); 2861 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 2862 mv_handle_fbs_ncq_dev_err(ap); 2863 } 2864 /* 2865 * Handle chip-reported errors, or continue on to handle PIO. 2866 */ 2867 if (unlikely(port_cause & ERR_IRQ)) { 2868 mv_err_intr(ap); 2869 } else if (!edma_was_enabled) { 2870 struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2871 if (qc) 2872 ata_bmdma_port_intr(ap, qc); 2873 else 2874 mv_unexpected_intr(ap, edma_was_enabled); 2875 } 2876 } 2877 2878 /** 2879 * mv_host_intr - Handle all interrupts on the given host controller 2880 * @host: host specific structure 2881 * @main_irq_cause: Main interrupt cause register for the chip. 2882 * 2883 * LOCKING: 2884 * Inherited from caller. 2885 */ 2886 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 2887 { 2888 struct mv_host_priv *hpriv = host->private_data; 2889 void __iomem *mmio = hpriv->base, *hc_mmio; 2890 unsigned int handled = 0, port; 2891 2892 /* If asserted, clear the "all ports" IRQ coalescing bit */ 2893 if (main_irq_cause & ALL_PORTS_COAL_DONE) 2894 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); 2895 2896 for (port = 0; port < hpriv->n_ports; port++) { 2897 struct ata_port *ap = host->ports[port]; 2898 unsigned int p, shift, hardport, port_cause; 2899 2900 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2901 /* 2902 * Each hc within the host has its own hc_irq_cause register, 2903 * where the interrupting ports bits get ack'd. 2904 */ 2905 if (hardport == 0) { /* first port on this hc ? */ 2906 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2907 u32 port_mask, ack_irqs; 2908 /* 2909 * Skip this entire hc if nothing pending for any ports 2910 */ 2911 if (!hc_cause) { 2912 port += MV_PORTS_PER_HC - 1; 2913 continue; 2914 } 2915 /* 2916 * We don't need/want to read the hc_irq_cause register, 2917 * because doing so hurts performance, and 2918 * main_irq_cause already gives us everything we need. 2919 * 2920 * But we do have to *write* to the hc_irq_cause to ack 2921 * the ports that we are handling this time through. 2922 * 2923 * This requires that we create a bitmap for those 2924 * ports which interrupted us, and use that bitmap 2925 * to ack (only) those ports via hc_irq_cause. 2926 */ 2927 ack_irqs = 0; 2928 if (hc_cause & PORTS_0_3_COAL_DONE) 2929 ack_irqs = HC_COAL_IRQ; 2930 for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2931 if ((port + p) >= hpriv->n_ports) 2932 break; 2933 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2934 if (hc_cause & port_mask) 2935 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2936 } 2937 hc_mmio = mv_hc_base_from_port(mmio, port); 2938 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); 2939 handled = 1; 2940 } 2941 /* 2942 * Handle interrupts signalled for this port: 2943 */ 2944 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2945 if (port_cause) 2946 mv_port_intr(ap, port_cause); 2947 } 2948 return handled; 2949 } 2950 2951 static int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2952 { 2953 struct mv_host_priv *hpriv = host->private_data; 2954 struct ata_port *ap; 2955 struct ata_queued_cmd *qc; 2956 struct ata_eh_info *ehi; 2957 unsigned int i, err_mask, printed = 0; 2958 u32 err_cause; 2959 2960 err_cause = readl(mmio + hpriv->irq_cause_offset); 2961 2962 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); 2963 2964 DPRINTK("All regs @ PCI error\n"); 2965 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2966 2967 writelfl(0, mmio + hpriv->irq_cause_offset); 2968 2969 for (i = 0; i < host->n_ports; i++) { 2970 ap = host->ports[i]; 2971 if (!ata_link_offline(&ap->link)) { 2972 ehi = &ap->link.eh_info; 2973 ata_ehi_clear_desc(ehi); 2974 if (!printed++) 2975 ata_ehi_push_desc(ehi, 2976 "PCI err cause 0x%08x", err_cause); 2977 err_mask = AC_ERR_HOST_BUS; 2978 ehi->action = ATA_EH_RESET; 2979 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2980 if (qc) 2981 qc->err_mask |= err_mask; 2982 else 2983 ehi->err_mask |= err_mask; 2984 2985 ata_port_freeze(ap); 2986 } 2987 } 2988 return 1; /* handled */ 2989 } 2990 2991 /** 2992 * mv_interrupt - Main interrupt event handler 2993 * @irq: unused 2994 * @dev_instance: private data; in this case the host structure 2995 * 2996 * Read the read only register to determine if any host 2997 * controllers have pending interrupts. If so, call lower level 2998 * routine to handle. Also check for PCI errors which are only 2999 * reported here. 3000 * 3001 * LOCKING: 3002 * This routine holds the host lock while processing pending 3003 * interrupts. 3004 */ 3005 static irqreturn_t mv_interrupt(int irq, void *dev_instance) 3006 { 3007 struct ata_host *host = dev_instance; 3008 struct mv_host_priv *hpriv = host->private_data; 3009 unsigned int handled = 0; 3010 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; 3011 u32 main_irq_cause, pending_irqs; 3012 3013 spin_lock(&host->lock); 3014 3015 /* for MSI: block new interrupts while in here */ 3016 if (using_msi) 3017 mv_write_main_irq_mask(0, hpriv); 3018 3019 main_irq_cause = readl(hpriv->main_irq_cause_addr); 3020 pending_irqs = main_irq_cause & hpriv->main_irq_mask; 3021 /* 3022 * Deal with cases where we either have nothing pending, or have read 3023 * a bogus register value which can indicate HW removal or PCI fault. 3024 */ 3025 if (pending_irqs && main_irq_cause != 0xffffffffU) { 3026 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 3027 handled = mv_pci_error(host, hpriv->base); 3028 else 3029 handled = mv_host_intr(host, pending_irqs); 3030 } 3031 3032 /* for MSI: unmask; interrupt cause bits will retrigger now */ 3033 if (using_msi) 3034 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); 3035 3036 spin_unlock(&host->lock); 3037 3038 return IRQ_RETVAL(handled); 3039 } 3040 3041 static unsigned int mv5_scr_offset(unsigned int sc_reg_in) 3042 { 3043 unsigned int ofs; 3044 3045 switch (sc_reg_in) { 3046 case SCR_STATUS: 3047 case SCR_ERROR: 3048 case SCR_CONTROL: 3049 ofs = sc_reg_in * sizeof(u32); 3050 break; 3051 default: 3052 ofs = 0xffffffffU; 3053 break; 3054 } 3055 return ofs; 3056 } 3057 3058 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 3059 { 3060 struct mv_host_priv *hpriv = link->ap->host->private_data; 3061 void __iomem *mmio = hpriv->base; 3062 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3063 unsigned int ofs = mv5_scr_offset(sc_reg_in); 3064 3065 if (ofs != 0xffffffffU) { 3066 *val = readl(addr + ofs); 3067 return 0; 3068 } else 3069 return -EINVAL; 3070 } 3071 3072 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 3073 { 3074 struct mv_host_priv *hpriv = link->ap->host->private_data; 3075 void __iomem *mmio = hpriv->base; 3076 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 3077 unsigned int ofs = mv5_scr_offset(sc_reg_in); 3078 3079 if (ofs != 0xffffffffU) { 3080 writelfl(val, addr + ofs); 3081 return 0; 3082 } else 3083 return -EINVAL; 3084 } 3085 3086 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 3087 { 3088 struct pci_dev *pdev = to_pci_dev(host->dev); 3089 int early_5080; 3090 3091 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 3092 3093 if (!early_5080) { 3094 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3095 tmp |= (1 << 0); 3096 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3097 } 3098 3099 mv_reset_pci_bus(host, mmio); 3100 } 3101 3102 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3103 { 3104 writel(0x0fcfffff, mmio + FLASH_CTL); 3105 } 3106 3107 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 3108 void __iomem *mmio) 3109 { 3110 void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 3111 u32 tmp; 3112 3113 tmp = readl(phy_mmio + MV5_PHY_MODE); 3114 3115 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 3116 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 3117 } 3118 3119 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3120 { 3121 u32 tmp; 3122 3123 writel(0, mmio + GPIO_PORT_CTL); 3124 3125 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 3126 3127 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 3128 tmp |= ~(1 << 0); 3129 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 3130 } 3131 3132 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 3133 unsigned int port) 3134 { 3135 void __iomem *phy_mmio = mv5_phy_base(mmio, port); 3136 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 3137 u32 tmp; 3138 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 3139 3140 if (fix_apm_sq) { 3141 tmp = readl(phy_mmio + MV5_LTMODE); 3142 tmp |= (1 << 19); 3143 writel(tmp, phy_mmio + MV5_LTMODE); 3144 3145 tmp = readl(phy_mmio + MV5_PHY_CTL); 3146 tmp &= ~0x3; 3147 tmp |= 0x1; 3148 writel(tmp, phy_mmio + MV5_PHY_CTL); 3149 } 3150 3151 tmp = readl(phy_mmio + MV5_PHY_MODE); 3152 tmp &= ~mask; 3153 tmp |= hpriv->signal[port].pre; 3154 tmp |= hpriv->signal[port].amps; 3155 writel(tmp, phy_mmio + MV5_PHY_MODE); 3156 } 3157 3158 3159 #undef ZERO 3160 #define ZERO(reg) writel(0, port_mmio + (reg)) 3161 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 3162 unsigned int port) 3163 { 3164 void __iomem *port_mmio = mv_port_base(mmio, port); 3165 3166 mv_reset_channel(hpriv, mmio, port); 3167 3168 ZERO(0x028); /* command */ 3169 writel(0x11f, port_mmio + EDMA_CFG); 3170 ZERO(0x004); /* timer */ 3171 ZERO(0x008); /* irq err cause */ 3172 ZERO(0x00c); /* irq err mask */ 3173 ZERO(0x010); /* rq bah */ 3174 ZERO(0x014); /* rq inp */ 3175 ZERO(0x018); /* rq outp */ 3176 ZERO(0x01c); /* respq bah */ 3177 ZERO(0x024); /* respq outp */ 3178 ZERO(0x020); /* respq inp */ 3179 ZERO(0x02c); /* test control */ 3180 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); 3181 } 3182 #undef ZERO 3183 3184 #define ZERO(reg) writel(0, hc_mmio + (reg)) 3185 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3186 unsigned int hc) 3187 { 3188 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3189 u32 tmp; 3190 3191 ZERO(0x00c); 3192 ZERO(0x010); 3193 ZERO(0x014); 3194 ZERO(0x018); 3195 3196 tmp = readl(hc_mmio + 0x20); 3197 tmp &= 0x1c1c1c1c; 3198 tmp |= 0x03030303; 3199 writel(tmp, hc_mmio + 0x20); 3200 } 3201 #undef ZERO 3202 3203 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3204 unsigned int n_hc) 3205 { 3206 unsigned int hc, port; 3207 3208 for (hc = 0; hc < n_hc; hc++) { 3209 for (port = 0; port < MV_PORTS_PER_HC; port++) 3210 mv5_reset_hc_port(hpriv, mmio, 3211 (hc * MV_PORTS_PER_HC) + port); 3212 3213 mv5_reset_one_hc(hpriv, mmio, hc); 3214 } 3215 3216 return 0; 3217 } 3218 3219 #undef ZERO 3220 #define ZERO(reg) writel(0, mmio + (reg)) 3221 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 3222 { 3223 struct mv_host_priv *hpriv = host->private_data; 3224 u32 tmp; 3225 3226 tmp = readl(mmio + MV_PCI_MODE); 3227 tmp &= 0xff00ffff; 3228 writel(tmp, mmio + MV_PCI_MODE); 3229 3230 ZERO(MV_PCI_DISC_TIMER); 3231 ZERO(MV_PCI_MSI_TRIGGER); 3232 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); 3233 ZERO(MV_PCI_SERR_MASK); 3234 ZERO(hpriv->irq_cause_offset); 3235 ZERO(hpriv->irq_mask_offset); 3236 ZERO(MV_PCI_ERR_LOW_ADDRESS); 3237 ZERO(MV_PCI_ERR_HIGH_ADDRESS); 3238 ZERO(MV_PCI_ERR_ATTRIBUTE); 3239 ZERO(MV_PCI_ERR_COMMAND); 3240 } 3241 #undef ZERO 3242 3243 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 3244 { 3245 u32 tmp; 3246 3247 mv5_reset_flash(hpriv, mmio); 3248 3249 tmp = readl(mmio + GPIO_PORT_CTL); 3250 tmp &= 0x3; 3251 tmp |= (1 << 5) | (1 << 6); 3252 writel(tmp, mmio + GPIO_PORT_CTL); 3253 } 3254 3255 /** 3256 * mv6_reset_hc - Perform the 6xxx global soft reset 3257 * @mmio: base address of the HBA 3258 * 3259 * This routine only applies to 6xxx parts. 3260 * 3261 * LOCKING: 3262 * Inherited from caller. 3263 */ 3264 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 3265 unsigned int n_hc) 3266 { 3267 void __iomem *reg = mmio + PCI_MAIN_CMD_STS; 3268 int i, rc = 0; 3269 u32 t; 3270 3271 /* Following procedure defined in PCI "main command and status 3272 * register" table. 3273 */ 3274 t = readl(reg); 3275 writel(t | STOP_PCI_MASTER, reg); 3276 3277 for (i = 0; i < 1000; i++) { 3278 udelay(1); 3279 t = readl(reg); 3280 if (PCI_MASTER_EMPTY & t) 3281 break; 3282 } 3283 if (!(PCI_MASTER_EMPTY & t)) { 3284 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 3285 rc = 1; 3286 goto done; 3287 } 3288 3289 /* set reset */ 3290 i = 5; 3291 do { 3292 writel(t | GLOB_SFT_RST, reg); 3293 t = readl(reg); 3294 udelay(1); 3295 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 3296 3297 if (!(GLOB_SFT_RST & t)) { 3298 printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 3299 rc = 1; 3300 goto done; 3301 } 3302 3303 /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 3304 i = 5; 3305 do { 3306 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 3307 t = readl(reg); 3308 udelay(1); 3309 } while ((GLOB_SFT_RST & t) && (i-- > 0)); 3310 3311 if (GLOB_SFT_RST & t) { 3312 printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 3313 rc = 1; 3314 } 3315 done: 3316 return rc; 3317 } 3318 3319 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 3320 void __iomem *mmio) 3321 { 3322 void __iomem *port_mmio; 3323 u32 tmp; 3324 3325 tmp = readl(mmio + RESET_CFG); 3326 if ((tmp & (1 << 0)) == 0) { 3327 hpriv->signal[idx].amps = 0x7 << 8; 3328 hpriv->signal[idx].pre = 0x1 << 5; 3329 return; 3330 } 3331 3332 port_mmio = mv_port_base(mmio, idx); 3333 tmp = readl(port_mmio + PHY_MODE2); 3334 3335 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3336 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3337 } 3338 3339 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 3340 { 3341 writel(0x00000060, mmio + GPIO_PORT_CTL); 3342 } 3343 3344 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 3345 unsigned int port) 3346 { 3347 void __iomem *port_mmio = mv_port_base(mmio, port); 3348 3349 u32 hp_flags = hpriv->hp_flags; 3350 int fix_phy_mode2 = 3351 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3352 int fix_phy_mode4 = 3353 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 3354 u32 m2, m3; 3355 3356 if (fix_phy_mode2) { 3357 m2 = readl(port_mmio + PHY_MODE2); 3358 m2 &= ~(1 << 16); 3359 m2 |= (1 << 31); 3360 writel(m2, port_mmio + PHY_MODE2); 3361 3362 udelay(200); 3363 3364 m2 = readl(port_mmio + PHY_MODE2); 3365 m2 &= ~((1 << 16) | (1 << 31)); 3366 writel(m2, port_mmio + PHY_MODE2); 3367 3368 udelay(200); 3369 } 3370 3371 /* 3372 * Gen-II/IIe PHY_MODE3 errata RM#2: 3373 * Achieves better receiver noise performance than the h/w default: 3374 */ 3375 m3 = readl(port_mmio + PHY_MODE3); 3376 m3 = (m3 & 0x1f) | (0x5555601 << 5); 3377 3378 /* Guideline 88F5182 (GL# SATA-S11) */ 3379 if (IS_SOC(hpriv)) 3380 m3 &= ~0x1c; 3381 3382 if (fix_phy_mode4) { 3383 u32 m4 = readl(port_mmio + PHY_MODE4); 3384 /* 3385 * Enforce reserved-bit restrictions on GenIIe devices only. 3386 * For earlier chipsets, force only the internal config field 3387 * (workaround for errata FEr SATA#10 part 1). 3388 */ 3389 if (IS_GEN_IIE(hpriv)) 3390 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 3391 else 3392 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 3393 writel(m4, port_mmio + PHY_MODE4); 3394 } 3395 /* 3396 * Workaround for 60x1-B2 errata SATA#13: 3397 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 3398 * so we must always rewrite PHY_MODE3 after PHY_MODE4. 3399 * Or ensure we use writelfl() when writing PHY_MODE4. 3400 */ 3401 writel(m3, port_mmio + PHY_MODE3); 3402 3403 /* Revert values of pre-emphasis and signal amps to the saved ones */ 3404 m2 = readl(port_mmio + PHY_MODE2); 3405 3406 m2 &= ~MV_M2_PREAMP_MASK; 3407 m2 |= hpriv->signal[port].amps; 3408 m2 |= hpriv->signal[port].pre; 3409 m2 &= ~(1 << 16); 3410 3411 /* according to mvSata 3.6.1, some IIE values are fixed */ 3412 if (IS_GEN_IIE(hpriv)) { 3413 m2 &= ~0xC30FF01F; 3414 m2 |= 0x0000900F; 3415 } 3416 3417 writel(m2, port_mmio + PHY_MODE2); 3418 } 3419 3420 /* TODO: use the generic LED interface to configure the SATA Presence */ 3421 /* & Acitivy LEDs on the board */ 3422 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 3423 void __iomem *mmio) 3424 { 3425 return; 3426 } 3427 3428 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 3429 void __iomem *mmio) 3430 { 3431 void __iomem *port_mmio; 3432 u32 tmp; 3433 3434 port_mmio = mv_port_base(mmio, idx); 3435 tmp = readl(port_mmio + PHY_MODE2); 3436 3437 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 3438 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 3439 } 3440 3441 #undef ZERO 3442 #define ZERO(reg) writel(0, port_mmio + (reg)) 3443 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 3444 void __iomem *mmio, unsigned int port) 3445 { 3446 void __iomem *port_mmio = mv_port_base(mmio, port); 3447 3448 mv_reset_channel(hpriv, mmio, port); 3449 3450 ZERO(0x028); /* command */ 3451 writel(0x101f, port_mmio + EDMA_CFG); 3452 ZERO(0x004); /* timer */ 3453 ZERO(0x008); /* irq err cause */ 3454 ZERO(0x00c); /* irq err mask */ 3455 ZERO(0x010); /* rq bah */ 3456 ZERO(0x014); /* rq inp */ 3457 ZERO(0x018); /* rq outp */ 3458 ZERO(0x01c); /* respq bah */ 3459 ZERO(0x024); /* respq outp */ 3460 ZERO(0x020); /* respq inp */ 3461 ZERO(0x02c); /* test control */ 3462 writel(0x800, port_mmio + EDMA_IORDY_TMOUT); 3463 } 3464 3465 #undef ZERO 3466 3467 #define ZERO(reg) writel(0, hc_mmio + (reg)) 3468 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 3469 void __iomem *mmio) 3470 { 3471 void __iomem *hc_mmio = mv_hc_base(mmio, 0); 3472 3473 ZERO(0x00c); 3474 ZERO(0x010); 3475 ZERO(0x014); 3476 3477 } 3478 3479 #undef ZERO 3480 3481 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 3482 void __iomem *mmio, unsigned int n_hc) 3483 { 3484 unsigned int port; 3485 3486 for (port = 0; port < hpriv->n_ports; port++) 3487 mv_soc_reset_hc_port(hpriv, mmio, port); 3488 3489 mv_soc_reset_one_hc(hpriv, mmio); 3490 3491 return 0; 3492 } 3493 3494 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 3495 void __iomem *mmio) 3496 { 3497 return; 3498 } 3499 3500 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 3501 { 3502 return; 3503 } 3504 3505 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, 3506 void __iomem *mmio, unsigned int port) 3507 { 3508 void __iomem *port_mmio = mv_port_base(mmio, port); 3509 u32 reg; 3510 3511 reg = readl(port_mmio + PHY_MODE3); 3512 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ 3513 reg |= (0x1 << 27); 3514 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ 3515 reg |= (0x1 << 29); 3516 writel(reg, port_mmio + PHY_MODE3); 3517 3518 reg = readl(port_mmio + PHY_MODE4); 3519 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ 3520 reg |= (0x1 << 16); 3521 writel(reg, port_mmio + PHY_MODE4); 3522 3523 reg = readl(port_mmio + PHY_MODE9_GEN2); 3524 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 3525 reg |= 0x8; 3526 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 3527 writel(reg, port_mmio + PHY_MODE9_GEN2); 3528 3529 reg = readl(port_mmio + PHY_MODE9_GEN1); 3530 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ 3531 reg |= 0x8; 3532 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ 3533 writel(reg, port_mmio + PHY_MODE9_GEN1); 3534 } 3535 3536 /** 3537 * soc_is_65 - check if the soc is 65 nano device 3538 * 3539 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS 3540 * register, this register should contain non-zero value and it exists only 3541 * in the 65 nano devices, when reading it from older devices we get 0. 3542 */ 3543 static bool soc_is_65n(struct mv_host_priv *hpriv) 3544 { 3545 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); 3546 3547 if (readl(port0_mmio + PHYCFG_OFS)) 3548 return true; 3549 return false; 3550 } 3551 3552 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 3553 { 3554 u32 ifcfg = readl(port_mmio + SATA_IFCFG); 3555 3556 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 3557 if (want_gen2i) 3558 ifcfg |= (1 << 7); /* enable gen2i speed */ 3559 writelfl(ifcfg, port_mmio + SATA_IFCFG); 3560 } 3561 3562 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 3563 unsigned int port_no) 3564 { 3565 void __iomem *port_mmio = mv_port_base(mmio, port_no); 3566 3567 /* 3568 * The datasheet warns against setting EDMA_RESET when EDMA is active 3569 * (but doesn't say what the problem might be). So we first try 3570 * to disable the EDMA engine before doing the EDMA_RESET operation. 3571 */ 3572 mv_stop_edma_engine(port_mmio); 3573 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3574 3575 if (!IS_GEN_I(hpriv)) { 3576 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 3577 mv_setup_ifcfg(port_mmio, 1); 3578 } 3579 /* 3580 * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 3581 * link, and physical layers. It resets all SATA interface registers 3582 * (except for SATA_IFCFG), and issues a COMRESET to the dev. 3583 */ 3584 writelfl(EDMA_RESET, port_mmio + EDMA_CMD); 3585 udelay(25); /* allow reset propagation */ 3586 writelfl(0, port_mmio + EDMA_CMD); 3587 3588 hpriv->ops->phy_errata(hpriv, mmio, port_no); 3589 3590 if (IS_GEN_I(hpriv)) 3591 mdelay(1); 3592 } 3593 3594 static void mv_pmp_select(struct ata_port *ap, int pmp) 3595 { 3596 if (sata_pmp_supported(ap)) { 3597 void __iomem *port_mmio = mv_ap_base(ap); 3598 u32 reg = readl(port_mmio + SATA_IFCTL); 3599 int old = reg & 0xf; 3600 3601 if (old != pmp) { 3602 reg = (reg & ~0xf) | pmp; 3603 writelfl(reg, port_mmio + SATA_IFCTL); 3604 } 3605 } 3606 } 3607 3608 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 3609 unsigned long deadline) 3610 { 3611 mv_pmp_select(link->ap, sata_srst_pmp(link)); 3612 return sata_std_hardreset(link, class, deadline); 3613 } 3614 3615 static int mv_softreset(struct ata_link *link, unsigned int *class, 3616 unsigned long deadline) 3617 { 3618 mv_pmp_select(link->ap, sata_srst_pmp(link)); 3619 return ata_sff_softreset(link, class, deadline); 3620 } 3621 3622 static int mv_hardreset(struct ata_link *link, unsigned int *class, 3623 unsigned long deadline) 3624 { 3625 struct ata_port *ap = link->ap; 3626 struct mv_host_priv *hpriv = ap->host->private_data; 3627 struct mv_port_priv *pp = ap->private_data; 3628 void __iomem *mmio = hpriv->base; 3629 int rc, attempts = 0, extra = 0; 3630 u32 sstatus; 3631 bool online; 3632 3633 mv_reset_channel(hpriv, mmio, ap->port_no); 3634 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 3635 pp->pp_flags &= 3636 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); 3637 3638 /* Workaround for errata FEr SATA#10 (part 2) */ 3639 do { 3640 const unsigned long *timing = 3641 sata_ehc_deb_timing(&link->eh_context); 3642 3643 rc = sata_link_hardreset(link, timing, deadline + extra, 3644 &online, NULL); 3645 rc = online ? -EAGAIN : rc; 3646 if (rc) 3647 return rc; 3648 sata_scr_read(link, SCR_STATUS, &sstatus); 3649 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 3650 /* Force 1.5gb/s link speed and try again */ 3651 mv_setup_ifcfg(mv_ap_base(ap), 0); 3652 if (time_after(jiffies + HZ, deadline)) 3653 extra = HZ; /* only extend it once, max */ 3654 } 3655 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 3656 mv_save_cached_regs(ap); 3657 mv_edma_cfg(ap, 0, 0); 3658 3659 return rc; 3660 } 3661 3662 static void mv_eh_freeze(struct ata_port *ap) 3663 { 3664 mv_stop_edma(ap); 3665 mv_enable_port_irqs(ap, 0); 3666 } 3667 3668 static void mv_eh_thaw(struct ata_port *ap) 3669 { 3670 struct mv_host_priv *hpriv = ap->host->private_data; 3671 unsigned int port = ap->port_no; 3672 unsigned int hardport = mv_hardport_from_port(port); 3673 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 3674 void __iomem *port_mmio = mv_ap_base(ap); 3675 u32 hc_irq_cause; 3676 3677 /* clear EDMA errors on this port */ 3678 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3679 3680 /* clear pending irq events */ 3681 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); 3682 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); 3683 3684 mv_enable_port_irqs(ap, ERR_IRQ); 3685 } 3686 3687 /** 3688 * mv_port_init - Perform some early initialization on a single port. 3689 * @port: libata data structure storing shadow register addresses 3690 * @port_mmio: base address of the port 3691 * 3692 * Initialize shadow register mmio addresses, clear outstanding 3693 * interrupts on the port, and unmask interrupts for the future 3694 * start of the port. 3695 * 3696 * LOCKING: 3697 * Inherited from caller. 3698 */ 3699 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 3700 { 3701 void __iomem *serr, *shd_base = port_mmio + SHD_BLK; 3702 3703 /* PIO related setup 3704 */ 3705 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 3706 port->error_addr = 3707 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 3708 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 3709 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 3710 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 3711 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 3712 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 3713 port->status_addr = 3714 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 3715 /* special case: control/altstatus doesn't have ATA_REG_ address */ 3716 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; 3717 3718 /* Clear any currently outstanding port interrupt conditions */ 3719 serr = port_mmio + mv_scr_offset(SCR_ERROR); 3720 writelfl(readl(serr), serr); 3721 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); 3722 3723 /* unmask all non-transient EDMA error interrupts */ 3724 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); 3725 3726 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 3727 readl(port_mmio + EDMA_CFG), 3728 readl(port_mmio + EDMA_ERR_IRQ_CAUSE), 3729 readl(port_mmio + EDMA_ERR_IRQ_MASK)); 3730 } 3731 3732 static unsigned int mv_in_pcix_mode(struct ata_host *host) 3733 { 3734 struct mv_host_priv *hpriv = host->private_data; 3735 void __iomem *mmio = hpriv->base; 3736 u32 reg; 3737 3738 if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 3739 return 0; /* not PCI-X capable */ 3740 reg = readl(mmio + MV_PCI_MODE); 3741 if ((reg & MV_PCI_MODE_MASK) == 0) 3742 return 0; /* conventional PCI mode */ 3743 return 1; /* chip is in PCI-X mode */ 3744 } 3745 3746 static int mv_pci_cut_through_okay(struct ata_host *host) 3747 { 3748 struct mv_host_priv *hpriv = host->private_data; 3749 void __iomem *mmio = hpriv->base; 3750 u32 reg; 3751 3752 if (!mv_in_pcix_mode(host)) { 3753 reg = readl(mmio + MV_PCI_COMMAND); 3754 if (reg & MV_PCI_COMMAND_MRDTRIG) 3755 return 0; /* not okay */ 3756 } 3757 return 1; /* okay */ 3758 } 3759 3760 static void mv_60x1b2_errata_pci7(struct ata_host *host) 3761 { 3762 struct mv_host_priv *hpriv = host->private_data; 3763 void __iomem *mmio = hpriv->base; 3764 3765 /* workaround for 60x1-B2 errata PCI#7 */ 3766 if (mv_in_pcix_mode(host)) { 3767 u32 reg = readl(mmio + MV_PCI_COMMAND); 3768 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); 3769 } 3770 } 3771 3772 static int mv_chip_id(struct ata_host *host, unsigned int board_idx) 3773 { 3774 struct pci_dev *pdev = to_pci_dev(host->dev); 3775 struct mv_host_priv *hpriv = host->private_data; 3776 u32 hp_flags = hpriv->hp_flags; 3777 3778 switch (board_idx) { 3779 case chip_5080: 3780 hpriv->ops = &mv5xxx_ops; 3781 hp_flags |= MV_HP_GEN_I; 3782 3783 switch (pdev->revision) { 3784 case 0x1: 3785 hp_flags |= MV_HP_ERRATA_50XXB0; 3786 break; 3787 case 0x3: 3788 hp_flags |= MV_HP_ERRATA_50XXB2; 3789 break; 3790 default: 3791 dev_warn(&pdev->dev, 3792 "Applying 50XXB2 workarounds to unknown rev\n"); 3793 hp_flags |= MV_HP_ERRATA_50XXB2; 3794 break; 3795 } 3796 break; 3797 3798 case chip_504x: 3799 case chip_508x: 3800 hpriv->ops = &mv5xxx_ops; 3801 hp_flags |= MV_HP_GEN_I; 3802 3803 switch (pdev->revision) { 3804 case 0x0: 3805 hp_flags |= MV_HP_ERRATA_50XXB0; 3806 break; 3807 case 0x3: 3808 hp_flags |= MV_HP_ERRATA_50XXB2; 3809 break; 3810 default: 3811 dev_warn(&pdev->dev, 3812 "Applying B2 workarounds to unknown rev\n"); 3813 hp_flags |= MV_HP_ERRATA_50XXB2; 3814 break; 3815 } 3816 break; 3817 3818 case chip_604x: 3819 case chip_608x: 3820 hpriv->ops = &mv6xxx_ops; 3821 hp_flags |= MV_HP_GEN_II; 3822 3823 switch (pdev->revision) { 3824 case 0x7: 3825 mv_60x1b2_errata_pci7(host); 3826 hp_flags |= MV_HP_ERRATA_60X1B2; 3827 break; 3828 case 0x9: 3829 hp_flags |= MV_HP_ERRATA_60X1C0; 3830 break; 3831 default: 3832 dev_warn(&pdev->dev, 3833 "Applying B2 workarounds to unknown rev\n"); 3834 hp_flags |= MV_HP_ERRATA_60X1B2; 3835 break; 3836 } 3837 break; 3838 3839 case chip_7042: 3840 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 3841 if (pdev->vendor == PCI_VENDOR_ID_TTI && 3842 (pdev->device == 0x2300 || pdev->device == 0x2310)) 3843 { 3844 /* 3845 * Highpoint RocketRAID PCIe 23xx series cards: 3846 * 3847 * Unconfigured drives are treated as "Legacy" 3848 * by the BIOS, and it overwrites sector 8 with 3849 * a "Lgcy" metadata block prior to Linux boot. 3850 * 3851 * Configured drives (RAID or JBOD) leave sector 8 3852 * alone, but instead overwrite a high numbered 3853 * sector for the RAID metadata. This sector can 3854 * be determined exactly, by truncating the physical 3855 * drive capacity to a nice even GB value. 3856 * 3857 * RAID metadata is at: (dev->n_sectors & ~0xfffff) 3858 * 3859 * Warn the user, lest they think we're just buggy. 3860 */ 3861 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 3862 " BIOS CORRUPTS DATA on all attached drives," 3863 " regardless of if/how they are configured." 3864 " BEWARE!\n"); 3865 printk(KERN_WARNING DRV_NAME ": For data safety, do not" 3866 " use sectors 8-9 on \"Legacy\" drives," 3867 " and avoid the final two gigabytes on" 3868 " all RocketRAID BIOS initialized drives.\n"); 3869 } 3870 /* drop through */ 3871 case chip_6042: 3872 hpriv->ops = &mv6xxx_ops; 3873 hp_flags |= MV_HP_GEN_IIE; 3874 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3875 hp_flags |= MV_HP_CUT_THROUGH; 3876 3877 switch (pdev->revision) { 3878 case 0x2: /* Rev.B0: the first/only public release */ 3879 hp_flags |= MV_HP_ERRATA_60X1C0; 3880 break; 3881 default: 3882 dev_warn(&pdev->dev, 3883 "Applying 60X1C0 workarounds to unknown rev\n"); 3884 hp_flags |= MV_HP_ERRATA_60X1C0; 3885 break; 3886 } 3887 break; 3888 case chip_soc: 3889 if (soc_is_65n(hpriv)) 3890 hpriv->ops = &mv_soc_65n_ops; 3891 else 3892 hpriv->ops = &mv_soc_ops; 3893 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3894 MV_HP_ERRATA_60X1C0; 3895 break; 3896 3897 default: 3898 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx); 3899 return 1; 3900 } 3901 3902 hpriv->hp_flags = hp_flags; 3903 if (hp_flags & MV_HP_PCIE) { 3904 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; 3905 hpriv->irq_mask_offset = PCIE_IRQ_MASK; 3906 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 3907 } else { 3908 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; 3909 hpriv->irq_mask_offset = PCI_IRQ_MASK; 3910 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 3911 } 3912 3913 return 0; 3914 } 3915 3916 /** 3917 * mv_init_host - Perform some early initialization of the host. 3918 * @host: ATA host to initialize 3919 * 3920 * If possible, do an early global reset of the host. Then do 3921 * our port init and clear/unmask all/relevant host interrupts. 3922 * 3923 * LOCKING: 3924 * Inherited from caller. 3925 */ 3926 static int mv_init_host(struct ata_host *host) 3927 { 3928 int rc = 0, n_hc, port, hc; 3929 struct mv_host_priv *hpriv = host->private_data; 3930 void __iomem *mmio = hpriv->base; 3931 3932 rc = mv_chip_id(host, hpriv->board_idx); 3933 if (rc) 3934 goto done; 3935 3936 if (IS_SOC(hpriv)) { 3937 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; 3938 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; 3939 } else { 3940 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; 3941 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; 3942 } 3943 3944 /* initialize shadow irq mask with register's value */ 3945 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); 3946 3947 /* global interrupt mask: 0 == mask everything */ 3948 mv_set_main_irq_mask(host, ~0, 0); 3949 3950 n_hc = mv_get_hc_count(host->ports[0]->flags); 3951 3952 for (port = 0; port < host->n_ports; port++) 3953 if (hpriv->ops->read_preamp) 3954 hpriv->ops->read_preamp(hpriv, port, mmio); 3955 3956 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 3957 if (rc) 3958 goto done; 3959 3960 hpriv->ops->reset_flash(hpriv, mmio); 3961 hpriv->ops->reset_bus(host, mmio); 3962 hpriv->ops->enable_leds(hpriv, mmio); 3963 3964 for (port = 0; port < host->n_ports; port++) { 3965 struct ata_port *ap = host->ports[port]; 3966 void __iomem *port_mmio = mv_port_base(mmio, port); 3967 3968 mv_port_init(&ap->ioaddr, port_mmio); 3969 } 3970 3971 for (hc = 0; hc < n_hc; hc++) { 3972 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3973 3974 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 3975 "(before clear)=0x%08x\n", hc, 3976 readl(hc_mmio + HC_CFG), 3977 readl(hc_mmio + HC_IRQ_CAUSE)); 3978 3979 /* Clear any currently outstanding hc interrupt conditions */ 3980 writelfl(0, hc_mmio + HC_IRQ_CAUSE); 3981 } 3982 3983 if (!IS_SOC(hpriv)) { 3984 /* Clear any currently outstanding host interrupt conditions */ 3985 writelfl(0, mmio + hpriv->irq_cause_offset); 3986 3987 /* and unmask interrupt generation for host regs */ 3988 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); 3989 } 3990 3991 /* 3992 * enable only global host interrupts for now. 3993 * The per-port interrupts get done later as ports are set up. 3994 */ 3995 mv_set_main_irq_mask(host, 0, PCI_ERR); 3996 mv_set_irq_coalescing(host, irq_coalescing_io_count, 3997 irq_coalescing_usecs); 3998 done: 3999 return rc; 4000 } 4001 4002 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 4003 { 4004 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 4005 MV_CRQB_Q_SZ, 0); 4006 if (!hpriv->crqb_pool) 4007 return -ENOMEM; 4008 4009 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 4010 MV_CRPB_Q_SZ, 0); 4011 if (!hpriv->crpb_pool) 4012 return -ENOMEM; 4013 4014 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 4015 MV_SG_TBL_SZ, 0); 4016 if (!hpriv->sg_tbl_pool) 4017 return -ENOMEM; 4018 4019 return 0; 4020 } 4021 4022 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 4023 const struct mbus_dram_target_info *dram) 4024 { 4025 int i; 4026 4027 for (i = 0; i < 4; i++) { 4028 writel(0, hpriv->base + WINDOW_CTRL(i)); 4029 writel(0, hpriv->base + WINDOW_BASE(i)); 4030 } 4031 4032 for (i = 0; i < dram->num_cs; i++) { 4033 const struct mbus_dram_window *cs = dram->cs + i; 4034 4035 writel(((cs->size - 1) & 0xffff0000) | 4036 (cs->mbus_attr << 8) | 4037 (dram->mbus_dram_target_id << 4) | 1, 4038 hpriv->base + WINDOW_CTRL(i)); 4039 writel(cs->base, hpriv->base + WINDOW_BASE(i)); 4040 } 4041 } 4042 4043 /** 4044 * mv_platform_probe - handle a positive probe of an soc Marvell 4045 * host 4046 * @pdev: platform device found 4047 * 4048 * LOCKING: 4049 * Inherited from caller. 4050 */ 4051 static int mv_platform_probe(struct platform_device *pdev) 4052 { 4053 const struct mv_sata_platform_data *mv_platform_data; 4054 const struct mbus_dram_target_info *dram; 4055 const struct ata_port_info *ppi[] = 4056 { &mv_port_info[chip_soc], NULL }; 4057 struct ata_host *host; 4058 struct mv_host_priv *hpriv; 4059 struct resource *res; 4060 int n_ports = 0, irq = 0; 4061 int rc; 4062 int port; 4063 4064 ata_print_version_once(&pdev->dev, DRV_VERSION); 4065 4066 /* 4067 * Simple resource validation .. 4068 */ 4069 if (unlikely(pdev->num_resources != 2)) { 4070 dev_err(&pdev->dev, "invalid number of resources\n"); 4071 return -EINVAL; 4072 } 4073 4074 /* 4075 * Get the register base first 4076 */ 4077 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4078 if (res == NULL) 4079 return -EINVAL; 4080 4081 /* allocate host */ 4082 if (pdev->dev.of_node) { 4083 of_property_read_u32(pdev->dev.of_node, "nr-ports", &n_ports); 4084 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 4085 } else { 4086 mv_platform_data = dev_get_platdata(&pdev->dev); 4087 n_ports = mv_platform_data->n_ports; 4088 irq = platform_get_irq(pdev, 0); 4089 } 4090 4091 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4092 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4093 4094 if (!host || !hpriv) 4095 return -ENOMEM; 4096 hpriv->port_clks = devm_kzalloc(&pdev->dev, 4097 sizeof(struct clk *) * n_ports, 4098 GFP_KERNEL); 4099 if (!hpriv->port_clks) 4100 return -ENOMEM; 4101 hpriv->port_phys = devm_kzalloc(&pdev->dev, 4102 sizeof(struct phy *) * n_ports, 4103 GFP_KERNEL); 4104 if (!hpriv->port_phys) 4105 return -ENOMEM; 4106 host->private_data = hpriv; 4107 hpriv->board_idx = chip_soc; 4108 4109 host->iomap = NULL; 4110 hpriv->base = devm_ioremap(&pdev->dev, res->start, 4111 resource_size(res)); 4112 hpriv->base -= SATAHC0_REG_BASE; 4113 4114 hpriv->clk = clk_get(&pdev->dev, NULL); 4115 if (IS_ERR(hpriv->clk)) 4116 dev_notice(&pdev->dev, "cannot get optional clkdev\n"); 4117 else 4118 clk_prepare_enable(hpriv->clk); 4119 4120 for (port = 0; port < n_ports; port++) { 4121 char port_number[16]; 4122 sprintf(port_number, "%d", port); 4123 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); 4124 if (!IS_ERR(hpriv->port_clks[port])) 4125 clk_prepare_enable(hpriv->port_clks[port]); 4126 4127 sprintf(port_number, "port%d", port); 4128 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, 4129 port_number); 4130 if (IS_ERR(hpriv->port_phys[port])) { 4131 rc = PTR_ERR(hpriv->port_phys[port]); 4132 hpriv->port_phys[port] = NULL; 4133 if (rc != -EPROBE_DEFER) 4134 dev_warn(&pdev->dev, "error getting phy %d", rc); 4135 4136 /* Cleanup only the initialized ports */ 4137 hpriv->n_ports = port; 4138 goto err; 4139 } else 4140 phy_power_on(hpriv->port_phys[port]); 4141 } 4142 4143 /* All the ports have been initialized */ 4144 hpriv->n_ports = n_ports; 4145 4146 /* 4147 * (Re-)program MBUS remapping windows if we are asked to. 4148 */ 4149 dram = mv_mbus_dram_info(); 4150 if (dram) 4151 mv_conf_mbus_windows(hpriv, dram); 4152 4153 rc = mv_create_dma_pools(hpriv, &pdev->dev); 4154 if (rc) 4155 goto err; 4156 4157 /* 4158 * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be 4159 * updated in the LP_PHY_CTL register. 4160 */ 4161 if (pdev->dev.of_node && 4162 of_device_is_compatible(pdev->dev.of_node, 4163 "marvell,armada-370-sata")) 4164 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; 4165 4166 /* initialize adapter */ 4167 rc = mv_init_host(host); 4168 if (rc) 4169 goto err; 4170 4171 dev_info(&pdev->dev, "slots %u ports %d\n", 4172 (unsigned)MV_MAX_Q_DEPTH, host->n_ports); 4173 4174 rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht); 4175 if (!rc) 4176 return 0; 4177 4178 err: 4179 if (!IS_ERR(hpriv->clk)) { 4180 clk_disable_unprepare(hpriv->clk); 4181 clk_put(hpriv->clk); 4182 } 4183 for (port = 0; port < hpriv->n_ports; port++) { 4184 if (!IS_ERR(hpriv->port_clks[port])) { 4185 clk_disable_unprepare(hpriv->port_clks[port]); 4186 clk_put(hpriv->port_clks[port]); 4187 } 4188 phy_power_off(hpriv->port_phys[port]); 4189 } 4190 4191 return rc; 4192 } 4193 4194 /* 4195 * 4196 * mv_platform_remove - unplug a platform interface 4197 * @pdev: platform device 4198 * 4199 * A platform bus SATA device has been unplugged. Perform the needed 4200 * cleanup. Also called on module unload for any active devices. 4201 */ 4202 static int mv_platform_remove(struct platform_device *pdev) 4203 { 4204 struct ata_host *host = platform_get_drvdata(pdev); 4205 struct mv_host_priv *hpriv = host->private_data; 4206 int port; 4207 ata_host_detach(host); 4208 4209 if (!IS_ERR(hpriv->clk)) { 4210 clk_disable_unprepare(hpriv->clk); 4211 clk_put(hpriv->clk); 4212 } 4213 for (port = 0; port < host->n_ports; port++) { 4214 if (!IS_ERR(hpriv->port_clks[port])) { 4215 clk_disable_unprepare(hpriv->port_clks[port]); 4216 clk_put(hpriv->port_clks[port]); 4217 } 4218 phy_power_off(hpriv->port_phys[port]); 4219 } 4220 return 0; 4221 } 4222 4223 #ifdef CONFIG_PM_SLEEP 4224 static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state) 4225 { 4226 struct ata_host *host = platform_get_drvdata(pdev); 4227 if (host) 4228 return ata_host_suspend(host, state); 4229 else 4230 return 0; 4231 } 4232 4233 static int mv_platform_resume(struct platform_device *pdev) 4234 { 4235 struct ata_host *host = platform_get_drvdata(pdev); 4236 const struct mbus_dram_target_info *dram; 4237 int ret; 4238 4239 if (host) { 4240 struct mv_host_priv *hpriv = host->private_data; 4241 4242 /* 4243 * (Re-)program MBUS remapping windows if we are asked to. 4244 */ 4245 dram = mv_mbus_dram_info(); 4246 if (dram) 4247 mv_conf_mbus_windows(hpriv, dram); 4248 4249 /* initialize adapter */ 4250 ret = mv_init_host(host); 4251 if (ret) { 4252 printk(KERN_ERR DRV_NAME ": Error during HW init\n"); 4253 return ret; 4254 } 4255 ata_host_resume(host); 4256 } 4257 4258 return 0; 4259 } 4260 #else 4261 #define mv_platform_suspend NULL 4262 #define mv_platform_resume NULL 4263 #endif 4264 4265 #ifdef CONFIG_OF 4266 static struct of_device_id mv_sata_dt_ids[] = { 4267 { .compatible = "marvell,armada-370-sata", }, 4268 { .compatible = "marvell,orion-sata", }, 4269 {}, 4270 }; 4271 MODULE_DEVICE_TABLE(of, mv_sata_dt_ids); 4272 #endif 4273 4274 static struct platform_driver mv_platform_driver = { 4275 .probe = mv_platform_probe, 4276 .remove = mv_platform_remove, 4277 .suspend = mv_platform_suspend, 4278 .resume = mv_platform_resume, 4279 .driver = { 4280 .name = DRV_NAME, 4281 .of_match_table = of_match_ptr(mv_sata_dt_ids), 4282 }, 4283 }; 4284 4285 4286 #ifdef CONFIG_PCI 4287 static int mv_pci_init_one(struct pci_dev *pdev, 4288 const struct pci_device_id *ent); 4289 #ifdef CONFIG_PM_SLEEP 4290 static int mv_pci_device_resume(struct pci_dev *pdev); 4291 #endif 4292 4293 4294 static struct pci_driver mv_pci_driver = { 4295 .name = DRV_NAME, 4296 .id_table = mv_pci_tbl, 4297 .probe = mv_pci_init_one, 4298 .remove = ata_pci_remove_one, 4299 #ifdef CONFIG_PM_SLEEP 4300 .suspend = ata_pci_device_suspend, 4301 .resume = mv_pci_device_resume, 4302 #endif 4303 4304 }; 4305 4306 /* move to PCI layer or libata core? */ 4307 static int pci_go_64(struct pci_dev *pdev) 4308 { 4309 int rc; 4310 4311 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 4312 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4313 if (rc) { 4314 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 4315 if (rc) { 4316 dev_err(&pdev->dev, 4317 "64-bit DMA enable failed\n"); 4318 return rc; 4319 } 4320 } 4321 } else { 4322 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4323 if (rc) { 4324 dev_err(&pdev->dev, "32-bit DMA enable failed\n"); 4325 return rc; 4326 } 4327 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 4328 if (rc) { 4329 dev_err(&pdev->dev, 4330 "32-bit consistent DMA enable failed\n"); 4331 return rc; 4332 } 4333 } 4334 4335 return rc; 4336 } 4337 4338 /** 4339 * mv_print_info - Dump key info to kernel log for perusal. 4340 * @host: ATA host to print info about 4341 * 4342 * FIXME: complete this. 4343 * 4344 * LOCKING: 4345 * Inherited from caller. 4346 */ 4347 static void mv_print_info(struct ata_host *host) 4348 { 4349 struct pci_dev *pdev = to_pci_dev(host->dev); 4350 struct mv_host_priv *hpriv = host->private_data; 4351 u8 scc; 4352 const char *scc_s, *gen; 4353 4354 /* Use this to determine the HW stepping of the chip so we know 4355 * what errata to workaround 4356 */ 4357 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 4358 if (scc == 0) 4359 scc_s = "SCSI"; 4360 else if (scc == 0x01) 4361 scc_s = "RAID"; 4362 else 4363 scc_s = "?"; 4364 4365 if (IS_GEN_I(hpriv)) 4366 gen = "I"; 4367 else if (IS_GEN_II(hpriv)) 4368 gen = "II"; 4369 else if (IS_GEN_IIE(hpriv)) 4370 gen = "IIE"; 4371 else 4372 gen = "?"; 4373 4374 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 4375 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 4376 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 4377 } 4378 4379 /** 4380 * mv_pci_init_one - handle a positive probe of a PCI Marvell host 4381 * @pdev: PCI device found 4382 * @ent: PCI device ID entry for the matched host 4383 * 4384 * LOCKING: 4385 * Inherited from caller. 4386 */ 4387 static int mv_pci_init_one(struct pci_dev *pdev, 4388 const struct pci_device_id *ent) 4389 { 4390 unsigned int board_idx = (unsigned int)ent->driver_data; 4391 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 4392 struct ata_host *host; 4393 struct mv_host_priv *hpriv; 4394 int n_ports, port, rc; 4395 4396 ata_print_version_once(&pdev->dev, DRV_VERSION); 4397 4398 /* allocate host */ 4399 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 4400 4401 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 4402 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 4403 if (!host || !hpriv) 4404 return -ENOMEM; 4405 host->private_data = hpriv; 4406 hpriv->n_ports = n_ports; 4407 hpriv->board_idx = board_idx; 4408 4409 /* acquire resources */ 4410 rc = pcim_enable_device(pdev); 4411 if (rc) 4412 return rc; 4413 4414 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 4415 if (rc == -EBUSY) 4416 pcim_pin_device(pdev); 4417 if (rc) 4418 return rc; 4419 host->iomap = pcim_iomap_table(pdev); 4420 hpriv->base = host->iomap[MV_PRIMARY_BAR]; 4421 4422 rc = pci_go_64(pdev); 4423 if (rc) 4424 return rc; 4425 4426 rc = mv_create_dma_pools(hpriv, &pdev->dev); 4427 if (rc) 4428 return rc; 4429 4430 for (port = 0; port < host->n_ports; port++) { 4431 struct ata_port *ap = host->ports[port]; 4432 void __iomem *port_mmio = mv_port_base(hpriv->base, port); 4433 unsigned int offset = port_mmio - hpriv->base; 4434 4435 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 4436 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 4437 } 4438 4439 /* initialize adapter */ 4440 rc = mv_init_host(host); 4441 if (rc) 4442 return rc; 4443 4444 /* Enable message-switched interrupts, if requested */ 4445 if (msi && pci_enable_msi(pdev) == 0) 4446 hpriv->hp_flags |= MV_HP_FLAG_MSI; 4447 4448 mv_dump_pci_cfg(pdev, 0x68); 4449 mv_print_info(host); 4450 4451 pci_set_master(pdev); 4452 pci_try_set_mwi(pdev); 4453 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 4454 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 4455 } 4456 4457 #ifdef CONFIG_PM_SLEEP 4458 static int mv_pci_device_resume(struct pci_dev *pdev) 4459 { 4460 struct ata_host *host = pci_get_drvdata(pdev); 4461 int rc; 4462 4463 rc = ata_pci_device_do_resume(pdev); 4464 if (rc) 4465 return rc; 4466 4467 /* initialize adapter */ 4468 rc = mv_init_host(host); 4469 if (rc) 4470 return rc; 4471 4472 ata_host_resume(host); 4473 4474 return 0; 4475 } 4476 #endif 4477 #endif 4478 4479 static int __init mv_init(void) 4480 { 4481 int rc = -ENODEV; 4482 #ifdef CONFIG_PCI 4483 rc = pci_register_driver(&mv_pci_driver); 4484 if (rc < 0) 4485 return rc; 4486 #endif 4487 rc = platform_driver_register(&mv_platform_driver); 4488 4489 #ifdef CONFIG_PCI 4490 if (rc < 0) 4491 pci_unregister_driver(&mv_pci_driver); 4492 #endif 4493 return rc; 4494 } 4495 4496 static void __exit mv_exit(void) 4497 { 4498 #ifdef CONFIG_PCI 4499 pci_unregister_driver(&mv_pci_driver); 4500 #endif 4501 platform_driver_unregister(&mv_platform_driver); 4502 } 4503 4504 MODULE_AUTHOR("Brett Russ"); 4505 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 4506 MODULE_LICENSE("GPL"); 4507 MODULE_DEVICE_TABLE(pci, mv_pci_tbl); 4508 MODULE_VERSION(DRV_VERSION); 4509 MODULE_ALIAS("platform:" DRV_NAME); 4510 4511 module_init(mv_init); 4512 module_exit(mv_exit); 4513