1 /* 2 * sata_mv.c - Marvell SATA support 3 * 4 * Copyright 2008: Marvell Corporation, all rights reserved. 5 * Copyright 2005: EMC Corporation, all rights reserved. 6 * Copyright 2005 Red Hat, Inc. All rights reserved. 7 * 8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; version 2 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 */ 24 25 /* 26 * sata_mv TODO list: 27 * 28 * --> Errata workaround for NCQ device errors. 29 * 30 * --> More errata workarounds for PCI-X. 31 * 32 * --> Complete a full errata audit for all chipsets to identify others. 33 * 34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it). 35 * 36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI). 37 * 38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead. 39 * 40 * --> Develop a low-power-consumption strategy, and implement it. 41 * 42 * --> [Experiment, low priority] Investigate interrupt coalescing. 43 * Quite often, especially with PCI Message Signalled Interrupts (MSI), 44 * the overhead reduced by interrupt mitigation is quite often not 45 * worth the latency cost. 46 * 47 * --> [Experiment, Marvell value added] Is it possible to use target 48 * mode to cross-connect two Linux boxes with Marvell cards? If so, 49 * creating LibATA target mode support would be very interesting. 50 * 51 * Target mode, for those without docs, is the ability to directly 52 * connect two SATA ports. 53 */ 54 55 #include <linux/kernel.h> 56 #include <linux/module.h> 57 #include <linux/pci.h> 58 #include <linux/init.h> 59 #include <linux/blkdev.h> 60 #include <linux/delay.h> 61 #include <linux/interrupt.h> 62 #include <linux/dmapool.h> 63 #include <linux/dma-mapping.h> 64 #include <linux/device.h> 65 #include <linux/platform_device.h> 66 #include <linux/ata_platform.h> 67 #include <linux/mbus.h> 68 #include <linux/bitops.h> 69 #include <scsi/scsi_host.h> 70 #include <scsi/scsi_cmnd.h> 71 #include <scsi/scsi_device.h> 72 #include <linux/libata.h> 73 74 #define DRV_NAME "sata_mv" 75 #define DRV_VERSION "1.24" 76 77 enum { 78 /* BAR's are enumerated in terms of pci_resource_start() terms */ 79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ 80 MV_IO_BAR = 2, /* offset 0x18: IO space */ 81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ 82 83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ 84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ 85 86 MV_PCI_REG_BASE = 0, 87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ 88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08), 89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88), 90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c), 91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc), 92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0), 93 94 MV_SATAHC0_REG_BASE = 0x20000, 95 MV_FLASH_CTL_OFS = 0x1046c, 96 MV_GPIO_PORT_CTL_OFS = 0x104f0, 97 MV_RESET_CFG_OFS = 0x180d8, 98 99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, 100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, 101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ 102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, 103 104 MV_MAX_Q_DEPTH = 32, 105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, 106 107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB 108 * CRPB needs alignment on a 256B boundary. Size == 256B 109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B 110 */ 111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), 112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), 113 MV_MAX_SG_CT = 256, 114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), 115 116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ 117 MV_PORT_HC_SHIFT = 2, 118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ 119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ 120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ 121 122 /* Host Flags */ 123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ 124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ 125 126 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 127 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | 128 ATA_FLAG_PIO_POLLING, 129 130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, 131 132 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 133 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 134 ATA_FLAG_NCQ | ATA_FLAG_AN, 135 136 CRQB_FLAG_READ = (1 << 0), 137 CRQB_TAG_SHIFT = 1, 138 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ 139 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ 140 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ 141 CRQB_CMD_ADDR_SHIFT = 8, 142 CRQB_CMD_CS = (0x2 << 11), 143 CRQB_CMD_LAST = (1 << 15), 144 145 CRPB_FLAG_STATUS_SHIFT = 8, 146 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ 147 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ 148 149 EPRD_FLAG_END_OF_TBL = (1 << 31), 150 151 /* PCI interface registers */ 152 153 PCI_COMMAND_OFS = 0xc00, 154 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ 155 156 PCI_MAIN_CMD_STS_OFS = 0xd30, 157 STOP_PCI_MASTER = (1 << 2), 158 PCI_MASTER_EMPTY = (1 << 3), 159 GLOB_SFT_RST = (1 << 4), 160 161 MV_PCI_MODE_OFS = 0xd00, 162 MV_PCI_MODE_MASK = 0x30, 163 164 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, 165 MV_PCI_DISC_TIMER = 0xd04, 166 MV_PCI_MSI_TRIGGER = 0xc38, 167 MV_PCI_SERR_MASK = 0xc28, 168 MV_PCI_XBAR_TMOUT_OFS = 0x1d04, 169 MV_PCI_ERR_LOW_ADDRESS = 0x1d40, 170 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, 171 MV_PCI_ERR_ATTRIBUTE = 0x1d48, 172 MV_PCI_ERR_COMMAND = 0x1d50, 173 174 PCI_IRQ_CAUSE_OFS = 0x1d58, 175 PCI_IRQ_MASK_OFS = 0x1d5c, 176 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ 177 178 PCIE_IRQ_CAUSE_OFS = 0x1900, 179 PCIE_IRQ_MASK_OFS = 0x1910, 180 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ 181 182 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ 183 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, 184 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64, 185 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020, 186 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024, 187 ERR_IRQ = (1 << 0), /* shift by port # */ 188 DONE_IRQ = (1 << 1), /* shift by port # */ 189 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ 190 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ 191 PCI_ERR = (1 << 18), 192 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ 193 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ 194 PORTS_0_3_COAL_DONE = (1 << 8), 195 PORTS_4_7_COAL_DONE = (1 << 17), 196 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ 197 GPIO_INT = (1 << 22), 198 SELF_INT = (1 << 23), 199 TWSI_INT = (1 << 24), 200 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ 201 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ 202 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ 203 204 /* SATAHC registers */ 205 HC_CFG_OFS = 0, 206 207 HC_IRQ_CAUSE_OFS = 0x14, 208 DMA_IRQ = (1 << 0), /* shift by port # */ 209 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ 210 DEV_IRQ = (1 << 8), /* shift by port # */ 211 212 /* Shadow block registers */ 213 SHD_BLK_OFS = 0x100, 214 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ 215 216 /* SATA registers */ 217 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ 218 SATA_ACTIVE_OFS = 0x350, 219 SATA_FIS_IRQ_CAUSE_OFS = 0x364, 220 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */ 221 222 LTMODE_OFS = 0x30c, 223 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ 224 225 PHY_MODE3 = 0x310, 226 PHY_MODE4 = 0x314, 227 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ 228 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ 229 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ 230 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ 231 232 PHY_MODE2 = 0x330, 233 SATA_IFCTL_OFS = 0x344, 234 SATA_TESTCTL_OFS = 0x348, 235 SATA_IFSTAT_OFS = 0x34c, 236 VENDOR_UNIQUE_FIS_OFS = 0x35c, 237 238 FISCFG_OFS = 0x360, 239 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ 240 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ 241 242 MV5_PHY_MODE = 0x74, 243 MV5_LTMODE_OFS = 0x30, 244 MV5_PHY_CTL_OFS = 0x0C, 245 SATA_INTERFACE_CFG_OFS = 0x050, 246 247 MV_M2_PREAMP_MASK = 0x7e0, 248 249 /* Port registers */ 250 EDMA_CFG_OFS = 0, 251 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ 252 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ 253 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ 254 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ 255 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ 256 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ 257 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ 258 259 EDMA_ERR_IRQ_CAUSE_OFS = 0x8, 260 EDMA_ERR_IRQ_MASK_OFS = 0xc, 261 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ 262 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ 263 EDMA_ERR_DEV = (1 << 2), /* device error */ 264 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ 265 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ 266 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ 267 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ 268 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ 269 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ 270 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ 271 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ 272 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ 273 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ 274 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ 275 276 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ 277 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ 278 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ 279 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ 280 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ 281 282 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ 283 284 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ 285 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ 286 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ 287 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ 288 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ 289 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ 290 291 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ 292 293 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ 294 EDMA_ERR_OVERRUN_5 = (1 << 5), 295 EDMA_ERR_UNDERRUN_5 = (1 << 6), 296 297 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | 298 EDMA_ERR_LNK_CTRL_RX_1 | 299 EDMA_ERR_LNK_CTRL_RX_3 | 300 EDMA_ERR_LNK_CTRL_TX, 301 302 EDMA_EH_FREEZE = EDMA_ERR_D_PAR | 303 EDMA_ERR_PRD_PAR | 304 EDMA_ERR_DEV_DCON | 305 EDMA_ERR_DEV_CON | 306 EDMA_ERR_SERR | 307 EDMA_ERR_SELF_DIS | 308 EDMA_ERR_CRQB_PAR | 309 EDMA_ERR_CRPB_PAR | 310 EDMA_ERR_INTRL_PAR | 311 EDMA_ERR_IORDY | 312 EDMA_ERR_LNK_CTRL_RX_2 | 313 EDMA_ERR_LNK_DATA_RX | 314 EDMA_ERR_LNK_DATA_TX | 315 EDMA_ERR_TRANS_PROTO, 316 317 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | 318 EDMA_ERR_PRD_PAR | 319 EDMA_ERR_DEV_DCON | 320 EDMA_ERR_DEV_CON | 321 EDMA_ERR_OVERRUN_5 | 322 EDMA_ERR_UNDERRUN_5 | 323 EDMA_ERR_SELF_DIS_5 | 324 EDMA_ERR_CRQB_PAR | 325 EDMA_ERR_CRPB_PAR | 326 EDMA_ERR_INTRL_PAR | 327 EDMA_ERR_IORDY, 328 329 EDMA_REQ_Q_BASE_HI_OFS = 0x10, 330 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ 331 332 EDMA_REQ_Q_OUT_PTR_OFS = 0x18, 333 EDMA_REQ_Q_PTR_SHIFT = 5, 334 335 EDMA_RSP_Q_BASE_HI_OFS = 0x1c, 336 EDMA_RSP_Q_IN_PTR_OFS = 0x20, 337 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ 338 EDMA_RSP_Q_PTR_SHIFT = 3, 339 340 EDMA_CMD_OFS = 0x28, /* EDMA command register */ 341 EDMA_EN = (1 << 0), /* enable EDMA */ 342 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ 343 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ 344 345 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */ 346 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ 347 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ 348 349 EDMA_IORDY_TMOUT_OFS = 0x34, 350 EDMA_ARB_CFG_OFS = 0x38, 351 352 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ 353 354 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */ 355 356 /* Host private flags (hp_flags) */ 357 MV_HP_FLAG_MSI = (1 << 0), 358 MV_HP_ERRATA_50XXB0 = (1 << 1), 359 MV_HP_ERRATA_50XXB2 = (1 << 2), 360 MV_HP_ERRATA_60X1B2 = (1 << 3), 361 MV_HP_ERRATA_60X1C0 = (1 << 4), 362 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ 363 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ 364 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ 365 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ 366 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 367 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 368 369 /* Port private flags (pp_flags) */ 370 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 371 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ 372 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ 373 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ 374 }; 375 376 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) 377 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) 378 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) 379 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) 380 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) 381 382 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) 383 #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) 384 385 enum { 386 /* DMA boundary 0xffff is required by the s/g splitting 387 * we need on /length/ in mv_fill-sg(). 388 */ 389 MV_DMA_BOUNDARY = 0xffffU, 390 391 /* mask of register bits containing lower 32 bits 392 * of EDMA request queue DMA address 393 */ 394 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, 395 396 /* ditto, for response queue */ 397 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, 398 }; 399 400 enum chip_type { 401 chip_504x, 402 chip_508x, 403 chip_5080, 404 chip_604x, 405 chip_608x, 406 chip_6042, 407 chip_7042, 408 chip_soc, 409 }; 410 411 /* Command ReQuest Block: 32B */ 412 struct mv_crqb { 413 __le32 sg_addr; 414 __le32 sg_addr_hi; 415 __le16 ctrl_flags; 416 __le16 ata_cmd[11]; 417 }; 418 419 struct mv_crqb_iie { 420 __le32 addr; 421 __le32 addr_hi; 422 __le32 flags; 423 __le32 len; 424 __le32 ata_cmd[4]; 425 }; 426 427 /* Command ResPonse Block: 8B */ 428 struct mv_crpb { 429 __le16 id; 430 __le16 flags; 431 __le32 tmstmp; 432 }; 433 434 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ 435 struct mv_sg { 436 __le32 addr; 437 __le32 flags_size; 438 __le32 addr_hi; 439 __le32 reserved; 440 }; 441 442 struct mv_port_priv { 443 struct mv_crqb *crqb; 444 dma_addr_t crqb_dma; 445 struct mv_crpb *crpb; 446 dma_addr_t crpb_dma; 447 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; 448 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; 449 450 unsigned int req_idx; 451 unsigned int resp_idx; 452 453 u32 pp_flags; 454 unsigned int delayed_eh_pmp_map; 455 }; 456 457 struct mv_port_signal { 458 u32 amps; 459 u32 pre; 460 }; 461 462 struct mv_host_priv { 463 u32 hp_flags; 464 u32 main_irq_mask; 465 struct mv_port_signal signal[8]; 466 const struct mv_hw_ops *ops; 467 int n_ports; 468 void __iomem *base; 469 void __iomem *main_irq_cause_addr; 470 void __iomem *main_irq_mask_addr; 471 u32 irq_cause_ofs; 472 u32 irq_mask_ofs; 473 u32 unmask_all_irqs; 474 /* 475 * These consistent DMA memory pools give us guaranteed 476 * alignment for hardware-accessed data structures, 477 * and less memory waste in accomplishing the alignment. 478 */ 479 struct dma_pool *crqb_pool; 480 struct dma_pool *crpb_pool; 481 struct dma_pool *sg_tbl_pool; 482 }; 483 484 struct mv_hw_ops { 485 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, 486 unsigned int port); 487 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); 488 void (*read_preamp)(struct mv_host_priv *hpriv, int idx, 489 void __iomem *mmio); 490 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, 491 unsigned int n_hc); 492 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); 493 void (*reset_bus)(struct ata_host *host, void __iomem *mmio); 494 }; 495 496 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 497 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 498 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); 499 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); 500 static int mv_port_start(struct ata_port *ap); 501 static void mv_port_stop(struct ata_port *ap); 502 static int mv_qc_defer(struct ata_queued_cmd *qc); 503 static void mv_qc_prep(struct ata_queued_cmd *qc); 504 static void mv_qc_prep_iie(struct ata_queued_cmd *qc); 505 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 506 static int mv_hardreset(struct ata_link *link, unsigned int *class, 507 unsigned long deadline); 508 static void mv_eh_freeze(struct ata_port *ap); 509 static void mv_eh_thaw(struct ata_port *ap); 510 static void mv6_dev_config(struct ata_device *dev); 511 512 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 513 unsigned int port); 514 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 515 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 516 void __iomem *mmio); 517 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 518 unsigned int n_hc); 519 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 520 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); 521 522 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 523 unsigned int port); 524 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); 525 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 526 void __iomem *mmio); 527 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 528 unsigned int n_hc); 529 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); 530 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 531 void __iomem *mmio); 532 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 533 void __iomem *mmio); 534 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 535 void __iomem *mmio, unsigned int n_hc); 536 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 537 void __iomem *mmio); 538 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); 539 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); 540 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 541 unsigned int port_no); 542 static int mv_stop_edma(struct ata_port *ap); 543 static int mv_stop_edma_engine(void __iomem *port_mmio); 544 static void mv_edma_cfg(struct ata_port *ap, int want_ncq); 545 546 static void mv_pmp_select(struct ata_port *ap, int pmp); 547 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 548 unsigned long deadline); 549 static int mv_softreset(struct ata_link *link, unsigned int *class, 550 unsigned long deadline); 551 static void mv_pmp_error_handler(struct ata_port *ap); 552 static void mv_process_crpb_entries(struct ata_port *ap, 553 struct mv_port_priv *pp); 554 555 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below 556 * because we have to allow room for worst case splitting of 557 * PRDs for 64K boundaries in mv_fill_sg(). 558 */ 559 static struct scsi_host_template mv5_sht = { 560 ATA_BASE_SHT(DRV_NAME), 561 .sg_tablesize = MV_MAX_SG_CT / 2, 562 .dma_boundary = MV_DMA_BOUNDARY, 563 }; 564 565 static struct scsi_host_template mv6_sht = { 566 ATA_NCQ_SHT(DRV_NAME), 567 .can_queue = MV_MAX_Q_DEPTH - 1, 568 .sg_tablesize = MV_MAX_SG_CT / 2, 569 .dma_boundary = MV_DMA_BOUNDARY, 570 }; 571 572 static struct ata_port_operations mv5_ops = { 573 .inherits = &ata_sff_port_ops, 574 575 .qc_defer = mv_qc_defer, 576 .qc_prep = mv_qc_prep, 577 .qc_issue = mv_qc_issue, 578 579 .freeze = mv_eh_freeze, 580 .thaw = mv_eh_thaw, 581 .hardreset = mv_hardreset, 582 .error_handler = ata_std_error_handler, /* avoid SFF EH */ 583 .post_internal_cmd = ATA_OP_NULL, 584 585 .scr_read = mv5_scr_read, 586 .scr_write = mv5_scr_write, 587 588 .port_start = mv_port_start, 589 .port_stop = mv_port_stop, 590 }; 591 592 static struct ata_port_operations mv6_ops = { 593 .inherits = &mv5_ops, 594 .dev_config = mv6_dev_config, 595 .scr_read = mv_scr_read, 596 .scr_write = mv_scr_write, 597 598 .pmp_hardreset = mv_pmp_hardreset, 599 .pmp_softreset = mv_softreset, 600 .softreset = mv_softreset, 601 .error_handler = mv_pmp_error_handler, 602 }; 603 604 static struct ata_port_operations mv_iie_ops = { 605 .inherits = &mv6_ops, 606 .dev_config = ATA_OP_NULL, 607 .qc_prep = mv_qc_prep_iie, 608 }; 609 610 static const struct ata_port_info mv_port_info[] = { 611 { /* chip_504x */ 612 .flags = MV_COMMON_FLAGS, 613 .pio_mask = 0x1f, /* pio0-4 */ 614 .udma_mask = ATA_UDMA6, 615 .port_ops = &mv5_ops, 616 }, 617 { /* chip_508x */ 618 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 619 .pio_mask = 0x1f, /* pio0-4 */ 620 .udma_mask = ATA_UDMA6, 621 .port_ops = &mv5_ops, 622 }, 623 { /* chip_5080 */ 624 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC, 625 .pio_mask = 0x1f, /* pio0-4 */ 626 .udma_mask = ATA_UDMA6, 627 .port_ops = &mv5_ops, 628 }, 629 { /* chip_604x */ 630 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 631 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 632 ATA_FLAG_NCQ, 633 .pio_mask = 0x1f, /* pio0-4 */ 634 .udma_mask = ATA_UDMA6, 635 .port_ops = &mv6_ops, 636 }, 637 { /* chip_608x */ 638 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS | 639 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA | 640 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC, 641 .pio_mask = 0x1f, /* pio0-4 */ 642 .udma_mask = ATA_UDMA6, 643 .port_ops = &mv6_ops, 644 }, 645 { /* chip_6042 */ 646 .flags = MV_GENIIE_FLAGS, 647 .pio_mask = 0x1f, /* pio0-4 */ 648 .udma_mask = ATA_UDMA6, 649 .port_ops = &mv_iie_ops, 650 }, 651 { /* chip_7042 */ 652 .flags = MV_GENIIE_FLAGS, 653 .pio_mask = 0x1f, /* pio0-4 */ 654 .udma_mask = ATA_UDMA6, 655 .port_ops = &mv_iie_ops, 656 }, 657 { /* chip_soc */ 658 .flags = MV_GENIIE_FLAGS, 659 .pio_mask = 0x1f, /* pio0-4 */ 660 .udma_mask = ATA_UDMA6, 661 .port_ops = &mv_iie_ops, 662 }, 663 }; 664 665 static const struct pci_device_id mv_pci_tbl[] = { 666 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, 667 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, 668 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, 669 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, 670 /* RocketRAID 1720/174x have different identifiers */ 671 { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, 672 { PCI_VDEVICE(TTI, 0x1740), chip_508x }, 673 { PCI_VDEVICE(TTI, 0x1742), chip_508x }, 674 675 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, 676 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, 677 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, 678 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, 679 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, 680 681 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, 682 683 /* Adaptec 1430SA */ 684 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, 685 686 /* Marvell 7042 support */ 687 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, 688 689 /* Highpoint RocketRAID PCIe series */ 690 { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, 691 { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, 692 693 { } /* terminate list */ 694 }; 695 696 static const struct mv_hw_ops mv5xxx_ops = { 697 .phy_errata = mv5_phy_errata, 698 .enable_leds = mv5_enable_leds, 699 .read_preamp = mv5_read_preamp, 700 .reset_hc = mv5_reset_hc, 701 .reset_flash = mv5_reset_flash, 702 .reset_bus = mv5_reset_bus, 703 }; 704 705 static const struct mv_hw_ops mv6xxx_ops = { 706 .phy_errata = mv6_phy_errata, 707 .enable_leds = mv6_enable_leds, 708 .read_preamp = mv6_read_preamp, 709 .reset_hc = mv6_reset_hc, 710 .reset_flash = mv6_reset_flash, 711 .reset_bus = mv_reset_pci_bus, 712 }; 713 714 static const struct mv_hw_ops mv_soc_ops = { 715 .phy_errata = mv6_phy_errata, 716 .enable_leds = mv_soc_enable_leds, 717 .read_preamp = mv_soc_read_preamp, 718 .reset_hc = mv_soc_reset_hc, 719 .reset_flash = mv_soc_reset_flash, 720 .reset_bus = mv_soc_reset_bus, 721 }; 722 723 /* 724 * Functions 725 */ 726 727 static inline void writelfl(unsigned long data, void __iomem *addr) 728 { 729 writel(data, addr); 730 (void) readl(addr); /* flush to avoid PCI posted write */ 731 } 732 733 static inline unsigned int mv_hc_from_port(unsigned int port) 734 { 735 return port >> MV_PORT_HC_SHIFT; 736 } 737 738 static inline unsigned int mv_hardport_from_port(unsigned int port) 739 { 740 return port & MV_PORT_MASK; 741 } 742 743 /* 744 * Consolidate some rather tricky bit shift calculations. 745 * This is hot-path stuff, so not a function. 746 * Simple code, with two return values, so macro rather than inline. 747 * 748 * port is the sole input, in range 0..7. 749 * shift is one output, for use with main_irq_cause / main_irq_mask registers. 750 * hardport is the other output, in range 0..3. 751 * 752 * Note that port and hardport may be the same variable in some cases. 753 */ 754 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ 755 { \ 756 shift = mv_hc_from_port(port) * HC_SHIFT; \ 757 hardport = mv_hardport_from_port(port); \ 758 shift += hardport * 2; \ 759 } 760 761 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) 762 { 763 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); 764 } 765 766 static inline void __iomem *mv_hc_base_from_port(void __iomem *base, 767 unsigned int port) 768 { 769 return mv_hc_base(base, mv_hc_from_port(port)); 770 } 771 772 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) 773 { 774 return mv_hc_base_from_port(base, port) + 775 MV_SATAHC_ARBTR_REG_SZ + 776 (mv_hardport_from_port(port) * MV_PORT_REG_SZ); 777 } 778 779 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) 780 { 781 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); 782 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; 783 784 return hc_mmio + ofs; 785 } 786 787 static inline void __iomem *mv_host_base(struct ata_host *host) 788 { 789 struct mv_host_priv *hpriv = host->private_data; 790 return hpriv->base; 791 } 792 793 static inline void __iomem *mv_ap_base(struct ata_port *ap) 794 { 795 return mv_port_base(mv_host_base(ap->host), ap->port_no); 796 } 797 798 static inline int mv_get_hc_count(unsigned long port_flags) 799 { 800 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); 801 } 802 803 static void mv_set_edma_ptrs(void __iomem *port_mmio, 804 struct mv_host_priv *hpriv, 805 struct mv_port_priv *pp) 806 { 807 u32 index; 808 809 /* 810 * initialize request queue 811 */ 812 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 813 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 814 815 WARN_ON(pp->crqb_dma & 0x3ff); 816 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); 817 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, 818 port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 819 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); 820 821 /* 822 * initialize response queue 823 */ 824 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ 825 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; 826 827 WARN_ON(pp->crpb_dma & 0xff); 828 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); 829 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); 830 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, 831 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 832 } 833 834 static void mv_set_main_irq_mask(struct ata_host *host, 835 u32 disable_bits, u32 enable_bits) 836 { 837 struct mv_host_priv *hpriv = host->private_data; 838 u32 old_mask, new_mask; 839 840 old_mask = hpriv->main_irq_mask; 841 new_mask = (old_mask & ~disable_bits) | enable_bits; 842 if (new_mask != old_mask) { 843 hpriv->main_irq_mask = new_mask; 844 writelfl(new_mask, hpriv->main_irq_mask_addr); 845 } 846 } 847 848 static void mv_enable_port_irqs(struct ata_port *ap, 849 unsigned int port_bits) 850 { 851 unsigned int shift, hardport, port = ap->port_no; 852 u32 disable_bits, enable_bits; 853 854 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 855 856 disable_bits = (DONE_IRQ | ERR_IRQ) << shift; 857 enable_bits = port_bits << shift; 858 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); 859 } 860 861 /** 862 * mv_start_dma - Enable eDMA engine 863 * @base: port base address 864 * @pp: port private data 865 * 866 * Verify the local cache of the eDMA state is accurate with a 867 * WARN_ON. 868 * 869 * LOCKING: 870 * Inherited from caller. 871 */ 872 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio, 873 struct mv_port_priv *pp, u8 protocol) 874 { 875 int want_ncq = (protocol == ATA_PROT_NCQ); 876 877 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { 878 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); 879 if (want_ncq != using_ncq) 880 mv_stop_edma(ap); 881 } 882 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { 883 struct mv_host_priv *hpriv = ap->host->private_data; 884 int hardport = mv_hardport_from_port(ap->port_no); 885 void __iomem *hc_mmio = mv_hc_base_from_port( 886 mv_host_base(ap->host), hardport); 887 u32 hc_irq_cause, ipending; 888 889 /* clear EDMA event indicators, if any */ 890 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 891 892 /* clear EDMA interrupt indicator, if any */ 893 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 894 ipending = (DEV_IRQ | DMA_IRQ) << hardport; 895 if (hc_irq_cause & ipending) { 896 writelfl(hc_irq_cause & ~ipending, 897 hc_mmio + HC_IRQ_CAUSE_OFS); 898 } 899 900 mv_edma_cfg(ap, want_ncq); 901 902 /* clear FIS IRQ Cause */ 903 if (IS_GEN_IIE(hpriv)) 904 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 905 906 mv_set_edma_ptrs(port_mmio, hpriv, pp); 907 mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ); 908 909 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); 910 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; 911 } 912 } 913 914 static void mv_wait_for_edma_empty_idle(struct ata_port *ap) 915 { 916 void __iomem *port_mmio = mv_ap_base(ap); 917 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); 918 const int per_loop = 5, timeout = (15 * 1000 / per_loop); 919 int i; 920 921 /* 922 * Wait for the EDMA engine to finish transactions in progress. 923 * No idea what a good "timeout" value might be, but measurements 924 * indicate that it often requires hundreds of microseconds 925 * with two drives in-use. So we use the 15msec value above 926 * as a rough guess at what even more drives might require. 927 */ 928 for (i = 0; i < timeout; ++i) { 929 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS); 930 if ((edma_stat & empty_idle) == empty_idle) 931 break; 932 udelay(per_loop); 933 } 934 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ 935 } 936 937 /** 938 * mv_stop_edma_engine - Disable eDMA engine 939 * @port_mmio: io base address 940 * 941 * LOCKING: 942 * Inherited from caller. 943 */ 944 static int mv_stop_edma_engine(void __iomem *port_mmio) 945 { 946 int i; 947 948 /* Disable eDMA. The disable bit auto clears. */ 949 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); 950 951 /* Wait for the chip to confirm eDMA is off. */ 952 for (i = 10000; i > 0; i--) { 953 u32 reg = readl(port_mmio + EDMA_CMD_OFS); 954 if (!(reg & EDMA_EN)) 955 return 0; 956 udelay(10); 957 } 958 return -EIO; 959 } 960 961 static int mv_stop_edma(struct ata_port *ap) 962 { 963 void __iomem *port_mmio = mv_ap_base(ap); 964 struct mv_port_priv *pp = ap->private_data; 965 966 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 967 return 0; 968 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 969 mv_wait_for_edma_empty_idle(ap); 970 if (mv_stop_edma_engine(port_mmio)) { 971 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); 972 return -EIO; 973 } 974 return 0; 975 } 976 977 #ifdef ATA_DEBUG 978 static void mv_dump_mem(void __iomem *start, unsigned bytes) 979 { 980 int b, w; 981 for (b = 0; b < bytes; ) { 982 DPRINTK("%p: ", start + b); 983 for (w = 0; b < bytes && w < 4; w++) { 984 printk("%08x ", readl(start + b)); 985 b += sizeof(u32); 986 } 987 printk("\n"); 988 } 989 } 990 #endif 991 992 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) 993 { 994 #ifdef ATA_DEBUG 995 int b, w; 996 u32 dw; 997 for (b = 0; b < bytes; ) { 998 DPRINTK("%02x: ", b); 999 for (w = 0; b < bytes && w < 4; w++) { 1000 (void) pci_read_config_dword(pdev, b, &dw); 1001 printk("%08x ", dw); 1002 b += sizeof(u32); 1003 } 1004 printk("\n"); 1005 } 1006 #endif 1007 } 1008 static void mv_dump_all_regs(void __iomem *mmio_base, int port, 1009 struct pci_dev *pdev) 1010 { 1011 #ifdef ATA_DEBUG 1012 void __iomem *hc_base = mv_hc_base(mmio_base, 1013 port >> MV_PORT_HC_SHIFT); 1014 void __iomem *port_base; 1015 int start_port, num_ports, p, start_hc, num_hcs, hc; 1016 1017 if (0 > port) { 1018 start_hc = start_port = 0; 1019 num_ports = 8; /* shld be benign for 4 port devs */ 1020 num_hcs = 2; 1021 } else { 1022 start_hc = port >> MV_PORT_HC_SHIFT; 1023 start_port = port; 1024 num_ports = num_hcs = 1; 1025 } 1026 DPRINTK("All registers for port(s) %u-%u:\n", start_port, 1027 num_ports > 1 ? num_ports - 1 : start_port); 1028 1029 if (NULL != pdev) { 1030 DPRINTK("PCI config space regs:\n"); 1031 mv_dump_pci_cfg(pdev, 0x68); 1032 } 1033 DPRINTK("PCI regs:\n"); 1034 mv_dump_mem(mmio_base+0xc00, 0x3c); 1035 mv_dump_mem(mmio_base+0xd00, 0x34); 1036 mv_dump_mem(mmio_base+0xf00, 0x4); 1037 mv_dump_mem(mmio_base+0x1d00, 0x6c); 1038 for (hc = start_hc; hc < start_hc + num_hcs; hc++) { 1039 hc_base = mv_hc_base(mmio_base, hc); 1040 DPRINTK("HC regs (HC %i):\n", hc); 1041 mv_dump_mem(hc_base, 0x1c); 1042 } 1043 for (p = start_port; p < start_port + num_ports; p++) { 1044 port_base = mv_port_base(mmio_base, p); 1045 DPRINTK("EDMA regs (port %i):\n", p); 1046 mv_dump_mem(port_base, 0x54); 1047 DPRINTK("SATA regs (port %i):\n", p); 1048 mv_dump_mem(port_base+0x300, 0x60); 1049 } 1050 #endif 1051 } 1052 1053 static unsigned int mv_scr_offset(unsigned int sc_reg_in) 1054 { 1055 unsigned int ofs; 1056 1057 switch (sc_reg_in) { 1058 case SCR_STATUS: 1059 case SCR_CONTROL: 1060 case SCR_ERROR: 1061 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); 1062 break; 1063 case SCR_ACTIVE: 1064 ofs = SATA_ACTIVE_OFS; /* active is not with the others */ 1065 break; 1066 default: 1067 ofs = 0xffffffffU; 1068 break; 1069 } 1070 return ofs; 1071 } 1072 1073 static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 1074 { 1075 unsigned int ofs = mv_scr_offset(sc_reg_in); 1076 1077 if (ofs != 0xffffffffU) { 1078 *val = readl(mv_ap_base(link->ap) + ofs); 1079 return 0; 1080 } else 1081 return -EINVAL; 1082 } 1083 1084 static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 1085 { 1086 unsigned int ofs = mv_scr_offset(sc_reg_in); 1087 1088 if (ofs != 0xffffffffU) { 1089 writelfl(val, mv_ap_base(link->ap) + ofs); 1090 return 0; 1091 } else 1092 return -EINVAL; 1093 } 1094 1095 static void mv6_dev_config(struct ata_device *adev) 1096 { 1097 /* 1098 * Deal with Gen-II ("mv6") hardware quirks/restrictions: 1099 * 1100 * Gen-II does not support NCQ over a port multiplier 1101 * (no FIS-based switching). 1102 * 1103 * We don't have hob_nsect when doing NCQ commands on Gen-II. 1104 * See mv_qc_prep() for more info. 1105 */ 1106 if (adev->flags & ATA_DFLAG_NCQ) { 1107 if (sata_pmp_attached(adev->link->ap)) { 1108 adev->flags &= ~ATA_DFLAG_NCQ; 1109 ata_dev_printk(adev, KERN_INFO, 1110 "NCQ disabled for command-based switching\n"); 1111 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) { 1112 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS; 1113 ata_dev_printk(adev, KERN_INFO, 1114 "max_sectors limited to %u for NCQ\n", 1115 adev->max_sectors); 1116 } 1117 } 1118 } 1119 1120 static int mv_qc_defer(struct ata_queued_cmd *qc) 1121 { 1122 struct ata_link *link = qc->dev->link; 1123 struct ata_port *ap = link->ap; 1124 struct mv_port_priv *pp = ap->private_data; 1125 1126 /* 1127 * Don't allow new commands if we're in a delayed EH state 1128 * for NCQ and/or FIS-based switching. 1129 */ 1130 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 1131 return ATA_DEFER_PORT; 1132 /* 1133 * If the port is completely idle, then allow the new qc. 1134 */ 1135 if (ap->nr_active_links == 0) 1136 return 0; 1137 1138 /* 1139 * The port is operating in host queuing mode (EDMA) with NCQ 1140 * enabled, allow multiple NCQ commands. EDMA also allows 1141 * queueing multiple DMA commands but libata core currently 1142 * doesn't allow it. 1143 */ 1144 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && 1145 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol)) 1146 return 0; 1147 1148 return ATA_DEFER_PORT; 1149 } 1150 1151 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs) 1152 { 1153 u32 new_fiscfg, old_fiscfg; 1154 u32 new_ltmode, old_ltmode; 1155 u32 new_haltcond, old_haltcond; 1156 1157 old_fiscfg = readl(port_mmio + FISCFG_OFS); 1158 old_ltmode = readl(port_mmio + LTMODE_OFS); 1159 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS); 1160 1161 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); 1162 new_ltmode = old_ltmode & ~LTMODE_BIT8; 1163 new_haltcond = old_haltcond | EDMA_ERR_DEV; 1164 1165 if (want_fbs) { 1166 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC; 1167 new_ltmode = old_ltmode | LTMODE_BIT8; 1168 if (want_ncq) 1169 new_haltcond &= ~EDMA_ERR_DEV; 1170 else 1171 new_fiscfg |= FISCFG_WAIT_DEV_ERR; 1172 } 1173 1174 if (new_fiscfg != old_fiscfg) 1175 writelfl(new_fiscfg, port_mmio + FISCFG_OFS); 1176 if (new_ltmode != old_ltmode) 1177 writelfl(new_ltmode, port_mmio + LTMODE_OFS); 1178 if (new_haltcond != old_haltcond) 1179 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS); 1180 } 1181 1182 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) 1183 { 1184 struct mv_host_priv *hpriv = ap->host->private_data; 1185 u32 old, new; 1186 1187 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ 1188 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS); 1189 if (want_ncq) 1190 new = old | (1 << 22); 1191 else 1192 new = old & ~(1 << 22); 1193 if (new != old) 1194 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS); 1195 } 1196 1197 static void mv_edma_cfg(struct ata_port *ap, int want_ncq) 1198 { 1199 u32 cfg; 1200 struct mv_port_priv *pp = ap->private_data; 1201 struct mv_host_priv *hpriv = ap->host->private_data; 1202 void __iomem *port_mmio = mv_ap_base(ap); 1203 1204 /* set up non-NCQ EDMA configuration */ 1205 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ 1206 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN; 1207 1208 if (IS_GEN_I(hpriv)) 1209 cfg |= (1 << 8); /* enab config burst size mask */ 1210 1211 else if (IS_GEN_II(hpriv)) { 1212 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; 1213 mv_60x1_errata_sata25(ap, want_ncq); 1214 1215 } else if (IS_GEN_IIE(hpriv)) { 1216 int want_fbs = sata_pmp_attached(ap); 1217 /* 1218 * Possible future enhancement: 1219 * 1220 * The chip can use FBS with non-NCQ, if we allow it, 1221 * But first we need to have the error handling in place 1222 * for this mode (datasheet section 7.3.15.4.2.3). 1223 * So disallow non-NCQ FBS for now. 1224 */ 1225 want_fbs &= want_ncq; 1226 1227 mv_config_fbs(port_mmio, want_ncq, want_fbs); 1228 1229 if (want_fbs) { 1230 pp->pp_flags |= MV_PP_FLAG_FBS_EN; 1231 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ 1232 } 1233 1234 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ 1235 cfg |= (1 << 22); /* enab 4-entry host queue cache */ 1236 if (!IS_SOC(hpriv)) 1237 cfg |= (1 << 18); /* enab early completion */ 1238 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) 1239 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ 1240 } 1241 1242 if (want_ncq) { 1243 cfg |= EDMA_CFG_NCQ; 1244 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; 1245 } else 1246 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN; 1247 1248 writelfl(cfg, port_mmio + EDMA_CFG_OFS); 1249 } 1250 1251 static void mv_port_free_dma_mem(struct ata_port *ap) 1252 { 1253 struct mv_host_priv *hpriv = ap->host->private_data; 1254 struct mv_port_priv *pp = ap->private_data; 1255 int tag; 1256 1257 if (pp->crqb) { 1258 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); 1259 pp->crqb = NULL; 1260 } 1261 if (pp->crpb) { 1262 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); 1263 pp->crpb = NULL; 1264 } 1265 /* 1266 * For GEN_I, there's no NCQ, so we have only a single sg_tbl. 1267 * For later hardware, we have one unique sg_tbl per NCQ tag. 1268 */ 1269 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1270 if (pp->sg_tbl[tag]) { 1271 if (tag == 0 || !IS_GEN_I(hpriv)) 1272 dma_pool_free(hpriv->sg_tbl_pool, 1273 pp->sg_tbl[tag], 1274 pp->sg_tbl_dma[tag]); 1275 pp->sg_tbl[tag] = NULL; 1276 } 1277 } 1278 } 1279 1280 /** 1281 * mv_port_start - Port specific init/start routine. 1282 * @ap: ATA channel to manipulate 1283 * 1284 * Allocate and point to DMA memory, init port private memory, 1285 * zero indices. 1286 * 1287 * LOCKING: 1288 * Inherited from caller. 1289 */ 1290 static int mv_port_start(struct ata_port *ap) 1291 { 1292 struct device *dev = ap->host->dev; 1293 struct mv_host_priv *hpriv = ap->host->private_data; 1294 struct mv_port_priv *pp; 1295 int tag; 1296 1297 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1298 if (!pp) 1299 return -ENOMEM; 1300 ap->private_data = pp; 1301 1302 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); 1303 if (!pp->crqb) 1304 return -ENOMEM; 1305 memset(pp->crqb, 0, MV_CRQB_Q_SZ); 1306 1307 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); 1308 if (!pp->crpb) 1309 goto out_port_free_dma_mem; 1310 memset(pp->crpb, 0, MV_CRPB_Q_SZ); 1311 1312 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ 1313 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) 1314 ap->flags |= ATA_FLAG_AN; 1315 /* 1316 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. 1317 * For later hardware, we need one unique sg_tbl per NCQ tag. 1318 */ 1319 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { 1320 if (tag == 0 || !IS_GEN_I(hpriv)) { 1321 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, 1322 GFP_KERNEL, &pp->sg_tbl_dma[tag]); 1323 if (!pp->sg_tbl[tag]) 1324 goto out_port_free_dma_mem; 1325 } else { 1326 pp->sg_tbl[tag] = pp->sg_tbl[0]; 1327 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; 1328 } 1329 } 1330 return 0; 1331 1332 out_port_free_dma_mem: 1333 mv_port_free_dma_mem(ap); 1334 return -ENOMEM; 1335 } 1336 1337 /** 1338 * mv_port_stop - Port specific cleanup/stop routine. 1339 * @ap: ATA channel to manipulate 1340 * 1341 * Stop DMA, cleanup port memory. 1342 * 1343 * LOCKING: 1344 * This routine uses the host lock to protect the DMA stop. 1345 */ 1346 static void mv_port_stop(struct ata_port *ap) 1347 { 1348 mv_stop_edma(ap); 1349 mv_enable_port_irqs(ap, 0); 1350 mv_port_free_dma_mem(ap); 1351 } 1352 1353 /** 1354 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries 1355 * @qc: queued command whose SG list to source from 1356 * 1357 * Populate the SG list and mark the last entry. 1358 * 1359 * LOCKING: 1360 * Inherited from caller. 1361 */ 1362 static void mv_fill_sg(struct ata_queued_cmd *qc) 1363 { 1364 struct mv_port_priv *pp = qc->ap->private_data; 1365 struct scatterlist *sg; 1366 struct mv_sg *mv_sg, *last_sg = NULL; 1367 unsigned int si; 1368 1369 mv_sg = pp->sg_tbl[qc->tag]; 1370 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1371 dma_addr_t addr = sg_dma_address(sg); 1372 u32 sg_len = sg_dma_len(sg); 1373 1374 while (sg_len) { 1375 u32 offset = addr & 0xffff; 1376 u32 len = sg_len; 1377 1378 if ((offset + sg_len > 0x10000)) 1379 len = 0x10000 - offset; 1380 1381 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); 1382 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); 1383 mv_sg->flags_size = cpu_to_le32(len & 0xffff); 1384 1385 sg_len -= len; 1386 addr += len; 1387 1388 last_sg = mv_sg; 1389 mv_sg++; 1390 } 1391 } 1392 1393 if (likely(last_sg)) 1394 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); 1395 } 1396 1397 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) 1398 { 1399 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | 1400 (last ? CRQB_CMD_LAST : 0); 1401 *cmdw = cpu_to_le16(tmp); 1402 } 1403 1404 /** 1405 * mv_qc_prep - Host specific command preparation. 1406 * @qc: queued command to prepare 1407 * 1408 * This routine simply redirects to the general purpose routine 1409 * if command is not DMA. Else, it handles prep of the CRQB 1410 * (command request block), does some sanity checking, and calls 1411 * the SG load routine. 1412 * 1413 * LOCKING: 1414 * Inherited from caller. 1415 */ 1416 static void mv_qc_prep(struct ata_queued_cmd *qc) 1417 { 1418 struct ata_port *ap = qc->ap; 1419 struct mv_port_priv *pp = ap->private_data; 1420 __le16 *cw; 1421 struct ata_taskfile *tf; 1422 u16 flags = 0; 1423 unsigned in_index; 1424 1425 if ((qc->tf.protocol != ATA_PROT_DMA) && 1426 (qc->tf.protocol != ATA_PROT_NCQ)) 1427 return; 1428 1429 /* Fill in command request block 1430 */ 1431 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1432 flags |= CRQB_FLAG_READ; 1433 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1434 flags |= qc->tag << CRQB_TAG_SHIFT; 1435 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1436 1437 /* get current queue index from software */ 1438 in_index = pp->req_idx; 1439 1440 pp->crqb[in_index].sg_addr = 1441 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1442 pp->crqb[in_index].sg_addr_hi = 1443 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1444 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); 1445 1446 cw = &pp->crqb[in_index].ata_cmd[0]; 1447 tf = &qc->tf; 1448 1449 /* Sadly, the CRQB cannot accomodate all registers--there are 1450 * only 11 bytes...so we must pick and choose required 1451 * registers based on the command. So, we drop feature and 1452 * hob_feature for [RW] DMA commands, but they are needed for 1453 * NCQ. NCQ will drop hob_nsect. 1454 */ 1455 switch (tf->command) { 1456 case ATA_CMD_READ: 1457 case ATA_CMD_READ_EXT: 1458 case ATA_CMD_WRITE: 1459 case ATA_CMD_WRITE_EXT: 1460 case ATA_CMD_WRITE_FUA_EXT: 1461 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); 1462 break; 1463 case ATA_CMD_FPDMA_READ: 1464 case ATA_CMD_FPDMA_WRITE: 1465 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); 1466 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); 1467 break; 1468 default: 1469 /* The only other commands EDMA supports in non-queued and 1470 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none 1471 * of which are defined/used by Linux. If we get here, this 1472 * driver needs work. 1473 * 1474 * FIXME: modify libata to give qc_prep a return value and 1475 * return error here. 1476 */ 1477 BUG_ON(tf->command); 1478 break; 1479 } 1480 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); 1481 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); 1482 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); 1483 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); 1484 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); 1485 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); 1486 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); 1487 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); 1488 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ 1489 1490 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1491 return; 1492 mv_fill_sg(qc); 1493 } 1494 1495 /** 1496 * mv_qc_prep_iie - Host specific command preparation. 1497 * @qc: queued command to prepare 1498 * 1499 * This routine simply redirects to the general purpose routine 1500 * if command is not DMA. Else, it handles prep of the CRQB 1501 * (command request block), does some sanity checking, and calls 1502 * the SG load routine. 1503 * 1504 * LOCKING: 1505 * Inherited from caller. 1506 */ 1507 static void mv_qc_prep_iie(struct ata_queued_cmd *qc) 1508 { 1509 struct ata_port *ap = qc->ap; 1510 struct mv_port_priv *pp = ap->private_data; 1511 struct mv_crqb_iie *crqb; 1512 struct ata_taskfile *tf; 1513 unsigned in_index; 1514 u32 flags = 0; 1515 1516 if ((qc->tf.protocol != ATA_PROT_DMA) && 1517 (qc->tf.protocol != ATA_PROT_NCQ)) 1518 return; 1519 1520 /* Fill in Gen IIE command request block */ 1521 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) 1522 flags |= CRQB_FLAG_READ; 1523 1524 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); 1525 flags |= qc->tag << CRQB_TAG_SHIFT; 1526 flags |= qc->tag << CRQB_HOSTQ_SHIFT; 1527 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; 1528 1529 /* get current queue index from software */ 1530 in_index = pp->req_idx; 1531 1532 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; 1533 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); 1534 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); 1535 crqb->flags = cpu_to_le32(flags); 1536 1537 tf = &qc->tf; 1538 crqb->ata_cmd[0] = cpu_to_le32( 1539 (tf->command << 16) | 1540 (tf->feature << 24) 1541 ); 1542 crqb->ata_cmd[1] = cpu_to_le32( 1543 (tf->lbal << 0) | 1544 (tf->lbam << 8) | 1545 (tf->lbah << 16) | 1546 (tf->device << 24) 1547 ); 1548 crqb->ata_cmd[2] = cpu_to_le32( 1549 (tf->hob_lbal << 0) | 1550 (tf->hob_lbam << 8) | 1551 (tf->hob_lbah << 16) | 1552 (tf->hob_feature << 24) 1553 ); 1554 crqb->ata_cmd[3] = cpu_to_le32( 1555 (tf->nsect << 0) | 1556 (tf->hob_nsect << 8) 1557 ); 1558 1559 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 1560 return; 1561 mv_fill_sg(qc); 1562 } 1563 1564 /** 1565 * mv_qc_issue - Initiate a command to the host 1566 * @qc: queued command to start 1567 * 1568 * This routine simply redirects to the general purpose routine 1569 * if command is not DMA. Else, it sanity checks our local 1570 * caches of the request producer/consumer indices then enables 1571 * DMA and bumps the request producer index. 1572 * 1573 * LOCKING: 1574 * Inherited from caller. 1575 */ 1576 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) 1577 { 1578 struct ata_port *ap = qc->ap; 1579 void __iomem *port_mmio = mv_ap_base(ap); 1580 struct mv_port_priv *pp = ap->private_data; 1581 u32 in_index; 1582 1583 if ((qc->tf.protocol != ATA_PROT_DMA) && 1584 (qc->tf.protocol != ATA_PROT_NCQ)) { 1585 static int limit_warnings = 10; 1586 /* 1587 * Errata SATA#16, SATA#24: warn if multiple DRQs expected. 1588 * 1589 * Someday, we might implement special polling workarounds 1590 * for these, but it all seems rather unnecessary since we 1591 * normally use only DMA for commands which transfer more 1592 * than a single block of data. 1593 * 1594 * Much of the time, this could just work regardless. 1595 * So for now, just log the incident, and allow the attempt. 1596 */ 1597 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { 1598 --limit_warnings; 1599 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME 1600 ": attempting PIO w/multiple DRQ: " 1601 "this may fail due to h/w errata\n"); 1602 } 1603 /* 1604 * We're about to send a non-EDMA capable command to the 1605 * port. Turn off EDMA so there won't be problems accessing 1606 * shadow block, etc registers. 1607 */ 1608 mv_stop_edma(ap); 1609 mv_enable_port_irqs(ap, ERR_IRQ); 1610 mv_pmp_select(ap, qc->dev->link->pmp); 1611 return ata_sff_qc_issue(qc); 1612 } 1613 1614 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol); 1615 1616 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; 1617 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; 1618 1619 /* and write the request in pointer to kick the EDMA to life */ 1620 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, 1621 port_mmio + EDMA_REQ_Q_IN_PTR_OFS); 1622 1623 return 0; 1624 } 1625 1626 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) 1627 { 1628 struct mv_port_priv *pp = ap->private_data; 1629 struct ata_queued_cmd *qc; 1630 1631 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) 1632 return NULL; 1633 qc = ata_qc_from_tag(ap, ap->link.active_tag); 1634 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1635 qc = NULL; 1636 return qc; 1637 } 1638 1639 static void mv_pmp_error_handler(struct ata_port *ap) 1640 { 1641 unsigned int pmp, pmp_map; 1642 struct mv_port_priv *pp = ap->private_data; 1643 1644 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { 1645 /* 1646 * Perform NCQ error analysis on failed PMPs 1647 * before we freeze the port entirely. 1648 * 1649 * The failed PMPs are marked earlier by mv_pmp_eh_prep(). 1650 */ 1651 pmp_map = pp->delayed_eh_pmp_map; 1652 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; 1653 for (pmp = 0; pmp_map != 0; pmp++) { 1654 unsigned int this_pmp = (1 << pmp); 1655 if (pmp_map & this_pmp) { 1656 struct ata_link *link = &ap->pmp_link[pmp]; 1657 pmp_map &= ~this_pmp; 1658 ata_eh_analyze_ncq_error(link); 1659 } 1660 } 1661 ata_port_freeze(ap); 1662 } 1663 sata_pmp_error_handler(ap); 1664 } 1665 1666 static unsigned int mv_get_err_pmp_map(struct ata_port *ap) 1667 { 1668 void __iomem *port_mmio = mv_ap_base(ap); 1669 1670 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16; 1671 } 1672 1673 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) 1674 { 1675 struct ata_eh_info *ehi; 1676 unsigned int pmp; 1677 1678 /* 1679 * Initialize EH info for PMPs which saw device errors 1680 */ 1681 ehi = &ap->link.eh_info; 1682 for (pmp = 0; pmp_map != 0; pmp++) { 1683 unsigned int this_pmp = (1 << pmp); 1684 if (pmp_map & this_pmp) { 1685 struct ata_link *link = &ap->pmp_link[pmp]; 1686 1687 pmp_map &= ~this_pmp; 1688 ehi = &link->eh_info; 1689 ata_ehi_clear_desc(ehi); 1690 ata_ehi_push_desc(ehi, "dev err"); 1691 ehi->err_mask |= AC_ERR_DEV; 1692 ehi->action |= ATA_EH_RESET; 1693 ata_link_abort(link); 1694 } 1695 } 1696 } 1697 1698 static int mv_req_q_empty(struct ata_port *ap) 1699 { 1700 void __iomem *port_mmio = mv_ap_base(ap); 1701 u32 in_ptr, out_ptr; 1702 1703 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS) 1704 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1705 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) 1706 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 1707 return (in_ptr == out_ptr); /* 1 == queue_is_empty */ 1708 } 1709 1710 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) 1711 { 1712 struct mv_port_priv *pp = ap->private_data; 1713 int failed_links; 1714 unsigned int old_map, new_map; 1715 1716 /* 1717 * Device error during FBS+NCQ operation: 1718 * 1719 * Set a port flag to prevent further I/O being enqueued. 1720 * Leave the EDMA running to drain outstanding commands from this port. 1721 * Perform the post-mortem/EH only when all responses are complete. 1722 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). 1723 */ 1724 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { 1725 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; 1726 pp->delayed_eh_pmp_map = 0; 1727 } 1728 old_map = pp->delayed_eh_pmp_map; 1729 new_map = old_map | mv_get_err_pmp_map(ap); 1730 1731 if (old_map != new_map) { 1732 pp->delayed_eh_pmp_map = new_map; 1733 mv_pmp_eh_prep(ap, new_map & ~old_map); 1734 } 1735 failed_links = hweight16(new_map); 1736 1737 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " 1738 "failed_links=%d nr_active_links=%d\n", 1739 __func__, pp->delayed_eh_pmp_map, 1740 ap->qc_active, failed_links, 1741 ap->nr_active_links); 1742 1743 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { 1744 mv_process_crpb_entries(ap, pp); 1745 mv_stop_edma(ap); 1746 mv_eh_freeze(ap); 1747 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); 1748 return 1; /* handled */ 1749 } 1750 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); 1751 return 1; /* handled */ 1752 } 1753 1754 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) 1755 { 1756 /* 1757 * Possible future enhancement: 1758 * 1759 * FBS+non-NCQ operation is not yet implemented. 1760 * See related notes in mv_edma_cfg(). 1761 * 1762 * Device error during FBS+non-NCQ operation: 1763 * 1764 * We need to snapshot the shadow registers for each failed command. 1765 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). 1766 */ 1767 return 0; /* not handled */ 1768 } 1769 1770 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) 1771 { 1772 struct mv_port_priv *pp = ap->private_data; 1773 1774 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) 1775 return 0; /* EDMA was not active: not handled */ 1776 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) 1777 return 0; /* FBS was not active: not handled */ 1778 1779 if (!(edma_err_cause & EDMA_ERR_DEV)) 1780 return 0; /* non DEV error: not handled */ 1781 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; 1782 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) 1783 return 0; /* other problems: not handled */ 1784 1785 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { 1786 /* 1787 * EDMA should NOT have self-disabled for this case. 1788 * If it did, then something is wrong elsewhere, 1789 * and we cannot handle it here. 1790 */ 1791 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1792 ata_port_printk(ap, KERN_WARNING, 1793 "%s: err_cause=0x%x pp_flags=0x%x\n", 1794 __func__, edma_err_cause, pp->pp_flags); 1795 return 0; /* not handled */ 1796 } 1797 return mv_handle_fbs_ncq_dev_err(ap); 1798 } else { 1799 /* 1800 * EDMA should have self-disabled for this case. 1801 * If it did not, then something is wrong elsewhere, 1802 * and we cannot handle it here. 1803 */ 1804 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { 1805 ata_port_printk(ap, KERN_WARNING, 1806 "%s: err_cause=0x%x pp_flags=0x%x\n", 1807 __func__, edma_err_cause, pp->pp_flags); 1808 return 0; /* not handled */ 1809 } 1810 return mv_handle_fbs_non_ncq_dev_err(ap); 1811 } 1812 return 0; /* not handled */ 1813 } 1814 1815 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) 1816 { 1817 struct ata_eh_info *ehi = &ap->link.eh_info; 1818 char *when = "idle"; 1819 1820 ata_ehi_clear_desc(ehi); 1821 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 1822 when = "disabled"; 1823 } else if (edma_was_enabled) { 1824 when = "EDMA enabled"; 1825 } else { 1826 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); 1827 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) 1828 when = "polling"; 1829 } 1830 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); 1831 ehi->err_mask |= AC_ERR_OTHER; 1832 ehi->action |= ATA_EH_RESET; 1833 ata_port_freeze(ap); 1834 } 1835 1836 /** 1837 * mv_err_intr - Handle error interrupts on the port 1838 * @ap: ATA channel to manipulate 1839 * 1840 * Most cases require a full reset of the chip's state machine, 1841 * which also performs a COMRESET. 1842 * Also, if the port disabled DMA, update our cached copy to match. 1843 * 1844 * LOCKING: 1845 * Inherited from caller. 1846 */ 1847 static void mv_err_intr(struct ata_port *ap) 1848 { 1849 void __iomem *port_mmio = mv_ap_base(ap); 1850 u32 edma_err_cause, eh_freeze_mask, serr = 0; 1851 u32 fis_cause = 0; 1852 struct mv_port_priv *pp = ap->private_data; 1853 struct mv_host_priv *hpriv = ap->host->private_data; 1854 unsigned int action = 0, err_mask = 0; 1855 struct ata_eh_info *ehi = &ap->link.eh_info; 1856 struct ata_queued_cmd *qc; 1857 int abort = 0; 1858 1859 /* 1860 * Read and clear the SError and err_cause bits. 1861 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear 1862 * the FIS_IRQ_CAUSE register before clearing edma_err_cause. 1863 */ 1864 sata_scr_read(&ap->link, SCR_ERROR, &serr); 1865 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); 1866 1867 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1868 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 1869 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 1870 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); 1871 } 1872 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 1873 1874 if (edma_err_cause & EDMA_ERR_DEV) { 1875 /* 1876 * Device errors during FIS-based switching operation 1877 * require special handling. 1878 */ 1879 if (mv_handle_dev_err(ap, edma_err_cause)) 1880 return; 1881 } 1882 1883 qc = mv_get_active_qc(ap); 1884 ata_ehi_clear_desc(ehi); 1885 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", 1886 edma_err_cause, pp->pp_flags); 1887 1888 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { 1889 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); 1890 if (fis_cause & SATA_FIS_IRQ_AN) { 1891 u32 ec = edma_err_cause & 1892 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); 1893 sata_async_notification(ap); 1894 if (!ec) 1895 return; /* Just an AN; no need for the nukes */ 1896 ata_ehi_push_desc(ehi, "SDB notify"); 1897 } 1898 } 1899 /* 1900 * All generations share these EDMA error cause bits: 1901 */ 1902 if (edma_err_cause & EDMA_ERR_DEV) { 1903 err_mask |= AC_ERR_DEV; 1904 action |= ATA_EH_RESET; 1905 ata_ehi_push_desc(ehi, "dev error"); 1906 } 1907 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | 1908 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | 1909 EDMA_ERR_INTRL_PAR)) { 1910 err_mask |= AC_ERR_ATA_BUS; 1911 action |= ATA_EH_RESET; 1912 ata_ehi_push_desc(ehi, "parity error"); 1913 } 1914 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { 1915 ata_ehi_hotplugged(ehi); 1916 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? 1917 "dev disconnect" : "dev connect"); 1918 action |= ATA_EH_RESET; 1919 } 1920 1921 /* 1922 * Gen-I has a different SELF_DIS bit, 1923 * different FREEZE bits, and no SERR bit: 1924 */ 1925 if (IS_GEN_I(hpriv)) { 1926 eh_freeze_mask = EDMA_EH_FREEZE_5; 1927 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { 1928 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1929 ata_ehi_push_desc(ehi, "EDMA self-disable"); 1930 } 1931 } else { 1932 eh_freeze_mask = EDMA_EH_FREEZE; 1933 if (edma_err_cause & EDMA_ERR_SELF_DIS) { 1934 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 1935 ata_ehi_push_desc(ehi, "EDMA self-disable"); 1936 } 1937 if (edma_err_cause & EDMA_ERR_SERR) { 1938 ata_ehi_push_desc(ehi, "SError=%08x", serr); 1939 err_mask |= AC_ERR_ATA_BUS; 1940 action |= ATA_EH_RESET; 1941 } 1942 } 1943 1944 if (!err_mask) { 1945 err_mask = AC_ERR_OTHER; 1946 action |= ATA_EH_RESET; 1947 } 1948 1949 ehi->serror |= serr; 1950 ehi->action |= action; 1951 1952 if (qc) 1953 qc->err_mask |= err_mask; 1954 else 1955 ehi->err_mask |= err_mask; 1956 1957 if (err_mask == AC_ERR_DEV) { 1958 /* 1959 * Cannot do ata_port_freeze() here, 1960 * because it would kill PIO access, 1961 * which is needed for further diagnosis. 1962 */ 1963 mv_eh_freeze(ap); 1964 abort = 1; 1965 } else if (edma_err_cause & eh_freeze_mask) { 1966 /* 1967 * Note to self: ata_port_freeze() calls ata_port_abort() 1968 */ 1969 ata_port_freeze(ap); 1970 } else { 1971 abort = 1; 1972 } 1973 1974 if (abort) { 1975 if (qc) 1976 ata_link_abort(qc->dev->link); 1977 else 1978 ata_port_abort(ap); 1979 } 1980 } 1981 1982 static void mv_process_crpb_response(struct ata_port *ap, 1983 struct mv_crpb *response, unsigned int tag, int ncq_enabled) 1984 { 1985 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); 1986 1987 if (qc) { 1988 u8 ata_status; 1989 u16 edma_status = le16_to_cpu(response->flags); 1990 /* 1991 * edma_status from a response queue entry: 1992 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). 1993 * MSB is saved ATA status from command completion. 1994 */ 1995 if (!ncq_enabled) { 1996 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; 1997 if (err_cause) { 1998 /* 1999 * Error will be seen/handled by mv_err_intr(). 2000 * So do nothing at all here. 2001 */ 2002 return; 2003 } 2004 } 2005 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; 2006 if (!ac_err_mask(ata_status)) 2007 ata_qc_complete(qc); 2008 /* else: leave it for mv_err_intr() */ 2009 } else { 2010 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", 2011 __func__, tag); 2012 } 2013 } 2014 2015 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) 2016 { 2017 void __iomem *port_mmio = mv_ap_base(ap); 2018 struct mv_host_priv *hpriv = ap->host->private_data; 2019 u32 in_index; 2020 bool work_done = false; 2021 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); 2022 2023 /* Get the hardware queue position index */ 2024 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) 2025 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; 2026 2027 /* Process new responses from since the last time we looked */ 2028 while (in_index != pp->resp_idx) { 2029 unsigned int tag; 2030 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; 2031 2032 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; 2033 2034 if (IS_GEN_I(hpriv)) { 2035 /* 50xx: no NCQ, only one command active at a time */ 2036 tag = ap->link.active_tag; 2037 } else { 2038 /* Gen II/IIE: get command tag from CRPB entry */ 2039 tag = le16_to_cpu(response->id) & 0x1f; 2040 } 2041 mv_process_crpb_response(ap, response, tag, ncq_enabled); 2042 work_done = true; 2043 } 2044 2045 /* Update the software queue position index in hardware */ 2046 if (work_done) 2047 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | 2048 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), 2049 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); 2050 } 2051 2052 static void mv_port_intr(struct ata_port *ap, u32 port_cause) 2053 { 2054 struct mv_port_priv *pp; 2055 int edma_was_enabled; 2056 2057 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { 2058 mv_unexpected_intr(ap, 0); 2059 return; 2060 } 2061 /* 2062 * Grab a snapshot of the EDMA_EN flag setting, 2063 * so that we have a consistent view for this port, 2064 * even if something we call of our routines changes it. 2065 */ 2066 pp = ap->private_data; 2067 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); 2068 /* 2069 * Process completed CRPB response(s) before other events. 2070 */ 2071 if (edma_was_enabled && (port_cause & DONE_IRQ)) { 2072 mv_process_crpb_entries(ap, pp); 2073 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) 2074 mv_handle_fbs_ncq_dev_err(ap); 2075 } 2076 /* 2077 * Handle chip-reported errors, or continue on to handle PIO. 2078 */ 2079 if (unlikely(port_cause & ERR_IRQ)) { 2080 mv_err_intr(ap); 2081 } else if (!edma_was_enabled) { 2082 struct ata_queued_cmd *qc = mv_get_active_qc(ap); 2083 if (qc) 2084 ata_sff_host_intr(ap, qc); 2085 else 2086 mv_unexpected_intr(ap, edma_was_enabled); 2087 } 2088 } 2089 2090 /** 2091 * mv_host_intr - Handle all interrupts on the given host controller 2092 * @host: host specific structure 2093 * @main_irq_cause: Main interrupt cause register for the chip. 2094 * 2095 * LOCKING: 2096 * Inherited from caller. 2097 */ 2098 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) 2099 { 2100 struct mv_host_priv *hpriv = host->private_data; 2101 void __iomem *mmio = hpriv->base, *hc_mmio; 2102 unsigned int handled = 0, port; 2103 2104 for (port = 0; port < hpriv->n_ports; port++) { 2105 struct ata_port *ap = host->ports[port]; 2106 unsigned int p, shift, hardport, port_cause; 2107 2108 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); 2109 /* 2110 * Each hc within the host has its own hc_irq_cause register, 2111 * where the interrupting ports bits get ack'd. 2112 */ 2113 if (hardport == 0) { /* first port on this hc ? */ 2114 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; 2115 u32 port_mask, ack_irqs; 2116 /* 2117 * Skip this entire hc if nothing pending for any ports 2118 */ 2119 if (!hc_cause) { 2120 port += MV_PORTS_PER_HC - 1; 2121 continue; 2122 } 2123 /* 2124 * We don't need/want to read the hc_irq_cause register, 2125 * because doing so hurts performance, and 2126 * main_irq_cause already gives us everything we need. 2127 * 2128 * But we do have to *write* to the hc_irq_cause to ack 2129 * the ports that we are handling this time through. 2130 * 2131 * This requires that we create a bitmap for those 2132 * ports which interrupted us, and use that bitmap 2133 * to ack (only) those ports via hc_irq_cause. 2134 */ 2135 ack_irqs = 0; 2136 for (p = 0; p < MV_PORTS_PER_HC; ++p) { 2137 if ((port + p) >= hpriv->n_ports) 2138 break; 2139 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); 2140 if (hc_cause & port_mask) 2141 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; 2142 } 2143 hc_mmio = mv_hc_base_from_port(mmio, port); 2144 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS); 2145 handled = 1; 2146 } 2147 /* 2148 * Handle interrupts signalled for this port: 2149 */ 2150 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); 2151 if (port_cause) 2152 mv_port_intr(ap, port_cause); 2153 } 2154 return handled; 2155 } 2156 2157 static int mv_pci_error(struct ata_host *host, void __iomem *mmio) 2158 { 2159 struct mv_host_priv *hpriv = host->private_data; 2160 struct ata_port *ap; 2161 struct ata_queued_cmd *qc; 2162 struct ata_eh_info *ehi; 2163 unsigned int i, err_mask, printed = 0; 2164 u32 err_cause; 2165 2166 err_cause = readl(mmio + hpriv->irq_cause_ofs); 2167 2168 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", 2169 err_cause); 2170 2171 DPRINTK("All regs @ PCI error\n"); 2172 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); 2173 2174 writelfl(0, mmio + hpriv->irq_cause_ofs); 2175 2176 for (i = 0; i < host->n_ports; i++) { 2177 ap = host->ports[i]; 2178 if (!ata_link_offline(&ap->link)) { 2179 ehi = &ap->link.eh_info; 2180 ata_ehi_clear_desc(ehi); 2181 if (!printed++) 2182 ata_ehi_push_desc(ehi, 2183 "PCI err cause 0x%08x", err_cause); 2184 err_mask = AC_ERR_HOST_BUS; 2185 ehi->action = ATA_EH_RESET; 2186 qc = ata_qc_from_tag(ap, ap->link.active_tag); 2187 if (qc) 2188 qc->err_mask |= err_mask; 2189 else 2190 ehi->err_mask |= err_mask; 2191 2192 ata_port_freeze(ap); 2193 } 2194 } 2195 return 1; /* handled */ 2196 } 2197 2198 /** 2199 * mv_interrupt - Main interrupt event handler 2200 * @irq: unused 2201 * @dev_instance: private data; in this case the host structure 2202 * 2203 * Read the read only register to determine if any host 2204 * controllers have pending interrupts. If so, call lower level 2205 * routine to handle. Also check for PCI errors which are only 2206 * reported here. 2207 * 2208 * LOCKING: 2209 * This routine holds the host lock while processing pending 2210 * interrupts. 2211 */ 2212 static irqreturn_t mv_interrupt(int irq, void *dev_instance) 2213 { 2214 struct ata_host *host = dev_instance; 2215 struct mv_host_priv *hpriv = host->private_data; 2216 unsigned int handled = 0; 2217 u32 main_irq_cause, pending_irqs; 2218 2219 spin_lock(&host->lock); 2220 main_irq_cause = readl(hpriv->main_irq_cause_addr); 2221 pending_irqs = main_irq_cause & hpriv->main_irq_mask; 2222 /* 2223 * Deal with cases where we either have nothing pending, or have read 2224 * a bogus register value which can indicate HW removal or PCI fault. 2225 */ 2226 if (pending_irqs && main_irq_cause != 0xffffffffU) { 2227 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) 2228 handled = mv_pci_error(host, hpriv->base); 2229 else 2230 handled = mv_host_intr(host, pending_irqs); 2231 } 2232 spin_unlock(&host->lock); 2233 return IRQ_RETVAL(handled); 2234 } 2235 2236 static unsigned int mv5_scr_offset(unsigned int sc_reg_in) 2237 { 2238 unsigned int ofs; 2239 2240 switch (sc_reg_in) { 2241 case SCR_STATUS: 2242 case SCR_ERROR: 2243 case SCR_CONTROL: 2244 ofs = sc_reg_in * sizeof(u32); 2245 break; 2246 default: 2247 ofs = 0xffffffffU; 2248 break; 2249 } 2250 return ofs; 2251 } 2252 2253 static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) 2254 { 2255 struct mv_host_priv *hpriv = link->ap->host->private_data; 2256 void __iomem *mmio = hpriv->base; 2257 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2258 unsigned int ofs = mv5_scr_offset(sc_reg_in); 2259 2260 if (ofs != 0xffffffffU) { 2261 *val = readl(addr + ofs); 2262 return 0; 2263 } else 2264 return -EINVAL; 2265 } 2266 2267 static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) 2268 { 2269 struct mv_host_priv *hpriv = link->ap->host->private_data; 2270 void __iomem *mmio = hpriv->base; 2271 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); 2272 unsigned int ofs = mv5_scr_offset(sc_reg_in); 2273 2274 if (ofs != 0xffffffffU) { 2275 writelfl(val, addr + ofs); 2276 return 0; 2277 } else 2278 return -EINVAL; 2279 } 2280 2281 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) 2282 { 2283 struct pci_dev *pdev = to_pci_dev(host->dev); 2284 int early_5080; 2285 2286 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); 2287 2288 if (!early_5080) { 2289 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2290 tmp |= (1 << 0); 2291 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2292 } 2293 2294 mv_reset_pci_bus(host, mmio); 2295 } 2296 2297 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2298 { 2299 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS); 2300 } 2301 2302 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, 2303 void __iomem *mmio) 2304 { 2305 void __iomem *phy_mmio = mv5_phy_base(mmio, idx); 2306 u32 tmp; 2307 2308 tmp = readl(phy_mmio + MV5_PHY_MODE); 2309 2310 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ 2311 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ 2312 } 2313 2314 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2315 { 2316 u32 tmp; 2317 2318 writel(0, mmio + MV_GPIO_PORT_CTL_OFS); 2319 2320 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ 2321 2322 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); 2323 tmp |= ~(1 << 0); 2324 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); 2325 } 2326 2327 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 2328 unsigned int port) 2329 { 2330 void __iomem *phy_mmio = mv5_phy_base(mmio, port); 2331 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); 2332 u32 tmp; 2333 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); 2334 2335 if (fix_apm_sq) { 2336 tmp = readl(phy_mmio + MV5_LTMODE_OFS); 2337 tmp |= (1 << 19); 2338 writel(tmp, phy_mmio + MV5_LTMODE_OFS); 2339 2340 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS); 2341 tmp &= ~0x3; 2342 tmp |= 0x1; 2343 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS); 2344 } 2345 2346 tmp = readl(phy_mmio + MV5_PHY_MODE); 2347 tmp &= ~mask; 2348 tmp |= hpriv->signal[port].pre; 2349 tmp |= hpriv->signal[port].amps; 2350 writel(tmp, phy_mmio + MV5_PHY_MODE); 2351 } 2352 2353 2354 #undef ZERO 2355 #define ZERO(reg) writel(0, port_mmio + (reg)) 2356 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, 2357 unsigned int port) 2358 { 2359 void __iomem *port_mmio = mv_port_base(mmio, port); 2360 2361 mv_reset_channel(hpriv, mmio, port); 2362 2363 ZERO(0x028); /* command */ 2364 writel(0x11f, port_mmio + EDMA_CFG_OFS); 2365 ZERO(0x004); /* timer */ 2366 ZERO(0x008); /* irq err cause */ 2367 ZERO(0x00c); /* irq err mask */ 2368 ZERO(0x010); /* rq bah */ 2369 ZERO(0x014); /* rq inp */ 2370 ZERO(0x018); /* rq outp */ 2371 ZERO(0x01c); /* respq bah */ 2372 ZERO(0x024); /* respq outp */ 2373 ZERO(0x020); /* respq inp */ 2374 ZERO(0x02c); /* test control */ 2375 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2376 } 2377 #undef ZERO 2378 2379 #define ZERO(reg) writel(0, hc_mmio + (reg)) 2380 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2381 unsigned int hc) 2382 { 2383 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 2384 u32 tmp; 2385 2386 ZERO(0x00c); 2387 ZERO(0x010); 2388 ZERO(0x014); 2389 ZERO(0x018); 2390 2391 tmp = readl(hc_mmio + 0x20); 2392 tmp &= 0x1c1c1c1c; 2393 tmp |= 0x03030303; 2394 writel(tmp, hc_mmio + 0x20); 2395 } 2396 #undef ZERO 2397 2398 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2399 unsigned int n_hc) 2400 { 2401 unsigned int hc, port; 2402 2403 for (hc = 0; hc < n_hc; hc++) { 2404 for (port = 0; port < MV_PORTS_PER_HC; port++) 2405 mv5_reset_hc_port(hpriv, mmio, 2406 (hc * MV_PORTS_PER_HC) + port); 2407 2408 mv5_reset_one_hc(hpriv, mmio, hc); 2409 } 2410 2411 return 0; 2412 } 2413 2414 #undef ZERO 2415 #define ZERO(reg) writel(0, mmio + (reg)) 2416 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) 2417 { 2418 struct mv_host_priv *hpriv = host->private_data; 2419 u32 tmp; 2420 2421 tmp = readl(mmio + MV_PCI_MODE_OFS); 2422 tmp &= 0xff00ffff; 2423 writel(tmp, mmio + MV_PCI_MODE_OFS); 2424 2425 ZERO(MV_PCI_DISC_TIMER); 2426 ZERO(MV_PCI_MSI_TRIGGER); 2427 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); 2428 ZERO(MV_PCI_SERR_MASK); 2429 ZERO(hpriv->irq_cause_ofs); 2430 ZERO(hpriv->irq_mask_ofs); 2431 ZERO(MV_PCI_ERR_LOW_ADDRESS); 2432 ZERO(MV_PCI_ERR_HIGH_ADDRESS); 2433 ZERO(MV_PCI_ERR_ATTRIBUTE); 2434 ZERO(MV_PCI_ERR_COMMAND); 2435 } 2436 #undef ZERO 2437 2438 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) 2439 { 2440 u32 tmp; 2441 2442 mv5_reset_flash(hpriv, mmio); 2443 2444 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS); 2445 tmp &= 0x3; 2446 tmp |= (1 << 5) | (1 << 6); 2447 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS); 2448 } 2449 2450 /** 2451 * mv6_reset_hc - Perform the 6xxx global soft reset 2452 * @mmio: base address of the HBA 2453 * 2454 * This routine only applies to 6xxx parts. 2455 * 2456 * LOCKING: 2457 * Inherited from caller. 2458 */ 2459 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, 2460 unsigned int n_hc) 2461 { 2462 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; 2463 int i, rc = 0; 2464 u32 t; 2465 2466 /* Following procedure defined in PCI "main command and status 2467 * register" table. 2468 */ 2469 t = readl(reg); 2470 writel(t | STOP_PCI_MASTER, reg); 2471 2472 for (i = 0; i < 1000; i++) { 2473 udelay(1); 2474 t = readl(reg); 2475 if (PCI_MASTER_EMPTY & t) 2476 break; 2477 } 2478 if (!(PCI_MASTER_EMPTY & t)) { 2479 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); 2480 rc = 1; 2481 goto done; 2482 } 2483 2484 /* set reset */ 2485 i = 5; 2486 do { 2487 writel(t | GLOB_SFT_RST, reg); 2488 t = readl(reg); 2489 udelay(1); 2490 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); 2491 2492 if (!(GLOB_SFT_RST & t)) { 2493 printk(KERN_ERR DRV_NAME ": can't set global reset\n"); 2494 rc = 1; 2495 goto done; 2496 } 2497 2498 /* clear reset and *reenable the PCI master* (not mentioned in spec) */ 2499 i = 5; 2500 do { 2501 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); 2502 t = readl(reg); 2503 udelay(1); 2504 } while ((GLOB_SFT_RST & t) && (i-- > 0)); 2505 2506 if (GLOB_SFT_RST & t) { 2507 printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); 2508 rc = 1; 2509 } 2510 done: 2511 return rc; 2512 } 2513 2514 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, 2515 void __iomem *mmio) 2516 { 2517 void __iomem *port_mmio; 2518 u32 tmp; 2519 2520 tmp = readl(mmio + MV_RESET_CFG_OFS); 2521 if ((tmp & (1 << 0)) == 0) { 2522 hpriv->signal[idx].amps = 0x7 << 8; 2523 hpriv->signal[idx].pre = 0x1 << 5; 2524 return; 2525 } 2526 2527 port_mmio = mv_port_base(mmio, idx); 2528 tmp = readl(port_mmio + PHY_MODE2); 2529 2530 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2531 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2532 } 2533 2534 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) 2535 { 2536 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS); 2537 } 2538 2539 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, 2540 unsigned int port) 2541 { 2542 void __iomem *port_mmio = mv_port_base(mmio, port); 2543 2544 u32 hp_flags = hpriv->hp_flags; 2545 int fix_phy_mode2 = 2546 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2547 int fix_phy_mode4 = 2548 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); 2549 u32 m2, m3; 2550 2551 if (fix_phy_mode2) { 2552 m2 = readl(port_mmio + PHY_MODE2); 2553 m2 &= ~(1 << 16); 2554 m2 |= (1 << 31); 2555 writel(m2, port_mmio + PHY_MODE2); 2556 2557 udelay(200); 2558 2559 m2 = readl(port_mmio + PHY_MODE2); 2560 m2 &= ~((1 << 16) | (1 << 31)); 2561 writel(m2, port_mmio + PHY_MODE2); 2562 2563 udelay(200); 2564 } 2565 2566 /* 2567 * Gen-II/IIe PHY_MODE3 errata RM#2: 2568 * Achieves better receiver noise performance than the h/w default: 2569 */ 2570 m3 = readl(port_mmio + PHY_MODE3); 2571 m3 = (m3 & 0x1f) | (0x5555601 << 5); 2572 2573 /* Guideline 88F5182 (GL# SATA-S11) */ 2574 if (IS_SOC(hpriv)) 2575 m3 &= ~0x1c; 2576 2577 if (fix_phy_mode4) { 2578 u32 m4 = readl(port_mmio + PHY_MODE4); 2579 /* 2580 * Enforce reserved-bit restrictions on GenIIe devices only. 2581 * For earlier chipsets, force only the internal config field 2582 * (workaround for errata FEr SATA#10 part 1). 2583 */ 2584 if (IS_GEN_IIE(hpriv)) 2585 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; 2586 else 2587 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; 2588 writel(m4, port_mmio + PHY_MODE4); 2589 } 2590 /* 2591 * Workaround for 60x1-B2 errata SATA#13: 2592 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, 2593 * so we must always rewrite PHY_MODE3 after PHY_MODE4. 2594 */ 2595 writel(m3, port_mmio + PHY_MODE3); 2596 2597 /* Revert values of pre-emphasis and signal amps to the saved ones */ 2598 m2 = readl(port_mmio + PHY_MODE2); 2599 2600 m2 &= ~MV_M2_PREAMP_MASK; 2601 m2 |= hpriv->signal[port].amps; 2602 m2 |= hpriv->signal[port].pre; 2603 m2 &= ~(1 << 16); 2604 2605 /* according to mvSata 3.6.1, some IIE values are fixed */ 2606 if (IS_GEN_IIE(hpriv)) { 2607 m2 &= ~0xC30FF01F; 2608 m2 |= 0x0000900F; 2609 } 2610 2611 writel(m2, port_mmio + PHY_MODE2); 2612 } 2613 2614 /* TODO: use the generic LED interface to configure the SATA Presence */ 2615 /* & Acitivy LEDs on the board */ 2616 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, 2617 void __iomem *mmio) 2618 { 2619 return; 2620 } 2621 2622 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, 2623 void __iomem *mmio) 2624 { 2625 void __iomem *port_mmio; 2626 u32 tmp; 2627 2628 port_mmio = mv_port_base(mmio, idx); 2629 tmp = readl(port_mmio + PHY_MODE2); 2630 2631 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ 2632 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ 2633 } 2634 2635 #undef ZERO 2636 #define ZERO(reg) writel(0, port_mmio + (reg)) 2637 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, 2638 void __iomem *mmio, unsigned int port) 2639 { 2640 void __iomem *port_mmio = mv_port_base(mmio, port); 2641 2642 mv_reset_channel(hpriv, mmio, port); 2643 2644 ZERO(0x028); /* command */ 2645 writel(0x101f, port_mmio + EDMA_CFG_OFS); 2646 ZERO(0x004); /* timer */ 2647 ZERO(0x008); /* irq err cause */ 2648 ZERO(0x00c); /* irq err mask */ 2649 ZERO(0x010); /* rq bah */ 2650 ZERO(0x014); /* rq inp */ 2651 ZERO(0x018); /* rq outp */ 2652 ZERO(0x01c); /* respq bah */ 2653 ZERO(0x024); /* respq outp */ 2654 ZERO(0x020); /* respq inp */ 2655 ZERO(0x02c); /* test control */ 2656 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); 2657 } 2658 2659 #undef ZERO 2660 2661 #define ZERO(reg) writel(0, hc_mmio + (reg)) 2662 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, 2663 void __iomem *mmio) 2664 { 2665 void __iomem *hc_mmio = mv_hc_base(mmio, 0); 2666 2667 ZERO(0x00c); 2668 ZERO(0x010); 2669 ZERO(0x014); 2670 2671 } 2672 2673 #undef ZERO 2674 2675 static int mv_soc_reset_hc(struct mv_host_priv *hpriv, 2676 void __iomem *mmio, unsigned int n_hc) 2677 { 2678 unsigned int port; 2679 2680 for (port = 0; port < hpriv->n_ports; port++) 2681 mv_soc_reset_hc_port(hpriv, mmio, port); 2682 2683 mv_soc_reset_one_hc(hpriv, mmio); 2684 2685 return 0; 2686 } 2687 2688 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, 2689 void __iomem *mmio) 2690 { 2691 return; 2692 } 2693 2694 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) 2695 { 2696 return; 2697 } 2698 2699 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) 2700 { 2701 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); 2702 2703 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ 2704 if (want_gen2i) 2705 ifcfg |= (1 << 7); /* enable gen2i speed */ 2706 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS); 2707 } 2708 2709 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, 2710 unsigned int port_no) 2711 { 2712 void __iomem *port_mmio = mv_port_base(mmio, port_no); 2713 2714 /* 2715 * The datasheet warns against setting EDMA_RESET when EDMA is active 2716 * (but doesn't say what the problem might be). So we first try 2717 * to disable the EDMA engine before doing the EDMA_RESET operation. 2718 */ 2719 mv_stop_edma_engine(port_mmio); 2720 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2721 2722 if (!IS_GEN_I(hpriv)) { 2723 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ 2724 mv_setup_ifcfg(port_mmio, 1); 2725 } 2726 /* 2727 * Strobing EDMA_RESET here causes a hard reset of the SATA transport, 2728 * link, and physical layers. It resets all SATA interface registers 2729 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. 2730 */ 2731 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); 2732 udelay(25); /* allow reset propagation */ 2733 writelfl(0, port_mmio + EDMA_CMD_OFS); 2734 2735 hpriv->ops->phy_errata(hpriv, mmio, port_no); 2736 2737 if (IS_GEN_I(hpriv)) 2738 mdelay(1); 2739 } 2740 2741 static void mv_pmp_select(struct ata_port *ap, int pmp) 2742 { 2743 if (sata_pmp_supported(ap)) { 2744 void __iomem *port_mmio = mv_ap_base(ap); 2745 u32 reg = readl(port_mmio + SATA_IFCTL_OFS); 2746 int old = reg & 0xf; 2747 2748 if (old != pmp) { 2749 reg = (reg & ~0xf) | pmp; 2750 writelfl(reg, port_mmio + SATA_IFCTL_OFS); 2751 } 2752 } 2753 } 2754 2755 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, 2756 unsigned long deadline) 2757 { 2758 mv_pmp_select(link->ap, sata_srst_pmp(link)); 2759 return sata_std_hardreset(link, class, deadline); 2760 } 2761 2762 static int mv_softreset(struct ata_link *link, unsigned int *class, 2763 unsigned long deadline) 2764 { 2765 mv_pmp_select(link->ap, sata_srst_pmp(link)); 2766 return ata_sff_softreset(link, class, deadline); 2767 } 2768 2769 static int mv_hardreset(struct ata_link *link, unsigned int *class, 2770 unsigned long deadline) 2771 { 2772 struct ata_port *ap = link->ap; 2773 struct mv_host_priv *hpriv = ap->host->private_data; 2774 struct mv_port_priv *pp = ap->private_data; 2775 void __iomem *mmio = hpriv->base; 2776 int rc, attempts = 0, extra = 0; 2777 u32 sstatus; 2778 bool online; 2779 2780 mv_reset_channel(hpriv, mmio, ap->port_no); 2781 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; 2782 2783 /* Workaround for errata FEr SATA#10 (part 2) */ 2784 do { 2785 const unsigned long *timing = 2786 sata_ehc_deb_timing(&link->eh_context); 2787 2788 rc = sata_link_hardreset(link, timing, deadline + extra, 2789 &online, NULL); 2790 rc = online ? -EAGAIN : rc; 2791 if (rc) 2792 return rc; 2793 sata_scr_read(link, SCR_STATUS, &sstatus); 2794 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { 2795 /* Force 1.5gb/s link speed and try again */ 2796 mv_setup_ifcfg(mv_ap_base(ap), 0); 2797 if (time_after(jiffies + HZ, deadline)) 2798 extra = HZ; /* only extend it once, max */ 2799 } 2800 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); 2801 2802 return rc; 2803 } 2804 2805 static void mv_eh_freeze(struct ata_port *ap) 2806 { 2807 mv_stop_edma(ap); 2808 mv_enable_port_irqs(ap, 0); 2809 } 2810 2811 static void mv_eh_thaw(struct ata_port *ap) 2812 { 2813 struct mv_host_priv *hpriv = ap->host->private_data; 2814 unsigned int port = ap->port_no; 2815 unsigned int hardport = mv_hardport_from_port(port); 2816 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); 2817 void __iomem *port_mmio = mv_ap_base(ap); 2818 u32 hc_irq_cause; 2819 2820 /* clear EDMA errors on this port */ 2821 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2822 2823 /* clear pending irq events */ 2824 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); 2825 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport); 2826 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); 2827 2828 mv_enable_port_irqs(ap, ERR_IRQ); 2829 } 2830 2831 /** 2832 * mv_port_init - Perform some early initialization on a single port. 2833 * @port: libata data structure storing shadow register addresses 2834 * @port_mmio: base address of the port 2835 * 2836 * Initialize shadow register mmio addresses, clear outstanding 2837 * interrupts on the port, and unmask interrupts for the future 2838 * start of the port. 2839 * 2840 * LOCKING: 2841 * Inherited from caller. 2842 */ 2843 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) 2844 { 2845 void __iomem *shd_base = port_mmio + SHD_BLK_OFS; 2846 unsigned serr_ofs; 2847 2848 /* PIO related setup 2849 */ 2850 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); 2851 port->error_addr = 2852 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); 2853 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); 2854 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); 2855 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); 2856 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); 2857 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); 2858 port->status_addr = 2859 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); 2860 /* special case: control/altstatus doesn't have ATA_REG_ address */ 2861 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; 2862 2863 /* unused: */ 2864 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; 2865 2866 /* Clear any currently outstanding port interrupt conditions */ 2867 serr_ofs = mv_scr_offset(SCR_ERROR); 2868 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); 2869 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); 2870 2871 /* unmask all non-transient EDMA error interrupts */ 2872 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); 2873 2874 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", 2875 readl(port_mmio + EDMA_CFG_OFS), 2876 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), 2877 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 2878 } 2879 2880 static unsigned int mv_in_pcix_mode(struct ata_host *host) 2881 { 2882 struct mv_host_priv *hpriv = host->private_data; 2883 void __iomem *mmio = hpriv->base; 2884 u32 reg; 2885 2886 if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) 2887 return 0; /* not PCI-X capable */ 2888 reg = readl(mmio + MV_PCI_MODE_OFS); 2889 if ((reg & MV_PCI_MODE_MASK) == 0) 2890 return 0; /* conventional PCI mode */ 2891 return 1; /* chip is in PCI-X mode */ 2892 } 2893 2894 static int mv_pci_cut_through_okay(struct ata_host *host) 2895 { 2896 struct mv_host_priv *hpriv = host->private_data; 2897 void __iomem *mmio = hpriv->base; 2898 u32 reg; 2899 2900 if (!mv_in_pcix_mode(host)) { 2901 reg = readl(mmio + PCI_COMMAND_OFS); 2902 if (reg & PCI_COMMAND_MRDTRIG) 2903 return 0; /* not okay */ 2904 } 2905 return 1; /* okay */ 2906 } 2907 2908 static int mv_chip_id(struct ata_host *host, unsigned int board_idx) 2909 { 2910 struct pci_dev *pdev = to_pci_dev(host->dev); 2911 struct mv_host_priv *hpriv = host->private_data; 2912 u32 hp_flags = hpriv->hp_flags; 2913 2914 switch (board_idx) { 2915 case chip_5080: 2916 hpriv->ops = &mv5xxx_ops; 2917 hp_flags |= MV_HP_GEN_I; 2918 2919 switch (pdev->revision) { 2920 case 0x1: 2921 hp_flags |= MV_HP_ERRATA_50XXB0; 2922 break; 2923 case 0x3: 2924 hp_flags |= MV_HP_ERRATA_50XXB2; 2925 break; 2926 default: 2927 dev_printk(KERN_WARNING, &pdev->dev, 2928 "Applying 50XXB2 workarounds to unknown rev\n"); 2929 hp_flags |= MV_HP_ERRATA_50XXB2; 2930 break; 2931 } 2932 break; 2933 2934 case chip_504x: 2935 case chip_508x: 2936 hpriv->ops = &mv5xxx_ops; 2937 hp_flags |= MV_HP_GEN_I; 2938 2939 switch (pdev->revision) { 2940 case 0x0: 2941 hp_flags |= MV_HP_ERRATA_50XXB0; 2942 break; 2943 case 0x3: 2944 hp_flags |= MV_HP_ERRATA_50XXB2; 2945 break; 2946 default: 2947 dev_printk(KERN_WARNING, &pdev->dev, 2948 "Applying B2 workarounds to unknown rev\n"); 2949 hp_flags |= MV_HP_ERRATA_50XXB2; 2950 break; 2951 } 2952 break; 2953 2954 case chip_604x: 2955 case chip_608x: 2956 hpriv->ops = &mv6xxx_ops; 2957 hp_flags |= MV_HP_GEN_II; 2958 2959 switch (pdev->revision) { 2960 case 0x7: 2961 hp_flags |= MV_HP_ERRATA_60X1B2; 2962 break; 2963 case 0x9: 2964 hp_flags |= MV_HP_ERRATA_60X1C0; 2965 break; 2966 default: 2967 dev_printk(KERN_WARNING, &pdev->dev, 2968 "Applying B2 workarounds to unknown rev\n"); 2969 hp_flags |= MV_HP_ERRATA_60X1B2; 2970 break; 2971 } 2972 break; 2973 2974 case chip_7042: 2975 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; 2976 if (pdev->vendor == PCI_VENDOR_ID_TTI && 2977 (pdev->device == 0x2300 || pdev->device == 0x2310)) 2978 { 2979 /* 2980 * Highpoint RocketRAID PCIe 23xx series cards: 2981 * 2982 * Unconfigured drives are treated as "Legacy" 2983 * by the BIOS, and it overwrites sector 8 with 2984 * a "Lgcy" metadata block prior to Linux boot. 2985 * 2986 * Configured drives (RAID or JBOD) leave sector 8 2987 * alone, but instead overwrite a high numbered 2988 * sector for the RAID metadata. This sector can 2989 * be determined exactly, by truncating the physical 2990 * drive capacity to a nice even GB value. 2991 * 2992 * RAID metadata is at: (dev->n_sectors & ~0xfffff) 2993 * 2994 * Warn the user, lest they think we're just buggy. 2995 */ 2996 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" 2997 " BIOS CORRUPTS DATA on all attached drives," 2998 " regardless of if/how they are configured." 2999 " BEWARE!\n"); 3000 printk(KERN_WARNING DRV_NAME ": For data safety, do not" 3001 " use sectors 8-9 on \"Legacy\" drives," 3002 " and avoid the final two gigabytes on" 3003 " all RocketRAID BIOS initialized drives.\n"); 3004 } 3005 /* drop through */ 3006 case chip_6042: 3007 hpriv->ops = &mv6xxx_ops; 3008 hp_flags |= MV_HP_GEN_IIE; 3009 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) 3010 hp_flags |= MV_HP_CUT_THROUGH; 3011 3012 switch (pdev->revision) { 3013 case 0x2: /* Rev.B0: the first/only public release */ 3014 hp_flags |= MV_HP_ERRATA_60X1C0; 3015 break; 3016 default: 3017 dev_printk(KERN_WARNING, &pdev->dev, 3018 "Applying 60X1C0 workarounds to unknown rev\n"); 3019 hp_flags |= MV_HP_ERRATA_60X1C0; 3020 break; 3021 } 3022 break; 3023 case chip_soc: 3024 hpriv->ops = &mv_soc_ops; 3025 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | 3026 MV_HP_ERRATA_60X1C0; 3027 break; 3028 3029 default: 3030 dev_printk(KERN_ERR, host->dev, 3031 "BUG: invalid board index %u\n", board_idx); 3032 return 1; 3033 } 3034 3035 hpriv->hp_flags = hp_flags; 3036 if (hp_flags & MV_HP_PCIE) { 3037 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; 3038 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; 3039 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; 3040 } else { 3041 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; 3042 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; 3043 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; 3044 } 3045 3046 return 0; 3047 } 3048 3049 /** 3050 * mv_init_host - Perform some early initialization of the host. 3051 * @host: ATA host to initialize 3052 * @board_idx: controller index 3053 * 3054 * If possible, do an early global reset of the host. Then do 3055 * our port init and clear/unmask all/relevant host interrupts. 3056 * 3057 * LOCKING: 3058 * Inherited from caller. 3059 */ 3060 static int mv_init_host(struct ata_host *host, unsigned int board_idx) 3061 { 3062 int rc = 0, n_hc, port, hc; 3063 struct mv_host_priv *hpriv = host->private_data; 3064 void __iomem *mmio = hpriv->base; 3065 3066 rc = mv_chip_id(host, board_idx); 3067 if (rc) 3068 goto done; 3069 3070 if (IS_SOC(hpriv)) { 3071 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; 3072 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; 3073 } else { 3074 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; 3075 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; 3076 } 3077 3078 /* global interrupt mask: 0 == mask everything */ 3079 mv_set_main_irq_mask(host, ~0, 0); 3080 3081 n_hc = mv_get_hc_count(host->ports[0]->flags); 3082 3083 for (port = 0; port < host->n_ports; port++) 3084 hpriv->ops->read_preamp(hpriv, port, mmio); 3085 3086 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 3087 if (rc) 3088 goto done; 3089 3090 hpriv->ops->reset_flash(hpriv, mmio); 3091 hpriv->ops->reset_bus(host, mmio); 3092 hpriv->ops->enable_leds(hpriv, mmio); 3093 3094 for (port = 0; port < host->n_ports; port++) { 3095 struct ata_port *ap = host->ports[port]; 3096 void __iomem *port_mmio = mv_port_base(mmio, port); 3097 3098 mv_port_init(&ap->ioaddr, port_mmio); 3099 3100 #ifdef CONFIG_PCI 3101 if (!IS_SOC(hpriv)) { 3102 unsigned int offset = port_mmio - mmio; 3103 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); 3104 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); 3105 } 3106 #endif 3107 } 3108 3109 for (hc = 0; hc < n_hc; hc++) { 3110 void __iomem *hc_mmio = mv_hc_base(mmio, hc); 3111 3112 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " 3113 "(before clear)=0x%08x\n", hc, 3114 readl(hc_mmio + HC_CFG_OFS), 3115 readl(hc_mmio + HC_IRQ_CAUSE_OFS)); 3116 3117 /* Clear any currently outstanding hc interrupt conditions */ 3118 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); 3119 } 3120 3121 if (!IS_SOC(hpriv)) { 3122 /* Clear any currently outstanding host interrupt conditions */ 3123 writelfl(0, mmio + hpriv->irq_cause_ofs); 3124 3125 /* and unmask interrupt generation for host regs */ 3126 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); 3127 3128 /* 3129 * enable only global host interrupts for now. 3130 * The per-port interrupts get done later as ports are set up. 3131 */ 3132 mv_set_main_irq_mask(host, 0, PCI_ERR); 3133 } 3134 done: 3135 return rc; 3136 } 3137 3138 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) 3139 { 3140 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, 3141 MV_CRQB_Q_SZ, 0); 3142 if (!hpriv->crqb_pool) 3143 return -ENOMEM; 3144 3145 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, 3146 MV_CRPB_Q_SZ, 0); 3147 if (!hpriv->crpb_pool) 3148 return -ENOMEM; 3149 3150 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, 3151 MV_SG_TBL_SZ, 0); 3152 if (!hpriv->sg_tbl_pool) 3153 return -ENOMEM; 3154 3155 return 0; 3156 } 3157 3158 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, 3159 struct mbus_dram_target_info *dram) 3160 { 3161 int i; 3162 3163 for (i = 0; i < 4; i++) { 3164 writel(0, hpriv->base + WINDOW_CTRL(i)); 3165 writel(0, hpriv->base + WINDOW_BASE(i)); 3166 } 3167 3168 for (i = 0; i < dram->num_cs; i++) { 3169 struct mbus_dram_window *cs = dram->cs + i; 3170 3171 writel(((cs->size - 1) & 0xffff0000) | 3172 (cs->mbus_attr << 8) | 3173 (dram->mbus_dram_target_id << 4) | 1, 3174 hpriv->base + WINDOW_CTRL(i)); 3175 writel(cs->base, hpriv->base + WINDOW_BASE(i)); 3176 } 3177 } 3178 3179 /** 3180 * mv_platform_probe - handle a positive probe of an soc Marvell 3181 * host 3182 * @pdev: platform device found 3183 * 3184 * LOCKING: 3185 * Inherited from caller. 3186 */ 3187 static int mv_platform_probe(struct platform_device *pdev) 3188 { 3189 static int printed_version; 3190 const struct mv_sata_platform_data *mv_platform_data; 3191 const struct ata_port_info *ppi[] = 3192 { &mv_port_info[chip_soc], NULL }; 3193 struct ata_host *host; 3194 struct mv_host_priv *hpriv; 3195 struct resource *res; 3196 int n_ports, rc; 3197 3198 if (!printed_version++) 3199 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3200 3201 /* 3202 * Simple resource validation .. 3203 */ 3204 if (unlikely(pdev->num_resources != 2)) { 3205 dev_err(&pdev->dev, "invalid number of resources\n"); 3206 return -EINVAL; 3207 } 3208 3209 /* 3210 * Get the register base first 3211 */ 3212 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3213 if (res == NULL) 3214 return -EINVAL; 3215 3216 /* allocate host */ 3217 mv_platform_data = pdev->dev.platform_data; 3218 n_ports = mv_platform_data->n_ports; 3219 3220 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3221 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3222 3223 if (!host || !hpriv) 3224 return -ENOMEM; 3225 host->private_data = hpriv; 3226 hpriv->n_ports = n_ports; 3227 3228 host->iomap = NULL; 3229 hpriv->base = devm_ioremap(&pdev->dev, res->start, 3230 res->end - res->start + 1); 3231 hpriv->base -= MV_SATAHC0_REG_BASE; 3232 3233 /* 3234 * (Re-)program MBUS remapping windows if we are asked to. 3235 */ 3236 if (mv_platform_data->dram != NULL) 3237 mv_conf_mbus_windows(hpriv, mv_platform_data->dram); 3238 3239 rc = mv_create_dma_pools(hpriv, &pdev->dev); 3240 if (rc) 3241 return rc; 3242 3243 /* initialize adapter */ 3244 rc = mv_init_host(host, chip_soc); 3245 if (rc) 3246 return rc; 3247 3248 dev_printk(KERN_INFO, &pdev->dev, 3249 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, 3250 host->n_ports); 3251 3252 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, 3253 IRQF_SHARED, &mv6_sht); 3254 } 3255 3256 /* 3257 * 3258 * mv_platform_remove - unplug a platform interface 3259 * @pdev: platform device 3260 * 3261 * A platform bus SATA device has been unplugged. Perform the needed 3262 * cleanup. Also called on module unload for any active devices. 3263 */ 3264 static int __devexit mv_platform_remove(struct platform_device *pdev) 3265 { 3266 struct device *dev = &pdev->dev; 3267 struct ata_host *host = dev_get_drvdata(dev); 3268 3269 ata_host_detach(host); 3270 return 0; 3271 } 3272 3273 static struct platform_driver mv_platform_driver = { 3274 .probe = mv_platform_probe, 3275 .remove = __devexit_p(mv_platform_remove), 3276 .driver = { 3277 .name = DRV_NAME, 3278 .owner = THIS_MODULE, 3279 }, 3280 }; 3281 3282 3283 #ifdef CONFIG_PCI 3284 static int mv_pci_init_one(struct pci_dev *pdev, 3285 const struct pci_device_id *ent); 3286 3287 3288 static struct pci_driver mv_pci_driver = { 3289 .name = DRV_NAME, 3290 .id_table = mv_pci_tbl, 3291 .probe = mv_pci_init_one, 3292 .remove = ata_pci_remove_one, 3293 }; 3294 3295 /* 3296 * module options 3297 */ 3298 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */ 3299 3300 3301 /* move to PCI layer or libata core? */ 3302 static int pci_go_64(struct pci_dev *pdev) 3303 { 3304 int rc; 3305 3306 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 3307 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 3308 if (rc) { 3309 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 3310 if (rc) { 3311 dev_printk(KERN_ERR, &pdev->dev, 3312 "64-bit DMA enable failed\n"); 3313 return rc; 3314 } 3315 } 3316 } else { 3317 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 3318 if (rc) { 3319 dev_printk(KERN_ERR, &pdev->dev, 3320 "32-bit DMA enable failed\n"); 3321 return rc; 3322 } 3323 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 3324 if (rc) { 3325 dev_printk(KERN_ERR, &pdev->dev, 3326 "32-bit consistent DMA enable failed\n"); 3327 return rc; 3328 } 3329 } 3330 3331 return rc; 3332 } 3333 3334 /** 3335 * mv_print_info - Dump key info to kernel log for perusal. 3336 * @host: ATA host to print info about 3337 * 3338 * FIXME: complete this. 3339 * 3340 * LOCKING: 3341 * Inherited from caller. 3342 */ 3343 static void mv_print_info(struct ata_host *host) 3344 { 3345 struct pci_dev *pdev = to_pci_dev(host->dev); 3346 struct mv_host_priv *hpriv = host->private_data; 3347 u8 scc; 3348 const char *scc_s, *gen; 3349 3350 /* Use this to determine the HW stepping of the chip so we know 3351 * what errata to workaround 3352 */ 3353 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); 3354 if (scc == 0) 3355 scc_s = "SCSI"; 3356 else if (scc == 0x01) 3357 scc_s = "RAID"; 3358 else 3359 scc_s = "?"; 3360 3361 if (IS_GEN_I(hpriv)) 3362 gen = "I"; 3363 else if (IS_GEN_II(hpriv)) 3364 gen = "II"; 3365 else if (IS_GEN_IIE(hpriv)) 3366 gen = "IIE"; 3367 else 3368 gen = "?"; 3369 3370 dev_printk(KERN_INFO, &pdev->dev, 3371 "Gen-%s %u slots %u ports %s mode IRQ via %s\n", 3372 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, 3373 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 3374 } 3375 3376 /** 3377 * mv_pci_init_one - handle a positive probe of a PCI Marvell host 3378 * @pdev: PCI device found 3379 * @ent: PCI device ID entry for the matched host 3380 * 3381 * LOCKING: 3382 * Inherited from caller. 3383 */ 3384 static int mv_pci_init_one(struct pci_dev *pdev, 3385 const struct pci_device_id *ent) 3386 { 3387 static int printed_version; 3388 unsigned int board_idx = (unsigned int)ent->driver_data; 3389 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; 3390 struct ata_host *host; 3391 struct mv_host_priv *hpriv; 3392 int n_ports, rc; 3393 3394 if (!printed_version++) 3395 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 3396 3397 /* allocate host */ 3398 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; 3399 3400 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); 3401 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 3402 if (!host || !hpriv) 3403 return -ENOMEM; 3404 host->private_data = hpriv; 3405 hpriv->n_ports = n_ports; 3406 3407 /* acquire resources */ 3408 rc = pcim_enable_device(pdev); 3409 if (rc) 3410 return rc; 3411 3412 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 3413 if (rc == -EBUSY) 3414 pcim_pin_device(pdev); 3415 if (rc) 3416 return rc; 3417 host->iomap = pcim_iomap_table(pdev); 3418 hpriv->base = host->iomap[MV_PRIMARY_BAR]; 3419 3420 rc = pci_go_64(pdev); 3421 if (rc) 3422 return rc; 3423 3424 rc = mv_create_dma_pools(hpriv, &pdev->dev); 3425 if (rc) 3426 return rc; 3427 3428 /* initialize adapter */ 3429 rc = mv_init_host(host, board_idx); 3430 if (rc) 3431 return rc; 3432 3433 /* Enable interrupts */ 3434 if (msi && pci_enable_msi(pdev)) 3435 pci_intx(pdev, 1); 3436 3437 mv_dump_pci_cfg(pdev, 0x68); 3438 mv_print_info(host); 3439 3440 pci_set_master(pdev); 3441 pci_try_set_mwi(pdev); 3442 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, 3443 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); 3444 } 3445 #endif 3446 3447 static int mv_platform_probe(struct platform_device *pdev); 3448 static int __devexit mv_platform_remove(struct platform_device *pdev); 3449 3450 static int __init mv_init(void) 3451 { 3452 int rc = -ENODEV; 3453 #ifdef CONFIG_PCI 3454 rc = pci_register_driver(&mv_pci_driver); 3455 if (rc < 0) 3456 return rc; 3457 #endif 3458 rc = platform_driver_register(&mv_platform_driver); 3459 3460 #ifdef CONFIG_PCI 3461 if (rc < 0) 3462 pci_unregister_driver(&mv_pci_driver); 3463 #endif 3464 return rc; 3465 } 3466 3467 static void __exit mv_exit(void) 3468 { 3469 #ifdef CONFIG_PCI 3470 pci_unregister_driver(&mv_pci_driver); 3471 #endif 3472 platform_driver_unregister(&mv_platform_driver); 3473 } 3474 3475 MODULE_AUTHOR("Brett Russ"); 3476 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); 3477 MODULE_LICENSE("GPL"); 3478 MODULE_DEVICE_TABLE(pci, mv_pci_tbl); 3479 MODULE_VERSION(DRV_VERSION); 3480 MODULE_ALIAS("platform:" DRV_NAME); 3481 3482 #ifdef CONFIG_PCI 3483 module_param(msi, int, 0444); 3484 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); 3485 #endif 3486 3487 module_init(mv_init); 3488 module_exit(mv_exit); 3489