1 /* 2 * sata_inic162x.c - Driver for Initio 162x SATA controllers 3 * 4 * Copyright 2006 SUSE Linux Products GmbH 5 * Copyright 2006 Tejun Heo <teheo@novell.com> 6 * 7 * This file is released under GPL v2. 8 * 9 * This controller is eccentric and easily locks up if something isn't 10 * right. Documentation is available at initio's website but it only 11 * documents registers (not programming model). 12 * 13 * - ATA disks work. 14 * - Hotplug works. 15 * - ATAPI read works but burning doesn't. This thing is really 16 * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and 17 * ATAPI DMA WRITE should be programmed. If you've got a clue, be 18 * my guest. 19 * - Both STR and STD work. 20 */ 21 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <scsi/scsi_host.h> 26 #include <linux/libata.h> 27 #include <linux/blkdev.h> 28 #include <scsi/scsi_device.h> 29 30 #define DRV_NAME "sata_inic162x" 31 #define DRV_VERSION "0.1" 32 33 enum { 34 MMIO_BAR = 5, 35 36 NR_PORTS = 2, 37 38 HOST_CTL = 0x7c, 39 HOST_STAT = 0x7e, 40 HOST_IRQ_STAT = 0xbc, 41 HOST_IRQ_MASK = 0xbe, 42 43 PORT_SIZE = 0x40, 44 45 /* registers for ATA TF operation */ 46 PORT_TF = 0x00, 47 PORT_ALT_STAT = 0x08, 48 PORT_IRQ_STAT = 0x09, 49 PORT_IRQ_MASK = 0x0a, 50 PORT_PRD_CTL = 0x0b, 51 PORT_PRD_ADDR = 0x0c, 52 PORT_PRD_XFERLEN = 0x10, 53 54 /* IDMA register */ 55 PORT_IDMA_CTL = 0x14, 56 57 PORT_SCR = 0x20, 58 59 /* HOST_CTL bits */ 60 HCTL_IRQOFF = (1 << 8), /* global IRQ off */ 61 HCTL_PWRDWN = (1 << 13), /* power down PHYs */ 62 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */ 63 HCTL_RPGSEL = (1 << 15), /* register page select */ 64 65 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST | 66 HCTL_RPGSEL, 67 68 /* HOST_IRQ_(STAT|MASK) bits */ 69 HIRQ_PORT0 = (1 << 0), 70 HIRQ_PORT1 = (1 << 1), 71 HIRQ_SOFT = (1 << 14), 72 HIRQ_GLOBAL = (1 << 15), /* STAT only */ 73 74 /* PORT_IRQ_(STAT|MASK) bits */ 75 PIRQ_OFFLINE = (1 << 0), /* device unplugged */ 76 PIRQ_ONLINE = (1 << 1), /* device plugged */ 77 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */ 78 PIRQ_FATAL = (1 << 3), /* fatal error */ 79 PIRQ_ATA = (1 << 4), /* ATA interrupt */ 80 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */ 81 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */ 82 83 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL, 84 85 PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA, 86 PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE, 87 PIRQ_MASK_FREEZE = 0xff, 88 89 /* PORT_PRD_CTL bits */ 90 PRD_CTL_START = (1 << 0), 91 PRD_CTL_WR = (1 << 3), 92 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */ 93 94 /* PORT_IDMA_CTL bits */ 95 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */ 96 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */ 97 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */ 98 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */ 99 }; 100 101 struct inic_host_priv { 102 u16 cached_hctl; 103 }; 104 105 struct inic_port_priv { 106 u8 dfl_prdctl; 107 u8 cached_prdctl; 108 u8 cached_pirq_mask; 109 }; 110 111 static int inic_slave_config(struct scsi_device *sdev) 112 { 113 /* This controller is braindamaged. dma_boundary is 0xffff 114 * like others but it will lock up the whole machine HARD if 115 * 65536 byte PRD entry is fed. Reduce maximum segment size. 116 */ 117 blk_queue_max_segment_size(sdev->request_queue, 65536 - 512); 118 119 return ata_scsi_slave_config(sdev); 120 } 121 122 static struct scsi_host_template inic_sht = { 123 .module = THIS_MODULE, 124 .name = DRV_NAME, 125 .ioctl = ata_scsi_ioctl, 126 .queuecommand = ata_scsi_queuecmd, 127 .can_queue = ATA_DEF_QUEUE, 128 .this_id = ATA_SHT_THIS_ID, 129 .sg_tablesize = LIBATA_MAX_PRD, 130 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 131 .emulated = ATA_SHT_EMULATED, 132 .use_clustering = ATA_SHT_USE_CLUSTERING, 133 .proc_name = DRV_NAME, 134 .dma_boundary = ATA_DMA_BOUNDARY, 135 .slave_configure = inic_slave_config, 136 .slave_destroy = ata_scsi_slave_destroy, 137 .bios_param = ata_std_bios_param, 138 #ifdef CONFIG_PM 139 .suspend = ata_scsi_device_suspend, 140 .resume = ata_scsi_device_resume, 141 #endif 142 }; 143 144 static const int scr_map[] = { 145 [SCR_STATUS] = 0, 146 [SCR_ERROR] = 1, 147 [SCR_CONTROL] = 2, 148 }; 149 150 static void __iomem * inic_port_base(struct ata_port *ap) 151 { 152 return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE; 153 } 154 155 static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask) 156 { 157 void __iomem *port_base = inic_port_base(ap); 158 struct inic_port_priv *pp = ap->private_data; 159 160 writeb(mask, port_base + PORT_IRQ_MASK); 161 pp->cached_pirq_mask = mask; 162 } 163 164 static void inic_set_pirq_mask(struct ata_port *ap, u8 mask) 165 { 166 struct inic_port_priv *pp = ap->private_data; 167 168 if (pp->cached_pirq_mask != mask) 169 __inic_set_pirq_mask(ap, mask); 170 } 171 172 static void inic_reset_port(void __iomem *port_base) 173 { 174 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; 175 u16 ctl; 176 177 ctl = readw(idma_ctl); 178 ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO); 179 180 /* mask IRQ and assert reset */ 181 writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl); 182 readw(idma_ctl); /* flush */ 183 184 /* give it some time */ 185 msleep(1); 186 187 /* release reset */ 188 writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl); 189 190 /* clear irq */ 191 writeb(0xff, port_base + PORT_IRQ_STAT); 192 193 /* reenable ATA IRQ, turn off IDMA mode */ 194 writew(ctl, idma_ctl); 195 } 196 197 static u32 inic_scr_read(struct ata_port *ap, unsigned sc_reg) 198 { 199 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; 200 void __iomem *addr; 201 u32 val; 202 203 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) 204 return 0xffffffffU; 205 206 addr = scr_addr + scr_map[sc_reg] * 4; 207 val = readl(scr_addr + scr_map[sc_reg] * 4); 208 209 /* this controller has stuck DIAG.N, ignore it */ 210 if (sc_reg == SCR_ERROR) 211 val &= ~SERR_PHYRDY_CHG; 212 return val; 213 } 214 215 static void inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) 216 { 217 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; 218 void __iomem *addr; 219 220 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map))) 221 return; 222 223 addr = scr_addr + scr_map[sc_reg] * 4; 224 writel(val, scr_addr + scr_map[sc_reg] * 4); 225 } 226 227 /* 228 * In TF mode, inic162x is very similar to SFF device. TF registers 229 * function the same. DMA engine behaves similary using the same PRD 230 * format as BMDMA but different command register, interrupt and event 231 * notification methods are used. The following inic_bmdma_*() 232 * functions do the impedance matching. 233 */ 234 static void inic_bmdma_setup(struct ata_queued_cmd *qc) 235 { 236 struct ata_port *ap = qc->ap; 237 struct inic_port_priv *pp = ap->private_data; 238 void __iomem *port_base = inic_port_base(ap); 239 int rw = qc->tf.flags & ATA_TFLAG_WRITE; 240 241 /* make sure device sees PRD table writes */ 242 wmb(); 243 244 /* load transfer length */ 245 writel(qc->nbytes, port_base + PORT_PRD_XFERLEN); 246 247 /* turn on DMA and specify data direction */ 248 pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN; 249 if (!rw) 250 pp->cached_prdctl |= PRD_CTL_WR; 251 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL); 252 253 /* issue r/w command */ 254 ap->ops->exec_command(ap, &qc->tf); 255 } 256 257 static void inic_bmdma_start(struct ata_queued_cmd *qc) 258 { 259 struct ata_port *ap = qc->ap; 260 struct inic_port_priv *pp = ap->private_data; 261 void __iomem *port_base = inic_port_base(ap); 262 263 /* start host DMA transaction */ 264 pp->cached_prdctl |= PRD_CTL_START; 265 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL); 266 } 267 268 static void inic_bmdma_stop(struct ata_queued_cmd *qc) 269 { 270 struct ata_port *ap = qc->ap; 271 struct inic_port_priv *pp = ap->private_data; 272 void __iomem *port_base = inic_port_base(ap); 273 274 /* stop DMA engine */ 275 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL); 276 } 277 278 static u8 inic_bmdma_status(struct ata_port *ap) 279 { 280 /* event is already verified by the interrupt handler */ 281 return ATA_DMA_INTR; 282 } 283 284 static void inic_irq_clear(struct ata_port *ap) 285 { 286 /* noop */ 287 } 288 289 static void inic_host_intr(struct ata_port *ap) 290 { 291 void __iomem *port_base = inic_port_base(ap); 292 struct ata_eh_info *ehi = &ap->eh_info; 293 u8 irq_stat; 294 295 /* fetch and clear irq */ 296 irq_stat = readb(port_base + PORT_IRQ_STAT); 297 writeb(irq_stat, port_base + PORT_IRQ_STAT); 298 299 if (likely(!(irq_stat & PIRQ_ERR))) { 300 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); 301 302 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { 303 ata_chk_status(ap); /* clear ATA interrupt */ 304 return; 305 } 306 307 if (likely(ata_host_intr(ap, qc))) 308 return; 309 310 ata_chk_status(ap); /* clear ATA interrupt */ 311 ata_port_printk(ap, KERN_WARNING, "unhandled " 312 "interrupt, irq_stat=%x\n", irq_stat); 313 return; 314 } 315 316 /* error */ 317 ata_ehi_push_desc(ehi, "irq_stat=0x%x", irq_stat); 318 319 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) { 320 ata_ehi_hotplugged(ehi); 321 ata_port_freeze(ap); 322 } else 323 ata_port_abort(ap); 324 } 325 326 static irqreturn_t inic_interrupt(int irq, void *dev_instance) 327 { 328 struct ata_host *host = dev_instance; 329 void __iomem *mmio_base = host->iomap[MMIO_BAR]; 330 u16 host_irq_stat; 331 int i, handled = 0;; 332 333 host_irq_stat = readw(mmio_base + HOST_IRQ_STAT); 334 335 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL))) 336 goto out; 337 338 spin_lock(&host->lock); 339 340 for (i = 0; i < NR_PORTS; i++) { 341 struct ata_port *ap = host->ports[i]; 342 343 if (!(host_irq_stat & (HIRQ_PORT0 << i))) 344 continue; 345 346 if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) { 347 inic_host_intr(ap); 348 handled++; 349 } else { 350 if (ata_ratelimit()) 351 dev_printk(KERN_ERR, host->dev, "interrupt " 352 "from disabled port %d (0x%x)\n", 353 i, host_irq_stat); 354 } 355 } 356 357 spin_unlock(&host->lock); 358 359 out: 360 return IRQ_RETVAL(handled); 361 } 362 363 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc) 364 { 365 struct ata_port *ap = qc->ap; 366 367 /* ATA IRQ doesn't wait for DMA transfer completion and vice 368 * versa. Mask IRQ selectively to detect command completion. 369 * Without it, ATA DMA read command can cause data corruption. 370 * 371 * Something similar might be needed for ATAPI writes. I 372 * tried a lot of combinations but couldn't find the solution. 373 */ 374 if (qc->tf.protocol == ATA_PROT_DMA && 375 !(qc->tf.flags & ATA_TFLAG_WRITE)) 376 inic_set_pirq_mask(ap, PIRQ_MASK_DMA_READ); 377 else 378 inic_set_pirq_mask(ap, PIRQ_MASK_OTHER); 379 380 /* Issuing a command to yet uninitialized port locks up the 381 * controller. Most of the time, this happens for the first 382 * command after reset which are ATA and ATAPI IDENTIFYs. 383 * Fast fail if stat is 0x7f or 0xff for those commands. 384 */ 385 if (unlikely(qc->tf.command == ATA_CMD_ID_ATA || 386 qc->tf.command == ATA_CMD_ID_ATAPI)) { 387 u8 stat = ata_chk_status(ap); 388 if (stat == 0x7f || stat == 0xff) 389 return AC_ERR_HSM; 390 } 391 392 return ata_qc_issue_prot(qc); 393 } 394 395 static void inic_freeze(struct ata_port *ap) 396 { 397 void __iomem *port_base = inic_port_base(ap); 398 399 __inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE); 400 401 ata_chk_status(ap); 402 writeb(0xff, port_base + PORT_IRQ_STAT); 403 404 readb(port_base + PORT_IRQ_STAT); /* flush */ 405 } 406 407 static void inic_thaw(struct ata_port *ap) 408 { 409 void __iomem *port_base = inic_port_base(ap); 410 411 ata_chk_status(ap); 412 writeb(0xff, port_base + PORT_IRQ_STAT); 413 414 __inic_set_pirq_mask(ap, PIRQ_MASK_OTHER); 415 416 readb(port_base + PORT_IRQ_STAT); /* flush */ 417 } 418 419 /* 420 * SRST and SControl hardreset don't give valid signature on this 421 * controller. Only controller specific hardreset mechanism works. 422 */ 423 static int inic_hardreset(struct ata_port *ap, unsigned int *class) 424 { 425 void __iomem *port_base = inic_port_base(ap); 426 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL; 427 const unsigned long *timing = sata_ehc_deb_timing(&ap->eh_context); 428 u16 val; 429 int rc; 430 431 /* hammer it into sane state */ 432 inic_reset_port(port_base); 433 434 val = readw(idma_ctl); 435 writew(val | IDMA_CTL_RST_ATA, idma_ctl); 436 readw(idma_ctl); /* flush */ 437 msleep(1); 438 writew(val & ~IDMA_CTL_RST_ATA, idma_ctl); 439 440 rc = sata_phy_resume(ap, timing); 441 if (rc) { 442 ata_port_printk(ap, KERN_WARNING, "failed to resume " 443 "link after reset (errno=%d)\n", rc); 444 return rc; 445 } 446 447 *class = ATA_DEV_NONE; 448 if (ata_port_online(ap)) { 449 struct ata_taskfile tf; 450 451 /* wait a while before checking status */ 452 msleep(150); 453 454 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) { 455 ata_port_printk(ap, KERN_WARNING, 456 "device busy after hardreset\n"); 457 return -EIO; 458 } 459 460 ata_tf_read(ap, &tf); 461 *class = ata_dev_classify(&tf); 462 if (*class == ATA_DEV_UNKNOWN) 463 *class = ATA_DEV_NONE; 464 } 465 466 return 0; 467 } 468 469 static void inic_error_handler(struct ata_port *ap) 470 { 471 void __iomem *port_base = inic_port_base(ap); 472 struct inic_port_priv *pp = ap->private_data; 473 unsigned long flags; 474 475 /* reset PIO HSM and stop DMA engine */ 476 inic_reset_port(port_base); 477 478 spin_lock_irqsave(ap->lock, flags); 479 ap->hsm_task_state = HSM_ST_IDLE; 480 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL); 481 spin_unlock_irqrestore(ap->lock, flags); 482 483 /* PIO and DMA engines have been stopped, perform recovery */ 484 ata_do_eh(ap, ata_std_prereset, NULL, inic_hardreset, 485 ata_std_postreset); 486 } 487 488 static void inic_post_internal_cmd(struct ata_queued_cmd *qc) 489 { 490 /* make DMA engine forget about the failed command */ 491 if (qc->err_mask) 492 inic_reset_port(inic_port_base(qc->ap)); 493 } 494 495 static void inic_dev_config(struct ata_port *ap, struct ata_device *dev) 496 { 497 /* inic can only handle upto LBA28 max sectors */ 498 if (dev->max_sectors > ATA_MAX_SECTORS) 499 dev->max_sectors = ATA_MAX_SECTORS; 500 } 501 502 static void init_port(struct ata_port *ap) 503 { 504 void __iomem *port_base = inic_port_base(ap); 505 506 /* Setup PRD address */ 507 writel(ap->prd_dma, port_base + PORT_PRD_ADDR); 508 } 509 510 static int inic_port_resume(struct ata_port *ap) 511 { 512 init_port(ap); 513 return 0; 514 } 515 516 static int inic_port_start(struct ata_port *ap) 517 { 518 void __iomem *port_base = inic_port_base(ap); 519 struct inic_port_priv *pp; 520 u8 tmp; 521 int rc; 522 523 /* alloc and initialize private data */ 524 pp = devm_kzalloc(ap->host->dev, sizeof(*pp), GFP_KERNEL); 525 if (!pp) 526 return -ENOMEM; 527 ap->private_data = pp; 528 529 /* default PRD_CTL value, DMAEN, WR and START off */ 530 tmp = readb(port_base + PORT_PRD_CTL); 531 tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START); 532 pp->dfl_prdctl = tmp; 533 534 /* Alloc resources */ 535 rc = ata_port_start(ap); 536 if (rc) { 537 kfree(pp); 538 return rc; 539 } 540 541 init_port(ap); 542 543 return 0; 544 } 545 546 static struct ata_port_operations inic_port_ops = { 547 .port_disable = ata_port_disable, 548 .tf_load = ata_tf_load, 549 .tf_read = ata_tf_read, 550 .check_status = ata_check_status, 551 .exec_command = ata_exec_command, 552 .dev_select = ata_std_dev_select, 553 554 .scr_read = inic_scr_read, 555 .scr_write = inic_scr_write, 556 557 .bmdma_setup = inic_bmdma_setup, 558 .bmdma_start = inic_bmdma_start, 559 .bmdma_stop = inic_bmdma_stop, 560 .bmdma_status = inic_bmdma_status, 561 562 .irq_handler = inic_interrupt, 563 .irq_clear = inic_irq_clear, 564 .irq_on = ata_irq_on, 565 .irq_ack = ata_irq_ack, 566 567 .qc_prep = ata_qc_prep, 568 .qc_issue = inic_qc_issue, 569 .data_xfer = ata_data_xfer, 570 571 .freeze = inic_freeze, 572 .thaw = inic_thaw, 573 .error_handler = inic_error_handler, 574 .post_internal_cmd = inic_post_internal_cmd, 575 .dev_config = inic_dev_config, 576 577 .port_resume = inic_port_resume, 578 579 .port_start = inic_port_start, 580 }; 581 582 static struct ata_port_info inic_port_info = { 583 .sht = &inic_sht, 584 /* For some reason, ATA_PROT_ATAPI is broken on this 585 * controller, and no, PIO_POLLING does't fix it. It somehow 586 * manages to report the wrong ireason and ignoring ireason 587 * results in machine lock up. Tell libata to always prefer 588 * DMA. 589 */ 590 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, 591 .pio_mask = 0x1f, /* pio0-4 */ 592 .mwdma_mask = 0x07, /* mwdma0-2 */ 593 .udma_mask = 0x7f, /* udma0-6 */ 594 .port_ops = &inic_port_ops 595 }; 596 597 static int init_controller(void __iomem *mmio_base, u16 hctl) 598 { 599 int i; 600 u16 val; 601 602 hctl &= ~HCTL_KNOWN_BITS; 603 604 /* Soft reset whole controller. Spec says reset duration is 3 605 * PCI clocks, be generous and give it 10ms. 606 */ 607 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); 608 readw(mmio_base + HOST_CTL); /* flush */ 609 610 for (i = 0; i < 10; i++) { 611 msleep(1); 612 val = readw(mmio_base + HOST_CTL); 613 if (!(val & HCTL_SOFTRST)) 614 break; 615 } 616 617 if (val & HCTL_SOFTRST) 618 return -EIO; 619 620 /* mask all interrupts and reset ports */ 621 for (i = 0; i < NR_PORTS; i++) { 622 void __iomem *port_base = mmio_base + i * PORT_SIZE; 623 624 writeb(0xff, port_base + PORT_IRQ_MASK); 625 inic_reset_port(port_base); 626 } 627 628 /* port IRQ is masked now, unmask global IRQ */ 629 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); 630 val = readw(mmio_base + HOST_IRQ_MASK); 631 val &= ~(HIRQ_PORT0 | HIRQ_PORT1); 632 writew(val, mmio_base + HOST_IRQ_MASK); 633 634 return 0; 635 } 636 637 #ifdef CONFIG_PM 638 static int inic_pci_device_resume(struct pci_dev *pdev) 639 { 640 struct ata_host *host = dev_get_drvdata(&pdev->dev); 641 struct inic_host_priv *hpriv = host->private_data; 642 void __iomem *mmio_base = host->iomap[MMIO_BAR]; 643 int rc; 644 645 ata_pci_device_do_resume(pdev); 646 647 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 648 rc = init_controller(mmio_base, hpriv->cached_hctl); 649 if (rc) 650 return rc; 651 } 652 653 ata_host_resume(host); 654 655 return 0; 656 } 657 #endif 658 659 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 660 { 661 static int printed_version; 662 struct ata_port_info *pinfo = &inic_port_info; 663 struct ata_probe_ent *probe_ent; 664 struct inic_host_priv *hpriv; 665 void __iomem * const *iomap; 666 int i, rc; 667 668 if (!printed_version++) 669 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 670 671 rc = pcim_enable_device(pdev); 672 if (rc) 673 return rc; 674 675 rc = pci_request_regions(pdev, DRV_NAME); 676 if (rc) 677 return rc; 678 679 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); 680 if (rc) 681 return rc; 682 iomap = pcim_iomap_table(pdev); 683 684 /* Set dma_mask. This devices doesn't support 64bit addressing. */ 685 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 686 if (rc) { 687 dev_printk(KERN_ERR, &pdev->dev, 688 "32-bit DMA enable failed\n"); 689 return rc; 690 } 691 692 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 693 if (rc) { 694 dev_printk(KERN_ERR, &pdev->dev, 695 "32-bit consistent DMA enable failed\n"); 696 return rc; 697 } 698 699 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); 700 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); 701 if (!probe_ent || !hpriv) 702 return -ENOMEM; 703 704 probe_ent->dev = &pdev->dev; 705 INIT_LIST_HEAD(&probe_ent->node); 706 707 probe_ent->sht = pinfo->sht; 708 probe_ent->port_flags = pinfo->flags; 709 probe_ent->pio_mask = pinfo->pio_mask; 710 probe_ent->mwdma_mask = pinfo->mwdma_mask; 711 probe_ent->udma_mask = pinfo->udma_mask; 712 probe_ent->port_ops = pinfo->port_ops; 713 probe_ent->n_ports = NR_PORTS; 714 715 probe_ent->irq = pdev->irq; 716 probe_ent->irq_flags = IRQF_SHARED; 717 718 probe_ent->iomap = iomap; 719 720 for (i = 0; i < NR_PORTS; i++) { 721 struct ata_ioports *port = &probe_ent->port[i]; 722 void __iomem *port_base = iomap[MMIO_BAR] + i * PORT_SIZE; 723 724 port->cmd_addr = iomap[2 * i]; 725 port->altstatus_addr = 726 port->ctl_addr = (void __iomem *) 727 ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS); 728 port->scr_addr = port_base + PORT_SCR; 729 730 ata_std_ports(port); 731 } 732 733 probe_ent->private_data = hpriv; 734 hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL); 735 736 rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl); 737 if (rc) { 738 dev_printk(KERN_ERR, &pdev->dev, 739 "failed to initialize controller\n"); 740 return rc; 741 } 742 743 pci_set_master(pdev); 744 745 if (!ata_device_add(probe_ent)) 746 return -ENODEV; 747 748 devm_kfree(&pdev->dev, probe_ent); 749 750 return 0; 751 } 752 753 static const struct pci_device_id inic_pci_tbl[] = { 754 { PCI_VDEVICE(INIT, 0x1622), }, 755 { }, 756 }; 757 758 static struct pci_driver inic_pci_driver = { 759 .name = DRV_NAME, 760 .id_table = inic_pci_tbl, 761 #ifdef CONFIG_PM 762 .suspend = ata_pci_device_suspend, 763 .resume = inic_pci_device_resume, 764 #endif 765 .probe = inic_init_one, 766 .remove = ata_pci_remove_one, 767 }; 768 769 static int __init inic_init(void) 770 { 771 return pci_register_driver(&inic_pci_driver); 772 } 773 774 static void __exit inic_exit(void) 775 { 776 pci_unregister_driver(&inic_pci_driver); 777 } 778 779 MODULE_AUTHOR("Tejun Heo"); 780 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA"); 781 MODULE_LICENSE("GPL v2"); 782 MODULE_DEVICE_TABLE(pci, inic_pci_tbl); 783 MODULE_VERSION(DRV_VERSION); 784 785 module_init(inic_init); 786 module_exit(inic_exit); 787