1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cortina Systems Gemini SATA bridge add-on to Faraday FTIDE010 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 */ 6 7 #include <linux/init.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/bitops.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/regmap.h> 13 #include <linux/delay.h> 14 #include <linux/of.h> 15 #include <linux/clk.h> 16 #include <linux/io.h> 17 #include <linux/pinctrl/consumer.h> 18 #include "sata_gemini.h" 19 20 #define DRV_NAME "gemini_sata_bridge" 21 22 /** 23 * struct sata_gemini - a state container for a Gemini SATA bridge 24 * @dev: the containing device 25 * @base: remapped I/O memory base 26 * @muxmode: the current muxing mode 27 * @ide_pins: if the device is using the plain IDE interface pins 28 * @sata_bridge: if the device enables the SATA bridge 29 * @sata0_pclk: SATA0 PCLK handler 30 * @sata1_pclk: SATA1 PCLK handler 31 */ 32 struct sata_gemini { 33 struct device *dev; 34 void __iomem *base; 35 enum gemini_muxmode muxmode; 36 bool ide_pins; 37 bool sata_bridge; 38 struct clk *sata0_pclk; 39 struct clk *sata1_pclk; 40 }; 41 42 /* Miscellaneous Control Register */ 43 #define GEMINI_GLOBAL_MISC_CTRL 0x30 44 /* 45 * Values of IDE IOMUX bits in the misc control register 46 * 47 * Bits 26:24 are "IDE IO Select", which decides what SATA 48 * adapters are connected to which of the two IDE/ATA 49 * controllers in the Gemini. We can connect the two IDE blocks 50 * to one SATA adapter each, both acting as master, or one IDE 51 * blocks to two SATA adapters so the IDE block can act in a 52 * master/slave configuration. 53 * 54 * We also bring out different blocks on the actual IDE 55 * pins (not SATA pins) if (and only if) these are muxed in. 56 * 57 * 111-100 - Reserved 58 * Mode 0: 000 - ata0 master <-> sata0 59 * ata1 master <-> sata1 60 * ata0 slave interface brought out on IDE pads 61 * Mode 1: 001 - ata0 master <-> sata0 62 * ata1 master <-> sata1 63 * ata1 slave interface brought out on IDE pads 64 * Mode 2: 010 - ata1 master <-> sata1 65 * ata1 slave <-> sata0 66 * ata0 master and slave interfaces brought out 67 * on IDE pads 68 * Mode 3: 011 - ata0 master <-> sata0 69 * ata1 slave <-> sata1 70 * ata1 master and slave interfaces brought out 71 * on IDE pads 72 */ 73 #define GEMINI_IDE_IOMUX_MASK (7 << 24) 74 #define GEMINI_IDE_IOMUX_MODE0 (0 << 24) 75 #define GEMINI_IDE_IOMUX_MODE1 (1 << 24) 76 #define GEMINI_IDE_IOMUX_MODE2 (2 << 24) 77 #define GEMINI_IDE_IOMUX_MODE3 (3 << 24) 78 #define GEMINI_IDE_IOMUX_SHIFT (24) 79 80 /* 81 * Registers directly controlling the PATA<->SATA adapters 82 */ 83 #define GEMINI_SATA_ID 0x00 84 #define GEMINI_SATA_PHY_ID 0x04 85 #define GEMINI_SATA0_STATUS 0x08 86 #define GEMINI_SATA1_STATUS 0x0c 87 #define GEMINI_SATA0_CTRL 0x18 88 #define GEMINI_SATA1_CTRL 0x1c 89 90 #define GEMINI_SATA_STATUS_BIST_DONE BIT(5) 91 #define GEMINI_SATA_STATUS_BIST_OK BIT(4) 92 #define GEMINI_SATA_STATUS_PHY_READY BIT(0) 93 94 #define GEMINI_SATA_CTRL_PHY_BIST_EN BIT(14) 95 #define GEMINI_SATA_CTRL_PHY_FORCE_IDLE BIT(13) 96 #define GEMINI_SATA_CTRL_PHY_FORCE_READY BIT(12) 97 #define GEMINI_SATA_CTRL_PHY_AFE_LOOP_EN BIT(10) 98 #define GEMINI_SATA_CTRL_PHY_DIG_LOOP_EN BIT(9) 99 #define GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN BIT(4) 100 #define GEMINI_SATA_CTRL_ATAPI_EN BIT(3) 101 #define GEMINI_SATA_CTRL_BUS_WITH_20 BIT(2) 102 #define GEMINI_SATA_CTRL_SLAVE_EN BIT(1) 103 #define GEMINI_SATA_CTRL_EN BIT(0) 104 105 /* 106 * There is only ever one instance of this bridge on a system, 107 * so create a singleton so that the FTIDE010 instances can grab 108 * a reference to it. 109 */ 110 static struct sata_gemini *sg_singleton; 111 112 struct sata_gemini *gemini_sata_bridge_get(void) 113 { 114 if (sg_singleton) 115 return sg_singleton; 116 return ERR_PTR(-EPROBE_DEFER); 117 } 118 EXPORT_SYMBOL(gemini_sata_bridge_get); 119 120 bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1) 121 { 122 if (!sg->sata_bridge) 123 return false; 124 /* 125 * In muxmode 2 and 3 one of the ATA controllers is 126 * actually not connected to any SATA bridge. 127 */ 128 if ((sg->muxmode == GEMINI_MUXMODE_2) && 129 !is_ata1) 130 return false; 131 if ((sg->muxmode == GEMINI_MUXMODE_3) && 132 is_ata1) 133 return false; 134 135 return true; 136 } 137 EXPORT_SYMBOL(gemini_sata_bridge_enabled); 138 139 enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg) 140 { 141 return sg->muxmode; 142 } 143 EXPORT_SYMBOL(gemini_sata_get_muxmode); 144 145 static int gemini_sata_setup_bridge(struct sata_gemini *sg, 146 unsigned int bridge) 147 { 148 unsigned long timeout = jiffies + (HZ * 1); 149 bool bridge_online; 150 u32 val; 151 152 if (bridge == 0) { 153 val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; 154 /* SATA0 slave mode is only used in muxmode 2 */ 155 if (sg->muxmode == GEMINI_MUXMODE_2) 156 val |= GEMINI_SATA_CTRL_SLAVE_EN; 157 writel(val, sg->base + GEMINI_SATA0_CTRL); 158 } else { 159 val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; 160 /* SATA1 slave mode is only used in muxmode 3 */ 161 if (sg->muxmode == GEMINI_MUXMODE_3) 162 val |= GEMINI_SATA_CTRL_SLAVE_EN; 163 writel(val, sg->base + GEMINI_SATA1_CTRL); 164 } 165 166 /* Vendor code waits 10 ms here */ 167 msleep(10); 168 169 /* Wait for PHY to become ready */ 170 do { 171 msleep(100); 172 173 if (bridge == 0) 174 val = readl(sg->base + GEMINI_SATA0_STATUS); 175 else 176 val = readl(sg->base + GEMINI_SATA1_STATUS); 177 if (val & GEMINI_SATA_STATUS_PHY_READY) 178 break; 179 } while (time_before(jiffies, timeout)); 180 181 bridge_online = !!(val & GEMINI_SATA_STATUS_PHY_READY); 182 183 dev_info(sg->dev, "SATA%d PHY %s\n", bridge, 184 bridge_online ? "ready" : "not ready"); 185 186 return bridge_online ? 0: -ENODEV; 187 } 188 189 int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge) 190 { 191 struct clk *pclk; 192 int ret; 193 194 if (bridge == 0) 195 pclk = sg->sata0_pclk; 196 else 197 pclk = sg->sata1_pclk; 198 ret = clk_enable(pclk); 199 if (ret) 200 return ret; 201 202 msleep(10); 203 204 /* Do not keep clocking a bridge that is not online */ 205 ret = gemini_sata_setup_bridge(sg, bridge); 206 if (ret) 207 clk_disable(pclk); 208 209 return ret; 210 } 211 EXPORT_SYMBOL(gemini_sata_start_bridge); 212 213 void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge) 214 { 215 if (bridge == 0) 216 clk_disable(sg->sata0_pclk); 217 else if (bridge == 1) 218 clk_disable(sg->sata1_pclk); 219 } 220 EXPORT_SYMBOL(gemini_sata_stop_bridge); 221 222 static int gemini_sata_bridge_init(struct sata_gemini *sg) 223 { 224 struct device *dev = sg->dev; 225 u32 sata_id, sata_phy_id; 226 int ret; 227 228 sg->sata0_pclk = devm_clk_get(dev, "SATA0_PCLK"); 229 if (IS_ERR(sg->sata0_pclk)) { 230 dev_err(dev, "no SATA0 PCLK"); 231 return -ENODEV; 232 } 233 sg->sata1_pclk = devm_clk_get(dev, "SATA1_PCLK"); 234 if (IS_ERR(sg->sata1_pclk)) { 235 dev_err(dev, "no SATA1 PCLK"); 236 return -ENODEV; 237 } 238 239 ret = clk_prepare_enable(sg->sata0_pclk); 240 if (ret) { 241 dev_err(dev, "failed to enable SATA0 PCLK\n"); 242 return ret; 243 } 244 ret = clk_prepare_enable(sg->sata1_pclk); 245 if (ret) { 246 dev_err(dev, "failed to enable SATA1 PCLK\n"); 247 clk_disable_unprepare(sg->sata0_pclk); 248 return ret; 249 } 250 251 sata_id = readl(sg->base + GEMINI_SATA_ID); 252 sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID); 253 sg->sata_bridge = true; 254 clk_disable(sg->sata0_pclk); 255 clk_disable(sg->sata1_pclk); 256 257 dev_info(dev, "SATA ID %08x, PHY ID: %08x\n", sata_id, sata_phy_id); 258 259 return 0; 260 } 261 262 static int gemini_setup_ide_pins(struct device *dev) 263 { 264 struct pinctrl *p; 265 struct pinctrl_state *ide_state; 266 int ret; 267 268 p = devm_pinctrl_get(dev); 269 if (IS_ERR(p)) 270 return PTR_ERR(p); 271 272 ide_state = pinctrl_lookup_state(p, "ide"); 273 if (IS_ERR(ide_state)) 274 return PTR_ERR(ide_state); 275 276 ret = pinctrl_select_state(p, ide_state); 277 if (ret) { 278 dev_err(dev, "could not select IDE state\n"); 279 return ret; 280 } 281 282 return 0; 283 } 284 285 static int gemini_sata_probe(struct platform_device *pdev) 286 { 287 struct device *dev = &pdev->dev; 288 struct device_node *np = dev->of_node; 289 struct sata_gemini *sg; 290 struct regmap *map; 291 enum gemini_muxmode muxmode; 292 u32 gmode; 293 u32 gmask; 294 int ret; 295 296 sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL); 297 if (!sg) 298 return -ENOMEM; 299 sg->dev = dev; 300 301 sg->base = devm_platform_ioremap_resource(pdev, 0); 302 if (IS_ERR(sg->base)) 303 return PTR_ERR(sg->base); 304 305 map = syscon_regmap_lookup_by_phandle(np, "syscon"); 306 if (IS_ERR(map)) { 307 dev_err(dev, "no global syscon\n"); 308 return PTR_ERR(map); 309 } 310 311 /* Set up the SATA bridge if need be */ 312 if (of_property_read_bool(np, "cortina,gemini-enable-sata-bridge")) { 313 ret = gemini_sata_bridge_init(sg); 314 if (ret) 315 return ret; 316 } 317 318 if (of_property_read_bool(np, "cortina,gemini-enable-ide-pins")) 319 sg->ide_pins = true; 320 321 if (!sg->sata_bridge && !sg->ide_pins) { 322 dev_err(dev, "neither SATA bridge or IDE output enabled\n"); 323 ret = -EINVAL; 324 goto out_unprep_clk; 325 } 326 327 ret = of_property_read_u32(np, "cortina,gemini-ata-muxmode", &muxmode); 328 if (ret) { 329 dev_err(dev, "could not parse ATA muxmode\n"); 330 goto out_unprep_clk; 331 } 332 if (muxmode > GEMINI_MUXMODE_3) { 333 dev_err(dev, "illegal muxmode %d\n", muxmode); 334 ret = -EINVAL; 335 goto out_unprep_clk; 336 } 337 sg->muxmode = muxmode; 338 gmask = GEMINI_IDE_IOMUX_MASK; 339 gmode = (muxmode << GEMINI_IDE_IOMUX_SHIFT); 340 341 ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, gmask, gmode); 342 if (ret) { 343 dev_err(dev, "unable to set up IDE muxing\n"); 344 ret = -ENODEV; 345 goto out_unprep_clk; 346 } 347 348 /* 349 * Route out the IDE pins if desired. 350 * This is done by looking up a special pin control state called 351 * "ide" that will route out the IDE pins. 352 */ 353 if (sg->ide_pins) { 354 ret = gemini_setup_ide_pins(dev); 355 if (ret) 356 return ret; 357 } 358 359 dev_info(dev, "set up the Gemini IDE/SATA nexus\n"); 360 platform_set_drvdata(pdev, sg); 361 sg_singleton = sg; 362 363 return 0; 364 365 out_unprep_clk: 366 if (sg->sata_bridge) { 367 clk_unprepare(sg->sata1_pclk); 368 clk_unprepare(sg->sata0_pclk); 369 } 370 return ret; 371 } 372 373 static void gemini_sata_remove(struct platform_device *pdev) 374 { 375 struct sata_gemini *sg = platform_get_drvdata(pdev); 376 377 if (sg->sata_bridge) { 378 clk_unprepare(sg->sata1_pclk); 379 clk_unprepare(sg->sata0_pclk); 380 } 381 sg_singleton = NULL; 382 } 383 384 static const struct of_device_id gemini_sata_of_match[] = { 385 { .compatible = "cortina,gemini-sata-bridge", }, 386 { /* sentinel */ } 387 }; 388 MODULE_DEVICE_TABLE(of, gemini_sata_of_match); 389 390 static struct platform_driver gemini_sata_driver = { 391 .driver = { 392 .name = DRV_NAME, 393 .of_match_table = gemini_sata_of_match, 394 }, 395 .probe = gemini_sata_probe, 396 .remove = gemini_sata_remove, 397 }; 398 module_platform_driver(gemini_sata_driver); 399 400 MODULE_DESCRIPTION("low level driver for Cortina Systems Gemini SATA bridge"); 401 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 402 MODULE_LICENSE("GPL"); 403 MODULE_ALIAS("platform:" DRV_NAME); 404