1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Cortina Systems Gemini SATA bridge add-on to Faraday FTIDE010 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 */ 6 7 #include <linux/init.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/bitops.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/regmap.h> 13 #include <linux/delay.h> 14 #include <linux/reset.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/clk.h> 18 #include <linux/io.h> 19 #include <linux/pinctrl/consumer.h> 20 #include "sata_gemini.h" 21 22 #define DRV_NAME "gemini_sata_bridge" 23 24 /** 25 * struct sata_gemini - a state container for a Gemini SATA bridge 26 * @dev: the containing device 27 * @base: remapped I/O memory base 28 * @muxmode: the current muxing mode 29 * @ide_pins: if the device is using the plain IDE interface pins 30 * @sata_bridge: if the device enables the SATA bridge 31 * @sata0_reset: SATA0 reset handler 32 * @sata1_reset: SATA1 reset handler 33 * @sata0_pclk: SATA0 PCLK handler 34 * @sata1_pclk: SATA1 PCLK handler 35 */ 36 struct sata_gemini { 37 struct device *dev; 38 void __iomem *base; 39 enum gemini_muxmode muxmode; 40 bool ide_pins; 41 bool sata_bridge; 42 struct reset_control *sata0_reset; 43 struct reset_control *sata1_reset; 44 struct clk *sata0_pclk; 45 struct clk *sata1_pclk; 46 }; 47 48 /* Miscellaneous Control Register */ 49 #define GEMINI_GLOBAL_MISC_CTRL 0x30 50 /* 51 * Values of IDE IOMUX bits in the misc control register 52 * 53 * Bits 26:24 are "IDE IO Select", which decides what SATA 54 * adapters are connected to which of the two IDE/ATA 55 * controllers in the Gemini. We can connect the two IDE blocks 56 * to one SATA adapter each, both acting as master, or one IDE 57 * blocks to two SATA adapters so the IDE block can act in a 58 * master/slave configuration. 59 * 60 * We also bring out different blocks on the actual IDE 61 * pins (not SATA pins) if (and only if) these are muxed in. 62 * 63 * 111-100 - Reserved 64 * Mode 0: 000 - ata0 master <-> sata0 65 * ata1 master <-> sata1 66 * ata0 slave interface brought out on IDE pads 67 * Mode 1: 001 - ata0 master <-> sata0 68 * ata1 master <-> sata1 69 * ata1 slave interface brought out on IDE pads 70 * Mode 2: 010 - ata1 master <-> sata1 71 * ata1 slave <-> sata0 72 * ata0 master and slave interfaces brought out 73 * on IDE pads 74 * Mode 3: 011 - ata0 master <-> sata0 75 * ata1 slave <-> sata1 76 * ata1 master and slave interfaces brought out 77 * on IDE pads 78 */ 79 #define GEMINI_IDE_IOMUX_MASK (7 << 24) 80 #define GEMINI_IDE_IOMUX_MODE0 (0 << 24) 81 #define GEMINI_IDE_IOMUX_MODE1 (1 << 24) 82 #define GEMINI_IDE_IOMUX_MODE2 (2 << 24) 83 #define GEMINI_IDE_IOMUX_MODE3 (3 << 24) 84 #define GEMINI_IDE_IOMUX_SHIFT (24) 85 86 /* 87 * Registers directly controlling the PATA<->SATA adapters 88 */ 89 #define GEMINI_SATA_ID 0x00 90 #define GEMINI_SATA_PHY_ID 0x04 91 #define GEMINI_SATA0_STATUS 0x08 92 #define GEMINI_SATA1_STATUS 0x0c 93 #define GEMINI_SATA0_CTRL 0x18 94 #define GEMINI_SATA1_CTRL 0x1c 95 96 #define GEMINI_SATA_STATUS_BIST_DONE BIT(5) 97 #define GEMINI_SATA_STATUS_BIST_OK BIT(4) 98 #define GEMINI_SATA_STATUS_PHY_READY BIT(0) 99 100 #define GEMINI_SATA_CTRL_PHY_BIST_EN BIT(14) 101 #define GEMINI_SATA_CTRL_PHY_FORCE_IDLE BIT(13) 102 #define GEMINI_SATA_CTRL_PHY_FORCE_READY BIT(12) 103 #define GEMINI_SATA_CTRL_PHY_AFE_LOOP_EN BIT(10) 104 #define GEMINI_SATA_CTRL_PHY_DIG_LOOP_EN BIT(9) 105 #define GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN BIT(4) 106 #define GEMINI_SATA_CTRL_ATAPI_EN BIT(3) 107 #define GEMINI_SATA_CTRL_BUS_WITH_20 BIT(2) 108 #define GEMINI_SATA_CTRL_SLAVE_EN BIT(1) 109 #define GEMINI_SATA_CTRL_EN BIT(0) 110 111 /* 112 * There is only ever one instance of this bridge on a system, 113 * so create a singleton so that the FTIDE010 instances can grab 114 * a reference to it. 115 */ 116 static struct sata_gemini *sg_singleton; 117 118 struct sata_gemini *gemini_sata_bridge_get(void) 119 { 120 if (sg_singleton) 121 return sg_singleton; 122 return ERR_PTR(-EPROBE_DEFER); 123 } 124 EXPORT_SYMBOL(gemini_sata_bridge_get); 125 126 bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1) 127 { 128 if (!sg->sata_bridge) 129 return false; 130 /* 131 * In muxmode 2 and 3 one of the ATA controllers is 132 * actually not connected to any SATA bridge. 133 */ 134 if ((sg->muxmode == GEMINI_MUXMODE_2) && 135 !is_ata1) 136 return false; 137 if ((sg->muxmode == GEMINI_MUXMODE_3) && 138 is_ata1) 139 return false; 140 141 return true; 142 } 143 EXPORT_SYMBOL(gemini_sata_bridge_enabled); 144 145 enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg) 146 { 147 return sg->muxmode; 148 } 149 EXPORT_SYMBOL(gemini_sata_get_muxmode); 150 151 static int gemini_sata_setup_bridge(struct sata_gemini *sg, 152 unsigned int bridge) 153 { 154 unsigned long timeout = jiffies + (HZ * 1); 155 bool bridge_online; 156 u32 val; 157 158 if (bridge == 0) { 159 val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; 160 /* SATA0 slave mode is only used in muxmode 2 */ 161 if (sg->muxmode == GEMINI_MUXMODE_2) 162 val |= GEMINI_SATA_CTRL_SLAVE_EN; 163 writel(val, sg->base + GEMINI_SATA0_CTRL); 164 } else { 165 val = GEMINI_SATA_CTRL_HOTPLUG_DETECT_EN | GEMINI_SATA_CTRL_EN; 166 /* SATA1 slave mode is only used in muxmode 3 */ 167 if (sg->muxmode == GEMINI_MUXMODE_3) 168 val |= GEMINI_SATA_CTRL_SLAVE_EN; 169 writel(val, sg->base + GEMINI_SATA1_CTRL); 170 } 171 172 /* Vendor code waits 10 ms here */ 173 msleep(10); 174 175 /* Wait for PHY to become ready */ 176 do { 177 msleep(100); 178 179 if (bridge == 0) 180 val = readl(sg->base + GEMINI_SATA0_STATUS); 181 else 182 val = readl(sg->base + GEMINI_SATA1_STATUS); 183 if (val & GEMINI_SATA_STATUS_PHY_READY) 184 break; 185 } while (time_before(jiffies, timeout)); 186 187 bridge_online = !!(val & GEMINI_SATA_STATUS_PHY_READY); 188 189 dev_info(sg->dev, "SATA%d PHY %s\n", bridge, 190 bridge_online ? "ready" : "not ready"); 191 192 return bridge_online ? 0: -ENODEV; 193 } 194 195 int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge) 196 { 197 struct clk *pclk; 198 int ret; 199 200 if (bridge == 0) 201 pclk = sg->sata0_pclk; 202 else 203 pclk = sg->sata1_pclk; 204 clk_enable(pclk); 205 msleep(10); 206 207 /* Do not keep clocking a bridge that is not online */ 208 ret = gemini_sata_setup_bridge(sg, bridge); 209 if (ret) 210 clk_disable(pclk); 211 212 return ret; 213 } 214 EXPORT_SYMBOL(gemini_sata_start_bridge); 215 216 void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge) 217 { 218 if (bridge == 0) 219 clk_disable(sg->sata0_pclk); 220 else if (bridge == 1) 221 clk_disable(sg->sata1_pclk); 222 } 223 EXPORT_SYMBOL(gemini_sata_stop_bridge); 224 225 int gemini_sata_reset_bridge(struct sata_gemini *sg, 226 unsigned int bridge) 227 { 228 if (bridge == 0) 229 reset_control_reset(sg->sata0_reset); 230 else 231 reset_control_reset(sg->sata1_reset); 232 msleep(10); 233 return gemini_sata_setup_bridge(sg, bridge); 234 } 235 EXPORT_SYMBOL(gemini_sata_reset_bridge); 236 237 static int gemini_sata_bridge_init(struct sata_gemini *sg) 238 { 239 struct device *dev = sg->dev; 240 u32 sata_id, sata_phy_id; 241 int ret; 242 243 sg->sata0_pclk = devm_clk_get(dev, "SATA0_PCLK"); 244 if (IS_ERR(sg->sata0_pclk)) { 245 dev_err(dev, "no SATA0 PCLK"); 246 return -ENODEV; 247 } 248 sg->sata1_pclk = devm_clk_get(dev, "SATA1_PCLK"); 249 if (IS_ERR(sg->sata1_pclk)) { 250 dev_err(dev, "no SATA1 PCLK"); 251 return -ENODEV; 252 } 253 254 ret = clk_prepare_enable(sg->sata0_pclk); 255 if (ret) { 256 dev_err(dev, "failed to enable SATA0 PCLK\n"); 257 return ret; 258 } 259 ret = clk_prepare_enable(sg->sata1_pclk); 260 if (ret) { 261 dev_err(dev, "failed to enable SATA1 PCLK\n"); 262 clk_disable_unprepare(sg->sata0_pclk); 263 return ret; 264 } 265 266 sg->sata0_reset = devm_reset_control_get_exclusive(dev, "sata0"); 267 if (IS_ERR(sg->sata0_reset)) { 268 dev_err(dev, "no SATA0 reset controller\n"); 269 clk_disable_unprepare(sg->sata1_pclk); 270 clk_disable_unprepare(sg->sata0_pclk); 271 return PTR_ERR(sg->sata0_reset); 272 } 273 sg->sata1_reset = devm_reset_control_get_exclusive(dev, "sata1"); 274 if (IS_ERR(sg->sata1_reset)) { 275 dev_err(dev, "no SATA1 reset controller\n"); 276 clk_disable_unprepare(sg->sata1_pclk); 277 clk_disable_unprepare(sg->sata0_pclk); 278 return PTR_ERR(sg->sata1_reset); 279 } 280 281 sata_id = readl(sg->base + GEMINI_SATA_ID); 282 sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID); 283 sg->sata_bridge = true; 284 clk_disable(sg->sata0_pclk); 285 clk_disable(sg->sata1_pclk); 286 287 dev_info(dev, "SATA ID %08x, PHY ID: %08x\n", sata_id, sata_phy_id); 288 289 return 0; 290 } 291 292 static int gemini_setup_ide_pins(struct device *dev) 293 { 294 struct pinctrl *p; 295 struct pinctrl_state *ide_state; 296 int ret; 297 298 p = devm_pinctrl_get(dev); 299 if (IS_ERR(p)) 300 return PTR_ERR(p); 301 302 ide_state = pinctrl_lookup_state(p, "ide"); 303 if (IS_ERR(ide_state)) 304 return PTR_ERR(ide_state); 305 306 ret = pinctrl_select_state(p, ide_state); 307 if (ret) { 308 dev_err(dev, "could not select IDE state\n"); 309 return ret; 310 } 311 312 return 0; 313 } 314 315 static int gemini_sata_probe(struct platform_device *pdev) 316 { 317 struct device *dev = &pdev->dev; 318 struct device_node *np = dev->of_node; 319 struct sata_gemini *sg; 320 struct regmap *map; 321 enum gemini_muxmode muxmode; 322 u32 gmode; 323 u32 gmask; 324 int ret; 325 326 sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL); 327 if (!sg) 328 return -ENOMEM; 329 sg->dev = dev; 330 331 sg->base = devm_platform_ioremap_resource(pdev, 0); 332 if (IS_ERR(sg->base)) 333 return PTR_ERR(sg->base); 334 335 map = syscon_regmap_lookup_by_phandle(np, "syscon"); 336 if (IS_ERR(map)) { 337 dev_err(dev, "no global syscon\n"); 338 return PTR_ERR(map); 339 } 340 341 /* Set up the SATA bridge if need be */ 342 if (of_property_read_bool(np, "cortina,gemini-enable-sata-bridge")) { 343 ret = gemini_sata_bridge_init(sg); 344 if (ret) 345 return ret; 346 } 347 348 if (of_property_read_bool(np, "cortina,gemini-enable-ide-pins")) 349 sg->ide_pins = true; 350 351 if (!sg->sata_bridge && !sg->ide_pins) { 352 dev_err(dev, "neither SATA bridge or IDE output enabled\n"); 353 ret = -EINVAL; 354 goto out_unprep_clk; 355 } 356 357 ret = of_property_read_u32(np, "cortina,gemini-ata-muxmode", &muxmode); 358 if (ret) { 359 dev_err(dev, "could not parse ATA muxmode\n"); 360 goto out_unprep_clk; 361 } 362 if (muxmode > GEMINI_MUXMODE_3) { 363 dev_err(dev, "illegal muxmode %d\n", muxmode); 364 ret = -EINVAL; 365 goto out_unprep_clk; 366 } 367 sg->muxmode = muxmode; 368 gmask = GEMINI_IDE_IOMUX_MASK; 369 gmode = (muxmode << GEMINI_IDE_IOMUX_SHIFT); 370 371 ret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, gmask, gmode); 372 if (ret) { 373 dev_err(dev, "unable to set up IDE muxing\n"); 374 ret = -ENODEV; 375 goto out_unprep_clk; 376 } 377 378 /* 379 * Route out the IDE pins if desired. 380 * This is done by looking up a special pin control state called 381 * "ide" that will route out the IDE pins. 382 */ 383 if (sg->ide_pins) { 384 ret = gemini_setup_ide_pins(dev); 385 if (ret) 386 return ret; 387 } 388 389 dev_info(dev, "set up the Gemini IDE/SATA nexus\n"); 390 platform_set_drvdata(pdev, sg); 391 sg_singleton = sg; 392 393 return 0; 394 395 out_unprep_clk: 396 if (sg->sata_bridge) { 397 clk_unprepare(sg->sata1_pclk); 398 clk_unprepare(sg->sata0_pclk); 399 } 400 return ret; 401 } 402 403 static int gemini_sata_remove(struct platform_device *pdev) 404 { 405 struct sata_gemini *sg = platform_get_drvdata(pdev); 406 407 if (sg->sata_bridge) { 408 clk_unprepare(sg->sata1_pclk); 409 clk_unprepare(sg->sata0_pclk); 410 } 411 sg_singleton = NULL; 412 413 return 0; 414 } 415 416 static const struct of_device_id gemini_sata_of_match[] = { 417 { .compatible = "cortina,gemini-sata-bridge", }, 418 { /* sentinel */ } 419 }; 420 421 static struct platform_driver gemini_sata_driver = { 422 .driver = { 423 .name = DRV_NAME, 424 .of_match_table = of_match_ptr(gemini_sata_of_match), 425 }, 426 .probe = gemini_sata_probe, 427 .remove = gemini_sata_remove, 428 }; 429 module_platform_driver(gemini_sata_driver); 430 431 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 432 MODULE_LICENSE("GPL"); 433 MODULE_ALIAS("platform:" DRV_NAME); 434