1 /* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 22 #include <scsi/scsi_host.h> 23 #include <scsi/scsi_cmnd.h> 24 #include <linux/libata.h> 25 #include <asm/io.h> 26 #include <linux/of_platform.h> 27 28 /* Controller information */ 29 enum { 30 SATA_FSL_QUEUE_DEPTH = 16, 31 SATA_FSL_MAX_PRD = 63, 32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 34 35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 37 ATA_FLAG_NCQ), 38 SATA_FSL_HOST_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY, 39 40 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 41 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 42 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 43 44 /* 45 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 46 * chained indirect PRDEs upto a max count of 63. 47 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will 48 * be setup as an indirect descriptor, pointing to it's next 49 * (contigious) PRDE. Though chained indirect PRDE arrays are 50 * supported,it will be more efficient to use a direct PRDT and 51 * a single chain/link to indirect PRDE array/PRDT. 52 */ 53 54 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 55 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 56 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 57 SATA_FSL_CMD_DESC_RSRVD = 16, 58 59 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 60 SATA_FSL_CMD_DESC_SFIS_SZ + 61 SATA_FSL_CMD_DESC_ACMD_SZ + 62 SATA_FSL_CMD_DESC_RSRVD + 63 SATA_FSL_MAX_PRD * 16), 64 65 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 66 (SATA_FSL_CMD_DESC_CFIS_SZ + 67 SATA_FSL_CMD_DESC_SFIS_SZ + 68 SATA_FSL_CMD_DESC_ACMD_SZ + 69 SATA_FSL_CMD_DESC_RSRVD), 70 71 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 72 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 73 SATA_FSL_CMD_DESC_AR_SZ), 74 75 /* 76 * MPC8315 has two SATA controllers, SATA1 & SATA2 77 * (one port per controller) 78 * MPC837x has 2/4 controllers, one port per controller 79 */ 80 81 SATA_FSL_MAX_PORTS = 1, 82 83 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 84 }; 85 86 /* 87 * Host Controller command register set - per port 88 */ 89 enum { 90 CQ = 0, 91 CA = 8, 92 CC = 0x10, 93 CE = 0x18, 94 DE = 0x20, 95 CHBA = 0x24, 96 HSTATUS = 0x28, 97 HCONTROL = 0x2C, 98 CQPMP = 0x30, 99 SIGNATURE = 0x34, 100 ICC = 0x38, 101 102 /* 103 * Host Status Register (HStatus) bitdefs 104 */ 105 ONLINE = (1 << 31), 106 GOING_OFFLINE = (1 << 30), 107 BIST_ERR = (1 << 29), 108 109 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 110 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 111 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 112 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 113 FATAL_ERR_DATA_OVERRUN = (1 << 12), 114 FATAL_ERR_CRC_ERR_TX = (1 << 11), 115 FATAL_ERR_CRC_ERR_RX = (1 << 10), 116 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 117 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 118 119 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 120 FATAL_ERR_PARITY_ERR_TX | 121 FATAL_ERR_PARITY_ERR_RX | 122 FATAL_ERR_DATA_UNDERRUN | 123 FATAL_ERR_DATA_OVERRUN | 124 FATAL_ERR_CRC_ERR_TX | 125 FATAL_ERR_CRC_ERR_RX | 126 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 127 128 INT_ON_FATAL_ERR = (1 << 5), 129 INT_ON_PHYRDY_CHG = (1 << 4), 130 131 INT_ON_SIGNATURE_UPDATE = (1 << 3), 132 INT_ON_SNOTIFY_UPDATE = (1 << 2), 133 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 134 INT_ON_CMD_COMPLETE = 1, 135 136 INT_ON_ERROR = INT_ON_FATAL_ERR | 137 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 138 139 /* 140 * Host Control Register (HControl) bitdefs 141 */ 142 HCONTROL_ONLINE_PHY_RST = (1 << 31), 143 HCONTROL_FORCE_OFFLINE = (1 << 30), 144 HCONTROL_PARITY_PROT_MOD = (1 << 14), 145 HCONTROL_DPATH_PARITY = (1 << 12), 146 HCONTROL_SNOOP_ENABLE = (1 << 10), 147 HCONTROL_PMP_ATTACHED = (1 << 9), 148 HCONTROL_COPYOUT_STATFIS = (1 << 8), 149 IE_ON_FATAL_ERR = (1 << 5), 150 IE_ON_PHYRDY_CHG = (1 << 4), 151 IE_ON_SIGNATURE_UPDATE = (1 << 3), 152 IE_ON_SNOTIFY_UPDATE = (1 << 2), 153 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 154 IE_ON_CMD_COMPLETE = 1, 155 156 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 157 IE_ON_SIGNATURE_UPDATE | 158 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 159 160 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 161 DATA_SNOOP_ENABLE = (1 << 22), 162 }; 163 164 /* 165 * SATA Superset Registers 166 */ 167 enum { 168 SSTATUS = 0, 169 SERROR = 4, 170 SCONTROL = 8, 171 SNOTIFY = 0xC, 172 }; 173 174 /* 175 * Control Status Register Set 176 */ 177 enum { 178 TRANSCFG = 0, 179 TRANSSTATUS = 4, 180 LINKCFG = 8, 181 LINKCFG1 = 0xC, 182 LINKCFG2 = 0x10, 183 LINKSTATUS = 0x14, 184 LINKSTATUS1 = 0x18, 185 PHYCTRLCFG = 0x1C, 186 COMMANDSTAT = 0x20, 187 }; 188 189 /* PHY (link-layer) configuration control */ 190 enum { 191 PHY_BIST_ENABLE = 0x01, 192 }; 193 194 /* 195 * Command Header Table entry, i.e, command slot 196 * 4 Dwords per command slot, command header size == 64 Dwords. 197 */ 198 struct cmdhdr_tbl_entry { 199 u32 cda; 200 u32 prde_fis_len; 201 u32 ttl; 202 u32 desc_info; 203 }; 204 205 /* 206 * Description information bitdefs 207 */ 208 enum { 209 VENDOR_SPECIFIC_BIST = (1 << 10), 210 CMD_DESC_SNOOP_ENABLE = (1 << 9), 211 FPDMA_QUEUED_CMD = (1 << 8), 212 SRST_CMD = (1 << 7), 213 BIST = (1 << 6), 214 ATAPI_CMD = (1 << 5), 215 }; 216 217 /* 218 * Command Descriptor 219 */ 220 struct command_desc { 221 u8 cfis[8 * 4]; 222 u8 sfis[8 * 4]; 223 u8 acmd[4 * 4]; 224 u8 fill[4 * 4]; 225 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 226 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 227 }; 228 229 /* 230 * Physical region table descriptor(PRD) 231 */ 232 233 struct prde { 234 u32 dba; 235 u8 fill[2 * 4]; 236 u32 ddc_and_ext; 237 }; 238 239 /* 240 * ata_port private data 241 * This is our per-port instance data. 242 */ 243 struct sata_fsl_port_priv { 244 struct cmdhdr_tbl_entry *cmdslot; 245 dma_addr_t cmdslot_paddr; 246 struct command_desc *cmdentry; 247 dma_addr_t cmdentry_paddr; 248 249 /* 250 * SATA FSL controller has a Status FIS which should contain the 251 * received D2H FIS & taskfile registers. This SFIS is present in 252 * the command descriptor, and to have a ready reference to it, 253 * we are caching it here, quite similar to what is done in H/W on 254 * AHCI compliant devices by copying taskfile fields to a 32-bit 255 * register. 256 */ 257 258 struct ata_taskfile tf; 259 }; 260 261 /* 262 * ata_port->host_set private data 263 */ 264 struct sata_fsl_host_priv { 265 void __iomem *hcr_base; 266 void __iomem *ssr_base; 267 void __iomem *csr_base; 268 int irq; 269 }; 270 271 static inline unsigned int sata_fsl_tag(unsigned int tag, 272 void __iomem *hcr_base) 273 { 274 /* We let libATA core do actual (queue) tag allocation */ 275 276 /* all non NCQ/queued commands should have tag#0 */ 277 if (ata_tag_internal(tag)) { 278 DPRINTK("mapping internal cmds to tag#0\n"); 279 return 0; 280 } 281 282 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 283 DPRINTK("tag %d invalid : out of range\n", tag); 284 return 0; 285 } 286 287 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 288 DPRINTK("tag %d invalid : in use!!\n", tag); 289 return 0; 290 } 291 292 return tag; 293 } 294 295 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 296 unsigned int tag, u32 desc_info, 297 u32 data_xfer_len, u8 num_prde, 298 u8 fis_len) 299 { 300 dma_addr_t cmd_descriptor_address; 301 302 cmd_descriptor_address = pp->cmdentry_paddr + 303 tag * SATA_FSL_CMD_DESC_SIZE; 304 305 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 306 307 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 308 pp->cmdslot[tag].prde_fis_len = 309 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 310 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 311 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 312 313 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 314 pp->cmdslot[tag].cda, 315 pp->cmdslot[tag].prde_fis_len, 316 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 317 318 } 319 320 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 321 u32 *ttl, dma_addr_t cmd_desc_paddr) 322 { 323 struct scatterlist *sg; 324 unsigned int num_prde = 0; 325 u32 ttl_dwords = 0; 326 327 /* 328 * NOTE : direct & indirect prdt's are contigiously allocated 329 */ 330 struct prde *prd = (struct prde *)&((struct command_desc *) 331 cmd_desc)->prdt; 332 333 struct prde *prd_ptr_to_indirect_ext = NULL; 334 unsigned indirect_ext_segment_sz = 0; 335 dma_addr_t indirect_ext_segment_paddr; 336 337 VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc, prd); 338 339 indirect_ext_segment_paddr = cmd_desc_paddr + 340 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 341 342 ata_for_each_sg(sg, qc) { 343 dma_addr_t sg_addr = sg_dma_address(sg); 344 u32 sg_len = sg_dma_len(sg); 345 346 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n", 347 sg_addr, sg_len); 348 349 /* warn if each s/g element is not dword aligned */ 350 if (sg_addr & 0x03) 351 ata_port_printk(qc->ap, KERN_ERR, 352 "s/g addr unaligned : 0x%x\n", sg_addr); 353 if (sg_len & 0x03) 354 ata_port_printk(qc->ap, KERN_ERR, 355 "s/g len unaligned : 0x%x\n", sg_len); 356 357 if ((num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1)) && 358 (qc->n_iter + 1 != qc->n_elem)) { 359 VPRINTK("setting indirect prde\n"); 360 prd_ptr_to_indirect_ext = prd; 361 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 362 indirect_ext_segment_sz = 0; 363 ++prd; 364 ++num_prde; 365 } 366 367 ttl_dwords += sg_len; 368 prd->dba = cpu_to_le32(sg_addr); 369 prd->ddc_and_ext = 370 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03)); 371 372 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 373 ttl_dwords, prd->dba, prd->ddc_and_ext); 374 375 ++num_prde; 376 ++prd; 377 if (prd_ptr_to_indirect_ext) 378 indirect_ext_segment_sz += sg_len; 379 } 380 381 if (prd_ptr_to_indirect_ext) { 382 /* set indirect extension flag along with indirect ext. size */ 383 prd_ptr_to_indirect_ext->ddc_and_ext = 384 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 385 DATA_SNOOP_ENABLE | 386 (indirect_ext_segment_sz & ~0x03))); 387 } 388 389 *ttl = ttl_dwords; 390 return num_prde; 391 } 392 393 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 394 { 395 struct ata_port *ap = qc->ap; 396 struct sata_fsl_port_priv *pp = ap->private_data; 397 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 398 void __iomem *hcr_base = host_priv->hcr_base; 399 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 400 struct command_desc *cd; 401 u32 desc_info = CMD_DESC_SNOOP_ENABLE; 402 u32 num_prde = 0; 403 u32 ttl_dwords = 0; 404 dma_addr_t cd_paddr; 405 406 cd = (struct command_desc *)pp->cmdentry + tag; 407 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 408 409 ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) &cd->cfis); 410 411 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 412 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 413 414 if (qc->tf.protocol == ATA_PROT_NCQ) { 415 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 416 cd->cfis[3], cd->cfis[11]); 417 } 418 419 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 420 if (is_atapi_taskfile(&qc->tf)) { 421 desc_info |= ATAPI_CMD; 422 memset((void *)&cd->acmd, 0, 32); 423 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 424 } 425 426 if (qc->flags & ATA_QCFLAG_DMAMAP) 427 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 428 &ttl_dwords, cd_paddr); 429 430 if (qc->tf.protocol == ATA_PROT_NCQ) 431 desc_info |= FPDMA_QUEUED_CMD; 432 433 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 434 num_prde, 5); 435 436 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 437 desc_info, ttl_dwords, num_prde); 438 } 439 440 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 441 { 442 struct ata_port *ap = qc->ap; 443 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 444 void __iomem *hcr_base = host_priv->hcr_base; 445 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 446 447 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 448 ioread32(CQ + hcr_base), 449 ioread32(CA + hcr_base), 450 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 451 452 /* Simply queue command to the controller/device */ 453 iowrite32(1 << tag, CQ + hcr_base); 454 455 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 456 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 457 458 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 459 ioread32(CE + hcr_base), 460 ioread32(DE + hcr_base), 461 ioread32(CC + hcr_base), ioread32(COMMANDSTAT + csr_base)); 462 463 return 0; 464 } 465 466 static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in, 467 u32 val) 468 { 469 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 470 void __iomem *ssr_base = host_priv->ssr_base; 471 unsigned int sc_reg; 472 473 switch (sc_reg_in) { 474 case SCR_STATUS: 475 case SCR_ERROR: 476 case SCR_CONTROL: 477 case SCR_ACTIVE: 478 sc_reg = sc_reg_in; 479 break; 480 default: 481 return -EINVAL; 482 } 483 484 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 485 486 iowrite32(val, ssr_base + (sc_reg * 4)); 487 return 0; 488 } 489 490 static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in, 491 u32 *val) 492 { 493 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 494 void __iomem *ssr_base = host_priv->ssr_base; 495 unsigned int sc_reg; 496 497 switch (sc_reg_in) { 498 case SCR_STATUS: 499 case SCR_ERROR: 500 case SCR_CONTROL: 501 case SCR_ACTIVE: 502 sc_reg = sc_reg_in; 503 break; 504 default: 505 return -EINVAL; 506 } 507 508 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 509 510 *val = ioread32(ssr_base + (sc_reg * 4)); 511 return 0; 512 } 513 514 static void sata_fsl_freeze(struct ata_port *ap) 515 { 516 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 517 void __iomem *hcr_base = host_priv->hcr_base; 518 u32 temp; 519 520 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 521 ioread32(CQ + hcr_base), 522 ioread32(CA + hcr_base), 523 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 524 VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base + COMMANDSTAT)); 525 526 /* disable interrupts on the controller/port */ 527 temp = ioread32(hcr_base + HCONTROL); 528 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 529 530 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 531 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 532 } 533 534 static void sata_fsl_thaw(struct ata_port *ap) 535 { 536 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 537 void __iomem *hcr_base = host_priv->hcr_base; 538 u32 temp; 539 540 /* ack. any pending IRQs for this controller/port */ 541 temp = ioread32(hcr_base + HSTATUS); 542 543 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 544 545 if (temp & 0x3F) 546 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 547 548 /* enable interrupts on the controller/port */ 549 temp = ioread32(hcr_base + HCONTROL); 550 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 551 552 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 553 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 554 } 555 556 /* 557 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor. 558 */ 559 static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd 560 *qc, 561 struct ata_port *ap) 562 { 563 struct sata_fsl_port_priv *pp = ap->private_data; 564 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 565 void __iomem *hcr_base = host_priv->hcr_base; 566 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 567 struct command_desc *cd; 568 569 cd = pp->cmdentry + tag; 570 571 ata_tf_from_fis(cd->sfis, &pp->tf); 572 } 573 574 static u8 sata_fsl_check_status(struct ata_port *ap) 575 { 576 struct sata_fsl_port_priv *pp = ap->private_data; 577 578 return pp->tf.command; 579 } 580 581 static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 582 { 583 struct sata_fsl_port_priv *pp = ap->private_data; 584 585 *tf = pp->tf; 586 } 587 588 static int sata_fsl_port_start(struct ata_port *ap) 589 { 590 struct device *dev = ap->host->dev; 591 struct sata_fsl_port_priv *pp; 592 int retval; 593 void *mem; 594 dma_addr_t mem_dma; 595 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 596 void __iomem *hcr_base = host_priv->hcr_base; 597 u32 temp; 598 599 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 600 if (!pp) 601 return -ENOMEM; 602 603 /* 604 * allocate per command dma alignment pad buffer, which is used 605 * internally by libATA to ensure that all transfers ending on 606 * unaligned boundaries are padded, to align on Dword boundaries 607 */ 608 retval = ata_pad_alloc(ap, dev); 609 if (retval) { 610 kfree(pp); 611 return retval; 612 } 613 614 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 615 GFP_KERNEL); 616 if (!mem) { 617 ata_pad_free(ap, dev); 618 kfree(pp); 619 return -ENOMEM; 620 } 621 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); 622 623 pp->cmdslot = mem; 624 pp->cmdslot_paddr = mem_dma; 625 626 mem += SATA_FSL_CMD_SLOT_SIZE; 627 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 628 629 pp->cmdentry = mem; 630 pp->cmdentry_paddr = mem_dma; 631 632 ap->private_data = pp; 633 634 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 635 pp->cmdslot_paddr, pp->cmdentry_paddr); 636 637 /* Now, update the CHBA register in host controller cmd register set */ 638 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 639 640 /* 641 * Now, we can bring the controller on-line & also initiate 642 * the COMINIT sequence, we simply return here and the boot-probing 643 * & device discovery process is re-initiated by libATA using a 644 * Softreset EH (dummy) session. Hence, boot probing and device 645 * discovey will be part of sata_fsl_softreset() callback. 646 */ 647 648 temp = ioread32(hcr_base + HCONTROL); 649 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 650 651 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 652 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 653 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 654 655 #ifdef CONFIG_MPC8315_DS 656 /* 657 * Workaround for 8315DS board 3gbps link-up issue, 658 * currently limit SATA port to GEN1 speed 659 */ 660 sata_fsl_scr_read(ap, SCR_CONTROL, &temp); 661 temp &= ~(0xF << 4); 662 temp |= (0x1 << 4); 663 sata_fsl_scr_write(ap, SCR_CONTROL, temp); 664 665 sata_fsl_scr_read(ap, SCR_CONTROL, &temp); 666 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n", 667 temp); 668 #endif 669 670 return 0; 671 } 672 673 static void sata_fsl_port_stop(struct ata_port *ap) 674 { 675 struct device *dev = ap->host->dev; 676 struct sata_fsl_port_priv *pp = ap->private_data; 677 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 678 void __iomem *hcr_base = host_priv->hcr_base; 679 u32 temp; 680 681 /* 682 * Force host controller to go off-line, aborting current operations 683 */ 684 temp = ioread32(hcr_base + HCONTROL); 685 temp &= ~HCONTROL_ONLINE_PHY_RST; 686 temp |= HCONTROL_FORCE_OFFLINE; 687 iowrite32(temp, hcr_base + HCONTROL); 688 689 /* Poll for controller to go offline - should happen immediately */ 690 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 691 692 ap->private_data = NULL; 693 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 694 pp->cmdslot, pp->cmdslot_paddr); 695 696 ata_pad_free(ap, dev); 697 kfree(pp); 698 } 699 700 static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 701 { 702 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 703 void __iomem *hcr_base = host_priv->hcr_base; 704 struct ata_taskfile tf; 705 u32 temp; 706 707 temp = ioread32(hcr_base + SIGNATURE); 708 709 VPRINTK("raw sig = 0x%x\n", temp); 710 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 711 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 712 713 tf.lbah = (temp >> 24) & 0xff; 714 tf.lbam = (temp >> 16) & 0xff; 715 tf.lbal = (temp >> 8) & 0xff; 716 tf.nsect = temp & 0xff; 717 718 return ata_dev_classify(&tf); 719 } 720 721 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 722 unsigned long deadline) 723 { 724 struct ata_port *ap = link->ap; 725 struct sata_fsl_port_priv *pp = ap->private_data; 726 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 727 void __iomem *hcr_base = host_priv->hcr_base; 728 u32 temp; 729 struct ata_taskfile tf; 730 u8 *cfis; 731 u32 Serror; 732 int i = 0; 733 unsigned long start_jiffies; 734 735 DPRINTK("in xx_softreset\n"); 736 737 try_offline_again: 738 /* 739 * Force host controller to go off-line, aborting current operations 740 */ 741 temp = ioread32(hcr_base + HCONTROL); 742 temp &= ~HCONTROL_ONLINE_PHY_RST; 743 iowrite32(temp, hcr_base + HCONTROL); 744 745 /* Poll for controller to go offline */ 746 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); 747 748 if (temp & ONLINE) { 749 ata_port_printk(ap, KERN_ERR, 750 "Softreset failed, not off-lined %d\n", i); 751 752 /* 753 * Try to offline controller atleast twice 754 */ 755 i++; 756 if (i == 2) 757 goto err; 758 else 759 goto try_offline_again; 760 } 761 762 DPRINTK("softreset, controller off-lined\n"); 763 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 764 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 765 766 /* 767 * PHY reset should remain asserted for atleast 1ms 768 */ 769 msleep(1); 770 771 /* 772 * Now, bring the host controller online again, this can take time 773 * as PHY reset and communication establishment, 1st D2H FIS and 774 * device signature update is done, on safe side assume 500ms 775 * NOTE : Host online status may be indicated immediately!! 776 */ 777 778 temp = ioread32(hcr_base + HCONTROL); 779 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 780 iowrite32(temp, hcr_base + HCONTROL); 781 782 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); 783 784 if (!(temp & ONLINE)) { 785 ata_port_printk(ap, KERN_ERR, 786 "Softreset failed, not on-lined\n"); 787 goto err; 788 } 789 790 DPRINTK("softreset, controller off-lined & on-lined\n"); 791 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 792 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 793 794 /* 795 * First, wait for the PHYRDY change to occur before waiting for 796 * the signature, and also verify if SStatus indicates device 797 * presence 798 */ 799 800 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); 801 if ((!(temp & 0x10)) || ata_link_offline(link)) { 802 ata_port_printk(ap, KERN_WARNING, 803 "No Device OR PHYRDY change,Hstatus = 0x%x\n", 804 ioread32(hcr_base + HSTATUS)); 805 goto err; 806 } 807 808 /* 809 * Wait for the first D2H from device,i.e,signature update notification 810 */ 811 start_jiffies = jiffies; 812 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, 813 500, jiffies_to_msecs(deadline - start_jiffies)); 814 815 if ((temp & 0xFF) != 0x18) { 816 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n"); 817 goto err; 818 } else { 819 ata_port_printk(ap, KERN_INFO, 820 "Signature Update detected @ %d msecs\n", 821 jiffies_to_msecs(jiffies - start_jiffies)); 822 } 823 824 /* 825 * Send a device reset (SRST) explicitly on command slot #0 826 * Check : will the command queue (reg) be cleared during offlining ?? 827 * Also we will be online only if Phy commn. has been established 828 * and device presence has been detected, therefore if we have 829 * reached here, we can send a command to the target device 830 */ 831 832 DPRINTK("Sending SRST/device reset\n"); 833 834 ata_tf_init(link->device, &tf); 835 cfis = (u8 *) &pp->cmdentry->cfis; 836 837 /* device reset/SRST is a control register update FIS, uses tag0 */ 838 sata_fsl_setup_cmd_hdr_entry(pp, 0, 839 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 840 841 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 842 ata_tf_to_fis(&tf, 0, 0, cfis); 843 844 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 845 cfis[0], cfis[1], cfis[2], cfis[3]); 846 847 /* 848 * Queue SRST command to the controller/device, ensure that no 849 * other commands are active on the controller/device 850 */ 851 852 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 853 ioread32(CQ + hcr_base), 854 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 855 856 iowrite32(0xFFFF, CC + hcr_base); 857 iowrite32(1, CQ + hcr_base); 858 859 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); 860 if (temp & 0x1) { 861 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); 862 863 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 864 ioread32(CQ + hcr_base), 865 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 866 867 sata_fsl_scr_read(ap, SCR_ERROR, &Serror); 868 869 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 870 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 871 DPRINTK("Serror = 0x%x\n", Serror); 872 goto err; 873 } 874 875 msleep(1); 876 877 /* 878 * SATA device enters reset state after receving a Control register 879 * FIS with SRST bit asserted and it awaits another H2D Control reg. 880 * FIS with SRST bit cleared, then the device does internal diags & 881 * initialization, followed by indicating it's initialization status 882 * using ATA signature D2H register FIS to the host controller. 883 */ 884 885 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 886 887 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 888 ata_tf_to_fis(&tf, 0, 0, cfis); 889 890 iowrite32(1, CQ + hcr_base); 891 msleep(150); /* ?? */ 892 893 /* 894 * The above command would have signalled an interrupt on command 895 * complete, which needs special handling, by clearing the Nth 896 * command bit of the CCreg 897 */ 898 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 899 900 DPRINTK("SATA FSL : Now checking device signature\n"); 901 902 *class = ATA_DEV_NONE; 903 904 /* Verify if SStatus indicates device presence */ 905 if (ata_link_online(link)) { 906 /* 907 * if we are here, device presence has been detected, 908 * 1st D2H FIS would have been received, but sfis in 909 * command desc. is not updated, but signature register 910 * would have been updated 911 */ 912 913 *class = sata_fsl_dev_classify(ap); 914 915 DPRINTK("class = %d\n", *class); 916 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 917 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 918 } 919 920 return 0; 921 922 err: 923 return -EIO; 924 } 925 926 static void sata_fsl_error_handler(struct ata_port *ap) 927 { 928 929 DPRINTK("in xx_error_handler\n"); 930 931 /* perform recovery */ 932 ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_std_hardreset, 933 ata_std_postreset); 934 } 935 936 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 937 { 938 if (qc->flags & ATA_QCFLAG_FAILED) 939 qc->err_mask |= AC_ERR_OTHER; 940 941 if (qc->err_mask) { 942 /* make DMA engine forget about the failed command */ 943 944 } 945 } 946 947 static void sata_fsl_irq_clear(struct ata_port *ap) 948 { 949 /* unused */ 950 } 951 952 static void sata_fsl_error_intr(struct ata_port *ap) 953 { 954 struct ata_link *link = &ap->link; 955 struct ata_eh_info *ehi = &link->eh_info; 956 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 957 void __iomem *hcr_base = host_priv->hcr_base; 958 u32 hstatus, dereg, cereg = 0, SError = 0; 959 unsigned int err_mask = 0, action = 0; 960 struct ata_queued_cmd *qc; 961 int freeze = 0; 962 963 hstatus = ioread32(hcr_base + HSTATUS); 964 cereg = ioread32(hcr_base + CE); 965 966 ata_ehi_clear_desc(ehi); 967 968 /* 969 * Handle & Clear SError 970 */ 971 972 sata_fsl_scr_read(ap, SCR_ERROR, &SError); 973 if (unlikely(SError & 0xFFFF0000)) { 974 sata_fsl_scr_write(ap, SCR_ERROR, SError); 975 err_mask |= AC_ERR_ATA_BUS; 976 } 977 978 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 979 hstatus, cereg, ioread32(hcr_base + DE), SError); 980 981 /* handle single device errors */ 982 if (cereg) { 983 /* 984 * clear the command error, also clears queue to the device 985 * in error, and we can (re)issue commands to this device. 986 * When a device is in error all commands queued into the 987 * host controller and at the device are considered aborted 988 * and the queue for that device is stopped. Now, after 989 * clearing the device error, we can issue commands to the 990 * device to interrogate it to find the source of the error. 991 */ 992 dereg = ioread32(hcr_base + DE); 993 iowrite32(dereg, hcr_base + DE); 994 iowrite32(cereg, hcr_base + CE); 995 996 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 997 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 998 /* 999 * We should consider this as non fatal error, and TF must 1000 * be updated as done below. 1001 */ 1002 1003 err_mask |= AC_ERR_DEV; 1004 } 1005 1006 /* handle fatal errors */ 1007 if (hstatus & FATAL_ERROR_DECODE) { 1008 err_mask |= AC_ERR_ATA_BUS; 1009 action |= ATA_EH_SOFTRESET; 1010 /* how will fatal error interrupts be completed ?? */ 1011 freeze = 1; 1012 } 1013 1014 /* Handle PHYRDY change notification */ 1015 if (hstatus & INT_ON_PHYRDY_CHG) { 1016 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1017 1018 /* Setup a soft-reset EH action */ 1019 ata_ehi_hotplugged(ehi); 1020 freeze = 1; 1021 } 1022 1023 /* record error info */ 1024 qc = ata_qc_from_tag(ap, link->active_tag); 1025 1026 if (qc) { 1027 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap); 1028 qc->err_mask |= err_mask; 1029 } else 1030 ehi->err_mask |= err_mask; 1031 1032 ehi->action |= action; 1033 ehi->serror |= SError; 1034 1035 /* freeze or abort */ 1036 if (freeze) 1037 ata_port_freeze(ap); 1038 else 1039 ata_port_abort(ap); 1040 } 1041 1042 static void sata_fsl_qc_complete(struct ata_queued_cmd *qc) 1043 { 1044 if (qc->flags & ATA_QCFLAG_RESULT_TF) { 1045 DPRINTK("xx_qc_complete called\n"); 1046 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap); 1047 } 1048 } 1049 1050 static void sata_fsl_host_intr(struct ata_port *ap) 1051 { 1052 struct ata_link *link = &ap->link; 1053 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1054 void __iomem *hcr_base = host_priv->hcr_base; 1055 u32 hstatus, qc_active = 0; 1056 struct ata_queued_cmd *qc; 1057 u32 SError; 1058 1059 hstatus = ioread32(hcr_base + HSTATUS); 1060 1061 sata_fsl_scr_read(ap, SCR_ERROR, &SError); 1062 1063 if (unlikely(SError & 0xFFFF0000)) { 1064 DPRINTK("serror @host_intr : 0x%x\n", SError); 1065 sata_fsl_error_intr(ap); 1066 1067 } 1068 1069 if (unlikely(hstatus & INT_ON_ERROR)) { 1070 DPRINTK("error interrupt!!\n"); 1071 sata_fsl_error_intr(ap); 1072 return; 1073 } 1074 1075 if (link->sactive) { /* only true for NCQ commands */ 1076 int i; 1077 /* Read command completed register */ 1078 qc_active = ioread32(hcr_base + CC); 1079 /* clear CC bit, this will also complete the interrupt */ 1080 iowrite32(qc_active, hcr_base + CC); 1081 1082 DPRINTK("Status of all queues :\n"); 1083 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1084 qc_active, ioread32(hcr_base + CA), 1085 ioread32(hcr_base + CE)); 1086 1087 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1088 if (qc_active & (1 << i)) { 1089 qc = ata_qc_from_tag(ap, i); 1090 if (qc) { 1091 sata_fsl_qc_complete(qc); 1092 ata_qc_complete(qc); 1093 } 1094 DPRINTK 1095 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1096 i, ioread32(hcr_base + CC), 1097 ioread32(hcr_base + CA)); 1098 } 1099 } 1100 return; 1101 1102 } else if (ap->qc_active) { 1103 iowrite32(1, hcr_base + CC); 1104 qc = ata_qc_from_tag(ap, link->active_tag); 1105 1106 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n", 1107 link->active_tag, ioread32(hcr_base + CC)); 1108 1109 if (qc) { 1110 sata_fsl_qc_complete(qc); 1111 ata_qc_complete(qc); 1112 } 1113 } else { 1114 /* Spurious Interrupt!! */ 1115 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1116 ioread32(hcr_base + CC)); 1117 return; 1118 } 1119 } 1120 1121 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1122 { 1123 struct ata_host *host = dev_instance; 1124 struct sata_fsl_host_priv *host_priv = host->private_data; 1125 void __iomem *hcr_base = host_priv->hcr_base; 1126 u32 interrupt_enables; 1127 unsigned handled = 0; 1128 struct ata_port *ap; 1129 1130 /* ack. any pending IRQs for this controller/port */ 1131 interrupt_enables = ioread32(hcr_base + HSTATUS); 1132 interrupt_enables &= 0x3F; 1133 1134 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1135 1136 if (!interrupt_enables) 1137 return IRQ_NONE; 1138 1139 spin_lock(&host->lock); 1140 1141 /* Assuming one port per host controller */ 1142 1143 ap = host->ports[0]; 1144 if (ap) { 1145 sata_fsl_host_intr(ap); 1146 } else { 1147 dev_printk(KERN_WARNING, host->dev, 1148 "interrupt on disabled port 0\n"); 1149 } 1150 1151 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1152 handled = 1; 1153 1154 spin_unlock(&host->lock); 1155 1156 return IRQ_RETVAL(handled); 1157 } 1158 1159 /* 1160 * Multiple ports are represented by multiple SATA controllers with 1161 * one port per controller 1162 */ 1163 static int sata_fsl_init_controller(struct ata_host *host) 1164 { 1165 struct sata_fsl_host_priv *host_priv = host->private_data; 1166 void __iomem *hcr_base = host_priv->hcr_base; 1167 u32 temp; 1168 1169 /* 1170 * NOTE : We cannot bring the controller online before setting 1171 * the CHBA, hence main controller initialization is done as 1172 * part of the port_start() callback 1173 */ 1174 1175 /* ack. any pending IRQs for this controller/port */ 1176 temp = ioread32(hcr_base + HSTATUS); 1177 if (temp & 0x3F) 1178 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1179 1180 /* Keep interrupts disabled on the controller */ 1181 temp = ioread32(hcr_base + HCONTROL); 1182 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1183 1184 /* Disable interrupt coalescing control(icc), for the moment */ 1185 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1186 iowrite32(0x01000000, hcr_base + ICC); 1187 1188 /* clear error registers, SError is cleared by libATA */ 1189 iowrite32(0x00000FFFF, hcr_base + CE); 1190 iowrite32(0x00000FFFF, hcr_base + DE); 1191 1192 /* initially assuming no Port multiplier, set CQPMP to 0 */ 1193 iowrite32(0x0, hcr_base + CQPMP); 1194 1195 /* 1196 * host controller will be brought on-line, during xx_port_start() 1197 * callback, that should also initiate the OOB, COMINIT sequence 1198 */ 1199 1200 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1201 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1202 1203 return 0; 1204 } 1205 1206 /* 1207 * scsi mid-layer and libata interface structures 1208 */ 1209 static struct scsi_host_template sata_fsl_sht = { 1210 .module = THIS_MODULE, 1211 .name = "sata_fsl", 1212 .ioctl = ata_scsi_ioctl, 1213 .queuecommand = ata_scsi_queuecmd, 1214 .change_queue_depth = ata_scsi_change_queue_depth, 1215 .can_queue = SATA_FSL_QUEUE_DEPTH, 1216 .this_id = ATA_SHT_THIS_ID, 1217 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1218 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 1219 .emulated = ATA_SHT_EMULATED, 1220 .use_clustering = ATA_SHT_USE_CLUSTERING, 1221 .proc_name = "sata_fsl", 1222 .dma_boundary = ATA_DMA_BOUNDARY, 1223 .slave_configure = ata_scsi_slave_config, 1224 .slave_destroy = ata_scsi_slave_destroy, 1225 .bios_param = ata_std_bios_param, 1226 }; 1227 1228 static const struct ata_port_operations sata_fsl_ops = { 1229 .check_status = sata_fsl_check_status, 1230 .check_altstatus = sata_fsl_check_status, 1231 .dev_select = ata_noop_dev_select, 1232 1233 .tf_read = sata_fsl_tf_read, 1234 1235 .qc_prep = sata_fsl_qc_prep, 1236 .qc_issue = sata_fsl_qc_issue, 1237 .irq_clear = sata_fsl_irq_clear, 1238 1239 .scr_read = sata_fsl_scr_read, 1240 .scr_write = sata_fsl_scr_write, 1241 1242 .freeze = sata_fsl_freeze, 1243 .thaw = sata_fsl_thaw, 1244 .error_handler = sata_fsl_error_handler, 1245 .post_internal_cmd = sata_fsl_post_internal_cmd, 1246 1247 .port_start = sata_fsl_port_start, 1248 .port_stop = sata_fsl_port_stop, 1249 }; 1250 1251 static const struct ata_port_info sata_fsl_port_info[] = { 1252 { 1253 .flags = SATA_FSL_HOST_FLAGS, 1254 .link_flags = SATA_FSL_HOST_LFLAGS, 1255 .pio_mask = 0x1f, /* pio 0-4 */ 1256 .udma_mask = 0x7f, /* udma 0-6 */ 1257 .port_ops = &sata_fsl_ops, 1258 }, 1259 }; 1260 1261 static int sata_fsl_probe(struct of_device *ofdev, 1262 const struct of_device_id *match) 1263 { 1264 int retval = 0; 1265 void __iomem *hcr_base = NULL; 1266 void __iomem *ssr_base = NULL; 1267 void __iomem *csr_base = NULL; 1268 struct sata_fsl_host_priv *host_priv = NULL; 1269 struct resource *r; 1270 int irq; 1271 struct ata_host *host; 1272 1273 struct ata_port_info pi = sata_fsl_port_info[0]; 1274 const struct ata_port_info *ppi[] = { &pi, NULL }; 1275 1276 dev_printk(KERN_INFO, &ofdev->dev, 1277 "Sata FSL Platform/CSB Driver init\n"); 1278 1279 r = kmalloc(sizeof(struct resource), GFP_KERNEL); 1280 1281 hcr_base = of_iomap(ofdev->node, 0); 1282 if (!hcr_base) 1283 goto error_exit_with_cleanup; 1284 1285 ssr_base = hcr_base + 0x100; 1286 csr_base = hcr_base + 0x140; 1287 1288 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1289 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1290 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1291 1292 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1293 if (!host_priv) 1294 goto error_exit_with_cleanup; 1295 1296 host_priv->hcr_base = hcr_base; 1297 host_priv->ssr_base = ssr_base; 1298 host_priv->csr_base = csr_base; 1299 1300 irq = irq_of_parse_and_map(ofdev->node, 0); 1301 if (irq < 0) { 1302 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n"); 1303 goto error_exit_with_cleanup; 1304 } 1305 host_priv->irq = irq; 1306 1307 /* allocate host structure */ 1308 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1309 1310 /* host->iomap is not used currently */ 1311 host->private_data = host_priv; 1312 1313 /* setup port(s) */ 1314 1315 host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base; 1316 host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base; 1317 1318 /* initialize host controller */ 1319 sata_fsl_init_controller(host); 1320 1321 /* 1322 * Now, register with libATA core, this will also initiate the 1323 * device discovery process, invoking our port_start() handler & 1324 * error_handler() to execute a dummy Softreset EH session 1325 */ 1326 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1327 &sata_fsl_sht); 1328 1329 dev_set_drvdata(&ofdev->dev, host); 1330 1331 return 0; 1332 1333 error_exit_with_cleanup: 1334 1335 if (hcr_base) 1336 iounmap(hcr_base); 1337 if (host_priv) 1338 kfree(host_priv); 1339 1340 return retval; 1341 } 1342 1343 static int sata_fsl_remove(struct of_device *ofdev) 1344 { 1345 struct ata_host *host = dev_get_drvdata(&ofdev->dev); 1346 struct sata_fsl_host_priv *host_priv = host->private_data; 1347 1348 ata_host_detach(host); 1349 1350 dev_set_drvdata(&ofdev->dev, NULL); 1351 1352 irq_dispose_mapping(host_priv->irq); 1353 iounmap(host_priv->hcr_base); 1354 kfree(host_priv); 1355 1356 return 0; 1357 } 1358 1359 static struct of_device_id fsl_sata_match[] = { 1360 { 1361 .compatible = "fsl,mpc8315-sata", 1362 }, 1363 { 1364 .compatible = "fsl,mpc8379-sata", 1365 }, 1366 {}, 1367 }; 1368 1369 MODULE_DEVICE_TABLE(of, fsl_sata_match); 1370 1371 static struct of_platform_driver fsl_sata_driver = { 1372 .name = "fsl-sata", 1373 .match_table = fsl_sata_match, 1374 .probe = sata_fsl_probe, 1375 .remove = sata_fsl_remove, 1376 }; 1377 1378 static int __init sata_fsl_init(void) 1379 { 1380 of_register_platform_driver(&fsl_sata_driver); 1381 return 0; 1382 } 1383 1384 static void __exit sata_fsl_exit(void) 1385 { 1386 of_unregister_platform_driver(&fsl_sata_driver); 1387 } 1388 1389 MODULE_LICENSE("GPL"); 1390 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1391 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1392 MODULE_VERSION("1.10"); 1393 1394 module_init(sata_fsl_init); 1395 module_exit(sata_fsl_exit); 1396