1 /* 2 * pdc_adma.c - Pacific Digital Corporation ADMA 3 * 4 * Maintained by: Mark Lord <mlord@pobox.com> 5 * 6 * Copyright 2005 Mark Lord 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * 23 * libata documentation is available via 'make {ps|pdf}docs', 24 * as Documentation/DocBook/libata.* 25 * 26 * 27 * Supports ATA disks in single-packet ADMA mode. 28 * Uses PIO for everything else. 29 * 30 * TODO: Use ADMA transfers for ATAPI devices, when possible. 31 * This requires careful attention to a number of quirks of the chip. 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/device.h> 43 #include <scsi/scsi_host.h> 44 #include <linux/libata.h> 45 46 #define DRV_NAME "pdc_adma" 47 #define DRV_VERSION "0.05" 48 49 /* macro to calculate base address for ATA regs */ 50 #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40)) 51 52 /* macro to calculate base address for ADMA regs */ 53 #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20)) 54 55 /* macro to obtain addresses from ata_host */ 56 #define ADMA_HOST_REGS(host,port_no) \ 57 ADMA_REGS((host)->iomap[ADMA_MMIO_BAR], port_no) 58 59 enum { 60 ADMA_MMIO_BAR = 4, 61 62 ADMA_PORTS = 2, 63 ADMA_CPB_BYTES = 40, 64 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, 65 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES, 66 67 ADMA_DMA_BOUNDARY = 0xffffffff, 68 69 /* global register offsets */ 70 ADMA_MODE_LOCK = 0x00c7, 71 72 /* per-channel register offsets */ 73 ADMA_CONTROL = 0x0000, /* ADMA control */ 74 ADMA_STATUS = 0x0002, /* ADMA status */ 75 ADMA_CPB_COUNT = 0x0004, /* CPB count */ 76 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */ 77 ADMA_CPB_NEXT = 0x000c, /* next CPB address */ 78 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */ 79 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */ 80 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */ 81 82 /* ADMA_CONTROL register bits */ 83 aNIEN = (1 << 8), /* irq mask: 1==masked */ 84 aGO = (1 << 7), /* packet trigger ("Go!") */ 85 aRSTADM = (1 << 5), /* ADMA logic reset */ 86 aPIOMD4 = 0x0003, /* PIO mode 4 */ 87 88 /* ADMA_STATUS register bits */ 89 aPSD = (1 << 6), 90 aUIRQ = (1 << 4), 91 aPERR = (1 << 0), 92 93 /* CPB bits */ 94 cDONE = (1 << 0), 95 cVLD = (1 << 0), 96 cDAT = (1 << 2), 97 cIEN = (1 << 3), 98 99 /* PRD bits */ 100 pORD = (1 << 4), 101 pDIRO = (1 << 5), 102 pEND = (1 << 7), 103 104 /* ATA register flags */ 105 rIGN = (1 << 5), 106 rEND = (1 << 7), 107 108 /* ATA register addresses */ 109 ADMA_REGS_CONTROL = 0x0e, 110 ADMA_REGS_SECTOR_COUNT = 0x12, 111 ADMA_REGS_LBA_LOW = 0x13, 112 ADMA_REGS_LBA_MID = 0x14, 113 ADMA_REGS_LBA_HIGH = 0x15, 114 ADMA_REGS_DEVICE = 0x16, 115 ADMA_REGS_COMMAND = 0x17, 116 117 /* PCI device IDs */ 118 board_1841_idx = 0, /* ADMA 2-port controller */ 119 }; 120 121 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t; 122 123 struct adma_port_priv { 124 u8 *pkt; 125 dma_addr_t pkt_dma; 126 adma_state_t state; 127 }; 128 129 static int adma_ata_init_one (struct pci_dev *pdev, 130 const struct pci_device_id *ent); 131 static irqreturn_t adma_intr (int irq, void *dev_instance); 132 static int adma_port_start(struct ata_port *ap); 133 static void adma_host_stop(struct ata_host *host); 134 static void adma_port_stop(struct ata_port *ap); 135 static void adma_phy_reset(struct ata_port *ap); 136 static void adma_qc_prep(struct ata_queued_cmd *qc); 137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc); 138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc); 139 static void adma_bmdma_stop(struct ata_queued_cmd *qc); 140 static u8 adma_bmdma_status(struct ata_port *ap); 141 static void adma_irq_clear(struct ata_port *ap); 142 static void adma_eng_timeout(struct ata_port *ap); 143 144 static struct scsi_host_template adma_ata_sht = { 145 .module = THIS_MODULE, 146 .name = DRV_NAME, 147 .ioctl = ata_scsi_ioctl, 148 .queuecommand = ata_scsi_queuecmd, 149 .can_queue = ATA_DEF_QUEUE, 150 .this_id = ATA_SHT_THIS_ID, 151 .sg_tablesize = LIBATA_MAX_PRD, 152 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 153 .emulated = ATA_SHT_EMULATED, 154 .use_clustering = ENABLE_CLUSTERING, 155 .proc_name = DRV_NAME, 156 .dma_boundary = ADMA_DMA_BOUNDARY, 157 .slave_configure = ata_scsi_slave_config, 158 .slave_destroy = ata_scsi_slave_destroy, 159 .bios_param = ata_std_bios_param, 160 }; 161 162 static const struct ata_port_operations adma_ata_ops = { 163 .port_disable = ata_port_disable, 164 .tf_load = ata_tf_load, 165 .tf_read = ata_tf_read, 166 .check_status = ata_check_status, 167 .check_atapi_dma = adma_check_atapi_dma, 168 .exec_command = ata_exec_command, 169 .dev_select = ata_std_dev_select, 170 .phy_reset = adma_phy_reset, 171 .qc_prep = adma_qc_prep, 172 .qc_issue = adma_qc_issue, 173 .eng_timeout = adma_eng_timeout, 174 .data_xfer = ata_data_xfer, 175 .irq_handler = adma_intr, 176 .irq_clear = adma_irq_clear, 177 .irq_on = ata_irq_on, 178 .irq_ack = ata_irq_ack, 179 .port_start = adma_port_start, 180 .port_stop = adma_port_stop, 181 .host_stop = adma_host_stop, 182 .bmdma_stop = adma_bmdma_stop, 183 .bmdma_status = adma_bmdma_status, 184 }; 185 186 static struct ata_port_info adma_port_info[] = { 187 /* board_1841_idx */ 188 { 189 .sht = &adma_ata_sht, 190 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | 191 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | 192 ATA_FLAG_PIO_POLLING, 193 .pio_mask = 0x10, /* pio4 */ 194 .udma_mask = 0x1f, /* udma0-4 */ 195 .port_ops = &adma_ata_ops, 196 }, 197 }; 198 199 static const struct pci_device_id adma_ata_pci_tbl[] = { 200 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx }, 201 202 { } /* terminate list */ 203 }; 204 205 static struct pci_driver adma_ata_pci_driver = { 206 .name = DRV_NAME, 207 .id_table = adma_ata_pci_tbl, 208 .probe = adma_ata_init_one, 209 .remove = ata_pci_remove_one, 210 }; 211 212 static int adma_check_atapi_dma(struct ata_queued_cmd *qc) 213 { 214 return 1; /* ATAPI DMA not yet supported */ 215 } 216 217 static void adma_bmdma_stop(struct ata_queued_cmd *qc) 218 { 219 /* nothing */ 220 } 221 222 static u8 adma_bmdma_status(struct ata_port *ap) 223 { 224 return 0; 225 } 226 227 static void adma_irq_clear(struct ata_port *ap) 228 { 229 /* nothing */ 230 } 231 232 static void adma_reset_engine(void __iomem *chan) 233 { 234 /* reset ADMA to idle state */ 235 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); 236 udelay(2); 237 writew(aPIOMD4, chan + ADMA_CONTROL); 238 udelay(2); 239 } 240 241 static void adma_reinit_engine(struct ata_port *ap) 242 { 243 struct adma_port_priv *pp = ap->private_data; 244 void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no); 245 246 /* mask/clear ATA interrupts */ 247 writeb(ATA_NIEN, ap->ioaddr.ctl_addr); 248 ata_check_status(ap); 249 250 /* reset the ADMA engine */ 251 adma_reset_engine(chan); 252 253 /* set in-FIFO threshold to 0x100 */ 254 writew(0x100, chan + ADMA_FIFO_IN); 255 256 /* set CPB pointer */ 257 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT); 258 259 /* set out-FIFO threshold to 0x100 */ 260 writew(0x100, chan + ADMA_FIFO_OUT); 261 262 /* set CPB count */ 263 writew(1, chan + ADMA_CPB_COUNT); 264 265 /* read/discard ADMA status */ 266 readb(chan + ADMA_STATUS); 267 } 268 269 static inline void adma_enter_reg_mode(struct ata_port *ap) 270 { 271 void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no); 272 273 writew(aPIOMD4, chan + ADMA_CONTROL); 274 readb(chan + ADMA_STATUS); /* flush */ 275 } 276 277 static void adma_phy_reset(struct ata_port *ap) 278 { 279 struct adma_port_priv *pp = ap->private_data; 280 281 pp->state = adma_state_idle; 282 adma_reinit_engine(ap); 283 ata_port_probe(ap); 284 ata_bus_reset(ap); 285 } 286 287 static void adma_eng_timeout(struct ata_port *ap) 288 { 289 struct adma_port_priv *pp = ap->private_data; 290 291 if (pp->state != adma_state_idle) /* healthy paranoia */ 292 pp->state = adma_state_mmio; 293 adma_reinit_engine(ap); 294 ata_eng_timeout(ap); 295 } 296 297 static int adma_fill_sg(struct ata_queued_cmd *qc) 298 { 299 struct scatterlist *sg; 300 struct ata_port *ap = qc->ap; 301 struct adma_port_priv *pp = ap->private_data; 302 u8 *buf = pp->pkt; 303 int i = (2 + buf[3]) * 8; 304 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); 305 306 ata_for_each_sg(sg, qc) { 307 u32 addr; 308 u32 len; 309 310 addr = (u32)sg_dma_address(sg); 311 *(__le32 *)(buf + i) = cpu_to_le32(addr); 312 i += 4; 313 314 len = sg_dma_len(sg) >> 3; 315 *(__le32 *)(buf + i) = cpu_to_le32(len); 316 i += 4; 317 318 if (ata_sg_is_last(sg, qc)) 319 pFLAGS |= pEND; 320 buf[i++] = pFLAGS; 321 buf[i++] = qc->dev->dma_mode & 0xf; 322 buf[i++] = 0; /* pPKLW */ 323 buf[i++] = 0; /* reserved */ 324 325 *(__le32 *)(buf + i) 326 = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4); 327 i += 4; 328 329 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4, 330 (unsigned long)addr, len); 331 } 332 return i; 333 } 334 335 static void adma_qc_prep(struct ata_queued_cmd *qc) 336 { 337 struct adma_port_priv *pp = qc->ap->private_data; 338 u8 *buf = pp->pkt; 339 u32 pkt_dma = (u32)pp->pkt_dma; 340 int i = 0; 341 342 VPRINTK("ENTER\n"); 343 344 adma_enter_reg_mode(qc->ap); 345 if (qc->tf.protocol != ATA_PROT_DMA) { 346 ata_qc_prep(qc); 347 return; 348 } 349 350 buf[i++] = 0; /* Response flags */ 351 buf[i++] = 0; /* reserved */ 352 buf[i++] = cVLD | cDAT | cIEN; 353 i++; /* cLEN, gets filled in below */ 354 355 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */ 356 i += 4; /* cNCPB */ 357 i += 4; /* cPRD, gets filled in below */ 358 359 buf[i++] = 0; /* reserved */ 360 buf[i++] = 0; /* reserved */ 361 buf[i++] = 0; /* reserved */ 362 buf[i++] = 0; /* reserved */ 363 364 /* ATA registers; must be a multiple of 4 */ 365 buf[i++] = qc->tf.device; 366 buf[i++] = ADMA_REGS_DEVICE; 367 if ((qc->tf.flags & ATA_TFLAG_LBA48)) { 368 buf[i++] = qc->tf.hob_nsect; 369 buf[i++] = ADMA_REGS_SECTOR_COUNT; 370 buf[i++] = qc->tf.hob_lbal; 371 buf[i++] = ADMA_REGS_LBA_LOW; 372 buf[i++] = qc->tf.hob_lbam; 373 buf[i++] = ADMA_REGS_LBA_MID; 374 buf[i++] = qc->tf.hob_lbah; 375 buf[i++] = ADMA_REGS_LBA_HIGH; 376 } 377 buf[i++] = qc->tf.nsect; 378 buf[i++] = ADMA_REGS_SECTOR_COUNT; 379 buf[i++] = qc->tf.lbal; 380 buf[i++] = ADMA_REGS_LBA_LOW; 381 buf[i++] = qc->tf.lbam; 382 buf[i++] = ADMA_REGS_LBA_MID; 383 buf[i++] = qc->tf.lbah; 384 buf[i++] = ADMA_REGS_LBA_HIGH; 385 buf[i++] = 0; 386 buf[i++] = ADMA_REGS_CONTROL; 387 buf[i++] = rIGN; 388 buf[i++] = 0; 389 buf[i++] = qc->tf.command; 390 buf[i++] = ADMA_REGS_COMMAND | rEND; 391 392 buf[3] = (i >> 3) - 2; /* cLEN */ 393 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */ 394 395 i = adma_fill_sg(qc); 396 wmb(); /* flush PRDs and pkt to memory */ 397 #if 0 398 /* dump out CPB + PRDs for debug */ 399 { 400 int j, len = 0; 401 static char obuf[2048]; 402 for (j = 0; j < i; ++j) { 403 len += sprintf(obuf+len, "%02x ", buf[j]); 404 if ((j & 7) == 7) { 405 printk("%s\n", obuf); 406 len = 0; 407 } 408 } 409 if (len) 410 printk("%s\n", obuf); 411 } 412 #endif 413 } 414 415 static inline void adma_packet_start(struct ata_queued_cmd *qc) 416 { 417 struct ata_port *ap = qc->ap; 418 void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no); 419 420 VPRINTK("ENTER, ap %p\n", ap); 421 422 /* fire up the ADMA engine */ 423 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL); 424 } 425 426 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) 427 { 428 struct adma_port_priv *pp = qc->ap->private_data; 429 430 switch (qc->tf.protocol) { 431 case ATA_PROT_DMA: 432 pp->state = adma_state_pkt; 433 adma_packet_start(qc); 434 return 0; 435 436 case ATA_PROT_ATAPI_DMA: 437 BUG(); 438 break; 439 440 default: 441 break; 442 } 443 444 pp->state = adma_state_mmio; 445 return ata_qc_issue_prot(qc); 446 } 447 448 static inline unsigned int adma_intr_pkt(struct ata_host *host) 449 { 450 unsigned int handled = 0, port_no; 451 452 for (port_no = 0; port_no < host->n_ports; ++port_no) { 453 struct ata_port *ap = host->ports[port_no]; 454 struct adma_port_priv *pp; 455 struct ata_queued_cmd *qc; 456 void __iomem *chan = ADMA_HOST_REGS(host, port_no); 457 u8 status = readb(chan + ADMA_STATUS); 458 459 if (status == 0) 460 continue; 461 handled = 1; 462 adma_enter_reg_mode(ap); 463 if (ap->flags & ATA_FLAG_DISABLED) 464 continue; 465 pp = ap->private_data; 466 if (!pp || pp->state != adma_state_pkt) 467 continue; 468 qc = ata_qc_from_tag(ap, ap->active_tag); 469 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 470 if ((status & (aPERR | aPSD | aUIRQ))) 471 qc->err_mask |= AC_ERR_OTHER; 472 else if (pp->pkt[0] != cDONE) 473 qc->err_mask |= AC_ERR_OTHER; 474 475 ata_qc_complete(qc); 476 } 477 } 478 return handled; 479 } 480 481 static inline unsigned int adma_intr_mmio(struct ata_host *host) 482 { 483 unsigned int handled = 0, port_no; 484 485 for (port_no = 0; port_no < host->n_ports; ++port_no) { 486 struct ata_port *ap; 487 ap = host->ports[port_no]; 488 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) { 489 struct ata_queued_cmd *qc; 490 struct adma_port_priv *pp = ap->private_data; 491 if (!pp || pp->state != adma_state_mmio) 492 continue; 493 qc = ata_qc_from_tag(ap, ap->active_tag); 494 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 495 496 /* check main status, clearing INTRQ */ 497 u8 status = ata_check_status(ap); 498 if ((status & ATA_BUSY)) 499 continue; 500 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", 501 ap->print_id, qc->tf.protocol, status); 502 503 /* complete taskfile transaction */ 504 pp->state = adma_state_idle; 505 qc->err_mask |= ac_err_mask(status); 506 ata_qc_complete(qc); 507 handled = 1; 508 } 509 } 510 } 511 return handled; 512 } 513 514 static irqreturn_t adma_intr(int irq, void *dev_instance) 515 { 516 struct ata_host *host = dev_instance; 517 unsigned int handled = 0; 518 519 VPRINTK("ENTER\n"); 520 521 spin_lock(&host->lock); 522 handled = adma_intr_pkt(host) | adma_intr_mmio(host); 523 spin_unlock(&host->lock); 524 525 VPRINTK("EXIT\n"); 526 527 return IRQ_RETVAL(handled); 528 } 529 530 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base) 531 { 532 port->cmd_addr = 533 port->data_addr = base + 0x000; 534 port->error_addr = 535 port->feature_addr = base + 0x004; 536 port->nsect_addr = base + 0x008; 537 port->lbal_addr = base + 0x00c; 538 port->lbam_addr = base + 0x010; 539 port->lbah_addr = base + 0x014; 540 port->device_addr = base + 0x018; 541 port->status_addr = 542 port->command_addr = base + 0x01c; 543 port->altstatus_addr = 544 port->ctl_addr = base + 0x038; 545 } 546 547 static int adma_port_start(struct ata_port *ap) 548 { 549 struct device *dev = ap->host->dev; 550 struct adma_port_priv *pp; 551 int rc; 552 553 rc = ata_port_start(ap); 554 if (rc) 555 return rc; 556 adma_enter_reg_mode(ap); 557 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 558 if (!pp) 559 return -ENOMEM; 560 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma, 561 GFP_KERNEL); 562 if (!pp->pkt) 563 return -ENOMEM; 564 /* paranoia? */ 565 if ((pp->pkt_dma & 7) != 0) { 566 printk("bad alignment for pp->pkt_dma: %08x\n", 567 (u32)pp->pkt_dma); 568 return -ENOMEM; 569 } 570 memset(pp->pkt, 0, ADMA_PKT_BYTES); 571 ap->private_data = pp; 572 adma_reinit_engine(ap); 573 return 0; 574 } 575 576 static void adma_port_stop(struct ata_port *ap) 577 { 578 adma_reset_engine(ADMA_HOST_REGS(ap->host, ap->port_no)); 579 } 580 581 static void adma_host_stop(struct ata_host *host) 582 { 583 unsigned int port_no; 584 585 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) 586 adma_reset_engine(ADMA_HOST_REGS(host, port_no)); 587 } 588 589 static void adma_host_init(unsigned int chip_id, 590 struct ata_probe_ent *probe_ent) 591 { 592 unsigned int port_no; 593 void __iomem *mmio_base = probe_ent->iomap[ADMA_MMIO_BAR]; 594 595 /* enable/lock aGO operation */ 596 writeb(7, mmio_base + ADMA_MODE_LOCK); 597 598 /* reset the ADMA logic */ 599 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) 600 adma_reset_engine(ADMA_REGS(mmio_base, port_no)); 601 } 602 603 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) 604 { 605 int rc; 606 607 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 608 if (rc) { 609 dev_printk(KERN_ERR, &pdev->dev, 610 "32-bit DMA enable failed\n"); 611 return rc; 612 } 613 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 614 if (rc) { 615 dev_printk(KERN_ERR, &pdev->dev, 616 "32-bit consistent DMA enable failed\n"); 617 return rc; 618 } 619 return 0; 620 } 621 622 static int adma_ata_init_one(struct pci_dev *pdev, 623 const struct pci_device_id *ent) 624 { 625 static int printed_version; 626 struct ata_probe_ent *probe_ent = NULL; 627 void __iomem *mmio_base; 628 unsigned int board_idx = (unsigned int) ent->driver_data; 629 int rc, port_no; 630 631 if (!printed_version++) 632 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 633 634 rc = pcim_enable_device(pdev); 635 if (rc) 636 return rc; 637 638 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) 639 return -ENODEV; 640 641 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME); 642 if (rc) 643 return rc; 644 mmio_base = pcim_iomap_table(pdev)[ADMA_MMIO_BAR]; 645 646 rc = adma_set_dma_masks(pdev, mmio_base); 647 if (rc) 648 return rc; 649 650 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); 651 if (probe_ent == NULL) 652 return -ENOMEM; 653 654 probe_ent->dev = pci_dev_to_dev(pdev); 655 INIT_LIST_HEAD(&probe_ent->node); 656 657 probe_ent->sht = adma_port_info[board_idx].sht; 658 probe_ent->port_flags = adma_port_info[board_idx].flags; 659 probe_ent->pio_mask = adma_port_info[board_idx].pio_mask; 660 probe_ent->mwdma_mask = adma_port_info[board_idx].mwdma_mask; 661 probe_ent->udma_mask = adma_port_info[board_idx].udma_mask; 662 probe_ent->port_ops = adma_port_info[board_idx].port_ops; 663 664 probe_ent->irq = pdev->irq; 665 probe_ent->irq_flags = IRQF_SHARED; 666 probe_ent->n_ports = ADMA_PORTS; 667 probe_ent->iomap = pcim_iomap_table(pdev); 668 669 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { 670 adma_ata_setup_port(&probe_ent->port[port_no], 671 ADMA_ATA_REGS(mmio_base, port_no)); 672 } 673 674 pci_set_master(pdev); 675 676 /* initialize adapter */ 677 adma_host_init(board_idx, probe_ent); 678 679 if (!ata_device_add(probe_ent)) 680 return -ENODEV; 681 682 devm_kfree(&pdev->dev, probe_ent); 683 return 0; 684 } 685 686 static int __init adma_ata_init(void) 687 { 688 return pci_register_driver(&adma_ata_pci_driver); 689 } 690 691 static void __exit adma_ata_exit(void) 692 { 693 pci_unregister_driver(&adma_ata_pci_driver); 694 } 695 696 MODULE_AUTHOR("Mark Lord"); 697 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver"); 698 MODULE_LICENSE("GPL"); 699 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl); 700 MODULE_VERSION(DRV_VERSION); 701 702 module_init(adma_ata_init); 703 module_exit(adma_ata_exit); 704