1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pdc_adma.c - Pacific Digital Corporation ADMA 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * 7 * Copyright 2005 Mark Lord 8 * 9 * libata documentation is available via 'make {ps|pdf}docs', 10 * as Documentation/driver-api/libata.rst 11 * 12 * Supports ATA disks in single-packet ADMA mode. 13 * Uses PIO for everything else. 14 * 15 * TODO: Use ADMA transfers for ATAPI devices, when possible. 16 * This requires careful attention to a number of quirks of the chip. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/gfp.h> 22 #include <linux/pci.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/device.h> 27 #include <scsi/scsi_host.h> 28 #include <linux/libata.h> 29 30 #define DRV_NAME "pdc_adma" 31 #define DRV_VERSION "1.0" 32 33 /* macro to calculate base address for ATA regs */ 34 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40)) 35 36 /* macro to calculate base address for ADMA regs */ 37 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20)) 38 39 /* macro to obtain addresses from ata_port */ 40 #define ADMA_PORT_REGS(ap) \ 41 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no) 42 43 enum { 44 ADMA_MMIO_BAR = 4, 45 46 ADMA_PORTS = 2, 47 ADMA_CPB_BYTES = 40, 48 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, 49 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES, 50 51 ADMA_DMA_BOUNDARY = 0xffffffff, 52 53 /* global register offsets */ 54 ADMA_MODE_LOCK = 0x00c7, 55 56 /* per-channel register offsets */ 57 ADMA_CONTROL = 0x0000, /* ADMA control */ 58 ADMA_STATUS = 0x0002, /* ADMA status */ 59 ADMA_CPB_COUNT = 0x0004, /* CPB count */ 60 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */ 61 ADMA_CPB_NEXT = 0x000c, /* next CPB address */ 62 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */ 63 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */ 64 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */ 65 66 /* ADMA_CONTROL register bits */ 67 aNIEN = (1 << 8), /* irq mask: 1==masked */ 68 aGO = (1 << 7), /* packet trigger ("Go!") */ 69 aRSTADM = (1 << 5), /* ADMA logic reset */ 70 aPIOMD4 = 0x0003, /* PIO mode 4 */ 71 72 /* ADMA_STATUS register bits */ 73 aPSD = (1 << 6), 74 aUIRQ = (1 << 4), 75 aPERR = (1 << 0), 76 77 /* CPB bits */ 78 cDONE = (1 << 0), 79 cATERR = (1 << 3), 80 81 cVLD = (1 << 0), 82 cDAT = (1 << 2), 83 cIEN = (1 << 3), 84 85 /* PRD bits */ 86 pORD = (1 << 4), 87 pDIRO = (1 << 5), 88 pEND = (1 << 7), 89 90 /* ATA register flags */ 91 rIGN = (1 << 5), 92 rEND = (1 << 7), 93 94 /* ATA register addresses */ 95 ADMA_REGS_CONTROL = 0x0e, 96 ADMA_REGS_SECTOR_COUNT = 0x12, 97 ADMA_REGS_LBA_LOW = 0x13, 98 ADMA_REGS_LBA_MID = 0x14, 99 ADMA_REGS_LBA_HIGH = 0x15, 100 ADMA_REGS_DEVICE = 0x16, 101 ADMA_REGS_COMMAND = 0x17, 102 103 /* PCI device IDs */ 104 board_1841_idx = 0, /* ADMA 2-port controller */ 105 }; 106 107 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t; 108 109 struct adma_port_priv { 110 u8 *pkt; 111 dma_addr_t pkt_dma; 112 adma_state_t state; 113 }; 114 115 static int adma_ata_init_one(struct pci_dev *pdev, 116 const struct pci_device_id *ent); 117 static int adma_port_start(struct ata_port *ap); 118 static void adma_port_stop(struct ata_port *ap); 119 static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc); 120 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc); 121 static int adma_check_atapi_dma(struct ata_queued_cmd *qc); 122 static void adma_freeze(struct ata_port *ap); 123 static void adma_thaw(struct ata_port *ap); 124 static int adma_prereset(struct ata_link *link, unsigned long deadline); 125 126 static const struct scsi_host_template adma_ata_sht = { 127 ATA_BASE_SHT(DRV_NAME), 128 .sg_tablesize = LIBATA_MAX_PRD, 129 .dma_boundary = ADMA_DMA_BOUNDARY, 130 }; 131 132 static struct ata_port_operations adma_ata_ops = { 133 .inherits = &ata_sff_port_ops, 134 135 .lost_interrupt = ATA_OP_NULL, 136 137 .check_atapi_dma = adma_check_atapi_dma, 138 .qc_prep = adma_qc_prep, 139 .qc_issue = adma_qc_issue, 140 141 .freeze = adma_freeze, 142 .thaw = adma_thaw, 143 .reset.prereset = adma_prereset, 144 145 .port_start = adma_port_start, 146 .port_stop = adma_port_stop, 147 }; 148 149 static struct ata_port_info adma_port_info[] = { 150 /* board_1841_idx */ 151 { 152 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_PIO_POLLING, 153 .pio_mask = ATA_PIO4_ONLY, 154 .udma_mask = ATA_UDMA4, 155 .port_ops = &adma_ata_ops, 156 }, 157 }; 158 159 static const struct pci_device_id adma_ata_pci_tbl[] = { 160 { PCI_VDEVICE(PDC, 0x1841), .driver_data = board_1841_idx }, 161 { } /* terminate list */ 162 }; 163 164 static struct pci_driver adma_ata_pci_driver = { 165 .name = DRV_NAME, 166 .id_table = adma_ata_pci_tbl, 167 .probe = adma_ata_init_one, 168 .remove = ata_pci_remove_one, 169 }; 170 171 static int adma_check_atapi_dma(struct ata_queued_cmd *qc) 172 { 173 return 1; /* ATAPI DMA not yet supported */ 174 } 175 176 static void adma_reset_engine(struct ata_port *ap) 177 { 178 void __iomem *chan = ADMA_PORT_REGS(ap); 179 180 /* reset ADMA to idle state */ 181 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); 182 udelay(2); 183 writew(aPIOMD4, chan + ADMA_CONTROL); 184 udelay(2); 185 } 186 187 static void adma_reinit_engine(struct ata_port *ap) 188 { 189 struct adma_port_priv *pp = ap->private_data; 190 void __iomem *chan = ADMA_PORT_REGS(ap); 191 192 /* mask/clear ATA interrupts */ 193 writeb(ATA_NIEN, ap->ioaddr.ctl_addr); 194 ata_sff_check_status(ap); 195 196 /* reset the ADMA engine */ 197 adma_reset_engine(ap); 198 199 /* set in-FIFO threshold to 0x100 */ 200 writew(0x100, chan + ADMA_FIFO_IN); 201 202 /* set CPB pointer */ 203 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT); 204 205 /* set out-FIFO threshold to 0x100 */ 206 writew(0x100, chan + ADMA_FIFO_OUT); 207 208 /* set CPB count */ 209 writew(1, chan + ADMA_CPB_COUNT); 210 211 /* read/discard ADMA status */ 212 readb(chan + ADMA_STATUS); 213 } 214 215 static inline void adma_enter_reg_mode(struct ata_port *ap) 216 { 217 void __iomem *chan = ADMA_PORT_REGS(ap); 218 219 writew(aPIOMD4, chan + ADMA_CONTROL); 220 readb(chan + ADMA_STATUS); /* flush */ 221 } 222 223 static void adma_freeze(struct ata_port *ap) 224 { 225 void __iomem *chan = ADMA_PORT_REGS(ap); 226 227 /* mask/clear ATA interrupts */ 228 writeb(ATA_NIEN, ap->ioaddr.ctl_addr); 229 ata_sff_check_status(ap); 230 231 /* reset ADMA to idle state */ 232 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); 233 udelay(2); 234 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL); 235 udelay(2); 236 } 237 238 static void adma_thaw(struct ata_port *ap) 239 { 240 adma_reinit_engine(ap); 241 } 242 243 static int adma_prereset(struct ata_link *link, unsigned long deadline) 244 { 245 struct ata_port *ap = link->ap; 246 struct adma_port_priv *pp = ap->private_data; 247 248 if (pp->state != adma_state_idle) /* healthy paranoia */ 249 pp->state = adma_state_mmio; 250 adma_reinit_engine(ap); 251 252 return ata_sff_prereset(link, deadline); 253 } 254 255 static int adma_fill_sg(struct ata_queued_cmd *qc) 256 { 257 struct scatterlist *sg; 258 struct ata_port *ap = qc->ap; 259 struct adma_port_priv *pp = ap->private_data; 260 u8 *buf = pp->pkt, *last_buf = NULL; 261 int i = (2 + buf[3]) * 8; 262 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); 263 unsigned int si; 264 265 for_each_sg(qc->sg, sg, qc->n_elem, si) { 266 u32 addr; 267 u32 len; 268 269 addr = (u32)sg_dma_address(sg); 270 *(__le32 *)(buf + i) = cpu_to_le32(addr); 271 i += 4; 272 273 len = sg_dma_len(sg) >> 3; 274 *(__le32 *)(buf + i) = cpu_to_le32(len); 275 i += 4; 276 277 last_buf = &buf[i]; 278 buf[i++] = pFLAGS; 279 buf[i++] = qc->dev->dma_mode & 0xf; 280 buf[i++] = 0; /* pPKLW */ 281 buf[i++] = 0; /* reserved */ 282 283 *(__le32 *)(buf + i) = 284 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4); 285 i += 4; 286 } 287 288 if (likely(last_buf)) 289 *last_buf |= pEND; 290 291 return i; 292 } 293 294 static enum ata_completion_errors adma_qc_prep(struct ata_queued_cmd *qc) 295 { 296 struct adma_port_priv *pp = qc->ap->private_data; 297 u8 *buf = pp->pkt; 298 u32 pkt_dma = (u32)pp->pkt_dma; 299 int i = 0; 300 301 adma_enter_reg_mode(qc->ap); 302 if (qc->tf.protocol != ATA_PROT_DMA) 303 return AC_ERR_OK; 304 305 buf[i++] = 0; /* Response flags */ 306 buf[i++] = 0; /* reserved */ 307 buf[i++] = cVLD | cDAT | cIEN; 308 i++; /* cLEN, gets filled in below */ 309 310 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */ 311 i += 4; /* cNCPB */ 312 i += 4; /* cPRD, gets filled in below */ 313 314 buf[i++] = 0; /* reserved */ 315 buf[i++] = 0; /* reserved */ 316 buf[i++] = 0; /* reserved */ 317 buf[i++] = 0; /* reserved */ 318 319 /* ATA registers; must be a multiple of 4 */ 320 buf[i++] = qc->tf.device; 321 buf[i++] = ADMA_REGS_DEVICE; 322 if ((qc->tf.flags & ATA_TFLAG_LBA48)) { 323 buf[i++] = qc->tf.hob_nsect; 324 buf[i++] = ADMA_REGS_SECTOR_COUNT; 325 buf[i++] = qc->tf.hob_lbal; 326 buf[i++] = ADMA_REGS_LBA_LOW; 327 buf[i++] = qc->tf.hob_lbam; 328 buf[i++] = ADMA_REGS_LBA_MID; 329 buf[i++] = qc->tf.hob_lbah; 330 buf[i++] = ADMA_REGS_LBA_HIGH; 331 } 332 buf[i++] = qc->tf.nsect; 333 buf[i++] = ADMA_REGS_SECTOR_COUNT; 334 buf[i++] = qc->tf.lbal; 335 buf[i++] = ADMA_REGS_LBA_LOW; 336 buf[i++] = qc->tf.lbam; 337 buf[i++] = ADMA_REGS_LBA_MID; 338 buf[i++] = qc->tf.lbah; 339 buf[i++] = ADMA_REGS_LBA_HIGH; 340 buf[i++] = 0; 341 buf[i++] = ADMA_REGS_CONTROL; 342 buf[i++] = rIGN; 343 buf[i++] = 0; 344 buf[i++] = qc->tf.command; 345 buf[i++] = ADMA_REGS_COMMAND | rEND; 346 347 buf[3] = (i >> 3) - 2; /* cLEN */ 348 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */ 349 350 i = adma_fill_sg(qc); 351 wmb(); /* flush PRDs and pkt to memory */ 352 return AC_ERR_OK; 353 } 354 355 static inline void adma_packet_start(struct ata_queued_cmd *qc) 356 { 357 struct ata_port *ap = qc->ap; 358 void __iomem *chan = ADMA_PORT_REGS(ap); 359 360 /* fire up the ADMA engine */ 361 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL); 362 } 363 364 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) 365 { 366 struct adma_port_priv *pp = qc->ap->private_data; 367 368 switch (qc->tf.protocol) { 369 case ATA_PROT_DMA: 370 pp->state = adma_state_pkt; 371 adma_packet_start(qc); 372 return 0; 373 374 case ATAPI_PROT_DMA: 375 BUG(); 376 break; 377 378 default: 379 break; 380 } 381 382 pp->state = adma_state_mmio; 383 return ata_sff_qc_issue(qc); 384 } 385 386 static inline unsigned int adma_intr_pkt(struct ata_host *host) 387 { 388 unsigned int handled = 0, port_no; 389 390 for (port_no = 0; port_no < host->n_ports; ++port_no) { 391 struct ata_port *ap = host->ports[port_no]; 392 struct adma_port_priv *pp; 393 struct ata_queued_cmd *qc; 394 void __iomem *chan = ADMA_PORT_REGS(ap); 395 u8 status = readb(chan + ADMA_STATUS); 396 397 if (status == 0) 398 continue; 399 handled = 1; 400 adma_enter_reg_mode(ap); 401 pp = ap->private_data; 402 if (!pp || pp->state != adma_state_pkt) 403 continue; 404 qc = ata_qc_from_tag(ap, ap->link.active_tag); 405 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 406 if (status & aPERR) 407 qc->err_mask |= AC_ERR_HOST_BUS; 408 else if ((status & (aPSD | aUIRQ))) 409 qc->err_mask |= AC_ERR_OTHER; 410 411 if (pp->pkt[0] & cATERR) 412 qc->err_mask |= AC_ERR_DEV; 413 else if (pp->pkt[0] != cDONE) 414 qc->err_mask |= AC_ERR_OTHER; 415 416 if (!qc->err_mask) 417 ata_qc_complete(qc); 418 else { 419 struct ata_eh_info *ehi = &ap->link.eh_info; 420 ata_ehi_clear_desc(ehi); 421 ata_ehi_push_desc(ehi, 422 "ADMA-status 0x%02X", status); 423 ata_ehi_push_desc(ehi, 424 "pkt[0] 0x%02X", pp->pkt[0]); 425 426 if (qc->err_mask == AC_ERR_DEV) 427 ata_port_abort(ap); 428 else 429 ata_port_freeze(ap); 430 } 431 } 432 } 433 return handled; 434 } 435 436 static inline unsigned int adma_intr_mmio(struct ata_host *host) 437 { 438 unsigned int handled = 0, port_no; 439 440 for (port_no = 0; port_no < host->n_ports; ++port_no) { 441 struct ata_port *ap = host->ports[port_no]; 442 struct adma_port_priv *pp = ap->private_data; 443 struct ata_queued_cmd *qc; 444 445 if (!pp || pp->state != adma_state_mmio) 446 continue; 447 qc = ata_qc_from_tag(ap, ap->link.active_tag); 448 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 449 450 /* check main status, clearing INTRQ */ 451 u8 status = ata_sff_check_status(ap); 452 if ((status & ATA_BUSY)) 453 continue; 454 455 /* complete taskfile transaction */ 456 pp->state = adma_state_idle; 457 qc->err_mask |= ac_err_mask(status); 458 if (!qc->err_mask) 459 ata_qc_complete(qc); 460 else { 461 struct ata_eh_info *ehi = &ap->link.eh_info; 462 ata_ehi_clear_desc(ehi); 463 ata_ehi_push_desc(ehi, "status 0x%02X", status); 464 465 if (qc->err_mask == AC_ERR_DEV) 466 ata_port_abort(ap); 467 else 468 ata_port_freeze(ap); 469 } 470 handled = 1; 471 } 472 } 473 return handled; 474 } 475 476 static irqreturn_t adma_intr(int irq, void *dev_instance) 477 { 478 struct ata_host *host = dev_instance; 479 unsigned int handled = 0; 480 481 spin_lock(&host->lock); 482 handled = adma_intr_pkt(host) | adma_intr_mmio(host); 483 spin_unlock(&host->lock); 484 485 return IRQ_RETVAL(handled); 486 } 487 488 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base) 489 { 490 port->cmd_addr = 491 port->data_addr = base + 0x000; 492 port->error_addr = 493 port->feature_addr = base + 0x004; 494 port->nsect_addr = base + 0x008; 495 port->lbal_addr = base + 0x00c; 496 port->lbam_addr = base + 0x010; 497 port->lbah_addr = base + 0x014; 498 port->device_addr = base + 0x018; 499 port->status_addr = 500 port->command_addr = base + 0x01c; 501 port->altstatus_addr = 502 port->ctl_addr = base + 0x038; 503 } 504 505 static int adma_port_start(struct ata_port *ap) 506 { 507 struct device *dev = ap->host->dev; 508 struct adma_port_priv *pp; 509 510 adma_enter_reg_mode(ap); 511 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 512 if (!pp) 513 return -ENOMEM; 514 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma, 515 GFP_KERNEL); 516 if (!pp->pkt) 517 return -ENOMEM; 518 /* paranoia? */ 519 if ((pp->pkt_dma & 7) != 0) { 520 ata_port_err(ap, "bad alignment for pp->pkt_dma: %08x\n", 521 (u32)pp->pkt_dma); 522 return -ENOMEM; 523 } 524 ap->private_data = pp; 525 adma_reinit_engine(ap); 526 return 0; 527 } 528 529 static void adma_port_stop(struct ata_port *ap) 530 { 531 adma_reset_engine(ap); 532 } 533 534 static void adma_host_init(struct ata_host *host, unsigned int chip_id) 535 { 536 unsigned int port_no; 537 538 /* enable/lock aGO operation */ 539 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK); 540 541 /* reset the ADMA logic */ 542 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) 543 adma_reset_engine(host->ports[port_no]); 544 } 545 546 static int adma_ata_init_one(struct pci_dev *pdev, 547 const struct pci_device_id *ent) 548 { 549 unsigned int board_idx = (unsigned int) ent->driver_data; 550 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL }; 551 struct ata_host *host; 552 void __iomem *mmio_base; 553 int rc, port_no; 554 555 ata_print_version_once(&pdev->dev, DRV_VERSION); 556 557 /* alloc host */ 558 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS); 559 if (!host) 560 return -ENOMEM; 561 562 /* acquire resources and fill host */ 563 rc = pcim_enable_device(pdev); 564 if (rc) 565 return rc; 566 567 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) 568 return -ENODEV; 569 570 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME); 571 if (rc) 572 return rc; 573 host->iomap = pcim_iomap_table(pdev); 574 mmio_base = host->iomap[ADMA_MMIO_BAR]; 575 576 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 577 if (rc) { 578 dev_err(&pdev->dev, "32-bit DMA enable failed\n"); 579 return rc; 580 } 581 582 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) { 583 struct ata_port *ap = host->ports[port_no]; 584 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no); 585 unsigned int offset = port_base - mmio_base; 586 587 adma_ata_setup_port(&ap->ioaddr, port_base); 588 589 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio"); 590 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port"); 591 } 592 593 /* initialize adapter */ 594 adma_host_init(host, board_idx); 595 596 pci_set_master(pdev); 597 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED, 598 &adma_ata_sht); 599 } 600 601 module_pci_driver(adma_ata_pci_driver); 602 603 MODULE_AUTHOR("Mark Lord"); 604 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver"); 605 MODULE_LICENSE("GPL"); 606 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl); 607 MODULE_VERSION(DRV_VERSION); 608