1 /* 2 * pdc_adma.c - Pacific Digital Corporation ADMA 3 * 4 * Maintained by: Mark Lord <mlord@pobox.com> 5 * 6 * Copyright 2005 Mark Lord 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * 23 * libata documentation is available via 'make {ps|pdf}docs', 24 * as Documentation/DocBook/libata.* 25 * 26 * 27 * Supports ATA disks in single-packet ADMA mode. 28 * Uses PIO for everything else. 29 * 30 * TODO: Use ADMA transfers for ATAPI devices, when possible. 31 * This requires careful attention to a number of quirks of the chip. 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/sched.h> 43 #include <linux/device.h> 44 #include <scsi/scsi_host.h> 45 #include <asm/io.h> 46 #include <linux/libata.h> 47 48 #define DRV_NAME "pdc_adma" 49 #define DRV_VERSION "0.04" 50 51 /* macro to calculate base address for ATA regs */ 52 #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40)) 53 54 /* macro to calculate base address for ADMA regs */ 55 #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20)) 56 57 enum { 58 ADMA_PORTS = 2, 59 ADMA_CPB_BYTES = 40, 60 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16, 61 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES, 62 63 ADMA_DMA_BOUNDARY = 0xffffffff, 64 65 /* global register offsets */ 66 ADMA_MODE_LOCK = 0x00c7, 67 68 /* per-channel register offsets */ 69 ADMA_CONTROL = 0x0000, /* ADMA control */ 70 ADMA_STATUS = 0x0002, /* ADMA status */ 71 ADMA_CPB_COUNT = 0x0004, /* CPB count */ 72 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */ 73 ADMA_CPB_NEXT = 0x000c, /* next CPB address */ 74 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */ 75 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */ 76 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */ 77 78 /* ADMA_CONTROL register bits */ 79 aNIEN = (1 << 8), /* irq mask: 1==masked */ 80 aGO = (1 << 7), /* packet trigger ("Go!") */ 81 aRSTADM = (1 << 5), /* ADMA logic reset */ 82 aPIOMD4 = 0x0003, /* PIO mode 4 */ 83 84 /* ADMA_STATUS register bits */ 85 aPSD = (1 << 6), 86 aUIRQ = (1 << 4), 87 aPERR = (1 << 0), 88 89 /* CPB bits */ 90 cDONE = (1 << 0), 91 cVLD = (1 << 0), 92 cDAT = (1 << 2), 93 cIEN = (1 << 3), 94 95 /* PRD bits */ 96 pORD = (1 << 4), 97 pDIRO = (1 << 5), 98 pEND = (1 << 7), 99 100 /* ATA register flags */ 101 rIGN = (1 << 5), 102 rEND = (1 << 7), 103 104 /* ATA register addresses */ 105 ADMA_REGS_CONTROL = 0x0e, 106 ADMA_REGS_SECTOR_COUNT = 0x12, 107 ADMA_REGS_LBA_LOW = 0x13, 108 ADMA_REGS_LBA_MID = 0x14, 109 ADMA_REGS_LBA_HIGH = 0x15, 110 ADMA_REGS_DEVICE = 0x16, 111 ADMA_REGS_COMMAND = 0x17, 112 113 /* PCI device IDs */ 114 board_1841_idx = 0, /* ADMA 2-port controller */ 115 }; 116 117 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t; 118 119 struct adma_port_priv { 120 u8 *pkt; 121 dma_addr_t pkt_dma; 122 adma_state_t state; 123 }; 124 125 static int adma_ata_init_one (struct pci_dev *pdev, 126 const struct pci_device_id *ent); 127 static irqreturn_t adma_intr (int irq, void *dev_instance); 128 static int adma_port_start(struct ata_port *ap); 129 static void adma_host_stop(struct ata_host *host); 130 static void adma_port_stop(struct ata_port *ap); 131 static void adma_phy_reset(struct ata_port *ap); 132 static void adma_qc_prep(struct ata_queued_cmd *qc); 133 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc); 134 static int adma_check_atapi_dma(struct ata_queued_cmd *qc); 135 static void adma_bmdma_stop(struct ata_queued_cmd *qc); 136 static u8 adma_bmdma_status(struct ata_port *ap); 137 static void adma_irq_clear(struct ata_port *ap); 138 static void adma_eng_timeout(struct ata_port *ap); 139 140 static struct scsi_host_template adma_ata_sht = { 141 .module = THIS_MODULE, 142 .name = DRV_NAME, 143 .ioctl = ata_scsi_ioctl, 144 .queuecommand = ata_scsi_queuecmd, 145 .can_queue = ATA_DEF_QUEUE, 146 .this_id = ATA_SHT_THIS_ID, 147 .sg_tablesize = LIBATA_MAX_PRD, 148 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 149 .emulated = ATA_SHT_EMULATED, 150 .use_clustering = ENABLE_CLUSTERING, 151 .proc_name = DRV_NAME, 152 .dma_boundary = ADMA_DMA_BOUNDARY, 153 .slave_configure = ata_scsi_slave_config, 154 .slave_destroy = ata_scsi_slave_destroy, 155 .bios_param = ata_std_bios_param, 156 }; 157 158 static const struct ata_port_operations adma_ata_ops = { 159 .port_disable = ata_port_disable, 160 .tf_load = ata_tf_load, 161 .tf_read = ata_tf_read, 162 .check_status = ata_check_status, 163 .check_atapi_dma = adma_check_atapi_dma, 164 .exec_command = ata_exec_command, 165 .dev_select = ata_std_dev_select, 166 .phy_reset = adma_phy_reset, 167 .qc_prep = adma_qc_prep, 168 .qc_issue = adma_qc_issue, 169 .eng_timeout = adma_eng_timeout, 170 .data_xfer = ata_mmio_data_xfer, 171 .irq_handler = adma_intr, 172 .irq_clear = adma_irq_clear, 173 .port_start = adma_port_start, 174 .port_stop = adma_port_stop, 175 .host_stop = adma_host_stop, 176 .bmdma_stop = adma_bmdma_stop, 177 .bmdma_status = adma_bmdma_status, 178 }; 179 180 static struct ata_port_info adma_port_info[] = { 181 /* board_1841_idx */ 182 { 183 .sht = &adma_ata_sht, 184 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | 185 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | 186 ATA_FLAG_PIO_POLLING, 187 .pio_mask = 0x10, /* pio4 */ 188 .udma_mask = 0x1f, /* udma0-4 */ 189 .port_ops = &adma_ata_ops, 190 }, 191 }; 192 193 static const struct pci_device_id adma_ata_pci_tbl[] = { 194 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx }, 195 196 { } /* terminate list */ 197 }; 198 199 static struct pci_driver adma_ata_pci_driver = { 200 .name = DRV_NAME, 201 .id_table = adma_ata_pci_tbl, 202 .probe = adma_ata_init_one, 203 .remove = ata_pci_remove_one, 204 }; 205 206 static int adma_check_atapi_dma(struct ata_queued_cmd *qc) 207 { 208 return 1; /* ATAPI DMA not yet supported */ 209 } 210 211 static void adma_bmdma_stop(struct ata_queued_cmd *qc) 212 { 213 /* nothing */ 214 } 215 216 static u8 adma_bmdma_status(struct ata_port *ap) 217 { 218 return 0; 219 } 220 221 static void adma_irq_clear(struct ata_port *ap) 222 { 223 /* nothing */ 224 } 225 226 static void adma_reset_engine(void __iomem *chan) 227 { 228 /* reset ADMA to idle state */ 229 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL); 230 udelay(2); 231 writew(aPIOMD4, chan + ADMA_CONTROL); 232 udelay(2); 233 } 234 235 static void adma_reinit_engine(struct ata_port *ap) 236 { 237 struct adma_port_priv *pp = ap->private_data; 238 void __iomem *mmio_base = ap->host->mmio_base; 239 void __iomem *chan = ADMA_REGS(mmio_base, ap->port_no); 240 241 /* mask/clear ATA interrupts */ 242 writeb(ATA_NIEN, (void __iomem *)ap->ioaddr.ctl_addr); 243 ata_check_status(ap); 244 245 /* reset the ADMA engine */ 246 adma_reset_engine(chan); 247 248 /* set in-FIFO threshold to 0x100 */ 249 writew(0x100, chan + ADMA_FIFO_IN); 250 251 /* set CPB pointer */ 252 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT); 253 254 /* set out-FIFO threshold to 0x100 */ 255 writew(0x100, chan + ADMA_FIFO_OUT); 256 257 /* set CPB count */ 258 writew(1, chan + ADMA_CPB_COUNT); 259 260 /* read/discard ADMA status */ 261 readb(chan + ADMA_STATUS); 262 } 263 264 static inline void adma_enter_reg_mode(struct ata_port *ap) 265 { 266 void __iomem *chan = ADMA_REGS(ap->host->mmio_base, ap->port_no); 267 268 writew(aPIOMD4, chan + ADMA_CONTROL); 269 readb(chan + ADMA_STATUS); /* flush */ 270 } 271 272 static void adma_phy_reset(struct ata_port *ap) 273 { 274 struct adma_port_priv *pp = ap->private_data; 275 276 pp->state = adma_state_idle; 277 adma_reinit_engine(ap); 278 ata_port_probe(ap); 279 ata_bus_reset(ap); 280 } 281 282 static void adma_eng_timeout(struct ata_port *ap) 283 { 284 struct adma_port_priv *pp = ap->private_data; 285 286 if (pp->state != adma_state_idle) /* healthy paranoia */ 287 pp->state = adma_state_mmio; 288 adma_reinit_engine(ap); 289 ata_eng_timeout(ap); 290 } 291 292 static int adma_fill_sg(struct ata_queued_cmd *qc) 293 { 294 struct scatterlist *sg; 295 struct ata_port *ap = qc->ap; 296 struct adma_port_priv *pp = ap->private_data; 297 u8 *buf = pp->pkt; 298 int i = (2 + buf[3]) * 8; 299 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0); 300 301 ata_for_each_sg(sg, qc) { 302 u32 addr; 303 u32 len; 304 305 addr = (u32)sg_dma_address(sg); 306 *(__le32 *)(buf + i) = cpu_to_le32(addr); 307 i += 4; 308 309 len = sg_dma_len(sg) >> 3; 310 *(__le32 *)(buf + i) = cpu_to_le32(len); 311 i += 4; 312 313 if (ata_sg_is_last(sg, qc)) 314 pFLAGS |= pEND; 315 buf[i++] = pFLAGS; 316 buf[i++] = qc->dev->dma_mode & 0xf; 317 buf[i++] = 0; /* pPKLW */ 318 buf[i++] = 0; /* reserved */ 319 320 *(__le32 *)(buf + i) 321 = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4); 322 i += 4; 323 324 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4, 325 (unsigned long)addr, len); 326 } 327 return i; 328 } 329 330 static void adma_qc_prep(struct ata_queued_cmd *qc) 331 { 332 struct adma_port_priv *pp = qc->ap->private_data; 333 u8 *buf = pp->pkt; 334 u32 pkt_dma = (u32)pp->pkt_dma; 335 int i = 0; 336 337 VPRINTK("ENTER\n"); 338 339 adma_enter_reg_mode(qc->ap); 340 if (qc->tf.protocol != ATA_PROT_DMA) { 341 ata_qc_prep(qc); 342 return; 343 } 344 345 buf[i++] = 0; /* Response flags */ 346 buf[i++] = 0; /* reserved */ 347 buf[i++] = cVLD | cDAT | cIEN; 348 i++; /* cLEN, gets filled in below */ 349 350 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */ 351 i += 4; /* cNCPB */ 352 i += 4; /* cPRD, gets filled in below */ 353 354 buf[i++] = 0; /* reserved */ 355 buf[i++] = 0; /* reserved */ 356 buf[i++] = 0; /* reserved */ 357 buf[i++] = 0; /* reserved */ 358 359 /* ATA registers; must be a multiple of 4 */ 360 buf[i++] = qc->tf.device; 361 buf[i++] = ADMA_REGS_DEVICE; 362 if ((qc->tf.flags & ATA_TFLAG_LBA48)) { 363 buf[i++] = qc->tf.hob_nsect; 364 buf[i++] = ADMA_REGS_SECTOR_COUNT; 365 buf[i++] = qc->tf.hob_lbal; 366 buf[i++] = ADMA_REGS_LBA_LOW; 367 buf[i++] = qc->tf.hob_lbam; 368 buf[i++] = ADMA_REGS_LBA_MID; 369 buf[i++] = qc->tf.hob_lbah; 370 buf[i++] = ADMA_REGS_LBA_HIGH; 371 } 372 buf[i++] = qc->tf.nsect; 373 buf[i++] = ADMA_REGS_SECTOR_COUNT; 374 buf[i++] = qc->tf.lbal; 375 buf[i++] = ADMA_REGS_LBA_LOW; 376 buf[i++] = qc->tf.lbam; 377 buf[i++] = ADMA_REGS_LBA_MID; 378 buf[i++] = qc->tf.lbah; 379 buf[i++] = ADMA_REGS_LBA_HIGH; 380 buf[i++] = 0; 381 buf[i++] = ADMA_REGS_CONTROL; 382 buf[i++] = rIGN; 383 buf[i++] = 0; 384 buf[i++] = qc->tf.command; 385 buf[i++] = ADMA_REGS_COMMAND | rEND; 386 387 buf[3] = (i >> 3) - 2; /* cLEN */ 388 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */ 389 390 i = adma_fill_sg(qc); 391 wmb(); /* flush PRDs and pkt to memory */ 392 #if 0 393 /* dump out CPB + PRDs for debug */ 394 { 395 int j, len = 0; 396 static char obuf[2048]; 397 for (j = 0; j < i; ++j) { 398 len += sprintf(obuf+len, "%02x ", buf[j]); 399 if ((j & 7) == 7) { 400 printk("%s\n", obuf); 401 len = 0; 402 } 403 } 404 if (len) 405 printk("%s\n", obuf); 406 } 407 #endif 408 } 409 410 static inline void adma_packet_start(struct ata_queued_cmd *qc) 411 { 412 struct ata_port *ap = qc->ap; 413 void __iomem *chan = ADMA_REGS(ap->host->mmio_base, ap->port_no); 414 415 VPRINTK("ENTER, ap %p\n", ap); 416 417 /* fire up the ADMA engine */ 418 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL); 419 } 420 421 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc) 422 { 423 struct adma_port_priv *pp = qc->ap->private_data; 424 425 switch (qc->tf.protocol) { 426 case ATA_PROT_DMA: 427 pp->state = adma_state_pkt; 428 adma_packet_start(qc); 429 return 0; 430 431 case ATA_PROT_ATAPI_DMA: 432 BUG(); 433 break; 434 435 default: 436 break; 437 } 438 439 pp->state = adma_state_mmio; 440 return ata_qc_issue_prot(qc); 441 } 442 443 static inline unsigned int adma_intr_pkt(struct ata_host *host) 444 { 445 unsigned int handled = 0, port_no; 446 u8 __iomem *mmio_base = host->mmio_base; 447 448 for (port_no = 0; port_no < host->n_ports; ++port_no) { 449 struct ata_port *ap = host->ports[port_no]; 450 struct adma_port_priv *pp; 451 struct ata_queued_cmd *qc; 452 void __iomem *chan = ADMA_REGS(mmio_base, port_no); 453 u8 status = readb(chan + ADMA_STATUS); 454 455 if (status == 0) 456 continue; 457 handled = 1; 458 adma_enter_reg_mode(ap); 459 if (ap->flags & ATA_FLAG_DISABLED) 460 continue; 461 pp = ap->private_data; 462 if (!pp || pp->state != adma_state_pkt) 463 continue; 464 qc = ata_qc_from_tag(ap, ap->active_tag); 465 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 466 if ((status & (aPERR | aPSD | aUIRQ))) 467 qc->err_mask |= AC_ERR_OTHER; 468 else if (pp->pkt[0] != cDONE) 469 qc->err_mask |= AC_ERR_OTHER; 470 471 ata_qc_complete(qc); 472 } 473 } 474 return handled; 475 } 476 477 static inline unsigned int adma_intr_mmio(struct ata_host *host) 478 { 479 unsigned int handled = 0, port_no; 480 481 for (port_no = 0; port_no < host->n_ports; ++port_no) { 482 struct ata_port *ap; 483 ap = host->ports[port_no]; 484 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) { 485 struct ata_queued_cmd *qc; 486 struct adma_port_priv *pp = ap->private_data; 487 if (!pp || pp->state != adma_state_mmio) 488 continue; 489 qc = ata_qc_from_tag(ap, ap->active_tag); 490 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) { 491 492 /* check main status, clearing INTRQ */ 493 u8 status = ata_check_status(ap); 494 if ((status & ATA_BUSY)) 495 continue; 496 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", 497 ap->id, qc->tf.protocol, status); 498 499 /* complete taskfile transaction */ 500 pp->state = adma_state_idle; 501 qc->err_mask |= ac_err_mask(status); 502 ata_qc_complete(qc); 503 handled = 1; 504 } 505 } 506 } 507 return handled; 508 } 509 510 static irqreturn_t adma_intr(int irq, void *dev_instance) 511 { 512 struct ata_host *host = dev_instance; 513 unsigned int handled = 0; 514 515 VPRINTK("ENTER\n"); 516 517 spin_lock(&host->lock); 518 handled = adma_intr_pkt(host) | adma_intr_mmio(host); 519 spin_unlock(&host->lock); 520 521 VPRINTK("EXIT\n"); 522 523 return IRQ_RETVAL(handled); 524 } 525 526 static void adma_ata_setup_port(struct ata_ioports *port, unsigned long base) 527 { 528 port->cmd_addr = 529 port->data_addr = base + 0x000; 530 port->error_addr = 531 port->feature_addr = base + 0x004; 532 port->nsect_addr = base + 0x008; 533 port->lbal_addr = base + 0x00c; 534 port->lbam_addr = base + 0x010; 535 port->lbah_addr = base + 0x014; 536 port->device_addr = base + 0x018; 537 port->status_addr = 538 port->command_addr = base + 0x01c; 539 port->altstatus_addr = 540 port->ctl_addr = base + 0x038; 541 } 542 543 static int adma_port_start(struct ata_port *ap) 544 { 545 struct device *dev = ap->host->dev; 546 struct adma_port_priv *pp; 547 int rc; 548 549 rc = ata_port_start(ap); 550 if (rc) 551 return rc; 552 adma_enter_reg_mode(ap); 553 rc = -ENOMEM; 554 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 555 if (!pp) 556 goto err_out; 557 pp->pkt = dma_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma, 558 GFP_KERNEL); 559 if (!pp->pkt) 560 goto err_out_kfree; 561 /* paranoia? */ 562 if ((pp->pkt_dma & 7) != 0) { 563 printk("bad alignment for pp->pkt_dma: %08x\n", 564 (u32)pp->pkt_dma); 565 dma_free_coherent(dev, ADMA_PKT_BYTES, 566 pp->pkt, pp->pkt_dma); 567 goto err_out_kfree; 568 } 569 memset(pp->pkt, 0, ADMA_PKT_BYTES); 570 ap->private_data = pp; 571 adma_reinit_engine(ap); 572 return 0; 573 574 err_out_kfree: 575 kfree(pp); 576 err_out: 577 ata_port_stop(ap); 578 return rc; 579 } 580 581 static void adma_port_stop(struct ata_port *ap) 582 { 583 struct device *dev = ap->host->dev; 584 struct adma_port_priv *pp = ap->private_data; 585 586 adma_reset_engine(ADMA_REGS(ap->host->mmio_base, ap->port_no)); 587 if (pp != NULL) { 588 ap->private_data = NULL; 589 if (pp->pkt != NULL) 590 dma_free_coherent(dev, ADMA_PKT_BYTES, 591 pp->pkt, pp->pkt_dma); 592 kfree(pp); 593 } 594 ata_port_stop(ap); 595 } 596 597 static void adma_host_stop(struct ata_host *host) 598 { 599 unsigned int port_no; 600 601 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) 602 adma_reset_engine(ADMA_REGS(host->mmio_base, port_no)); 603 604 ata_pci_host_stop(host); 605 } 606 607 static void adma_host_init(unsigned int chip_id, 608 struct ata_probe_ent *probe_ent) 609 { 610 unsigned int port_no; 611 void __iomem *mmio_base = probe_ent->mmio_base; 612 613 /* enable/lock aGO operation */ 614 writeb(7, mmio_base + ADMA_MODE_LOCK); 615 616 /* reset the ADMA logic */ 617 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) 618 adma_reset_engine(ADMA_REGS(mmio_base, port_no)); 619 } 620 621 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) 622 { 623 int rc; 624 625 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 626 if (rc) { 627 dev_printk(KERN_ERR, &pdev->dev, 628 "32-bit DMA enable failed\n"); 629 return rc; 630 } 631 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 632 if (rc) { 633 dev_printk(KERN_ERR, &pdev->dev, 634 "32-bit consistent DMA enable failed\n"); 635 return rc; 636 } 637 return 0; 638 } 639 640 static int adma_ata_init_one(struct pci_dev *pdev, 641 const struct pci_device_id *ent) 642 { 643 static int printed_version; 644 struct ata_probe_ent *probe_ent = NULL; 645 void __iomem *mmio_base; 646 unsigned int board_idx = (unsigned int) ent->driver_data; 647 int rc, port_no; 648 649 if (!printed_version++) 650 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 651 652 rc = pci_enable_device(pdev); 653 if (rc) 654 return rc; 655 656 rc = pci_request_regions(pdev, DRV_NAME); 657 if (rc) 658 goto err_out; 659 660 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) { 661 rc = -ENODEV; 662 goto err_out_regions; 663 } 664 665 mmio_base = pci_iomap(pdev, 4, 0); 666 if (mmio_base == NULL) { 667 rc = -ENOMEM; 668 goto err_out_regions; 669 } 670 671 rc = adma_set_dma_masks(pdev, mmio_base); 672 if (rc) 673 goto err_out_iounmap; 674 675 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); 676 if (probe_ent == NULL) { 677 rc = -ENOMEM; 678 goto err_out_iounmap; 679 } 680 681 probe_ent->dev = pci_dev_to_dev(pdev); 682 INIT_LIST_HEAD(&probe_ent->node); 683 684 probe_ent->sht = adma_port_info[board_idx].sht; 685 probe_ent->port_flags = adma_port_info[board_idx].flags; 686 probe_ent->pio_mask = adma_port_info[board_idx].pio_mask; 687 probe_ent->mwdma_mask = adma_port_info[board_idx].mwdma_mask; 688 probe_ent->udma_mask = adma_port_info[board_idx].udma_mask; 689 probe_ent->port_ops = adma_port_info[board_idx].port_ops; 690 691 probe_ent->irq = pdev->irq; 692 probe_ent->irq_flags = IRQF_SHARED; 693 probe_ent->mmio_base = mmio_base; 694 probe_ent->n_ports = ADMA_PORTS; 695 696 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { 697 adma_ata_setup_port(&probe_ent->port[port_no], 698 ADMA_ATA_REGS((unsigned long)mmio_base, port_no)); 699 } 700 701 pci_set_master(pdev); 702 703 /* initialize adapter */ 704 adma_host_init(board_idx, probe_ent); 705 706 rc = ata_device_add(probe_ent); 707 kfree(probe_ent); 708 if (rc != ADMA_PORTS) 709 goto err_out_iounmap; 710 return 0; 711 712 err_out_iounmap: 713 pci_iounmap(pdev, mmio_base); 714 err_out_regions: 715 pci_release_regions(pdev); 716 err_out: 717 pci_disable_device(pdev); 718 return rc; 719 } 720 721 static int __init adma_ata_init(void) 722 { 723 return pci_register_driver(&adma_ata_pci_driver); 724 } 725 726 static void __exit adma_ata_exit(void) 727 { 728 pci_unregister_driver(&adma_ata_pci_driver); 729 } 730 731 MODULE_AUTHOR("Mark Lord"); 732 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver"); 733 MODULE_LICENSE("GPL"); 734 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl); 735 MODULE_VERSION(DRV_VERSION); 736 737 module_init(adma_ata_init); 738 module_exit(adma_ata_exit); 739