1 /* 2 * pata_via.c - VIA PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * 5 * Documentation 6 * Most chipset documentation available under NDA only 7 * 8 * VIA version guide 9 * VIA VT82C561 - early design, uses ata_generic currently 10 * VIA VT82C576 - MWDMA, 33Mhz 11 * VIA VT82C586 - MWDMA, 33Mhz 12 * VIA VT82C586a - Added UDMA to 33Mhz 13 * VIA VT82C586b - UDMA33 14 * VIA VT82C596a - Nonfunctional UDMA66 15 * VIA VT82C596b - Working UDMA66 16 * VIA VT82C686 - Nonfunctional UDMA66 17 * VIA VT82C686a - Working UDMA66 18 * VIA VT82C686b - Updated to UDMA100 19 * VIA VT8231 - UDMA100 20 * VIA VT8233 - UDMA100 21 * VIA VT8233a - UDMA133 22 * VIA VT8233c - UDMA100 23 * VIA VT8235 - UDMA133 24 * VIA VT8237 - UDMA133 25 * VIA VT8237S - UDMA133 26 * VIA VT8251 - UDMA133 27 * 28 * Most registers remain compatible across chips. Others start reserved 29 * and acquire sensible semantics if set to 1 (eg cable detect). A few 30 * exceptions exist, notably around the FIFO settings. 31 * 32 * One additional quirk of the VIA design is that like ALi they use few 33 * PCI IDs for a lot of chips. 34 * 35 * Based heavily on: 36 * 37 * Version 3.38 38 * 39 * VIA IDE driver for Linux. Supported southbridges: 40 * 41 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, 42 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, 43 * vt8235, vt8237 44 * 45 * Copyright (c) 2000-2002 Vojtech Pavlik 46 * 47 * Based on the work of: 48 * Michel Aubry 49 * Jeff Garzik 50 * Andre Hedrick 51 52 */ 53 54 #include <linux/kernel.h> 55 #include <linux/module.h> 56 #include <linux/pci.h> 57 #include <linux/init.h> 58 #include <linux/blkdev.h> 59 #include <linux/delay.h> 60 #include <scsi/scsi_host.h> 61 #include <linux/libata.h> 62 #include <linux/dmi.h> 63 64 #define DRV_NAME "pata_via" 65 #define DRV_VERSION "0.3.3" 66 67 /* 68 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx 69 * driver. 70 */ 71 72 enum { 73 VIA_UDMA = 0x007, 74 VIA_UDMA_NONE = 0x000, 75 VIA_UDMA_33 = 0x001, 76 VIA_UDMA_66 = 0x002, 77 VIA_UDMA_100 = 0x003, 78 VIA_UDMA_133 = 0x004, 79 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */ 80 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */ 81 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */ 82 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */ 83 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */ 84 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */ 85 VIA_NO_ENABLES = 0x400, /* Has no enablebits */ 86 VIA_SATA_PATA = 0x800, /* SATA/PATA combined configuration */ 87 }; 88 89 enum { 90 VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */ 91 }; 92 93 /* 94 * VIA SouthBridge chips. 95 */ 96 97 static const struct via_isa_bridge { 98 const char *name; 99 u16 id; 100 u8 rev_min; 101 u8 rev_max; 102 u16 flags; 103 } via_isa_bridges[] = { 104 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, 105 VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, 106 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, VIA_UDMA_133 | 107 VIA_BAD_AST | VIA_SATA_PATA }, 108 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, 109 VIA_UDMA_133 | VIA_BAD_AST }, 110 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 111 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 112 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, 113 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES }, 114 { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES }, 115 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 116 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 117 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 118 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 119 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, 120 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, 121 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, 122 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, 123 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, 124 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 125 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, 126 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 127 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, 128 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, 129 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, 130 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, 131 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, 132 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, 133 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, 134 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, 135 VIA_UDMA_133 | VIA_BAD_AST }, 136 { NULL } 137 }; 138 139 140 /* 141 * Cable special cases 142 */ 143 144 static const struct dmi_system_id cable_dmi_table[] = { 145 { 146 .ident = "Acer Ferrari 3400", 147 .matches = { 148 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), 149 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), 150 }, 151 }, 152 { } 153 }; 154 155 static int via_cable_override(struct pci_dev *pdev) 156 { 157 /* Systems by DMI */ 158 if (dmi_check_system(cable_dmi_table)) 159 return 1; 160 /* Arima W730-K8/Targa Visionary 811/... */ 161 if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032) 162 return 1; 163 return 0; 164 } 165 166 167 /** 168 * via_cable_detect - cable detection 169 * @ap: ATA port 170 * 171 * Perform cable detection. Actually for the VIA case the BIOS 172 * already did this for us. We read the values provided by the 173 * BIOS. If you are using an 8235 in a non-PC configuration you 174 * may need to update this code. 175 * 176 * Hotplug also impacts on this. 177 */ 178 179 static int via_cable_detect(struct ata_port *ap) { 180 const struct via_isa_bridge *config = ap->host->private_data; 181 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 182 u32 ata66; 183 184 if (via_cable_override(pdev)) 185 return ATA_CBL_PATA40_SHORT; 186 187 if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0) 188 return ATA_CBL_SATA; 189 190 /* Early chips are 40 wire */ 191 if ((config->flags & VIA_UDMA) < VIA_UDMA_66) 192 return ATA_CBL_PATA40; 193 /* UDMA 66 chips have only drive side logic */ 194 else if ((config->flags & VIA_UDMA) < VIA_UDMA_100) 195 return ATA_CBL_PATA_UNK; 196 /* UDMA 100 or later */ 197 pci_read_config_dword(pdev, 0x50, &ata66); 198 /* Check both the drive cable reporting bits, we might not have 199 two drives */ 200 if (ata66 & (0x10100000 >> (16 * ap->port_no))) 201 return ATA_CBL_PATA80; 202 /* Check with ACPI so we can spot BIOS reported SATA bridges */ 203 if (ata_acpi_init_gtm(ap) && 204 ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap))) 205 return ATA_CBL_PATA80; 206 return ATA_CBL_PATA40; 207 } 208 209 static int via_pre_reset(struct ata_link *link, unsigned long deadline) 210 { 211 struct ata_port *ap = link->ap; 212 const struct via_isa_bridge *config = ap->host->private_data; 213 214 if (!(config->flags & VIA_NO_ENABLES)) { 215 static const struct pci_bits via_enable_bits[] = { 216 { 0x40, 1, 0x02, 0x02 }, 217 { 0x40, 1, 0x01, 0x01 } 218 }; 219 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 220 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) 221 return -ENOENT; 222 } 223 224 return ata_sff_prereset(link, deadline); 225 } 226 227 228 /** 229 * via_do_set_mode - set initial PIO mode data 230 * @ap: ATA interface 231 * @adev: ATA device 232 * @mode: ATA mode being programmed 233 * @tdiv: Clocks per PCI clock 234 * @set_ast: Set to program address setup 235 * @udma_type: UDMA mode/format of registers 236 * 237 * Program the VIA registers for DMA and PIO modes. Uses the ata timing 238 * support in order to compute modes. 239 * 240 * FIXME: Hotplug will require we serialize multiple mode changes 241 * on the two channels. 242 */ 243 244 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type) 245 { 246 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 247 struct ata_device *peer = ata_dev_pair(adev); 248 struct ata_timing t, p; 249 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */ 250 unsigned long T = 1000000000 / via_clock; 251 unsigned long UT = T/tdiv; 252 int ut; 253 int offset = 3 - (2*ap->port_no) - adev->devno; 254 255 /* Calculate the timing values we require */ 256 ata_timing_compute(adev, mode, &t, T, UT); 257 258 /* We share 8bit timing so we must merge the constraints */ 259 if (peer) { 260 if (peer->pio_mode) { 261 ata_timing_compute(peer, peer->pio_mode, &p, T, UT); 262 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); 263 } 264 } 265 266 /* Address setup is programmable but breaks on UDMA133 setups */ 267 if (set_ast) { 268 u8 setup; /* 2 bits per drive */ 269 int shift = 2 * offset; 270 271 pci_read_config_byte(pdev, 0x4C, &setup); 272 setup &= ~(3 << shift); 273 setup |= clamp_val(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */ 274 pci_write_config_byte(pdev, 0x4C, setup); 275 } 276 277 /* Load the PIO mode bits */ 278 pci_write_config_byte(pdev, 0x4F - ap->port_no, 279 ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1)); 280 pci_write_config_byte(pdev, 0x48 + offset, 281 ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1)); 282 283 /* Load the UDMA bits according to type */ 284 switch(udma_type) { 285 default: 286 /* BUG() ? */ 287 /* fall through */ 288 case 33: 289 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03; 290 break; 291 case 66: 292 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f; 293 break; 294 case 100: 295 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; 296 break; 297 case 133: 298 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; 299 break; 300 } 301 302 /* Set UDMA unless device is not UDMA capable */ 303 if (udma_type && t.udma) { 304 u8 cable80_status; 305 306 /* Get 80-wire cable detection bit */ 307 pci_read_config_byte(pdev, 0x50 + offset, &cable80_status); 308 cable80_status &= 0x10; 309 310 pci_write_config_byte(pdev, 0x50 + offset, ut | cable80_status); 311 } 312 } 313 314 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev) 315 { 316 const struct via_isa_bridge *config = ap->host->private_data; 317 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 318 int mode = config->flags & VIA_UDMA; 319 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 320 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 321 322 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]); 323 } 324 325 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) 326 { 327 const struct via_isa_bridge *config = ap->host->private_data; 328 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 329 int mode = config->flags & VIA_UDMA; 330 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 331 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 332 333 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]); 334 } 335 336 /** 337 * via_tf_load - send taskfile registers to host controller 338 * @ap: Port to which output is sent 339 * @tf: ATA taskfile register set 340 * 341 * Outputs ATA taskfile to standard ATA host controller. 342 * 343 * Note: This is to fix the internal bug of via chipsets, which 344 * will reset the device register after changing the IEN bit on 345 * ctl register 346 */ 347 static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 348 { 349 struct ata_taskfile tmp_tf; 350 351 if (ap->ctl != ap->last_ctl && !(tf->flags & ATA_TFLAG_DEVICE)) { 352 tmp_tf = *tf; 353 tmp_tf.flags |= ATA_TFLAG_DEVICE; 354 tf = &tmp_tf; 355 } 356 ata_sff_tf_load(ap, tf); 357 } 358 359 static struct scsi_host_template via_sht = { 360 ATA_BMDMA_SHT(DRV_NAME), 361 }; 362 363 static struct ata_port_operations via_port_ops = { 364 .inherits = &ata_bmdma_port_ops, 365 .cable_detect = via_cable_detect, 366 .set_piomode = via_set_piomode, 367 .set_dmamode = via_set_dmamode, 368 .prereset = via_pre_reset, 369 .sff_tf_load = via_tf_load, 370 }; 371 372 static struct ata_port_operations via_port_ops_noirq = { 373 .inherits = &via_port_ops, 374 .sff_data_xfer = ata_sff_data_xfer_noirq, 375 }; 376 377 /** 378 * via_config_fifo - set up the FIFO 379 * @pdev: PCI device 380 * @flags: configuration flags 381 * 382 * Set the FIFO properties for this device if necessary. Used both on 383 * set up and on and the resume path 384 */ 385 386 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags) 387 { 388 u8 enable; 389 390 /* 0x40 low bits indicate enabled channels */ 391 pci_read_config_byte(pdev, 0x40 , &enable); 392 enable &= 3; 393 394 if (flags & VIA_SET_FIFO) { 395 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20}; 396 u8 fifo; 397 398 pci_read_config_byte(pdev, 0x43, &fifo); 399 400 /* Clear PREQ# until DDACK# for errata */ 401 if (flags & VIA_BAD_PREQ) 402 fifo &= 0x7F; 403 else 404 fifo &= 0x9f; 405 /* Turn on FIFO for enabled channels */ 406 fifo |= fifo_setting[enable]; 407 pci_write_config_byte(pdev, 0x43, fifo); 408 } 409 } 410 411 /** 412 * via_init_one - discovery callback 413 * @pdev: PCI device 414 * @id: PCI table info 415 * 416 * A VIA IDE interface has been discovered. Figure out what revision 417 * and perform configuration work before handing it to the ATA layer 418 */ 419 420 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 421 { 422 /* Early VIA without UDMA support */ 423 static const struct ata_port_info via_mwdma_info = { 424 .flags = ATA_FLAG_SLAVE_POSS, 425 .pio_mask = ATA_PIO4, 426 .mwdma_mask = ATA_MWDMA2, 427 .port_ops = &via_port_ops 428 }; 429 /* Ditto with IRQ masking required */ 430 static const struct ata_port_info via_mwdma_info_borked = { 431 .flags = ATA_FLAG_SLAVE_POSS, 432 .pio_mask = ATA_PIO4, 433 .mwdma_mask = ATA_MWDMA2, 434 .port_ops = &via_port_ops_noirq, 435 }; 436 /* VIA UDMA 33 devices (and borked 66) */ 437 static const struct ata_port_info via_udma33_info = { 438 .flags = ATA_FLAG_SLAVE_POSS, 439 .pio_mask = ATA_PIO4, 440 .mwdma_mask = ATA_MWDMA2, 441 .udma_mask = ATA_UDMA2, 442 .port_ops = &via_port_ops 443 }; 444 /* VIA UDMA 66 devices */ 445 static const struct ata_port_info via_udma66_info = { 446 .flags = ATA_FLAG_SLAVE_POSS, 447 .pio_mask = ATA_PIO4, 448 .mwdma_mask = ATA_MWDMA2, 449 .udma_mask = ATA_UDMA4, 450 .port_ops = &via_port_ops 451 }; 452 /* VIA UDMA 100 devices */ 453 static const struct ata_port_info via_udma100_info = { 454 .flags = ATA_FLAG_SLAVE_POSS, 455 .pio_mask = ATA_PIO4, 456 .mwdma_mask = ATA_MWDMA2, 457 .udma_mask = ATA_UDMA5, 458 .port_ops = &via_port_ops 459 }; 460 /* UDMA133 with bad AST (All current 133) */ 461 static const struct ata_port_info via_udma133_info = { 462 .flags = ATA_FLAG_SLAVE_POSS, 463 .pio_mask = ATA_PIO4, 464 .mwdma_mask = ATA_MWDMA2, 465 .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */ 466 .port_ops = &via_port_ops 467 }; 468 const struct ata_port_info *ppi[] = { NULL, NULL }; 469 struct pci_dev *isa = NULL; 470 const struct via_isa_bridge *config; 471 static int printed_version; 472 u8 enable; 473 u32 timing; 474 unsigned long flags = id->driver_data; 475 int rc; 476 477 if (!printed_version++) 478 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 479 480 rc = pcim_enable_device(pdev); 481 if (rc) 482 return rc; 483 484 if (flags & VIA_IDFLAG_SINGLE) 485 ppi[1] = &ata_dummy_port_info; 486 487 /* To find out how the IDE will behave and what features we 488 actually have to look at the bridge not the IDE controller */ 489 for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON; 490 config++) 491 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + 492 !!(config->flags & VIA_BAD_ID), 493 config->id, NULL))) { 494 495 if (isa->revision >= config->rev_min && 496 isa->revision <= config->rev_max) 497 break; 498 pci_dev_put(isa); 499 } 500 501 pci_dev_put(isa); 502 503 if (!(config->flags & VIA_NO_ENABLES)) { 504 /* 0x40 low bits indicate enabled channels */ 505 pci_read_config_byte(pdev, 0x40 , &enable); 506 enable &= 3; 507 if (enable == 0) 508 return -ENODEV; 509 } 510 511 /* Initialise the FIFO for the enabled channels. */ 512 via_config_fifo(pdev, config->flags); 513 514 /* Clock set up */ 515 switch(config->flags & VIA_UDMA) { 516 case VIA_UDMA_NONE: 517 if (config->flags & VIA_NO_UNMASK) 518 ppi[0] = &via_mwdma_info_borked; 519 else 520 ppi[0] = &via_mwdma_info; 521 break; 522 case VIA_UDMA_33: 523 ppi[0] = &via_udma33_info; 524 break; 525 case VIA_UDMA_66: 526 ppi[0] = &via_udma66_info; 527 /* The 66 MHz devices require we enable the clock */ 528 pci_read_config_dword(pdev, 0x50, &timing); 529 timing |= 0x80008; 530 pci_write_config_dword(pdev, 0x50, timing); 531 break; 532 case VIA_UDMA_100: 533 ppi[0] = &via_udma100_info; 534 break; 535 case VIA_UDMA_133: 536 ppi[0] = &via_udma133_info; 537 break; 538 default: 539 WARN_ON(1); 540 return -ENODEV; 541 } 542 543 if (config->flags & VIA_BAD_CLK66) { 544 /* Disable the 66MHz clock on problem devices */ 545 pci_read_config_dword(pdev, 0x50, &timing); 546 timing &= ~0x80008; 547 pci_write_config_dword(pdev, 0x50, timing); 548 } 549 550 /* We have established the device type, now fire it up */ 551 return ata_pci_sff_init_one(pdev, ppi, &via_sht, (void *)config); 552 } 553 554 #ifdef CONFIG_PM 555 /** 556 * via_reinit_one - reinit after resume 557 * @pdev; PCI device 558 * 559 * Called when the VIA PATA device is resumed. We must then 560 * reconfigure the fifo and other setup we may have altered. In 561 * addition the kernel needs to have the resume methods on PCI 562 * quirk supported. 563 */ 564 565 static int via_reinit_one(struct pci_dev *pdev) 566 { 567 u32 timing; 568 struct ata_host *host = dev_get_drvdata(&pdev->dev); 569 const struct via_isa_bridge *config = host->private_data; 570 int rc; 571 572 rc = ata_pci_device_do_resume(pdev); 573 if (rc) 574 return rc; 575 576 via_config_fifo(pdev, config->flags); 577 578 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) { 579 /* The 66 MHz devices require we enable the clock */ 580 pci_read_config_dword(pdev, 0x50, &timing); 581 timing |= 0x80008; 582 pci_write_config_dword(pdev, 0x50, timing); 583 } 584 if (config->flags & VIA_BAD_CLK66) { 585 /* Disable the 66MHz clock on problem devices */ 586 pci_read_config_dword(pdev, 0x50, &timing); 587 timing &= ~0x80008; 588 pci_write_config_dword(pdev, 0x50, timing); 589 } 590 591 ata_host_resume(host); 592 return 0; 593 } 594 #endif 595 596 static const struct pci_device_id via[] = { 597 { PCI_VDEVICE(VIA, 0x0415), }, 598 { PCI_VDEVICE(VIA, 0x0571), }, 599 { PCI_VDEVICE(VIA, 0x0581), }, 600 { PCI_VDEVICE(VIA, 0x1571), }, 601 { PCI_VDEVICE(VIA, 0x3164), }, 602 { PCI_VDEVICE(VIA, 0x5324), }, 603 { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE }, 604 605 { }, 606 }; 607 608 static struct pci_driver via_pci_driver = { 609 .name = DRV_NAME, 610 .id_table = via, 611 .probe = via_init_one, 612 .remove = ata_pci_remove_one, 613 #ifdef CONFIG_PM 614 .suspend = ata_pci_device_suspend, 615 .resume = via_reinit_one, 616 #endif 617 }; 618 619 static int __init via_init(void) 620 { 621 return pci_register_driver(&via_pci_driver); 622 } 623 624 static void __exit via_exit(void) 625 { 626 pci_unregister_driver(&via_pci_driver); 627 } 628 629 MODULE_AUTHOR("Alan Cox"); 630 MODULE_DESCRIPTION("low-level driver for VIA PATA"); 631 MODULE_LICENSE("GPL"); 632 MODULE_DEVICE_TABLE(pci, via); 633 MODULE_VERSION(DRV_VERSION); 634 635 module_init(via_init); 636 module_exit(via_exit); 637