1 /* 2 * pata_via.c - VIA PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * Documentation 7 * Most chipset documentation available under NDA only 8 * 9 * VIA version guide 10 * VIA VT82C561 - early design, uses ata_generic currently 11 * VIA VT82C576 - MWDMA, 33Mhz 12 * VIA VT82C586 - MWDMA, 33Mhz 13 * VIA VT82C586a - Added UDMA to 33Mhz 14 * VIA VT82C586b - UDMA33 15 * VIA VT82C596a - Nonfunctional UDMA66 16 * VIA VT82C596b - Working UDMA66 17 * VIA VT82C686 - Nonfunctional UDMA66 18 * VIA VT82C686a - Working UDMA66 19 * VIA VT82C686b - Updated to UDMA100 20 * VIA VT8231 - UDMA100 21 * VIA VT8233 - UDMA100 22 * VIA VT8233a - UDMA133 23 * VIA VT8233c - UDMA100 24 * VIA VT8235 - UDMA133 25 * VIA VT8237 - UDMA133 26 * VIA VT8237S - UDMA133 27 * VIA VT8251 - UDMA133 28 * 29 * Most registers remain compatible across chips. Others start reserved 30 * and acquire sensible semantics if set to 1 (eg cable detect). A few 31 * exceptions exist, notably around the FIFO settings. 32 * 33 * One additional quirk of the VIA design is that like ALi they use few 34 * PCI IDs for a lot of chips. 35 * 36 * Based heavily on: 37 * 38 * Version 3.38 39 * 40 * VIA IDE driver for Linux. Supported southbridges: 41 * 42 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, 43 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, 44 * vt8235, vt8237 45 * 46 * Copyright (c) 2000-2002 Vojtech Pavlik 47 * 48 * Based on the work of: 49 * Michel Aubry 50 * Jeff Garzik 51 * Andre Hedrick 52 53 */ 54 55 #include <linux/kernel.h> 56 #include <linux/module.h> 57 #include <linux/pci.h> 58 #include <linux/init.h> 59 #include <linux/blkdev.h> 60 #include <linux/delay.h> 61 #include <scsi/scsi_host.h> 62 #include <linux/libata.h> 63 64 #define DRV_NAME "pata_via" 65 #define DRV_VERSION "0.2.1" 66 67 /* 68 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx 69 * driver. 70 */ 71 72 enum { 73 VIA_UDMA = 0x007, 74 VIA_UDMA_NONE = 0x000, 75 VIA_UDMA_33 = 0x001, 76 VIA_UDMA_66 = 0x002, 77 VIA_UDMA_100 = 0x003, 78 VIA_UDMA_133 = 0x004, 79 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */ 80 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */ 81 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */ 82 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */ 83 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */ 84 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */ 85 VIA_NO_ENABLES = 0x400, /* Has no enablebits */ 86 }; 87 88 /* 89 * VIA SouthBridge chips. 90 */ 91 92 static const struct via_isa_bridge { 93 const char *name; 94 u16 id; 95 u8 rev_min; 96 u8 rev_max; 97 u16 flags; 98 } via_isa_bridges[] = { 99 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 100 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 101 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 102 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES}, 103 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 104 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 105 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 106 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 107 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, 108 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, 109 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, 110 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, 111 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, 112 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 113 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, 114 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 115 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, 116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, 117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, 118 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, 119 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, 120 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, 121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, 122 { NULL } 123 }; 124 125 /** 126 * via_cable_detect - cable detection 127 * @ap: ATA port 128 * 129 * Perform cable detection. Actually for the VIA case the BIOS 130 * already did this for us. We read the values provided by the 131 * BIOS. If you are using an 8235 in a non-PC configuration you 132 * may need to update this code. 133 * 134 * Hotplug also impacts on this. 135 */ 136 137 static int via_cable_detect(struct ata_port *ap) { 138 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 139 u32 ata66; 140 141 pci_read_config_dword(pdev, 0x50, &ata66); 142 /* Check both the drive cable reporting bits, we might not have 143 two drives */ 144 if (ata66 & (0x10100000 >> (16 * ap->port_no))) 145 return ATA_CBL_PATA80; 146 else 147 return ATA_CBL_PATA40; 148 } 149 150 static int via_pre_reset(struct ata_port *ap) 151 { 152 const struct via_isa_bridge *config = ap->host->private_data; 153 154 if (!(config->flags & VIA_NO_ENABLES)) { 155 static const struct pci_bits via_enable_bits[] = { 156 { 0x40, 1, 0x02, 0x02 }, 157 { 0x40, 1, 0x01, 0x01 } 158 }; 159 160 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 161 162 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) 163 return -ENOENT; 164 } 165 166 if ((config->flags & VIA_UDMA) >= VIA_UDMA_100) 167 ap->cbl = via_cable_detect(ap); 168 /* The UDMA66 series has no cable detect so do drive side detect */ 169 else if ((config->flags & VIA_UDMA) < VIA_UDMA_66) 170 ap->cbl = ATA_CBL_PATA40; 171 else 172 ap->cbl = ATA_CBL_PATA_UNK; 173 174 175 return ata_std_prereset(ap); 176 } 177 178 179 /** 180 * via_error_handler - reset for VIA chips 181 * @ap: ATA port 182 * 183 * Handle the reset callback for the later chips with cable detect 184 */ 185 186 static void via_error_handler(struct ata_port *ap) 187 { 188 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 189 } 190 191 /** 192 * via_do_set_mode - set initial PIO mode data 193 * @ap: ATA interface 194 * @adev: ATA device 195 * @mode: ATA mode being programmed 196 * @tdiv: Clocks per PCI clock 197 * @set_ast: Set to program address setup 198 * @udma_type: UDMA mode/format of registers 199 * 200 * Program the VIA registers for DMA and PIO modes. Uses the ata timing 201 * support in order to compute modes. 202 * 203 * FIXME: Hotplug will require we serialize multiple mode changes 204 * on the two channels. 205 */ 206 207 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type) 208 { 209 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 210 struct ata_device *peer = ata_dev_pair(adev); 211 struct ata_timing t, p; 212 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */ 213 unsigned long T = 1000000000 / via_clock; 214 unsigned long UT = T/tdiv; 215 int ut; 216 int offset = 3 - (2*ap->port_no) - adev->devno; 217 218 219 /* Calculate the timing values we require */ 220 ata_timing_compute(adev, mode, &t, T, UT); 221 222 /* We share 8bit timing so we must merge the constraints */ 223 if (peer) { 224 if (peer->pio_mode) { 225 ata_timing_compute(peer, peer->pio_mode, &p, T, UT); 226 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); 227 } 228 } 229 230 /* Address setup is programmable but breaks on UDMA133 setups */ 231 if (set_ast) { 232 u8 setup; /* 2 bits per drive */ 233 int shift = 2 * offset; 234 235 pci_read_config_byte(pdev, 0x4C, &setup); 236 setup &= ~(3 << shift); 237 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */ 238 pci_write_config_byte(pdev, 0x4C, setup); 239 } 240 241 /* Load the PIO mode bits */ 242 pci_write_config_byte(pdev, 0x4F - ap->port_no, 243 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1)); 244 pci_write_config_byte(pdev, 0x48 + offset, 245 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1)); 246 247 /* Load the UDMA bits according to type */ 248 switch(udma_type) { 249 default: 250 /* BUG() ? */ 251 /* fall through */ 252 case 33: 253 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03; 254 break; 255 case 66: 256 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f; 257 break; 258 case 100: 259 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07; 260 break; 261 case 133: 262 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07; 263 break; 264 } 265 /* Set UDMA unless device is not UDMA capable */ 266 if (udma_type) 267 pci_write_config_byte(pdev, 0x50 + offset, ut); 268 } 269 270 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev) 271 { 272 const struct via_isa_bridge *config = ap->host->private_data; 273 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 274 int mode = config->flags & VIA_UDMA; 275 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 276 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 277 278 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]); 279 } 280 281 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) 282 { 283 const struct via_isa_bridge *config = ap->host->private_data; 284 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 285 int mode = config->flags & VIA_UDMA; 286 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 287 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 288 289 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]); 290 } 291 292 static struct scsi_host_template via_sht = { 293 .module = THIS_MODULE, 294 .name = DRV_NAME, 295 .ioctl = ata_scsi_ioctl, 296 .queuecommand = ata_scsi_queuecmd, 297 .can_queue = ATA_DEF_QUEUE, 298 .this_id = ATA_SHT_THIS_ID, 299 .sg_tablesize = LIBATA_MAX_PRD, 300 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 301 .emulated = ATA_SHT_EMULATED, 302 .use_clustering = ATA_SHT_USE_CLUSTERING, 303 .proc_name = DRV_NAME, 304 .dma_boundary = ATA_DMA_BOUNDARY, 305 .slave_configure = ata_scsi_slave_config, 306 .slave_destroy = ata_scsi_slave_destroy, 307 .bios_param = ata_std_bios_param, 308 .resume = ata_scsi_device_resume, 309 .suspend = ata_scsi_device_suspend, 310 }; 311 312 static struct ata_port_operations via_port_ops = { 313 .port_disable = ata_port_disable, 314 .set_piomode = via_set_piomode, 315 .set_dmamode = via_set_dmamode, 316 .mode_filter = ata_pci_default_filter, 317 318 .tf_load = ata_tf_load, 319 .tf_read = ata_tf_read, 320 .check_status = ata_check_status, 321 .exec_command = ata_exec_command, 322 .dev_select = ata_std_dev_select, 323 324 .freeze = ata_bmdma_freeze, 325 .thaw = ata_bmdma_thaw, 326 .error_handler = via_error_handler, 327 .post_internal_cmd = ata_bmdma_post_internal_cmd, 328 329 .bmdma_setup = ata_bmdma_setup, 330 .bmdma_start = ata_bmdma_start, 331 .bmdma_stop = ata_bmdma_stop, 332 .bmdma_status = ata_bmdma_status, 333 334 .qc_prep = ata_qc_prep, 335 .qc_issue = ata_qc_issue_prot, 336 337 .data_xfer = ata_pio_data_xfer, 338 339 .irq_handler = ata_interrupt, 340 .irq_clear = ata_bmdma_irq_clear, 341 342 .port_start = ata_port_start, 343 .port_stop = ata_port_stop, 344 .host_stop = ata_host_stop 345 }; 346 347 static struct ata_port_operations via_port_ops_noirq = { 348 .port_disable = ata_port_disable, 349 .set_piomode = via_set_piomode, 350 .set_dmamode = via_set_dmamode, 351 .mode_filter = ata_pci_default_filter, 352 353 .tf_load = ata_tf_load, 354 .tf_read = ata_tf_read, 355 .check_status = ata_check_status, 356 .exec_command = ata_exec_command, 357 .dev_select = ata_std_dev_select, 358 359 .freeze = ata_bmdma_freeze, 360 .thaw = ata_bmdma_thaw, 361 .error_handler = via_error_handler, 362 .post_internal_cmd = ata_bmdma_post_internal_cmd, 363 364 .bmdma_setup = ata_bmdma_setup, 365 .bmdma_start = ata_bmdma_start, 366 .bmdma_stop = ata_bmdma_stop, 367 .bmdma_status = ata_bmdma_status, 368 369 .qc_prep = ata_qc_prep, 370 .qc_issue = ata_qc_issue_prot, 371 372 .data_xfer = ata_pio_data_xfer_noirq, 373 374 .irq_handler = ata_interrupt, 375 .irq_clear = ata_bmdma_irq_clear, 376 377 .port_start = ata_port_start, 378 .port_stop = ata_port_stop, 379 .host_stop = ata_host_stop 380 }; 381 382 /** 383 * via_config_fifo - set up the FIFO 384 * @pdev: PCI device 385 * @flags: configuration flags 386 * 387 * Set the FIFO properties for this device if neccessary. Used both on 388 * set up and on and the resume path 389 */ 390 391 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags) 392 { 393 u8 enable; 394 395 /* 0x40 low bits indicate enabled channels */ 396 pci_read_config_byte(pdev, 0x40 , &enable); 397 enable &= 3; 398 399 if (flags & VIA_SET_FIFO) { 400 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20}; 401 u8 fifo; 402 403 pci_read_config_byte(pdev, 0x43, &fifo); 404 405 /* Clear PREQ# until DDACK# for errata */ 406 if (flags & VIA_BAD_PREQ) 407 fifo &= 0x7F; 408 else 409 fifo &= 0x9f; 410 /* Turn on FIFO for enabled channels */ 411 fifo |= fifo_setting[enable]; 412 pci_write_config_byte(pdev, 0x43, fifo); 413 } 414 } 415 416 /** 417 * via_init_one - discovery callback 418 * @pdev: PCI device 419 * @id: PCI table info 420 * 421 * A VIA IDE interface has been discovered. Figure out what revision 422 * and perform configuration work before handing it to the ATA layer 423 */ 424 425 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 426 { 427 /* Early VIA without UDMA support */ 428 static struct ata_port_info via_mwdma_info = { 429 .sht = &via_sht, 430 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, 431 .pio_mask = 0x1f, 432 .mwdma_mask = 0x07, 433 .port_ops = &via_port_ops 434 }; 435 /* Ditto with IRQ masking required */ 436 static struct ata_port_info via_mwdma_info_borked = { 437 .sht = &via_sht, 438 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, 439 .pio_mask = 0x1f, 440 .mwdma_mask = 0x07, 441 .port_ops = &via_port_ops_noirq, 442 }; 443 /* VIA UDMA 33 devices (and borked 66) */ 444 static struct ata_port_info via_udma33_info = { 445 .sht = &via_sht, 446 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, 447 .pio_mask = 0x1f, 448 .mwdma_mask = 0x07, 449 .udma_mask = 0x7, 450 .port_ops = &via_port_ops 451 }; 452 /* VIA UDMA 66 devices */ 453 static struct ata_port_info via_udma66_info = { 454 .sht = &via_sht, 455 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, 456 .pio_mask = 0x1f, 457 .mwdma_mask = 0x07, 458 .udma_mask = 0x1f, 459 .port_ops = &via_port_ops 460 }; 461 /* VIA UDMA 100 devices */ 462 static struct ata_port_info via_udma100_info = { 463 .sht = &via_sht, 464 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, 465 .pio_mask = 0x1f, 466 .mwdma_mask = 0x07, 467 .udma_mask = 0x3f, 468 .port_ops = &via_port_ops 469 }; 470 /* UDMA133 with bad AST (All current 133) */ 471 static struct ata_port_info via_udma133_info = { 472 .sht = &via_sht, 473 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, 474 .pio_mask = 0x1f, 475 .mwdma_mask = 0x07, 476 .udma_mask = 0x7f, /* FIXME: should check north bridge */ 477 .port_ops = &via_port_ops 478 }; 479 struct ata_port_info *port_info[2], *type; 480 struct pci_dev *isa = NULL; 481 const struct via_isa_bridge *config; 482 static int printed_version; 483 u8 t; 484 u8 enable; 485 u32 timing; 486 487 if (!printed_version++) 488 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 489 490 /* To find out how the IDE will behave and what features we 491 actually have to look at the bridge not the IDE controller */ 492 for (config = via_isa_bridges; config->id; config++) 493 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + 494 !!(config->flags & VIA_BAD_ID), 495 config->id, NULL))) { 496 497 pci_read_config_byte(isa, PCI_REVISION_ID, &t); 498 if (t >= config->rev_min && 499 t <= config->rev_max) 500 break; 501 pci_dev_put(isa); 502 } 503 504 if (!config->id) { 505 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n"); 506 return -ENODEV; 507 } 508 pci_dev_put(isa); 509 510 /* 0x40 low bits indicate enabled channels */ 511 pci_read_config_byte(pdev, 0x40 , &enable); 512 enable &= 3; 513 if (enable == 0) { 514 return -ENODEV; 515 } 516 517 /* Initialise the FIFO for the enabled channels. */ 518 via_config_fifo(pdev, config->flags); 519 520 /* Clock set up */ 521 switch(config->flags & VIA_UDMA) { 522 case VIA_UDMA_NONE: 523 if (config->flags & VIA_NO_UNMASK) 524 type = &via_mwdma_info_borked; 525 else 526 type = &via_mwdma_info; 527 break; 528 case VIA_UDMA_33: 529 type = &via_udma33_info; 530 break; 531 case VIA_UDMA_66: 532 type = &via_udma66_info; 533 /* The 66 MHz devices require we enable the clock */ 534 pci_read_config_dword(pdev, 0x50, &timing); 535 timing |= 0x80008; 536 pci_write_config_dword(pdev, 0x50, timing); 537 break; 538 case VIA_UDMA_100: 539 type = &via_udma100_info; 540 break; 541 case VIA_UDMA_133: 542 type = &via_udma133_info; 543 break; 544 default: 545 WARN_ON(1); 546 return -ENODEV; 547 } 548 549 if (config->flags & VIA_BAD_CLK66) { 550 /* Disable the 66MHz clock on problem devices */ 551 pci_read_config_dword(pdev, 0x50, &timing); 552 timing &= ~0x80008; 553 pci_write_config_dword(pdev, 0x50, timing); 554 } 555 556 /* We have established the device type, now fire it up */ 557 type->private_data = (void *)config; 558 559 port_info[0] = port_info[1] = type; 560 return ata_pci_init_one(pdev, port_info, 2); 561 } 562 563 /** 564 * via_reinit_one - reinit after resume 565 * @pdev; PCI device 566 * 567 * Called when the VIA PATA device is resumed. We must then 568 * reconfigure the fifo and other setup we may have altered. In 569 * addition the kernel needs to have the resume methods on PCI 570 * quirk supported. 571 */ 572 573 static int via_reinit_one(struct pci_dev *pdev) 574 { 575 u32 timing; 576 struct ata_host *host = dev_get_drvdata(&pdev->dev); 577 const struct via_isa_bridge *config = host->private_data; 578 579 via_config_fifo(pdev, config->flags); 580 581 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) { 582 /* The 66 MHz devices require we enable the clock */ 583 pci_read_config_dword(pdev, 0x50, &timing); 584 timing |= 0x80008; 585 pci_write_config_dword(pdev, 0x50, timing); 586 } 587 if (config->flags & VIA_BAD_CLK66) { 588 /* Disable the 66MHz clock on problem devices */ 589 pci_read_config_dword(pdev, 0x50, &timing); 590 timing &= ~0x80008; 591 pci_write_config_dword(pdev, 0x50, timing); 592 } 593 return ata_pci_device_resume(pdev); 594 } 595 596 static const struct pci_device_id via[] = { 597 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), }, 598 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), }, 599 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), }, 600 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), }, 601 602 { }, 603 }; 604 605 static struct pci_driver via_pci_driver = { 606 .name = DRV_NAME, 607 .id_table = via, 608 .probe = via_init_one, 609 .remove = ata_pci_remove_one, 610 .suspend = ata_pci_device_suspend, 611 .resume = via_reinit_one, 612 }; 613 614 static int __init via_init(void) 615 { 616 return pci_register_driver(&via_pci_driver); 617 } 618 619 static void __exit via_exit(void) 620 { 621 pci_unregister_driver(&via_pci_driver); 622 } 623 624 MODULE_AUTHOR("Alan Cox"); 625 MODULE_DESCRIPTION("low-level driver for VIA PATA"); 626 MODULE_LICENSE("GPL"); 627 MODULE_DEVICE_TABLE(pci, via); 628 MODULE_VERSION(DRV_VERSION); 629 630 module_init(via_init); 631 module_exit(via_exit); 632