1 /* 2 * pata_via.c - VIA PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * 5 * Documentation 6 * Most chipset documentation available under NDA only 7 * 8 * VIA version guide 9 * VIA VT82C561 - early design, uses ata_generic currently 10 * VIA VT82C576 - MWDMA, 33Mhz 11 * VIA VT82C586 - MWDMA, 33Mhz 12 * VIA VT82C586a - Added UDMA to 33Mhz 13 * VIA VT82C586b - UDMA33 14 * VIA VT82C596a - Nonfunctional UDMA66 15 * VIA VT82C596b - Working UDMA66 16 * VIA VT82C686 - Nonfunctional UDMA66 17 * VIA VT82C686a - Working UDMA66 18 * VIA VT82C686b - Updated to UDMA100 19 * VIA VT8231 - UDMA100 20 * VIA VT8233 - UDMA100 21 * VIA VT8233a - UDMA133 22 * VIA VT8233c - UDMA100 23 * VIA VT8235 - UDMA133 24 * VIA VT8237 - UDMA133 25 * VIA VT8237S - UDMA133 26 * VIA VT8251 - UDMA133 27 * 28 * Most registers remain compatible across chips. Others start reserved 29 * and acquire sensible semantics if set to 1 (eg cable detect). A few 30 * exceptions exist, notably around the FIFO settings. 31 * 32 * One additional quirk of the VIA design is that like ALi they use few 33 * PCI IDs for a lot of chips. 34 * 35 * Based heavily on: 36 * 37 * Version 3.38 38 * 39 * VIA IDE driver for Linux. Supported southbridges: 40 * 41 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, 42 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, 43 * vt8235, vt8237 44 * 45 * Copyright (c) 2000-2002 Vojtech Pavlik 46 * 47 * Based on the work of: 48 * Michel Aubry 49 * Jeff Garzik 50 * Andre Hedrick 51 52 */ 53 54 #include <linux/kernel.h> 55 #include <linux/module.h> 56 #include <linux/pci.h> 57 #include <linux/init.h> 58 #include <linux/blkdev.h> 59 #include <linux/delay.h> 60 #include <scsi/scsi_host.h> 61 #include <linux/libata.h> 62 #include <linux/dmi.h> 63 64 #define DRV_NAME "pata_via" 65 #define DRV_VERSION "0.3.3" 66 67 /* 68 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx 69 * driver. 70 */ 71 72 enum { 73 VIA_UDMA = 0x007, 74 VIA_UDMA_NONE = 0x000, 75 VIA_UDMA_33 = 0x001, 76 VIA_UDMA_66 = 0x002, 77 VIA_UDMA_100 = 0x003, 78 VIA_UDMA_133 = 0x004, 79 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */ 80 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */ 81 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */ 82 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */ 83 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */ 84 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */ 85 VIA_NO_ENABLES = 0x400, /* Has no enablebits */ 86 VIA_SATA_PATA = 0x800, /* SATA/PATA combined configuration */ 87 }; 88 89 enum { 90 VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */ 91 }; 92 93 /* 94 * VIA SouthBridge chips. 95 */ 96 97 static const struct via_isa_bridge { 98 const char *name; 99 u16 id; 100 u8 rev_min; 101 u8 rev_max; 102 u16 flags; 103 } via_isa_bridges[] = { 104 { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, 105 VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, 106 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, VIA_UDMA_133 | 107 VIA_BAD_AST | VIA_SATA_PATA }, 108 { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, 109 VIA_UDMA_133 | VIA_BAD_AST }, 110 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 111 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 112 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, 113 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES}, 114 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 115 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 116 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 117 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, 118 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, 119 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, 120 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, 121 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, 122 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, 123 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 124 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, 125 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, 126 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, 127 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, 128 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, 129 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, 130 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, 131 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, 132 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, 133 { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, 134 VIA_UDMA_133 | VIA_BAD_AST }, 135 { NULL } 136 }; 137 138 139 /* 140 * Cable special cases 141 */ 142 143 static const struct dmi_system_id cable_dmi_table[] = { 144 { 145 .ident = "Acer Ferrari 3400", 146 .matches = { 147 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), 148 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), 149 }, 150 }, 151 { } 152 }; 153 154 static int via_cable_override(struct pci_dev *pdev) 155 { 156 /* Systems by DMI */ 157 if (dmi_check_system(cable_dmi_table)) 158 return 1; 159 /* Arima W730-K8/Targa Visionary 811/... */ 160 if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032) 161 return 1; 162 return 0; 163 } 164 165 166 /** 167 * via_cable_detect - cable detection 168 * @ap: ATA port 169 * 170 * Perform cable detection. Actually for the VIA case the BIOS 171 * already did this for us. We read the values provided by the 172 * BIOS. If you are using an 8235 in a non-PC configuration you 173 * may need to update this code. 174 * 175 * Hotplug also impacts on this. 176 */ 177 178 static int via_cable_detect(struct ata_port *ap) { 179 const struct via_isa_bridge *config = ap->host->private_data; 180 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 181 u32 ata66; 182 183 if (via_cable_override(pdev)) 184 return ATA_CBL_PATA40_SHORT; 185 186 if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0) 187 return ATA_CBL_SATA; 188 189 /* Early chips are 40 wire */ 190 if ((config->flags & VIA_UDMA) < VIA_UDMA_66) 191 return ATA_CBL_PATA40; 192 /* UDMA 66 chips have only drive side logic */ 193 else if ((config->flags & VIA_UDMA) < VIA_UDMA_100) 194 return ATA_CBL_PATA_UNK; 195 /* UDMA 100 or later */ 196 pci_read_config_dword(pdev, 0x50, &ata66); 197 /* Check both the drive cable reporting bits, we might not have 198 two drives */ 199 if (ata66 & (0x10100000 >> (16 * ap->port_no))) 200 return ATA_CBL_PATA80; 201 /* Check with ACPI so we can spot BIOS reported SATA bridges */ 202 if (ata_acpi_init_gtm(ap) && 203 ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap))) 204 return ATA_CBL_PATA80; 205 return ATA_CBL_PATA40; 206 } 207 208 static int via_pre_reset(struct ata_link *link, unsigned long deadline) 209 { 210 struct ata_port *ap = link->ap; 211 const struct via_isa_bridge *config = ap->host->private_data; 212 213 if (!(config->flags & VIA_NO_ENABLES)) { 214 static const struct pci_bits via_enable_bits[] = { 215 { 0x40, 1, 0x02, 0x02 }, 216 { 0x40, 1, 0x01, 0x01 } 217 }; 218 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 219 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) 220 return -ENOENT; 221 } 222 223 return ata_sff_prereset(link, deadline); 224 } 225 226 227 /** 228 * via_do_set_mode - set initial PIO mode data 229 * @ap: ATA interface 230 * @adev: ATA device 231 * @mode: ATA mode being programmed 232 * @tdiv: Clocks per PCI clock 233 * @set_ast: Set to program address setup 234 * @udma_type: UDMA mode/format of registers 235 * 236 * Program the VIA registers for DMA and PIO modes. Uses the ata timing 237 * support in order to compute modes. 238 * 239 * FIXME: Hotplug will require we serialize multiple mode changes 240 * on the two channels. 241 */ 242 243 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type) 244 { 245 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 246 struct ata_device *peer = ata_dev_pair(adev); 247 struct ata_timing t, p; 248 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */ 249 unsigned long T = 1000000000 / via_clock; 250 unsigned long UT = T/tdiv; 251 int ut; 252 int offset = 3 - (2*ap->port_no) - adev->devno; 253 254 /* Calculate the timing values we require */ 255 ata_timing_compute(adev, mode, &t, T, UT); 256 257 /* We share 8bit timing so we must merge the constraints */ 258 if (peer) { 259 if (peer->pio_mode) { 260 ata_timing_compute(peer, peer->pio_mode, &p, T, UT); 261 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); 262 } 263 } 264 265 /* Address setup is programmable but breaks on UDMA133 setups */ 266 if (set_ast) { 267 u8 setup; /* 2 bits per drive */ 268 int shift = 2 * offset; 269 270 pci_read_config_byte(pdev, 0x4C, &setup); 271 setup &= ~(3 << shift); 272 setup |= clamp_val(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */ 273 pci_write_config_byte(pdev, 0x4C, setup); 274 } 275 276 /* Load the PIO mode bits */ 277 pci_write_config_byte(pdev, 0x4F - ap->port_no, 278 ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1)); 279 pci_write_config_byte(pdev, 0x48 + offset, 280 ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1)); 281 282 /* Load the UDMA bits according to type */ 283 switch(udma_type) { 284 default: 285 /* BUG() ? */ 286 /* fall through */ 287 case 33: 288 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03; 289 break; 290 case 66: 291 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f; 292 break; 293 case 100: 294 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; 295 break; 296 case 133: 297 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; 298 break; 299 } 300 301 /* Set UDMA unless device is not UDMA capable */ 302 if (udma_type && t.udma) { 303 u8 cable80_status; 304 305 /* Get 80-wire cable detection bit */ 306 pci_read_config_byte(pdev, 0x50 + offset, &cable80_status); 307 cable80_status &= 0x10; 308 309 pci_write_config_byte(pdev, 0x50 + offset, ut | cable80_status); 310 } 311 } 312 313 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev) 314 { 315 const struct via_isa_bridge *config = ap->host->private_data; 316 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 317 int mode = config->flags & VIA_UDMA; 318 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 319 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 320 321 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]); 322 } 323 324 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) 325 { 326 const struct via_isa_bridge *config = ap->host->private_data; 327 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; 328 int mode = config->flags & VIA_UDMA; 329 static u8 tclock[5] = { 1, 1, 2, 3, 4 }; 330 static u8 udma[5] = { 0, 33, 66, 100, 133 }; 331 332 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]); 333 } 334 335 /** 336 * via_tf_load - send taskfile registers to host controller 337 * @ap: Port to which output is sent 338 * @tf: ATA taskfile register set 339 * 340 * Outputs ATA taskfile to standard ATA host controller. 341 * 342 * Note: This is to fix the internal bug of via chipsets, which 343 * will reset the device register after changing the IEN bit on 344 * ctl register 345 */ 346 static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 347 { 348 struct ata_taskfile tmp_tf; 349 350 if (ap->ctl != ap->last_ctl && !(tf->flags & ATA_TFLAG_DEVICE)) { 351 tmp_tf = *tf; 352 tmp_tf.flags |= ATA_TFLAG_DEVICE; 353 tf = &tmp_tf; 354 } 355 ata_sff_tf_load(ap, tf); 356 } 357 358 static struct scsi_host_template via_sht = { 359 ATA_BMDMA_SHT(DRV_NAME), 360 }; 361 362 static struct ata_port_operations via_port_ops = { 363 .inherits = &ata_bmdma_port_ops, 364 .cable_detect = via_cable_detect, 365 .set_piomode = via_set_piomode, 366 .set_dmamode = via_set_dmamode, 367 .prereset = via_pre_reset, 368 .sff_tf_load = via_tf_load, 369 }; 370 371 static struct ata_port_operations via_port_ops_noirq = { 372 .inherits = &via_port_ops, 373 .sff_data_xfer = ata_sff_data_xfer_noirq, 374 }; 375 376 /** 377 * via_config_fifo - set up the FIFO 378 * @pdev: PCI device 379 * @flags: configuration flags 380 * 381 * Set the FIFO properties for this device if necessary. Used both on 382 * set up and on and the resume path 383 */ 384 385 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags) 386 { 387 u8 enable; 388 389 /* 0x40 low bits indicate enabled channels */ 390 pci_read_config_byte(pdev, 0x40 , &enable); 391 enable &= 3; 392 393 if (flags & VIA_SET_FIFO) { 394 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20}; 395 u8 fifo; 396 397 pci_read_config_byte(pdev, 0x43, &fifo); 398 399 /* Clear PREQ# until DDACK# for errata */ 400 if (flags & VIA_BAD_PREQ) 401 fifo &= 0x7F; 402 else 403 fifo &= 0x9f; 404 /* Turn on FIFO for enabled channels */ 405 fifo |= fifo_setting[enable]; 406 pci_write_config_byte(pdev, 0x43, fifo); 407 } 408 } 409 410 /** 411 * via_init_one - discovery callback 412 * @pdev: PCI device 413 * @id: PCI table info 414 * 415 * A VIA IDE interface has been discovered. Figure out what revision 416 * and perform configuration work before handing it to the ATA layer 417 */ 418 419 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 420 { 421 /* Early VIA without UDMA support */ 422 static const struct ata_port_info via_mwdma_info = { 423 .flags = ATA_FLAG_SLAVE_POSS, 424 .pio_mask = 0x1f, 425 .mwdma_mask = 0x07, 426 .port_ops = &via_port_ops 427 }; 428 /* Ditto with IRQ masking required */ 429 static const struct ata_port_info via_mwdma_info_borked = { 430 .flags = ATA_FLAG_SLAVE_POSS, 431 .pio_mask = 0x1f, 432 .mwdma_mask = 0x07, 433 .port_ops = &via_port_ops_noirq, 434 }; 435 /* VIA UDMA 33 devices (and borked 66) */ 436 static const struct ata_port_info via_udma33_info = { 437 .flags = ATA_FLAG_SLAVE_POSS, 438 .pio_mask = 0x1f, 439 .mwdma_mask = 0x07, 440 .udma_mask = ATA_UDMA2, 441 .port_ops = &via_port_ops 442 }; 443 /* VIA UDMA 66 devices */ 444 static const struct ata_port_info via_udma66_info = { 445 .flags = ATA_FLAG_SLAVE_POSS, 446 .pio_mask = 0x1f, 447 .mwdma_mask = 0x07, 448 .udma_mask = ATA_UDMA4, 449 .port_ops = &via_port_ops 450 }; 451 /* VIA UDMA 100 devices */ 452 static const struct ata_port_info via_udma100_info = { 453 .flags = ATA_FLAG_SLAVE_POSS, 454 .pio_mask = 0x1f, 455 .mwdma_mask = 0x07, 456 .udma_mask = ATA_UDMA5, 457 .port_ops = &via_port_ops 458 }; 459 /* UDMA133 with bad AST (All current 133) */ 460 static const struct ata_port_info via_udma133_info = { 461 .flags = ATA_FLAG_SLAVE_POSS, 462 .pio_mask = 0x1f, 463 .mwdma_mask = 0x07, 464 .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */ 465 .port_ops = &via_port_ops 466 }; 467 const struct ata_port_info *ppi[] = { NULL, NULL }; 468 struct pci_dev *isa = NULL; 469 const struct via_isa_bridge *config; 470 static int printed_version; 471 u8 enable; 472 u32 timing; 473 unsigned long flags = id->driver_data; 474 int rc; 475 476 if (!printed_version++) 477 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 478 479 rc = pcim_enable_device(pdev); 480 if (rc) 481 return rc; 482 483 if (flags & VIA_IDFLAG_SINGLE) 484 ppi[1] = &ata_dummy_port_info; 485 486 /* To find out how the IDE will behave and what features we 487 actually have to look at the bridge not the IDE controller */ 488 for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON; 489 config++) 490 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + 491 !!(config->flags & VIA_BAD_ID), 492 config->id, NULL))) { 493 494 if (isa->revision >= config->rev_min && 495 isa->revision <= config->rev_max) 496 break; 497 pci_dev_put(isa); 498 } 499 500 pci_dev_put(isa); 501 502 if (!(config->flags & VIA_NO_ENABLES)) { 503 /* 0x40 low bits indicate enabled channels */ 504 pci_read_config_byte(pdev, 0x40 , &enable); 505 enable &= 3; 506 if (enable == 0) 507 return -ENODEV; 508 } 509 510 /* Initialise the FIFO for the enabled channels. */ 511 via_config_fifo(pdev, config->flags); 512 513 /* Clock set up */ 514 switch(config->flags & VIA_UDMA) { 515 case VIA_UDMA_NONE: 516 if (config->flags & VIA_NO_UNMASK) 517 ppi[0] = &via_mwdma_info_borked; 518 else 519 ppi[0] = &via_mwdma_info; 520 break; 521 case VIA_UDMA_33: 522 ppi[0] = &via_udma33_info; 523 break; 524 case VIA_UDMA_66: 525 ppi[0] = &via_udma66_info; 526 /* The 66 MHz devices require we enable the clock */ 527 pci_read_config_dword(pdev, 0x50, &timing); 528 timing |= 0x80008; 529 pci_write_config_dword(pdev, 0x50, timing); 530 break; 531 case VIA_UDMA_100: 532 ppi[0] = &via_udma100_info; 533 break; 534 case VIA_UDMA_133: 535 ppi[0] = &via_udma133_info; 536 break; 537 default: 538 WARN_ON(1); 539 return -ENODEV; 540 } 541 542 if (config->flags & VIA_BAD_CLK66) { 543 /* Disable the 66MHz clock on problem devices */ 544 pci_read_config_dword(pdev, 0x50, &timing); 545 timing &= ~0x80008; 546 pci_write_config_dword(pdev, 0x50, timing); 547 } 548 549 /* We have established the device type, now fire it up */ 550 return ata_pci_sff_init_one(pdev, ppi, &via_sht, (void *)config); 551 } 552 553 #ifdef CONFIG_PM 554 /** 555 * via_reinit_one - reinit after resume 556 * @pdev; PCI device 557 * 558 * Called when the VIA PATA device is resumed. We must then 559 * reconfigure the fifo and other setup we may have altered. In 560 * addition the kernel needs to have the resume methods on PCI 561 * quirk supported. 562 */ 563 564 static int via_reinit_one(struct pci_dev *pdev) 565 { 566 u32 timing; 567 struct ata_host *host = dev_get_drvdata(&pdev->dev); 568 const struct via_isa_bridge *config = host->private_data; 569 int rc; 570 571 rc = ata_pci_device_do_resume(pdev); 572 if (rc) 573 return rc; 574 575 via_config_fifo(pdev, config->flags); 576 577 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) { 578 /* The 66 MHz devices require we enable the clock */ 579 pci_read_config_dword(pdev, 0x50, &timing); 580 timing |= 0x80008; 581 pci_write_config_dword(pdev, 0x50, timing); 582 } 583 if (config->flags & VIA_BAD_CLK66) { 584 /* Disable the 66MHz clock on problem devices */ 585 pci_read_config_dword(pdev, 0x50, &timing); 586 timing &= ~0x80008; 587 pci_write_config_dword(pdev, 0x50, timing); 588 } 589 590 ata_host_resume(host); 591 return 0; 592 } 593 #endif 594 595 static const struct pci_device_id via[] = { 596 { PCI_VDEVICE(VIA, 0x0571), }, 597 { PCI_VDEVICE(VIA, 0x0581), }, 598 { PCI_VDEVICE(VIA, 0x1571), }, 599 { PCI_VDEVICE(VIA, 0x3164), }, 600 { PCI_VDEVICE(VIA, 0x5324), }, 601 { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE }, 602 603 { }, 604 }; 605 606 static struct pci_driver via_pci_driver = { 607 .name = DRV_NAME, 608 .id_table = via, 609 .probe = via_init_one, 610 .remove = ata_pci_remove_one, 611 #ifdef CONFIG_PM 612 .suspend = ata_pci_device_suspend, 613 .resume = via_reinit_one, 614 #endif 615 }; 616 617 static int __init via_init(void) 618 { 619 return pci_register_driver(&via_pci_driver); 620 } 621 622 static void __exit via_exit(void) 623 { 624 pci_unregister_driver(&via_pci_driver); 625 } 626 627 MODULE_AUTHOR("Alan Cox"); 628 MODULE_DESCRIPTION("low-level driver for VIA PATA"); 629 MODULE_LICENSE("GPL"); 630 MODULE_DEVICE_TABLE(pci, via); 631 MODULE_VERSION(DRV_VERSION); 632 633 module_init(via_init); 634 module_exit(via_exit); 635