1 /* 2 * pata_serverworks.c - Serverworks PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * based upon 7 * 8 * serverworks.c 9 * 10 * Copyright (C) 1998-2000 Michel Aubry 11 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz 12 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 13 * Portions copyright (c) 2001 Sun Microsystems 14 * 15 * 16 * RCC/ServerWorks IDE driver for Linux 17 * 18 * OSB4: `Open South Bridge' IDE Interface (fn 1) 19 * supports UDMA mode 2 (33 MB/s) 20 * 21 * CSB5: `Champion South Bridge' IDE Interface (fn 1) 22 * all revisions support UDMA mode 4 (66 MB/s) 23 * revision A2.0 and up support UDMA mode 5 (100 MB/s) 24 * 25 * *** The CSB5 does not provide ANY register *** 26 * *** to detect 80-conductor cable presence. *** 27 * 28 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) 29 * 30 * Documentation: 31 * Available under NDA only. Errata info very hard to get. 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/init.h> 38 #include <linux/blkdev.h> 39 #include <linux/delay.h> 40 #include <scsi/scsi_host.h> 41 #include <linux/libata.h> 42 43 #define DRV_NAME "pata_serverworks" 44 #define DRV_VERSION "0.4.2" 45 46 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ 47 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ 48 49 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 50 * can overrun their FIFOs when used with the CSB5 */ 51 52 static const char *csb_bad_ata100[] = { 53 "ST320011A", 54 "ST340016A", 55 "ST360021A", 56 "ST380021A", 57 NULL 58 }; 59 60 /** 61 * dell_cable - Dell serverworks cable detection 62 * @ap: ATA port to do cable detect 63 * 64 * Dell hide the 40/80 pin select for their interfaces in the top two 65 * bits of the subsystem ID. 66 */ 67 68 static int dell_cable(struct ata_port *ap) { 69 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 70 71 if (pdev->subsystem_device & (1 << (ap->port_no + 14))) 72 return ATA_CBL_PATA80; 73 return ATA_CBL_PATA40; 74 } 75 76 /** 77 * sun_cable - Sun Cobalt 'Alpine' cable detection 78 * @ap: ATA port to do cable select 79 * 80 * Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the 81 * subsystem ID the same as dell. We could use one function but we may 82 * need to extend the Dell one in future 83 */ 84 85 static int sun_cable(struct ata_port *ap) { 86 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 87 88 if (pdev->subsystem_device & (1 << (ap->port_no + 14))) 89 return ATA_CBL_PATA80; 90 return ATA_CBL_PATA40; 91 } 92 93 /** 94 * osb4_cable - OSB4 cable detect 95 * @ap: ATA port to check 96 * 97 * The OSB4 isn't UDMA66 capable so this is easy 98 */ 99 100 static int osb4_cable(struct ata_port *ap) { 101 return ATA_CBL_PATA40; 102 } 103 104 /** 105 * csb4_cable - CSB5/6 cable detect 106 * @ap: ATA port to check 107 * 108 * Serverworks default arrangement is to use the drive side detection 109 * only. 110 */ 111 112 static int csb_cable(struct ata_port *ap) { 113 return ATA_CBL_PATA80; 114 } 115 116 struct sv_cable_table { 117 int device; 118 int subvendor; 119 int (*cable_detect)(struct ata_port *ap); 120 }; 121 122 /* 123 * Note that we don't copy the old serverworks code because the old 124 * code contains obvious mistakes 125 */ 126 127 static struct sv_cable_table cable_detect[] = { 128 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable }, 129 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable }, 130 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable }, 131 { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable }, 132 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable }, 133 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable }, 134 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable }, 135 { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable }, 136 { } 137 }; 138 139 /** 140 * serverworks_cable_detect - cable detection 141 * @ap: ATA port 142 * @deadline: deadline jiffies for the operation 143 * 144 * Perform cable detection according to the device and subvendor 145 * identifications 146 */ 147 148 static int serverworks_cable_detect(struct ata_port *ap) 149 { 150 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 151 struct sv_cable_table *cb = cable_detect; 152 153 while(cb->device) { 154 if (cb->device == pdev->device && 155 (cb->subvendor == pdev->subsystem_vendor || 156 cb->subvendor == PCI_ANY_ID)) { 157 return cb->cable_detect(ap); 158 } 159 cb++; 160 } 161 162 BUG(); 163 return -1; /* kill compiler warning */ 164 } 165 166 /** 167 * serverworks_is_csb - Check for CSB or OSB 168 * @pdev: PCI device to check 169 * 170 * Returns true if the device being checked is known to be a CSB 171 * series device. 172 */ 173 174 static u8 serverworks_is_csb(struct pci_dev *pdev) 175 { 176 switch (pdev->device) { 177 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 178 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 179 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 180 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: 181 return 1; 182 default: 183 break; 184 } 185 return 0; 186 } 187 188 /** 189 * serverworks_osb4_filter - mode selection filter 190 * @adev: ATA device 191 * @mask: Mask of proposed modes 192 * 193 * Filter the offered modes for the device to apply controller 194 * specific rules. OSB4 requires no UDMA for disks due to a FIFO 195 * bug we hit. 196 */ 197 198 static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask) 199 { 200 if (adev->class == ATA_DEV_ATA) 201 mask &= ~ATA_MASK_UDMA; 202 return ata_pci_default_filter(adev, mask); 203 } 204 205 206 /** 207 * serverworks_csb_filter - mode selection filter 208 * @adev: ATA device 209 * @mask: Mask of proposed modes 210 * 211 * Check the blacklist and disable UDMA5 if matched 212 */ 213 214 static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask) 215 { 216 const char *p; 217 char model_num[ATA_ID_PROD_LEN + 1]; 218 int i; 219 220 /* Disk, UDMA */ 221 if (adev->class != ATA_DEV_ATA) 222 return ata_pci_default_filter(adev, mask); 223 224 /* Actually do need to check */ 225 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 226 227 for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) { 228 if (!strcmp(p, model_num)) 229 mask &= ~(0x1F << ATA_SHIFT_UDMA); 230 } 231 return ata_pci_default_filter(adev, mask); 232 } 233 234 235 /** 236 * serverworks_set_piomode - set initial PIO mode data 237 * @ap: ATA interface 238 * @adev: ATA device 239 * 240 * Program the OSB4/CSB5 timing registers for PIO. The PIO register 241 * load is done as a simple lookup. 242 */ 243 static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev) 244 { 245 static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 246 int offset = 1 + (2 * ap->port_no) - adev->devno; 247 int devbits = (2 * ap->port_no + adev->devno) * 4; 248 u16 csb5_pio; 249 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 250 int pio = adev->pio_mode - XFER_PIO_0; 251 252 pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]); 253 254 /* The OSB4 just requires the timing but the CSB series want the 255 mode number as well */ 256 if (serverworks_is_csb(pdev)) { 257 pci_read_config_word(pdev, 0x4A, &csb5_pio); 258 csb5_pio &= ~(0x0F << devbits); 259 pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits)); 260 } 261 } 262 263 /** 264 * serverworks_set_dmamode - set initial DMA mode data 265 * @ap: ATA interface 266 * @adev: ATA device 267 * 268 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5 269 * chipset. The MWDMA mode values are pulled from a lookup table 270 * while the chipset uses mode number for UDMA. 271 */ 272 273 static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev) 274 { 275 static const u8 dma_mode[] = { 0x77, 0x21, 0x20 }; 276 int offset = 1 + 2 * ap->port_no - adev->devno; 277 int devbits = 2 * ap->port_no + adev->devno; 278 u8 ultra; 279 u8 ultra_cfg; 280 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 281 282 pci_read_config_byte(pdev, 0x54, &ultra_cfg); 283 pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra); 284 ultra &= ~(0x0F << (adev->devno * 4)); 285 286 if (adev->dma_mode >= XFER_UDMA_0) { 287 pci_write_config_byte(pdev, 0x44 + offset, 0x20); 288 289 ultra |= (adev->dma_mode - XFER_UDMA_0) 290 << (adev->devno * 4); 291 ultra_cfg |= (1 << devbits); 292 } else { 293 pci_write_config_byte(pdev, 0x44 + offset, 294 dma_mode[adev->dma_mode - XFER_MW_DMA_0]); 295 ultra_cfg &= ~(1 << devbits); 296 } 297 pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra); 298 pci_write_config_byte(pdev, 0x54, ultra_cfg); 299 } 300 301 static struct scsi_host_template serverworks_sht = { 302 .module = THIS_MODULE, 303 .name = DRV_NAME, 304 .ioctl = ata_scsi_ioctl, 305 .queuecommand = ata_scsi_queuecmd, 306 .can_queue = ATA_DEF_QUEUE, 307 .this_id = ATA_SHT_THIS_ID, 308 .sg_tablesize = LIBATA_MAX_PRD, 309 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 310 .emulated = ATA_SHT_EMULATED, 311 .use_clustering = ATA_SHT_USE_CLUSTERING, 312 .proc_name = DRV_NAME, 313 .dma_boundary = ATA_DMA_BOUNDARY, 314 .slave_configure = ata_scsi_slave_config, 315 .slave_destroy = ata_scsi_slave_destroy, 316 .bios_param = ata_std_bios_param, 317 }; 318 319 static struct ata_port_operations serverworks_osb4_port_ops = { 320 .set_piomode = serverworks_set_piomode, 321 .set_dmamode = serverworks_set_dmamode, 322 .mode_filter = serverworks_osb4_filter, 323 324 .tf_load = ata_tf_load, 325 .tf_read = ata_tf_read, 326 .check_status = ata_check_status, 327 .exec_command = ata_exec_command, 328 .dev_select = ata_std_dev_select, 329 330 .freeze = ata_bmdma_freeze, 331 .thaw = ata_bmdma_thaw, 332 .error_handler = ata_bmdma_error_handler, 333 .post_internal_cmd = ata_bmdma_post_internal_cmd, 334 .cable_detect = serverworks_cable_detect, 335 336 .bmdma_setup = ata_bmdma_setup, 337 .bmdma_start = ata_bmdma_start, 338 .bmdma_stop = ata_bmdma_stop, 339 .bmdma_status = ata_bmdma_status, 340 341 .qc_prep = ata_qc_prep, 342 .qc_issue = ata_qc_issue_prot, 343 344 .data_xfer = ata_data_xfer, 345 346 .irq_handler = ata_interrupt, 347 .irq_clear = ata_bmdma_irq_clear, 348 .irq_on = ata_irq_on, 349 350 .port_start = ata_sff_port_start, 351 }; 352 353 static struct ata_port_operations serverworks_csb_port_ops = { 354 .set_piomode = serverworks_set_piomode, 355 .set_dmamode = serverworks_set_dmamode, 356 .mode_filter = serverworks_csb_filter, 357 358 .tf_load = ata_tf_load, 359 .tf_read = ata_tf_read, 360 .check_status = ata_check_status, 361 .exec_command = ata_exec_command, 362 .dev_select = ata_std_dev_select, 363 364 .freeze = ata_bmdma_freeze, 365 .thaw = ata_bmdma_thaw, 366 .error_handler = ata_bmdma_error_handler, 367 .post_internal_cmd = ata_bmdma_post_internal_cmd, 368 .cable_detect = serverworks_cable_detect, 369 370 .bmdma_setup = ata_bmdma_setup, 371 .bmdma_start = ata_bmdma_start, 372 .bmdma_stop = ata_bmdma_stop, 373 .bmdma_status = ata_bmdma_status, 374 375 .qc_prep = ata_qc_prep, 376 .qc_issue = ata_qc_issue_prot, 377 378 .data_xfer = ata_data_xfer, 379 380 .irq_handler = ata_interrupt, 381 .irq_clear = ata_bmdma_irq_clear, 382 .irq_on = ata_irq_on, 383 384 .port_start = ata_sff_port_start, 385 }; 386 387 static int serverworks_fixup_osb4(struct pci_dev *pdev) 388 { 389 u32 reg; 390 struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 391 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); 392 if (isa_dev) { 393 pci_read_config_dword(isa_dev, 0x64, ®); 394 reg &= ~0x00002000; /* disable 600ns interrupt mask */ 395 if (!(reg & 0x00004000)) 396 printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n"); 397 reg |= 0x00004000; /* enable UDMA/33 support */ 398 pci_write_config_dword(isa_dev, 0x64, reg); 399 pci_dev_put(isa_dev); 400 return 0; 401 } 402 printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n"); 403 return -ENODEV; 404 } 405 406 static int serverworks_fixup_csb(struct pci_dev *pdev) 407 { 408 u8 btr; 409 410 /* Third Channel Test */ 411 if (!(PCI_FUNC(pdev->devfn) & 1)) { 412 struct pci_dev * findev = NULL; 413 u32 reg4c = 0; 414 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 415 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); 416 if (findev) { 417 pci_read_config_dword(findev, 0x4C, ®4c); 418 reg4c &= ~0x000007FF; 419 reg4c |= 0x00000040; 420 reg4c |= 0x00000020; 421 pci_write_config_dword(findev, 0x4C, reg4c); 422 pci_dev_put(findev); 423 } 424 } else { 425 struct pci_dev * findev = NULL; 426 u8 reg41 = 0; 427 428 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 429 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); 430 if (findev) { 431 pci_read_config_byte(findev, 0x41, ®41); 432 reg41 &= ~0x40; 433 pci_write_config_byte(findev, 0x41, reg41); 434 pci_dev_put(findev); 435 } 436 } 437 /* setup the UDMA Control register 438 * 439 * 1. clear bit 6 to enable DMA 440 * 2. enable DMA modes with bits 0-1 441 * 00 : legacy 442 * 01 : udma2 443 * 10 : udma2/udma4 444 * 11 : udma2/udma4/udma5 445 */ 446 pci_read_config_byte(pdev, 0x5A, &btr); 447 btr &= ~0x40; 448 if (!(PCI_FUNC(pdev->devfn) & 1)) 449 btr |= 0x2; 450 else 451 btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; 452 pci_write_config_byte(pdev, 0x5A, btr); 453 454 return btr; 455 } 456 457 static void serverworks_fixup_ht1000(struct pci_dev *pdev) 458 { 459 u8 btr; 460 /* Setup HT1000 SouthBridge Controller - Single Channel Only */ 461 pci_read_config_byte(pdev, 0x5A, &btr); 462 btr &= ~0x40; 463 btr |= 0x3; 464 pci_write_config_byte(pdev, 0x5A, btr); 465 } 466 467 468 static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 469 { 470 static const struct ata_port_info info[4] = { 471 { /* OSB4 */ 472 .sht = &serverworks_sht, 473 .flags = ATA_FLAG_SLAVE_POSS, 474 .pio_mask = 0x1f, 475 .mwdma_mask = 0x07, 476 .udma_mask = 0x07, 477 .port_ops = &serverworks_osb4_port_ops 478 }, { /* OSB4 no UDMA */ 479 .sht = &serverworks_sht, 480 .flags = ATA_FLAG_SLAVE_POSS, 481 .pio_mask = 0x1f, 482 .mwdma_mask = 0x07, 483 .udma_mask = 0x00, 484 .port_ops = &serverworks_osb4_port_ops 485 }, { /* CSB5 */ 486 .sht = &serverworks_sht, 487 .flags = ATA_FLAG_SLAVE_POSS, 488 .pio_mask = 0x1f, 489 .mwdma_mask = 0x07, 490 .udma_mask = ATA_UDMA4, 491 .port_ops = &serverworks_csb_port_ops 492 }, { /* CSB5 - later revisions*/ 493 .sht = &serverworks_sht, 494 .flags = ATA_FLAG_SLAVE_POSS, 495 .pio_mask = 0x1f, 496 .mwdma_mask = 0x07, 497 .udma_mask = ATA_UDMA5, 498 .port_ops = &serverworks_csb_port_ops 499 } 500 }; 501 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL }; 502 503 /* Force master latency timer to 64 PCI clocks */ 504 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); 505 506 /* OSB4 : South Bridge and IDE */ 507 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { 508 /* Select non UDMA capable OSB4 if we can't do fixups */ 509 if ( serverworks_fixup_osb4(pdev) < 0) 510 ppi[0] = &info[1]; 511 } 512 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ 513 else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || 514 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || 515 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { 516 517 /* If the returned btr is the newer revision then 518 select the right info block */ 519 if (serverworks_fixup_csb(pdev) == 3) 520 ppi[0] = &info[3]; 521 522 /* Is this the 3rd channel CSB6 IDE ? */ 523 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) 524 ppi[1] = &ata_dummy_port_info; 525 } 526 /* setup HT1000E */ 527 else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) 528 serverworks_fixup_ht1000(pdev); 529 530 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) 531 ata_pci_clear_simplex(pdev); 532 533 return ata_pci_init_one(pdev, ppi); 534 } 535 536 #ifdef CONFIG_PM 537 static int serverworks_reinit_one(struct pci_dev *pdev) 538 { 539 /* Force master latency timer to 64 PCI clocks */ 540 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); 541 542 switch (pdev->device) 543 { 544 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE: 545 serverworks_fixup_osb4(pdev); 546 break; 547 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 548 ata_pci_clear_simplex(pdev); 549 /* fall through */ 550 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 551 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 552 serverworks_fixup_csb(pdev); 553 break; 554 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: 555 serverworks_fixup_ht1000(pdev); 556 break; 557 } 558 return ata_pci_device_resume(pdev); 559 } 560 #endif 561 562 static const struct pci_device_id serverworks[] = { 563 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0}, 564 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2}, 565 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2}, 566 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2}, 567 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2}, 568 569 { }, 570 }; 571 572 static struct pci_driver serverworks_pci_driver = { 573 .name = DRV_NAME, 574 .id_table = serverworks, 575 .probe = serverworks_init_one, 576 .remove = ata_pci_remove_one, 577 #ifdef CONFIG_PM 578 .suspend = ata_pci_device_suspend, 579 .resume = serverworks_reinit_one, 580 #endif 581 }; 582 583 static int __init serverworks_init(void) 584 { 585 return pci_register_driver(&serverworks_pci_driver); 586 } 587 588 static void __exit serverworks_exit(void) 589 { 590 pci_unregister_driver(&serverworks_pci_driver); 591 } 592 593 MODULE_AUTHOR("Alan Cox"); 594 MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6"); 595 MODULE_LICENSE("GPL"); 596 MODULE_DEVICE_TABLE(pci, serverworks); 597 MODULE_VERSION(DRV_VERSION); 598 599 module_init(serverworks_init); 600 module_exit(serverworks_exit); 601