1 /* 2 * pata_serverworks.c - Serverworks PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * (C) 2010 Bartlomiej Zolnierkiewicz 5 * 6 * based upon 7 * 8 * serverworks.c 9 * 10 * Copyright (C) 1998-2000 Michel Aubry 11 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz 12 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 13 * Portions copyright (c) 2001 Sun Microsystems 14 * 15 * 16 * RCC/ServerWorks IDE driver for Linux 17 * 18 * OSB4: `Open South Bridge' IDE Interface (fn 1) 19 * supports UDMA mode 2 (33 MB/s) 20 * 21 * CSB5: `Champion South Bridge' IDE Interface (fn 1) 22 * all revisions support UDMA mode 4 (66 MB/s) 23 * revision A2.0 and up support UDMA mode 5 (100 MB/s) 24 * 25 * *** The CSB5 does not provide ANY register *** 26 * *** to detect 80-conductor cable presence. *** 27 * 28 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel) 29 * 30 * Documentation: 31 * Available under NDA only. Errata info very hard to get. 32 */ 33 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/blkdev.h> 38 #include <linux/delay.h> 39 #include <scsi/scsi_host.h> 40 #include <linux/libata.h> 41 42 #define DRV_NAME "pata_serverworks" 43 #define DRV_VERSION "0.4.3" 44 45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */ 46 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */ 47 48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5 49 * can overrun their FIFOs when used with the CSB5 */ 50 51 static const char *csb_bad_ata100[] = { 52 "ST320011A", 53 "ST340016A", 54 "ST360021A", 55 "ST380021A", 56 NULL 57 }; 58 59 /** 60 * oem_cable - Dell/Sun serverworks cable detection 61 * @ap: ATA port to do cable detect 62 * 63 * Dell PowerEdge and Sun Cobalt 'Alpine' hide the 40/80 pin select 64 * for their interfaces in the top two bits of the subsystem ID. 65 */ 66 67 static int oem_cable(struct ata_port *ap) 68 { 69 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 70 71 if (pdev->subsystem_device & (1 << (ap->port_no + 14))) 72 return ATA_CBL_PATA80; 73 return ATA_CBL_PATA40; 74 } 75 76 struct sv_cable_table { 77 int device; 78 int subvendor; 79 int (*cable_detect)(struct ata_port *ap); 80 }; 81 82 static struct sv_cable_table cable_detect[] = { 83 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, oem_cable }, 84 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, oem_cable }, 85 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, oem_cable }, 86 { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, ata_cable_40wire }, 87 { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, ata_cable_unknown }, 88 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, ata_cable_unknown }, 89 { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, ata_cable_unknown }, 90 { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, ata_cable_unknown }, 91 { } 92 }; 93 94 /** 95 * serverworks_cable_detect - cable detection 96 * @ap: ATA port 97 * 98 * Perform cable detection according to the device and subvendor 99 * identifications 100 */ 101 102 static int serverworks_cable_detect(struct ata_port *ap) 103 { 104 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 105 struct sv_cable_table *cb = cable_detect; 106 107 while(cb->device) { 108 if (cb->device == pdev->device && 109 (cb->subvendor == pdev->subsystem_vendor || 110 cb->subvendor == PCI_ANY_ID)) { 111 return cb->cable_detect(ap); 112 } 113 cb++; 114 } 115 116 BUG(); 117 return -1; /* kill compiler warning */ 118 } 119 120 /** 121 * serverworks_is_csb - Check for CSB or OSB 122 * @pdev: PCI device to check 123 * 124 * Returns true if the device being checked is known to be a CSB 125 * series device. 126 */ 127 128 static u8 serverworks_is_csb(struct pci_dev *pdev) 129 { 130 switch (pdev->device) { 131 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 132 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 133 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 134 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: 135 return 1; 136 default: 137 break; 138 } 139 return 0; 140 } 141 142 /** 143 * serverworks_osb4_filter - mode selection filter 144 * @adev: ATA device 145 * @mask: Mask of proposed modes 146 * 147 * Filter the offered modes for the device to apply controller 148 * specific rules. OSB4 requires no UDMA for disks due to a FIFO 149 * bug we hit. 150 */ 151 152 static unsigned long serverworks_osb4_filter(struct ata_device *adev, unsigned long mask) 153 { 154 if (adev->class == ATA_DEV_ATA) 155 mask &= ~ATA_MASK_UDMA; 156 return mask; 157 } 158 159 160 /** 161 * serverworks_csb_filter - mode selection filter 162 * @adev: ATA device 163 * @mask: Mask of proposed modes 164 * 165 * Check the blacklist and disable UDMA5 if matched 166 */ 167 168 static unsigned long serverworks_csb_filter(struct ata_device *adev, unsigned long mask) 169 { 170 const char *p; 171 char model_num[ATA_ID_PROD_LEN + 1]; 172 int i; 173 174 /* Disk, UDMA */ 175 if (adev->class != ATA_DEV_ATA) 176 return mask; 177 178 /* Actually do need to check */ 179 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 180 181 for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) { 182 if (!strcmp(p, model_num)) 183 mask &= ~(0xE0 << ATA_SHIFT_UDMA); 184 } 185 return mask; 186 } 187 188 /** 189 * serverworks_set_piomode - set initial PIO mode data 190 * @ap: ATA interface 191 * @adev: ATA device 192 * 193 * Program the OSB4/CSB5 timing registers for PIO. The PIO register 194 * load is done as a simple lookup. 195 */ 196 static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev) 197 { 198 static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 199 int offset = 1 + 2 * ap->port_no - adev->devno; 200 int devbits = (2 * ap->port_no + adev->devno) * 4; 201 u16 csb5_pio; 202 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 203 int pio = adev->pio_mode - XFER_PIO_0; 204 205 pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]); 206 207 /* The OSB4 just requires the timing but the CSB series want the 208 mode number as well */ 209 if (serverworks_is_csb(pdev)) { 210 pci_read_config_word(pdev, 0x4A, &csb5_pio); 211 csb5_pio &= ~(0x0F << devbits); 212 pci_write_config_word(pdev, 0x4A, csb5_pio | (pio << devbits)); 213 } 214 } 215 216 /** 217 * serverworks_set_dmamode - set initial DMA mode data 218 * @ap: ATA interface 219 * @adev: ATA device 220 * 221 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5 222 * chipset. The MWDMA mode values are pulled from a lookup table 223 * while the chipset uses mode number for UDMA. 224 */ 225 226 static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev) 227 { 228 static const u8 dma_mode[] = { 0x77, 0x21, 0x20 }; 229 int offset = 1 + 2 * ap->port_no - adev->devno; 230 int devbits = 2 * ap->port_no + adev->devno; 231 u8 ultra; 232 u8 ultra_cfg; 233 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 234 235 pci_read_config_byte(pdev, 0x54, &ultra_cfg); 236 pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra); 237 ultra &= ~(0x0F << (adev->devno * 4)); 238 239 if (adev->dma_mode >= XFER_UDMA_0) { 240 pci_write_config_byte(pdev, 0x44 + offset, 0x20); 241 242 ultra |= (adev->dma_mode - XFER_UDMA_0) 243 << (adev->devno * 4); 244 ultra_cfg |= (1 << devbits); 245 } else { 246 pci_write_config_byte(pdev, 0x44 + offset, 247 dma_mode[adev->dma_mode - XFER_MW_DMA_0]); 248 ultra_cfg &= ~(1 << devbits); 249 } 250 pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra); 251 pci_write_config_byte(pdev, 0x54, ultra_cfg); 252 } 253 254 static struct scsi_host_template serverworks_sht = { 255 ATA_BMDMA_SHT(DRV_NAME), 256 }; 257 258 static struct ata_port_operations serverworks_osb4_port_ops = { 259 .inherits = &ata_bmdma_port_ops, 260 .cable_detect = serverworks_cable_detect, 261 .mode_filter = serverworks_osb4_filter, 262 .set_piomode = serverworks_set_piomode, 263 .set_dmamode = serverworks_set_dmamode, 264 }; 265 266 static struct ata_port_operations serverworks_csb_port_ops = { 267 .inherits = &serverworks_osb4_port_ops, 268 .mode_filter = serverworks_csb_filter, 269 }; 270 271 static int serverworks_fixup_osb4(struct pci_dev *pdev) 272 { 273 u32 reg; 274 struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 275 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL); 276 if (isa_dev) { 277 pci_read_config_dword(isa_dev, 0x64, ®); 278 reg &= ~0x00002000; /* disable 600ns interrupt mask */ 279 if (!(reg & 0x00004000)) 280 printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n"); 281 reg |= 0x00004000; /* enable UDMA/33 support */ 282 pci_write_config_dword(isa_dev, 0x64, reg); 283 pci_dev_put(isa_dev); 284 return 0; 285 } 286 printk(KERN_WARNING DRV_NAME ": Unable to find bridge.\n"); 287 return -ENODEV; 288 } 289 290 static int serverworks_fixup_csb(struct pci_dev *pdev) 291 { 292 u8 btr; 293 294 /* Third Channel Test */ 295 if (!(PCI_FUNC(pdev->devfn) & 1)) { 296 struct pci_dev * findev = NULL; 297 u32 reg4c = 0; 298 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 299 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL); 300 if (findev) { 301 pci_read_config_dword(findev, 0x4C, ®4c); 302 reg4c &= ~0x000007FF; 303 reg4c |= 0x00000040; 304 reg4c |= 0x00000020; 305 pci_write_config_dword(findev, 0x4C, reg4c); 306 pci_dev_put(findev); 307 } 308 } else { 309 struct pci_dev * findev = NULL; 310 u8 reg41 = 0; 311 312 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, 313 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL); 314 if (findev) { 315 pci_read_config_byte(findev, 0x41, ®41); 316 reg41 &= ~0x40; 317 pci_write_config_byte(findev, 0x41, reg41); 318 pci_dev_put(findev); 319 } 320 } 321 /* setup the UDMA Control register 322 * 323 * 1. clear bit 6 to enable DMA 324 * 2. enable DMA modes with bits 0-1 325 * 00 : legacy 326 * 01 : udma2 327 * 10 : udma2/udma4 328 * 11 : udma2/udma4/udma5 329 */ 330 pci_read_config_byte(pdev, 0x5A, &btr); 331 btr &= ~0x40; 332 if (!(PCI_FUNC(pdev->devfn) & 1)) 333 btr |= 0x2; 334 else 335 btr |= (pdev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2; 336 pci_write_config_byte(pdev, 0x5A, btr); 337 338 return btr; 339 } 340 341 static void serverworks_fixup_ht1000(struct pci_dev *pdev) 342 { 343 u8 btr; 344 /* Setup HT1000 SouthBridge Controller - Single Channel Only */ 345 pci_read_config_byte(pdev, 0x5A, &btr); 346 btr &= ~0x40; 347 btr |= 0x3; 348 pci_write_config_byte(pdev, 0x5A, btr); 349 } 350 351 static int serverworks_fixup(struct pci_dev *pdev) 352 { 353 int rc = 0; 354 355 /* Force master latency timer to 64 PCI clocks */ 356 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); 357 358 switch (pdev->device) { 359 case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE: 360 rc = serverworks_fixup_osb4(pdev); 361 break; 362 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE: 363 ata_pci_bmdma_clear_simplex(pdev); 364 /* fall through */ 365 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE: 366 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2: 367 rc = serverworks_fixup_csb(pdev); 368 break; 369 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE: 370 serverworks_fixup_ht1000(pdev); 371 break; 372 } 373 374 return rc; 375 } 376 377 static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 378 { 379 static const struct ata_port_info info[4] = { 380 { /* OSB4 */ 381 .flags = ATA_FLAG_SLAVE_POSS, 382 .pio_mask = ATA_PIO4, 383 .mwdma_mask = ATA_MWDMA2, 384 .udma_mask = ATA_UDMA2, 385 .port_ops = &serverworks_osb4_port_ops 386 }, { /* OSB4 no UDMA */ 387 .flags = ATA_FLAG_SLAVE_POSS, 388 .pio_mask = ATA_PIO4, 389 .mwdma_mask = ATA_MWDMA2, 390 /* No UDMA */ 391 .port_ops = &serverworks_osb4_port_ops 392 }, { /* CSB5 */ 393 .flags = ATA_FLAG_SLAVE_POSS, 394 .pio_mask = ATA_PIO4, 395 .mwdma_mask = ATA_MWDMA2, 396 .udma_mask = ATA_UDMA4, 397 .port_ops = &serverworks_csb_port_ops 398 }, { /* CSB5 - later revisions*/ 399 .flags = ATA_FLAG_SLAVE_POSS, 400 .pio_mask = ATA_PIO4, 401 .mwdma_mask = ATA_MWDMA2, 402 .udma_mask = ATA_UDMA5, 403 .port_ops = &serverworks_csb_port_ops 404 } 405 }; 406 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL }; 407 int rc; 408 409 rc = pcim_enable_device(pdev); 410 if (rc) 411 return rc; 412 413 rc = serverworks_fixup(pdev); 414 415 /* OSB4 : South Bridge and IDE */ 416 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) { 417 /* Select non UDMA capable OSB4 if we can't do fixups */ 418 if (rc < 0) 419 ppi[0] = &info[1]; 420 } 421 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */ 422 else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) || 423 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) || 424 (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) { 425 426 /* If the returned btr is the newer revision then 427 select the right info block */ 428 if (rc == 3) 429 ppi[0] = &info[3]; 430 431 /* Is this the 3rd channel CSB6 IDE ? */ 432 if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) 433 ppi[1] = &ata_dummy_port_info; 434 } 435 436 return ata_pci_bmdma_init_one(pdev, ppi, &serverworks_sht, NULL, 0); 437 } 438 439 #ifdef CONFIG_PM_SLEEP 440 static int serverworks_reinit_one(struct pci_dev *pdev) 441 { 442 struct ata_host *host = pci_get_drvdata(pdev); 443 int rc; 444 445 rc = ata_pci_device_do_resume(pdev); 446 if (rc) 447 return rc; 448 449 (void)serverworks_fixup(pdev); 450 451 ata_host_resume(host); 452 return 0; 453 } 454 #endif 455 456 static const struct pci_device_id serverworks[] = { 457 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0}, 458 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2}, 459 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2}, 460 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2}, 461 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2}, 462 463 { }, 464 }; 465 466 static struct pci_driver serverworks_pci_driver = { 467 .name = DRV_NAME, 468 .id_table = serverworks, 469 .probe = serverworks_init_one, 470 .remove = ata_pci_remove_one, 471 #ifdef CONFIG_PM_SLEEP 472 .suspend = ata_pci_device_suspend, 473 .resume = serverworks_reinit_one, 474 #endif 475 }; 476 477 module_pci_driver(serverworks_pci_driver); 478 479 MODULE_AUTHOR("Alan Cox"); 480 MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6"); 481 MODULE_LICENSE("GPL"); 482 MODULE_DEVICE_TABLE(pci, serverworks); 483 MODULE_VERSION(DRV_VERSION); 484