1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277. 4 * 5 * Ported to libata by: 6 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation 7 * 8 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> 9 * Portions Copyright (C) 1999 Promise Technology, Inc. 10 * 11 * Author: Frank Tiernan (frankt@promise.com) 12 * Released under terms of General Public License 13 * 14 * libata documentation is available via 'make {ps|pdf}docs', 15 * as Documentation/driver-api/libata.rst 16 * 17 * Hardware information only available under NDA. 18 */ 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <linux/device.h> 25 #include <linux/ktime.h> 26 #include <scsi/scsi.h> 27 #include <scsi/scsi_host.h> 28 #include <scsi/scsi_cmnd.h> 29 #include <linux/libata.h> 30 31 #define DRV_NAME "pata_pdc2027x" 32 #define DRV_VERSION "1.0" 33 #undef PDC_DEBUG 34 35 #ifdef PDC_DEBUG 36 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 37 #else 38 #define PDPRINTK(fmt, args...) 39 #endif 40 41 enum { 42 PDC_MMIO_BAR = 5, 43 44 PDC_UDMA_100 = 0, 45 PDC_UDMA_133 = 1, 46 47 PDC_100_MHZ = 100000000, 48 PDC_133_MHZ = 133333333, 49 50 PDC_SYS_CTL = 0x1100, 51 PDC_ATA_CTL = 0x1104, 52 PDC_GLOBAL_CTL = 0x1108, 53 PDC_CTCR0 = 0x110C, 54 PDC_CTCR1 = 0x1110, 55 PDC_BYTE_COUNT = 0x1120, 56 PDC_PLL_CTL = 0x1202, 57 }; 58 59 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 60 #ifdef CONFIG_PM_SLEEP 61 static int pdc2027x_reinit_one(struct pci_dev *pdev); 62 #endif 63 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline); 64 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev); 65 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev); 66 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc); 67 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask); 68 static int pdc2027x_cable_detect(struct ata_port *ap); 69 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed); 70 71 /* 72 * ATA Timing Tables based on 133MHz controller clock. 73 * These tables are only used when the controller is in 133MHz clock. 74 * If the controller is in 100MHz clock, the ASIC hardware will 75 * set the timing registers automatically when "set feature" command 76 * is issued to the device. However, if the controller clock is 133MHz, 77 * the following tables must be used. 78 */ 79 static const struct pdc2027x_pio_timing { 80 u8 value0, value1, value2; 81 } pdc2027x_pio_timing_tbl[] = { 82 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */ 83 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */ 84 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */ 85 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */ 86 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */ 87 }; 88 89 static const struct pdc2027x_mdma_timing { 90 u8 value0, value1; 91 } pdc2027x_mdma_timing_tbl[] = { 92 { 0xdf, 0x5f }, /* MDMA mode 0 */ 93 { 0x6b, 0x27 }, /* MDMA mode 1 */ 94 { 0x69, 0x25 }, /* MDMA mode 2 */ 95 }; 96 97 static const struct pdc2027x_udma_timing { 98 u8 value0, value1, value2; 99 } pdc2027x_udma_timing_tbl[] = { 100 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */ 101 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */ 102 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */ 103 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */ 104 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */ 105 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */ 106 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ 107 }; 108 109 static const struct pci_device_id pdc2027x_pci_tbl[] = { 110 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 }, 111 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 }, 112 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 }, 113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 }, 114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 }, 115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 }, 116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 }, 117 118 { } /* terminate list */ 119 }; 120 121 static struct pci_driver pdc2027x_pci_driver = { 122 .name = DRV_NAME, 123 .id_table = pdc2027x_pci_tbl, 124 .probe = pdc2027x_init_one, 125 .remove = ata_pci_remove_one, 126 #ifdef CONFIG_PM_SLEEP 127 .suspend = ata_pci_device_suspend, 128 .resume = pdc2027x_reinit_one, 129 #endif 130 }; 131 132 static struct scsi_host_template pdc2027x_sht = { 133 ATA_BMDMA_SHT(DRV_NAME), 134 }; 135 136 static struct ata_port_operations pdc2027x_pata100_ops = { 137 .inherits = &ata_bmdma_port_ops, 138 .check_atapi_dma = pdc2027x_check_atapi_dma, 139 .cable_detect = pdc2027x_cable_detect, 140 .prereset = pdc2027x_prereset, 141 }; 142 143 static struct ata_port_operations pdc2027x_pata133_ops = { 144 .inherits = &pdc2027x_pata100_ops, 145 .mode_filter = pdc2027x_mode_filter, 146 .set_piomode = pdc2027x_set_piomode, 147 .set_dmamode = pdc2027x_set_dmamode, 148 .set_mode = pdc2027x_set_mode, 149 }; 150 151 static struct ata_port_info pdc2027x_port_info[] = { 152 /* PDC_UDMA_100 */ 153 { 154 .flags = ATA_FLAG_SLAVE_POSS, 155 .pio_mask = ATA_PIO4, 156 .mwdma_mask = ATA_MWDMA2, 157 .udma_mask = ATA_UDMA5, 158 .port_ops = &pdc2027x_pata100_ops, 159 }, 160 /* PDC_UDMA_133 */ 161 { 162 .flags = ATA_FLAG_SLAVE_POSS, 163 .pio_mask = ATA_PIO4, 164 .mwdma_mask = ATA_MWDMA2, 165 .udma_mask = ATA_UDMA6, 166 .port_ops = &pdc2027x_pata133_ops, 167 }, 168 }; 169 170 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee"); 171 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277"); 172 MODULE_LICENSE("GPL"); 173 MODULE_VERSION(DRV_VERSION); 174 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl); 175 176 /** 177 * port_mmio - Get the MMIO address of PDC2027x extended registers 178 * @ap: Port 179 * @offset: offset from mmio base 180 */ 181 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) 182 { 183 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset; 184 } 185 186 /** 187 * dev_mmio - Get the MMIO address of PDC2027x extended registers 188 * @ap: Port 189 * @adev: device 190 * @offset: offset from mmio base 191 */ 192 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset) 193 { 194 u8 adj = (adev->devno) ? 0x08 : 0x00; 195 return port_mmio(ap, offset) + adj; 196 } 197 198 /** 199 * pdc2027x_pata_cable_detect - Probe host controller cable detect info 200 * @ap: Port for which cable detect info is desired 201 * 202 * Read 80c cable indicator from Promise extended register. 203 * This register is latched when the system is reset. 204 * 205 * LOCKING: 206 * None (inherited from caller). 207 */ 208 static int pdc2027x_cable_detect(struct ata_port *ap) 209 { 210 u32 cgcr; 211 212 /* check cable detect results */ 213 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL)); 214 if (cgcr & (1 << 26)) 215 goto cbl40; 216 217 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no); 218 219 return ATA_CBL_PATA80; 220 cbl40: 221 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no); 222 return ATA_CBL_PATA40; 223 } 224 225 /** 226 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled. 227 * @ap: Port to check 228 */ 229 static inline int pdc2027x_port_enabled(struct ata_port *ap) 230 { 231 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02; 232 } 233 234 /** 235 * pdc2027x_prereset - prereset for PATA host controller 236 * @link: Target link 237 * @deadline: deadline jiffies for the operation 238 * 239 * Probeinit including cable detection. 240 * 241 * LOCKING: 242 * None (inherited from caller). 243 */ 244 245 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline) 246 { 247 /* Check whether port enabled */ 248 if (!pdc2027x_port_enabled(link->ap)) 249 return -ENOENT; 250 return ata_sff_prereset(link, deadline); 251 } 252 253 /** 254 * pdc2720x_mode_filter - mode selection filter 255 * @adev: ATA device 256 * @mask: list of modes proposed 257 * 258 * Block UDMA on devices that cause trouble with this controller. 259 */ 260 261 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask) 262 { 263 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 264 struct ata_device *pair = ata_dev_pair(adev); 265 266 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL) 267 return mask; 268 269 /* Check for slave of a Maxtor at UDMA6 */ 270 ata_id_c_string(pair->id, model_num, ATA_ID_PROD, 271 ATA_ID_PROD_LEN + 1); 272 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */ 273 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6) 274 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA)); 275 276 return mask; 277 } 278 279 /** 280 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings 281 * @ap: Port to configure 282 * @adev: um 283 * 284 * Set PIO mode for device. 285 * 286 * LOCKING: 287 * None (inherited from caller). 288 */ 289 290 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev) 291 { 292 unsigned int pio = adev->pio_mode - XFER_PIO_0; 293 u32 ctcr0, ctcr1; 294 295 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode); 296 297 /* Sanity check */ 298 if (pio > 4) { 299 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio); 300 return; 301 302 } 303 304 /* Set the PIO timing registers using value table for 133MHz */ 305 PDPRINTK("Set pio regs... \n"); 306 307 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); 308 ctcr0 &= 0xffff0000; 309 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 | 310 (pdc2027x_pio_timing_tbl[pio].value1 << 8); 311 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); 312 313 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 314 ctcr1 &= 0x00ffffff; 315 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24); 316 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); 317 318 PDPRINTK("Set pio regs done\n"); 319 320 PDPRINTK("Set to pio mode[%u] \n", pio); 321 } 322 323 /** 324 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings 325 * @ap: Port to configure 326 * @adev: um 327 * 328 * Set UDMA mode for device. 329 * 330 * LOCKING: 331 * None (inherited from caller). 332 */ 333 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 334 { 335 unsigned int dma_mode = adev->dma_mode; 336 u32 ctcr0, ctcr1; 337 338 if ((dma_mode >= XFER_UDMA_0) && 339 (dma_mode <= XFER_UDMA_6)) { 340 /* Set the UDMA timing registers with value table for 133MHz */ 341 unsigned int udma_mode = dma_mode & 0x07; 342 343 if (dma_mode == XFER_UDMA_2) { 344 /* 345 * Turn off tHOLD. 346 * If tHOLD is '1', the hardware will add half clock for data hold time. 347 * This code segment seems to be no effect. tHOLD will be overwritten below. 348 */ 349 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 350 iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1)); 351 } 352 353 PDPRINTK("Set udma regs... \n"); 354 355 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1)); 356 ctcr1 &= 0xff000000; 357 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 | 358 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) | 359 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16); 360 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1)); 361 362 PDPRINTK("Set udma regs done\n"); 363 364 PDPRINTK("Set to udma mode[%u] \n", udma_mode); 365 366 } else if ((dma_mode >= XFER_MW_DMA_0) && 367 (dma_mode <= XFER_MW_DMA_2)) { 368 /* Set the MDMA timing registers with value table for 133MHz */ 369 unsigned int mdma_mode = dma_mode & 0x07; 370 371 PDPRINTK("Set mdma regs... \n"); 372 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0)); 373 374 ctcr0 &= 0x0000ffff; 375 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) | 376 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24); 377 378 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0)); 379 PDPRINTK("Set mdma regs done\n"); 380 381 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode); 382 } else { 383 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode); 384 } 385 } 386 387 /** 388 * pdc2027x_set_mode - Set the timing registers back to correct values. 389 * @link: link to configure 390 * @r_failed: Returned device for failure 391 * 392 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers 393 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL. 394 * This function overwrites the possibly incorrect values set by the hardware to be correct. 395 */ 396 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed) 397 { 398 struct ata_port *ap = link->ap; 399 struct ata_device *dev; 400 int rc; 401 402 rc = ata_do_set_mode(link, r_failed); 403 if (rc < 0) 404 return rc; 405 406 ata_for_each_dev(dev, link, ENABLED) { 407 pdc2027x_set_piomode(ap, dev); 408 409 /* 410 * Enable prefetch if the device support PIO only. 411 */ 412 if (dev->xfer_shift == ATA_SHIFT_PIO) { 413 u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1)); 414 ctcr1 |= (1 << 25); 415 iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1)); 416 417 PDPRINTK("Turn on prefetch\n"); 418 } else { 419 pdc2027x_set_dmamode(ap, dev); 420 } 421 } 422 return 0; 423 } 424 425 /** 426 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command 427 * @qc: Metadata associated with taskfile to check 428 * 429 * LOCKING: 430 * None (inherited from caller). 431 * 432 * RETURNS: 0 when ATAPI DMA can be used 433 * 1 otherwise 434 */ 435 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc) 436 { 437 struct scsi_cmnd *cmd = qc->scsicmd; 438 u8 *scsicmd = cmd->cmnd; 439 int rc = 1; /* atapi dma off by default */ 440 441 /* 442 * This workaround is from Promise's GPL driver. 443 * If ATAPI DMA is used for commands not in the 444 * following white list, say MODE_SENSE and REQUEST_SENSE, 445 * pdc2027x might hit the irq lost problem. 446 */ 447 switch (scsicmd[0]) { 448 case READ_10: 449 case WRITE_10: 450 case READ_12: 451 case WRITE_12: 452 case READ_6: 453 case WRITE_6: 454 case 0xad: /* READ_DVD_STRUCTURE */ 455 case 0xbe: /* READ_CD */ 456 /* ATAPI DMA is ok */ 457 rc = 0; 458 break; 459 default: 460 ; 461 } 462 463 return rc; 464 } 465 466 /** 467 * pdc_read_counter - Read the ctr counter 468 * @host: target ATA host 469 */ 470 471 static long pdc_read_counter(struct ata_host *host) 472 { 473 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 474 long counter; 475 int retry = 1; 476 u32 bccrl, bccrh, bccrlv, bccrhv; 477 478 retry: 479 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 480 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 481 482 /* Read the counter values again for verification */ 483 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 484 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 485 486 counter = (bccrh << 15) | bccrl; 487 488 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl); 489 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv); 490 491 /* 492 * The 30-bit decreasing counter are read by 2 pieces. 493 * Incorrect value may be read when both bccrh and bccrl are changing. 494 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read. 495 */ 496 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) { 497 retry--; 498 PDPRINTK("rereading counter\n"); 499 goto retry; 500 } 501 502 return counter; 503 } 504 505 /** 506 * adjust_pll - Adjust the PLL input clock in Hz. 507 * 508 * @pdc_controller: controller specific information 509 * @host: target ATA host 510 * @pll_clock: The input of PLL in HZ 511 */ 512 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx) 513 { 514 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 515 u16 pll_ctl; 516 long pll_clock_khz = pll_clock / 1000; 517 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ; 518 long ratio = pout_required / pll_clock_khz; 519 int F, R; 520 521 /* Sanity check */ 522 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) { 523 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz); 524 return; 525 } 526 527 #ifdef PDC_DEBUG 528 PDPRINTK("pout_required is %ld\n", pout_required); 529 530 /* Show the current clock value of PLL control register 531 * (maybe already configured by the firmware) 532 */ 533 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); 534 535 PDPRINTK("pll_ctl[%X]\n", pll_ctl); 536 #endif 537 538 /* 539 * Calculate the ratio of F, R and OD 540 * POUT = (F + 2) / (( R + 2) * NO) 541 */ 542 if (ratio < 8600L) { /* 8.6x */ 543 /* Using NO = 0x01, R = 0x0D */ 544 R = 0x0d; 545 } else if (ratio < 12900L) { /* 12.9x */ 546 /* Using NO = 0x01, R = 0x08 */ 547 R = 0x08; 548 } else if (ratio < 16100L) { /* 16.1x */ 549 /* Using NO = 0x01, R = 0x06 */ 550 R = 0x06; 551 } else if (ratio < 64000L) { /* 64x */ 552 R = 0x00; 553 } else { 554 /* Invalid ratio */ 555 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio); 556 return; 557 } 558 559 F = (ratio * (R+2)) / 1000 - 2; 560 561 if (unlikely(F < 0 || F > 127)) { 562 /* Invalid F */ 563 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F); 564 return; 565 } 566 567 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); 568 569 pll_ctl = (R << 8) | F; 570 571 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl); 572 573 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); 574 ioread16(mmio_base + PDC_PLL_CTL); /* flush */ 575 576 /* Wait the PLL circuit to be stable */ 577 msleep(30); 578 579 #ifdef PDC_DEBUG 580 /* 581 * Show the current clock value of PLL control register 582 * (maybe configured by the firmware) 583 */ 584 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); 585 586 PDPRINTK("pll_ctl[%X]\n", pll_ctl); 587 #endif 588 589 return; 590 } 591 592 /** 593 * detect_pll_input_clock - Detect the PLL input clock in Hz. 594 * @host: target ATA host 595 * Ex. 16949000 on 33MHz PCI bus for pdc20275. 596 * Half of the PCI clock. 597 */ 598 static long pdc_detect_pll_input_clock(struct ata_host *host) 599 { 600 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; 601 u32 scr; 602 long start_count, end_count; 603 ktime_t start_time, end_time; 604 long pll_clock, usec_elapsed; 605 606 /* Start the test mode */ 607 scr = ioread32(mmio_base + PDC_SYS_CTL); 608 PDPRINTK("scr[%X]\n", scr); 609 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL); 610 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ 611 612 /* Read current counter value */ 613 start_count = pdc_read_counter(host); 614 start_time = ktime_get(); 615 616 /* Let the counter run for 100 ms. */ 617 msleep(100); 618 619 /* Read the counter values again */ 620 end_count = pdc_read_counter(host); 621 end_time = ktime_get(); 622 623 /* Stop the test mode */ 624 scr = ioread32(mmio_base + PDC_SYS_CTL); 625 PDPRINTK("scr[%X]\n", scr); 626 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL); 627 ioread32(mmio_base + PDC_SYS_CTL); /* flush */ 628 629 /* calculate the input clock in Hz */ 630 usec_elapsed = (long) ktime_us_delta(end_time, start_time); 631 632 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 * 633 (100000000 / usec_elapsed); 634 635 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count); 636 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock); 637 638 return pll_clock; 639 } 640 641 /** 642 * pdc_hardware_init - Initialize the hardware. 643 * @host: target ATA host 644 * @board_idx: board identifier 645 */ 646 static void pdc_hardware_init(struct ata_host *host, unsigned int board_idx) 647 { 648 long pll_clock; 649 650 /* 651 * Detect PLL input clock rate. 652 * On some system, where PCI bus is running at non-standard clock rate. 653 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time. 654 * The pdc20275 controller employs PLL circuit to help correct timing registers setting. 655 */ 656 pll_clock = pdc_detect_pll_input_clock(host); 657 658 dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000); 659 660 /* Adjust PLL control register */ 661 pdc_adjust_pll(host, pll_clock, board_idx); 662 } 663 664 /** 665 * pdc_ata_setup_port - setup the mmio address 666 * @port: ata ioports to setup 667 * @base: base address 668 */ 669 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base) 670 { 671 port->cmd_addr = 672 port->data_addr = base; 673 port->feature_addr = 674 port->error_addr = base + 0x05; 675 port->nsect_addr = base + 0x0a; 676 port->lbal_addr = base + 0x0f; 677 port->lbam_addr = base + 0x10; 678 port->lbah_addr = base + 0x15; 679 port->device_addr = base + 0x1a; 680 port->command_addr = 681 port->status_addr = base + 0x1f; 682 port->altstatus_addr = 683 port->ctl_addr = base + 0x81a; 684 } 685 686 /** 687 * pdc2027x_init_one - PCI probe function 688 * Called when an instance of PCI adapter is inserted. 689 * This function checks whether the hardware is supported, 690 * initialize hardware and register an instance of ata_host to 691 * libata. (implements struct pci_driver.probe() ) 692 * 693 * @pdev: instance of pci_dev found 694 * @ent: matching entry in the id_tbl[] 695 */ 696 static int pdc2027x_init_one(struct pci_dev *pdev, 697 const struct pci_device_id *ent) 698 { 699 static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 }; 700 static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 }; 701 unsigned int board_idx = (unsigned int) ent->driver_data; 702 const struct ata_port_info *ppi[] = 703 { &pdc2027x_port_info[board_idx], NULL }; 704 struct ata_host *host; 705 void __iomem *mmio_base; 706 int i, rc; 707 708 ata_print_version_once(&pdev->dev, DRV_VERSION); 709 710 /* alloc host */ 711 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 712 if (!host) 713 return -ENOMEM; 714 715 /* acquire resources and fill host */ 716 rc = pcim_enable_device(pdev); 717 if (rc) 718 return rc; 719 720 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); 721 if (rc) 722 return rc; 723 host->iomap = pcim_iomap_table(pdev); 724 725 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); 726 if (rc) 727 return rc; 728 729 mmio_base = host->iomap[PDC_MMIO_BAR]; 730 731 for (i = 0; i < 2; i++) { 732 struct ata_port *ap = host->ports[i]; 733 734 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]); 735 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i]; 736 737 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); 738 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd"); 739 } 740 741 //pci_enable_intx(pdev); 742 743 /* initialize adapter */ 744 pdc_hardware_init(host, board_idx); 745 746 pci_set_master(pdev); 747 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 748 IRQF_SHARED, &pdc2027x_sht); 749 } 750 751 #ifdef CONFIG_PM_SLEEP 752 static int pdc2027x_reinit_one(struct pci_dev *pdev) 753 { 754 struct ata_host *host = pci_get_drvdata(pdev); 755 unsigned int board_idx; 756 int rc; 757 758 rc = ata_pci_device_do_resume(pdev); 759 if (rc) 760 return rc; 761 762 if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 || 763 pdev->device == PCI_DEVICE_ID_PROMISE_20270) 764 board_idx = PDC_UDMA_100; 765 else 766 board_idx = PDC_UDMA_133; 767 768 pdc_hardware_init(host, board_idx); 769 770 ata_host_resume(host); 771 return 0; 772 } 773 #endif 774 775 module_pci_driver(pdc2027x_pci_driver); 776