1 /* 2 * pata_optidma.c - Opti DMA PATA for new ATA layer 3 * (C) 2006 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * The Opti DMA controllers are related to the older PIO PCI controllers 7 * and indeed the VLB ones. The main differences are that the timing 8 * numbers are now based off PCI clocks not VLB and differ, and that 9 * MWDMA is supported. 10 * 11 * This driver should support Viper-N+, FireStar, FireStar Plus. 12 * 13 * These devices support virtual DMA for read (aka the CS5520). Later 14 * chips support UDMA33, but only if the rest of the board logic does, 15 * so you have to get this right. We don't support the virtual DMA 16 * but we do handle UDMA. 17 * 18 * Bits that are worth knowing 19 * Most control registers are shadowed into I/O registers 20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz 21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10 22 * UDMA requires a 66MHz FSB 23 * 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include <linux/init.h> 30 #include <linux/blkdev.h> 31 #include <linux/delay.h> 32 #include <scsi/scsi_host.h> 33 #include <linux/libata.h> 34 35 #define DRV_NAME "pata_optidma" 36 #define DRV_VERSION "0.2.4" 37 38 enum { 39 READ_REG = 0, /* index of Read cycle timing register */ 40 WRITE_REG = 1, /* index of Write cycle timing register */ 41 CNTRL_REG = 3, /* index of Control register */ 42 STRAP_REG = 5, /* index of Strap register */ 43 MISC_REG = 6 /* index of Miscellaneous register */ 44 }; 45 46 static int pci_clock; /* 0 = 33 1 = 25 */ 47 48 /** 49 * optidma_pre_reset - probe begin 50 * @ap: ATA port 51 * 52 * Set up cable type and use generic probe init 53 */ 54 55 static int optidma_pre_reset(struct ata_port *ap) 56 { 57 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 58 static const struct pci_bits optidma_enable_bits = { 59 0x40, 1, 0x08, 0x00 60 }; 61 62 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits)) 63 return -ENOENT; 64 65 ap->cbl = ATA_CBL_PATA40; 66 return ata_std_prereset(ap); 67 } 68 69 /** 70 * optidma_probe_reset - probe reset 71 * @ap: ATA port 72 * 73 * Perform the ATA probe and bus reset sequence plus specific handling 74 * for this hardware. The Opti needs little handling - we have no UDMA66 75 * capability that needs cable detection. All we must do is check the port 76 * is enabled. 77 */ 78 79 static void optidma_error_handler(struct ata_port *ap) 80 { 81 ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 82 } 83 84 /** 85 * optidma_unlock - unlock control registers 86 * @ap: ATA port 87 * 88 * Unlock the control register block for this adapter. Registers must not 89 * be unlocked in a situation where libata might look at them. 90 */ 91 92 static void optidma_unlock(struct ata_port *ap) 93 { 94 void __iomem *regio = ap->ioaddr.cmd_addr; 95 96 /* These 3 unlock the control register access */ 97 ioread16(regio + 1); 98 ioread16(regio + 1); 99 iowrite8(3, regio + 2); 100 } 101 102 /** 103 * optidma_lock - issue temporary relock 104 * @ap: ATA port 105 * 106 * Re-lock the configuration register settings. 107 */ 108 109 static void optidma_lock(struct ata_port *ap) 110 { 111 void __iomem *regio = ap->ioaddr.cmd_addr; 112 113 /* Relock */ 114 iowrite8(0x83, regio + 2); 115 } 116 117 /** 118 * optidma_set_mode - set mode data 119 * @ap: ATA interface 120 * @adev: ATA device 121 * @mode: Mode to set 122 * 123 * Called to do the DMA or PIO mode setup. Timing numbers are all 124 * pre computed to keep the code clean. There are two tables depending 125 * on the hardware clock speed. 126 * 127 * WARNING: While we do this the IDE registers vanish. If we take an 128 * IRQ here we depend on the host set locking to avoid catastrophe. 129 */ 130 131 static void optidma_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) 132 { 133 struct ata_device *pair = ata_dev_pair(adev); 134 int pio = adev->pio_mode - XFER_PIO_0; 135 int dma = adev->dma_mode - XFER_MW_DMA_0; 136 void __iomem *regio = ap->ioaddr.cmd_addr; 137 u8 addr; 138 139 /* Address table precomputed with a DCLK of 2 */ 140 static const u8 addr_timing[2][5] = { 141 { 0x30, 0x20, 0x20, 0x10, 0x10 }, 142 { 0x20, 0x20, 0x10, 0x10, 0x10 } 143 }; 144 static const u8 data_rec_timing[2][5] = { 145 { 0x59, 0x46, 0x30, 0x20, 0x20 }, 146 { 0x46, 0x32, 0x20, 0x20, 0x10 } 147 }; 148 static const u8 dma_data_rec_timing[2][3] = { 149 { 0x76, 0x20, 0x20 }, 150 { 0x54, 0x20, 0x10 } 151 }; 152 153 /* Switch from IDE to control mode */ 154 optidma_unlock(ap); 155 156 157 /* 158 * As with many controllers the address setup time is shared 159 * and must suit both devices if present. FIXME: Check if we 160 * need to look at slowest of PIO/DMA mode of either device 161 */ 162 163 if (mode >= XFER_MW_DMA_0) 164 addr = 0; 165 else 166 addr = addr_timing[pci_clock][pio]; 167 168 if (pair) { 169 u8 pair_addr; 170 /* Hardware constraint */ 171 if (pair->dma_mode) 172 pair_addr = 0; 173 else 174 pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0]; 175 if (pair_addr > addr) 176 addr = pair_addr; 177 } 178 179 /* Commence primary programming sequence */ 180 /* First we load the device number into the timing select */ 181 iowrite8(adev->devno, regio + MISC_REG); 182 /* Now we load the data timings into read data/write data */ 183 if (mode < XFER_MW_DMA_0) { 184 iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG); 185 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG); 186 } else if (mode < XFER_UDMA_0) { 187 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG); 188 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG); 189 } 190 /* Finally we load the address setup into the misc register */ 191 iowrite8(addr | adev->devno, regio + MISC_REG); 192 193 /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */ 194 iowrite8(0x85, regio + CNTRL_REG); 195 196 /* Switch back to IDE mode */ 197 optidma_lock(ap); 198 199 /* Note: at this point our programming is incomplete. We are 200 not supposed to program PCI 0x43 "things we hacked onto the chip" 201 until we've done both sets of PIO/DMA timings */ 202 } 203 204 /** 205 * optiplus_set_mode - DMA setup for Firestar Plus 206 * @ap: ATA port 207 * @adev: device 208 * @mode: desired mode 209 * 210 * The Firestar plus has additional UDMA functionality for UDMA0-2 and 211 * requires we do some additional work. Because the base work we must do 212 * is mostly shared we wrap the Firestar setup functionality in this 213 * one 214 */ 215 216 static void optiplus_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) 217 { 218 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 219 u8 udcfg; 220 u8 udslave; 221 int dev2 = 2 * adev->devno; 222 int unit = 2 * ap->port_no + adev->devno; 223 int udma = mode - XFER_UDMA_0; 224 225 pci_read_config_byte(pdev, 0x44, &udcfg); 226 if (mode <= XFER_UDMA_0) { 227 udcfg &= ~(1 << unit); 228 optidma_set_mode(ap, adev, adev->dma_mode); 229 } else { 230 udcfg |= (1 << unit); 231 if (ap->port_no) { 232 pci_read_config_byte(pdev, 0x45, &udslave); 233 udslave &= ~(0x03 << dev2); 234 udslave |= (udma << dev2); 235 pci_write_config_byte(pdev, 0x45, udslave); 236 } else { 237 udcfg &= ~(0x30 << dev2); 238 udcfg |= (udma << dev2); 239 } 240 } 241 pci_write_config_byte(pdev, 0x44, udcfg); 242 } 243 244 /** 245 * optidma_set_pio_mode - PIO setup callback 246 * @ap: ATA port 247 * @adev: Device 248 * 249 * The libata core provides separate functions for handling PIO and 250 * DMA programming. The architecture of the Firestar makes it easier 251 * for us to have a common function so we provide wrappers 252 */ 253 254 static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev) 255 { 256 optidma_set_mode(ap, adev, adev->pio_mode); 257 } 258 259 /** 260 * optidma_set_dma_mode - DMA setup callback 261 * @ap: ATA port 262 * @adev: Device 263 * 264 * The libata core provides separate functions for handling PIO and 265 * DMA programming. The architecture of the Firestar makes it easier 266 * for us to have a common function so we provide wrappers 267 */ 268 269 static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev) 270 { 271 optidma_set_mode(ap, adev, adev->dma_mode); 272 } 273 274 /** 275 * optiplus_set_pio_mode - PIO setup callback 276 * @ap: ATA port 277 * @adev: Device 278 * 279 * The libata core provides separate functions for handling PIO and 280 * DMA programming. The architecture of the Firestar makes it easier 281 * for us to have a common function so we provide wrappers 282 */ 283 284 static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev) 285 { 286 optiplus_set_mode(ap, adev, adev->pio_mode); 287 } 288 289 /** 290 * optiplus_set_dma_mode - DMA setup callback 291 * @ap: ATA port 292 * @adev: Device 293 * 294 * The libata core provides separate functions for handling PIO and 295 * DMA programming. The architecture of the Firestar makes it easier 296 * for us to have a common function so we provide wrappers 297 */ 298 299 static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev) 300 { 301 optiplus_set_mode(ap, adev, adev->dma_mode); 302 } 303 304 /** 305 * optidma_make_bits - PCI setup helper 306 * @adev: ATA device 307 * 308 * Turn the ATA device setup into PCI configuration bits 309 * for register 0x43 and return the two bits needed. 310 */ 311 312 static u8 optidma_make_bits43(struct ata_device *adev) 313 { 314 static const u8 bits43[5] = { 315 0, 0, 0, 1, 2 316 }; 317 if (!ata_dev_enabled(adev)) 318 return 0; 319 if (adev->dma_mode) 320 return adev->dma_mode - XFER_MW_DMA_0; 321 return bits43[adev->pio_mode - XFER_PIO_0]; 322 } 323 324 /** 325 * optidma_post_set_mode - finalize PCI setup 326 * @ap: port to set up 327 * 328 * Finalise the configuration by writing the nibble of extra bits 329 * of data into the chip. 330 */ 331 332 static void optidma_post_set_mode(struct ata_port *ap) 333 { 334 u8 r; 335 int nybble = 4 * ap->port_no; 336 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 337 338 pci_read_config_byte(pdev, 0x43, &r); 339 340 r &= (0x0F << nybble); 341 r |= (optidma_make_bits43(&ap->device[0]) + 342 (optidma_make_bits43(&ap->device[0]) << 2)) << nybble; 343 344 pci_write_config_byte(pdev, 0x43, r); 345 } 346 347 static struct scsi_host_template optidma_sht = { 348 .module = THIS_MODULE, 349 .name = DRV_NAME, 350 .ioctl = ata_scsi_ioctl, 351 .queuecommand = ata_scsi_queuecmd, 352 .can_queue = ATA_DEF_QUEUE, 353 .this_id = ATA_SHT_THIS_ID, 354 .sg_tablesize = LIBATA_MAX_PRD, 355 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 356 .emulated = ATA_SHT_EMULATED, 357 .use_clustering = ATA_SHT_USE_CLUSTERING, 358 .proc_name = DRV_NAME, 359 .dma_boundary = ATA_DMA_BOUNDARY, 360 .slave_configure = ata_scsi_slave_config, 361 .slave_destroy = ata_scsi_slave_destroy, 362 .bios_param = ata_std_bios_param, 363 #ifdef CONFIG_PM 364 .resume = ata_scsi_device_resume, 365 .suspend = ata_scsi_device_suspend, 366 #endif 367 }; 368 369 static struct ata_port_operations optidma_port_ops = { 370 .port_disable = ata_port_disable, 371 .set_piomode = optidma_set_pio_mode, 372 .set_dmamode = optidma_set_dma_mode, 373 374 .tf_load = ata_tf_load, 375 .tf_read = ata_tf_read, 376 .check_status = ata_check_status, 377 .exec_command = ata_exec_command, 378 .dev_select = ata_std_dev_select, 379 380 .freeze = ata_bmdma_freeze, 381 .thaw = ata_bmdma_thaw, 382 .post_internal_cmd = ata_bmdma_post_internal_cmd, 383 .error_handler = optidma_error_handler, 384 .post_set_mode = optidma_post_set_mode, 385 386 .bmdma_setup = ata_bmdma_setup, 387 .bmdma_start = ata_bmdma_start, 388 .bmdma_stop = ata_bmdma_stop, 389 .bmdma_status = ata_bmdma_status, 390 391 .qc_prep = ata_qc_prep, 392 .qc_issue = ata_qc_issue_prot, 393 394 .data_xfer = ata_data_xfer, 395 396 .irq_handler = ata_interrupt, 397 .irq_clear = ata_bmdma_irq_clear, 398 .irq_on = ata_irq_on, 399 .irq_ack = ata_irq_ack, 400 401 .port_start = ata_port_start, 402 }; 403 404 static struct ata_port_operations optiplus_port_ops = { 405 .port_disable = ata_port_disable, 406 .set_piomode = optiplus_set_pio_mode, 407 .set_dmamode = optiplus_set_dma_mode, 408 409 .tf_load = ata_tf_load, 410 .tf_read = ata_tf_read, 411 .check_status = ata_check_status, 412 .exec_command = ata_exec_command, 413 .dev_select = ata_std_dev_select, 414 415 .freeze = ata_bmdma_freeze, 416 .thaw = ata_bmdma_thaw, 417 .post_internal_cmd = ata_bmdma_post_internal_cmd, 418 .error_handler = optidma_error_handler, 419 .post_set_mode = optidma_post_set_mode, 420 421 .bmdma_setup = ata_bmdma_setup, 422 .bmdma_start = ata_bmdma_start, 423 .bmdma_stop = ata_bmdma_stop, 424 .bmdma_status = ata_bmdma_status, 425 426 .qc_prep = ata_qc_prep, 427 .qc_issue = ata_qc_issue_prot, 428 429 .data_xfer = ata_data_xfer, 430 431 .irq_handler = ata_interrupt, 432 .irq_clear = ata_bmdma_irq_clear, 433 .irq_on = ata_irq_on, 434 .irq_ack = ata_irq_ack, 435 436 .port_start = ata_port_start, 437 }; 438 439 /** 440 * optiplus_with_udma - Look for UDMA capable setup 441 * @pdev; ATA controller 442 */ 443 444 static int optiplus_with_udma(struct pci_dev *pdev) 445 { 446 u8 r; 447 int ret = 0; 448 int ioport = 0x22; 449 struct pci_dev *dev1; 450 451 /* Find function 1 */ 452 dev1 = pci_get_device(0x1045, 0xC701, NULL); 453 if(dev1 == NULL) 454 return 0; 455 456 /* Rev must be >= 0x10 */ 457 pci_read_config_byte(dev1, 0x08, &r); 458 if (r < 0x10) 459 goto done_nomsg; 460 /* Read the chipset system configuration to check our mode */ 461 pci_read_config_byte(dev1, 0x5F, &r); 462 ioport |= (r << 8); 463 outb(0x10, ioport); 464 /* Must be 66Mhz sync */ 465 if ((inb(ioport + 2) & 1) == 0) 466 goto done; 467 468 /* Check the ATA arbitration/timing is suitable */ 469 pci_read_config_byte(pdev, 0x42, &r); 470 if ((r & 0x36) != 0x36) 471 goto done; 472 pci_read_config_byte(dev1, 0x52, &r); 473 if (r & 0x80) /* IDEDIR disabled */ 474 ret = 1; 475 done: 476 printk(KERN_WARNING "UDMA not supported in this configuration.\n"); 477 done_nomsg: /* Wrong chip revision */ 478 pci_dev_put(dev1); 479 return ret; 480 } 481 482 static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id) 483 { 484 static struct ata_port_info info_82c700 = { 485 .sht = &optidma_sht, 486 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 487 .pio_mask = 0x1f, 488 .mwdma_mask = 0x07, 489 .port_ops = &optidma_port_ops 490 }; 491 static struct ata_port_info info_82c700_udma = { 492 .sht = &optidma_sht, 493 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 494 .pio_mask = 0x1f, 495 .mwdma_mask = 0x07, 496 .udma_mask = 0x07, 497 .port_ops = &optiplus_port_ops 498 }; 499 static struct ata_port_info *port_info[2]; 500 struct ata_port_info *info = &info_82c700; 501 static int printed_version; 502 503 if (!printed_version++) 504 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n"); 505 506 /* Fixed location chipset magic */ 507 inw(0x1F1); 508 inw(0x1F1); 509 pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */ 510 511 if (optiplus_with_udma(dev)) 512 info = &info_82c700_udma; 513 514 port_info[0] = port_info[1] = info; 515 return ata_pci_init_one(dev, port_info, 2); 516 } 517 518 static const struct pci_device_id optidma[] = { 519 { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */ 520 521 { }, 522 }; 523 524 static struct pci_driver optidma_pci_driver = { 525 .name = DRV_NAME, 526 .id_table = optidma, 527 .probe = optidma_init_one, 528 .remove = ata_pci_remove_one, 529 #ifdef CONFIG_PM 530 .suspend = ata_pci_device_suspend, 531 .resume = ata_pci_device_resume, 532 #endif 533 }; 534 535 static int __init optidma_init(void) 536 { 537 return pci_register_driver(&optidma_pci_driver); 538 } 539 540 static void __exit optidma_exit(void) 541 { 542 pci_unregister_driver(&optidma_pci_driver); 543 } 544 545 MODULE_AUTHOR("Alan Cox"); 546 MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus"); 547 MODULE_LICENSE("GPL"); 548 MODULE_DEVICE_TABLE(pci, optidma); 549 MODULE_VERSION(DRV_VERSION); 550 551 module_init(optidma_init); 552 module_exit(optidma_exit); 553