1 /* 2 * pata_oldpiix.c - Intel PATA/SATA controllers 3 * 4 * (C) 2005 Red Hat <alan@redhat.com> 5 * 6 * Some parts based on ata_piix.c by Jeff Garzik and others. 7 * 8 * Early PIIX differs significantly from the later PIIX as it lacks 9 * SITRE and the slave timing registers. This means that you have to 10 * set timing per channel, or be clever. Libata tells us whenever it 11 * does drive selection and we use this to reload the timings. 12 * 13 * Because of these behaviour differences PIIX gets its own driver module. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/pci.h> 19 #include <linux/init.h> 20 #include <linux/blkdev.h> 21 #include <linux/delay.h> 22 #include <linux/device.h> 23 #include <scsi/scsi_host.h> 24 #include <linux/libata.h> 25 #include <linux/ata.h> 26 27 #define DRV_NAME "pata_oldpiix" 28 #define DRV_VERSION "0.5.4" 29 30 /** 31 * oldpiix_pre_reset - probe begin 32 * @ap: ATA port 33 * 34 * Set up cable type and use generic probe init 35 */ 36 37 static int oldpiix_pre_reset(struct ata_port *ap) 38 { 39 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 40 static const struct pci_bits oldpiix_enable_bits[] = { 41 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 42 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 43 }; 44 45 if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no])) 46 return -ENOENT; 47 ap->cbl = ATA_CBL_PATA40; 48 return ata_std_prereset(ap); 49 } 50 51 /** 52 * oldpiix_pata_error_handler - Probe specified port on PATA host controller 53 * @ap: Port to probe 54 * @classes: 55 * 56 * LOCKING: 57 * None (inherited from caller). 58 */ 59 60 static void oldpiix_pata_error_handler(struct ata_port *ap) 61 { 62 ata_bmdma_drive_eh(ap, oldpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 63 } 64 65 /** 66 * oldpiix_set_piomode - Initialize host controller PATA PIO timings 67 * @ap: Port whose timings we are configuring 68 * @adev: um 69 * 70 * Set PIO mode for device, in host controller PCI config space. 71 * 72 * LOCKING: 73 * None (inherited from caller). 74 */ 75 76 static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev) 77 { 78 unsigned int pio = adev->pio_mode - XFER_PIO_0; 79 struct pci_dev *dev = to_pci_dev(ap->host->dev); 80 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40; 81 u16 idetm_data; 82 int control = 0; 83 84 /* 85 * See Intel Document 298600-004 for the timing programing rules 86 * for PIIX/ICH. Note that the early PIIX does not have the slave 87 * timing port at 0x44. 88 */ 89 90 static const /* ISP RTC */ 91 u8 timings[][2] = { { 0, 0 }, 92 { 0, 0 }, 93 { 1, 0 }, 94 { 2, 1 }, 95 { 2, 3 }, }; 96 97 if (pio > 1) 98 control |= 1; /* TIME */ 99 if (ata_pio_need_iordy(adev)) 100 control |= 2; /* IE */ 101 102 /* Intel specifies that the prefetch/posting is for disk only */ 103 if (adev->class == ATA_DEV_ATA) 104 control |= 4; /* PPE */ 105 106 pci_read_config_word(dev, idetm_port, &idetm_data); 107 108 /* 109 * Set PPE, IE and TIME as appropriate. 110 * Clear the other drive's timing bits. 111 */ 112 if (adev->devno == 0) { 113 idetm_data &= 0xCCE0; 114 idetm_data |= control; 115 } else { 116 idetm_data &= 0xCC0E; 117 idetm_data |= (control << 4); 118 } 119 idetm_data |= (timings[pio][0] << 12) | 120 (timings[pio][1] << 8); 121 pci_write_config_word(dev, idetm_port, idetm_data); 122 123 /* Track which port is configured */ 124 ap->private_data = adev; 125 } 126 127 /** 128 * oldpiix_set_dmamode - Initialize host controller PATA DMA timings 129 * @ap: Port whose timings we are configuring 130 * @adev: Device to program 131 * @isich: True if the device is an ICH and has IOCFG registers 132 * 133 * Set MWDMA mode for device, in host controller PCI config space. 134 * 135 * LOCKING: 136 * None (inherited from caller). 137 */ 138 139 static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev) 140 { 141 struct pci_dev *dev = to_pci_dev(ap->host->dev); 142 u8 idetm_port = ap->port_no ? 0x42 : 0x40; 143 u16 idetm_data; 144 145 static const /* ISP RTC */ 146 u8 timings[][2] = { { 0, 0 }, 147 { 0, 0 }, 148 { 1, 0 }, 149 { 2, 1 }, 150 { 2, 3 }, }; 151 152 /* 153 * MWDMA is driven by the PIO timings. We must also enable 154 * IORDY unconditionally along with TIME1. PPE has already 155 * been set when the PIO timing was set. 156 */ 157 158 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 159 unsigned int control; 160 const unsigned int needed_pio[3] = { 161 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 162 }; 163 int pio = needed_pio[mwdma] - XFER_PIO_0; 164 165 pci_read_config_word(dev, idetm_port, &idetm_data); 166 167 control = 3; /* IORDY|TIME0 */ 168 /* Intel specifies that the PPE functionality is for disk only */ 169 if (adev->class == ATA_DEV_ATA) 170 control |= 4; /* PPE enable */ 171 172 /* If the drive MWDMA is faster than it can do PIO then 173 we must force PIO into PIO0 */ 174 175 if (adev->pio_mode < needed_pio[mwdma]) 176 /* Enable DMA timing only */ 177 control |= 8; /* PIO cycles in PIO0 */ 178 179 /* Mask out the relevant control and timing bits we will load. Also 180 clear the other drive TIME register as a precaution */ 181 if (adev->devno == 0) { 182 idetm_data &= 0xCCE0; 183 idetm_data |= control; 184 } else { 185 idetm_data &= 0xCC0E; 186 idetm_data |= (control << 4); 187 } 188 idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); 189 pci_write_config_word(dev, idetm_port, idetm_data); 190 191 /* Track which port is configured */ 192 ap->private_data = adev; 193 } 194 195 /** 196 * oldpiix_qc_issue_prot - command issue 197 * @qc: command pending 198 * 199 * Called when the libata layer is about to issue a command. We wrap 200 * this interface so that we can load the correct ATA timings if 201 * neccessary. Our logic also clears TIME0/TIME1 for the other device so 202 * that, even if we get this wrong, cycles to the other device will 203 * be made PIO0. 204 */ 205 206 static unsigned int oldpiix_qc_issue_prot(struct ata_queued_cmd *qc) 207 { 208 struct ata_port *ap = qc->ap; 209 struct ata_device *adev = qc->dev; 210 211 if (adev != ap->private_data) { 212 oldpiix_set_piomode(ap, adev); 213 if (adev->dma_mode) 214 oldpiix_set_dmamode(ap, adev); 215 } 216 return ata_qc_issue_prot(qc); 217 } 218 219 220 static struct scsi_host_template oldpiix_sht = { 221 .module = THIS_MODULE, 222 .name = DRV_NAME, 223 .ioctl = ata_scsi_ioctl, 224 .queuecommand = ata_scsi_queuecmd, 225 .can_queue = ATA_DEF_QUEUE, 226 .this_id = ATA_SHT_THIS_ID, 227 .sg_tablesize = LIBATA_MAX_PRD, 228 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 229 .emulated = ATA_SHT_EMULATED, 230 .use_clustering = ATA_SHT_USE_CLUSTERING, 231 .proc_name = DRV_NAME, 232 .dma_boundary = ATA_DMA_BOUNDARY, 233 .slave_configure = ata_scsi_slave_config, 234 .slave_destroy = ata_scsi_slave_destroy, 235 .bios_param = ata_std_bios_param, 236 #ifdef CONFIG_PM 237 .resume = ata_scsi_device_resume, 238 .suspend = ata_scsi_device_suspend, 239 #endif 240 }; 241 242 static const struct ata_port_operations oldpiix_pata_ops = { 243 .port_disable = ata_port_disable, 244 .set_piomode = oldpiix_set_piomode, 245 .set_dmamode = oldpiix_set_dmamode, 246 .mode_filter = ata_pci_default_filter, 247 248 .tf_load = ata_tf_load, 249 .tf_read = ata_tf_read, 250 .check_status = ata_check_status, 251 .exec_command = ata_exec_command, 252 .dev_select = ata_std_dev_select, 253 254 .freeze = ata_bmdma_freeze, 255 .thaw = ata_bmdma_thaw, 256 .error_handler = oldpiix_pata_error_handler, 257 .post_internal_cmd = ata_bmdma_post_internal_cmd, 258 259 .bmdma_setup = ata_bmdma_setup, 260 .bmdma_start = ata_bmdma_start, 261 .bmdma_stop = ata_bmdma_stop, 262 .bmdma_status = ata_bmdma_status, 263 .qc_prep = ata_qc_prep, 264 .qc_issue = oldpiix_qc_issue_prot, 265 .data_xfer = ata_data_xfer, 266 267 .irq_handler = ata_interrupt, 268 .irq_clear = ata_bmdma_irq_clear, 269 .irq_on = ata_irq_on, 270 .irq_ack = ata_irq_ack, 271 272 .port_start = ata_port_start, 273 }; 274 275 276 /** 277 * oldpiix_init_one - Register PIIX ATA PCI device with kernel services 278 * @pdev: PCI device to register 279 * @ent: Entry in oldpiix_pci_tbl matching with @pdev 280 * 281 * Called from kernel PCI layer. We probe for combined mode (sigh), 282 * and then hand over control to libata, for it to do the rest. 283 * 284 * LOCKING: 285 * Inherited from PCI layer (may sleep). 286 * 287 * RETURNS: 288 * Zero on success, or -ERRNO value. 289 */ 290 291 static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 292 { 293 static int printed_version; 294 static struct ata_port_info info = { 295 .sht = &oldpiix_sht, 296 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 297 .pio_mask = 0x1f, /* pio0-4 */ 298 .mwdma_mask = 0x07, /* mwdma1-2 */ 299 .port_ops = &oldpiix_pata_ops, 300 }; 301 static struct ata_port_info *port_info[2] = { &info, &info }; 302 303 if (!printed_version++) 304 dev_printk(KERN_DEBUG, &pdev->dev, 305 "version " DRV_VERSION "\n"); 306 307 return ata_pci_init_one(pdev, port_info, 2); 308 } 309 310 static const struct pci_device_id oldpiix_pci_tbl[] = { 311 { PCI_VDEVICE(INTEL, 0x1230), }, 312 313 { } /* terminate list */ 314 }; 315 316 static struct pci_driver oldpiix_pci_driver = { 317 .name = DRV_NAME, 318 .id_table = oldpiix_pci_tbl, 319 .probe = oldpiix_init_one, 320 .remove = ata_pci_remove_one, 321 #ifdef CONFIG_PM 322 .suspend = ata_pci_device_suspend, 323 .resume = ata_pci_device_resume, 324 #endif 325 }; 326 327 static int __init oldpiix_init(void) 328 { 329 return pci_register_driver(&oldpiix_pci_driver); 330 } 331 332 static void __exit oldpiix_exit(void) 333 { 334 pci_unregister_driver(&oldpiix_pci_driver); 335 } 336 337 module_init(oldpiix_init); 338 module_exit(oldpiix_exit); 339 340 MODULE_AUTHOR("Alan Cox"); 341 MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers"); 342 MODULE_LICENSE("GPL"); 343 MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl); 344 MODULE_VERSION(DRV_VERSION); 345 346