1 /* 2 * pata_ninja32.c - Ninja32 PATA for new ATA layer 3 * (C) 2007 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * Note: The controller like many controllers has shared timings for 7 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back 8 * in the dma_stop function. Thus we actually don't need a set_dmamode 9 * method as the PIO method is always called and will set the right PIO 10 * timing parameters. 11 * 12 * The Ninja32 Cardbus is not a generic SFF controller. Instead it is 13 * laid out as follows off BAR 0. This is based upon Mark Lord's delkin 14 * driver and the extensive analysis done by the BSD developers, notably 15 * ITOH Yasufumi. 16 * 17 * Base + 0x00 IRQ Status 18 * Base + 0x01 IRQ control 19 * Base + 0x02 Chipset control 20 * Base + 0x04 VDMA and reset control + wait bits 21 * Base + 0x08 BMIMBA 22 * Base + 0x0C DMA Length 23 * Base + 0x10 Taskfile 24 * Base + 0x18 BMDMA Status ? 25 * Base + 0x1C 26 * Base + 0x1D Bus master control 27 * bit 0 = enable 28 * bit 1 = 0 write/1 read 29 * bit 2 = 1 sgtable 30 * bit 3 = go 31 * bit 4-6 wait bits 32 * bit 7 = done 33 * Base + 0x1E AltStatus 34 * Base + 0x1F timing register 35 */ 36 37 #include <linux/kernel.h> 38 #include <linux/module.h> 39 #include <linux/pci.h> 40 #include <linux/init.h> 41 #include <linux/blkdev.h> 42 #include <linux/delay.h> 43 #include <scsi/scsi_host.h> 44 #include <linux/libata.h> 45 46 #define DRV_NAME "pata_ninja32" 47 #define DRV_VERSION "0.0.1" 48 49 50 /** 51 * ninja32_set_piomode - set initial PIO mode data 52 * @ap: ATA interface 53 * @adev: ATA device 54 * 55 * Called to do the PIO mode setup. Our timing registers are shared 56 * but we want to set the PIO timing by default. 57 */ 58 59 static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev) 60 { 61 static u16 pio_timing[5] = { 62 0xd6, 0x85, 0x44, 0x33, 0x13 63 }; 64 iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0], 65 ap->ioaddr.bmdma_addr + 0x1f); 66 ap->private_data = adev; 67 } 68 69 70 static void ninja32_dev_select(struct ata_port *ap, unsigned int device) 71 { 72 struct ata_device *adev = &ap->link.device[device]; 73 if (ap->private_data != adev) { 74 iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f); 75 ata_std_dev_select(ap, device); 76 ninja32_set_piomode(ap, adev); 77 } 78 } 79 80 static struct scsi_host_template ninja32_sht = { 81 .module = THIS_MODULE, 82 .name = DRV_NAME, 83 .ioctl = ata_scsi_ioctl, 84 .queuecommand = ata_scsi_queuecmd, 85 .can_queue = ATA_DEF_QUEUE, 86 .this_id = ATA_SHT_THIS_ID, 87 .sg_tablesize = LIBATA_MAX_PRD, 88 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 89 .emulated = ATA_SHT_EMULATED, 90 .use_clustering = ATA_SHT_USE_CLUSTERING, 91 .proc_name = DRV_NAME, 92 .dma_boundary = ATA_DMA_BOUNDARY, 93 .slave_configure = ata_scsi_slave_config, 94 .slave_destroy = ata_scsi_slave_destroy, 95 .bios_param = ata_std_bios_param, 96 }; 97 98 static struct ata_port_operations ninja32_port_ops = { 99 .set_piomode = ninja32_set_piomode, 100 .mode_filter = ata_pci_default_filter, 101 102 .tf_load = ata_tf_load, 103 .tf_read = ata_tf_read, 104 .check_status = ata_check_status, 105 .exec_command = ata_exec_command, 106 .dev_select = ninja32_dev_select, 107 108 .freeze = ata_bmdma_freeze, 109 .thaw = ata_bmdma_thaw, 110 .error_handler = ata_bmdma_error_handler, 111 .post_internal_cmd = ata_bmdma_post_internal_cmd, 112 .cable_detect = ata_cable_40wire, 113 114 .bmdma_setup = ata_bmdma_setup, 115 .bmdma_start = ata_bmdma_start, 116 .bmdma_stop = ata_bmdma_stop, 117 .bmdma_status = ata_bmdma_status, 118 119 .qc_prep = ata_qc_prep, 120 .qc_issue = ata_qc_issue_prot, 121 122 .data_xfer = ata_data_xfer, 123 124 .irq_handler = ata_interrupt, 125 .irq_clear = ata_bmdma_irq_clear, 126 .irq_on = ata_irq_on, 127 128 .port_start = ata_sff_port_start, 129 }; 130 131 static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id) 132 { 133 struct ata_host *host; 134 struct ata_port *ap; 135 void __iomem *base; 136 int rc; 137 138 host = ata_host_alloc(&dev->dev, 1); 139 if (!host) 140 return -ENOMEM; 141 ap = host->ports[0]; 142 143 /* Set up the PCI device */ 144 rc = pcim_enable_device(dev); 145 if (rc) 146 return rc; 147 rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME); 148 if (rc == -EBUSY) 149 pcim_pin_device(dev); 150 if (rc) 151 return rc; 152 153 host->iomap = pcim_iomap_table(dev); 154 rc = pci_set_dma_mask(dev, ATA_DMA_MASK); 155 if (rc) 156 return rc; 157 rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK); 158 if (rc) 159 return rc; 160 pci_set_master(dev); 161 162 /* Set up the register mappings */ 163 base = host->iomap[0]; 164 if (!base) 165 return -ENOMEM; 166 ap->ops = &ninja32_port_ops; 167 ap->pio_mask = 0x1F; 168 ap->flags |= ATA_FLAG_SLAVE_POSS; 169 170 ap->ioaddr.cmd_addr = base + 0x10; 171 ap->ioaddr.ctl_addr = base + 0x1E; 172 ap->ioaddr.altstatus_addr = base + 0x1E; 173 ap->ioaddr.bmdma_addr = base; 174 ata_std_ports(&ap->ioaddr); 175 176 iowrite8(0x05, base + 0x01); /* Enable interrupt lines */ 177 iowrite8(0xB3, base + 0x02); /* Burst, ?? setup */ 178 iowrite8(0x00, base + 0x04); /* WAIT0 ? */ 179 /* FIXME: Should we disable them at remove ? */ 180 return ata_host_activate(host, dev->irq, ata_interrupt, 181 IRQF_SHARED, &ninja32_sht); 182 } 183 184 static const struct pci_device_id ninja32[] = { 185 { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 186 { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 187 { }, 188 }; 189 190 static struct pci_driver ninja32_pci_driver = { 191 .name = DRV_NAME, 192 .id_table = ninja32, 193 .probe = ninja32_init_one, 194 .remove = ata_pci_remove_one 195 }; 196 197 static int __init ninja32_init(void) 198 { 199 return pci_register_driver(&ninja32_pci_driver); 200 } 201 202 static void __exit ninja32_exit(void) 203 { 204 pci_unregister_driver(&ninja32_pci_driver); 205 } 206 207 MODULE_AUTHOR("Alan Cox"); 208 MODULE_DESCRIPTION("low-level driver for Ninja32 ATA"); 209 MODULE_LICENSE("GPL"); 210 MODULE_DEVICE_TABLE(pci, ninja32); 211 MODULE_VERSION(DRV_VERSION); 212 213 module_init(ninja32_init); 214 module_exit(ninja32_exit); 215