1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pata-legacy.c - Legacy port PATA/SATA controller driver. 4 * Copyright 2005/2006 Red Hat, all rights reserved. 5 * 6 * An ATA driver for the legacy ATA ports. 7 * 8 * Data Sources: 9 * Opti 82C465/82C611 support: Data sheets at opti-inc.com 10 * HT6560 series: 11 * Promise 20230/20620: 12 * http://www.ryston.cz/petr/vlb/pdc20230b.html 13 * http://www.ryston.cz/petr/vlb/pdc20230c.html 14 * http://www.ryston.cz/petr/vlb/pdc20630.html 15 * QDI65x0: 16 * http://www.ryston.cz/petr/vlb/qd6500.html 17 * http://www.ryston.cz/petr/vlb/qd6580.html 18 * 19 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c 20 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by 21 * Samuel Thibault <samuel.thibault@ens-lyon.org> 22 * 23 * Unsupported but docs exist: 24 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 25 * 26 * This driver handles legacy (that is "ISA/VLB side") IDE ports found 27 * on PC class systems. There are three hybrid devices that are exceptions 28 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and 29 * the MPIIX where the tuning is PCI side but the IDE is "ISA side". 30 * 31 * Specific support is included for the ht6560a/ht6560b/opti82c611a/ 32 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A 33 * 34 * Support for the Winbond 83759A when operating in advanced mode. 35 * Multichip mode is not currently supported. 36 * 37 * Use the autospeed and pio_mask options with: 38 * Appian ADI/2 aka CLPD7220 or AIC25VL01. 39 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with 40 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, 41 * Winbond W83759A, Promise PDC20230-B 42 * 43 * For now use autospeed and pio_mask as above with the W83759A. This may 44 * change. 45 */ 46 47 #include <linux/async.h> 48 #include <linux/kernel.h> 49 #include <linux/module.h> 50 #include <linux/pci.h> 51 #include <linux/init.h> 52 #include <linux/blkdev.h> 53 #include <linux/delay.h> 54 #include <scsi/scsi_host.h> 55 #include <linux/ata.h> 56 #include <linux/libata.h> 57 #include <linux/platform_device.h> 58 59 #define DRV_NAME "pata_legacy" 60 #define DRV_VERSION "0.6.5" 61 62 #define NR_HOST 6 63 64 static int all; 65 module_param(all, int, 0444); 66 MODULE_PARM_DESC(all, 67 "Set to probe unclaimed pri/sec ISA port ranges even if PCI"); 68 69 static int probe_all; 70 module_param(probe_all, int, 0); 71 MODULE_PARM_DESC(probe_all, 72 "Set to probe tertiary+ ISA port ranges even if PCI"); 73 74 static int probe_mask = ~0; 75 module_param(probe_mask, int, 0); 76 MODULE_PARM_DESC(probe_mask, "Probe mask for legacy ISA PATA ports"); 77 78 static int autospeed; 79 module_param(autospeed, int, 0); 80 MODULE_PARM_DESC(autospeed, "Chip present that snoops speed changes"); 81 82 static int pio_mask = ATA_PIO4; 83 module_param(pio_mask, int, 0); 84 MODULE_PARM_DESC(pio_mask, "PIO range for autospeed devices"); 85 86 static int iordy_mask = 0xFFFFFFFF; 87 module_param(iordy_mask, int, 0); 88 MODULE_PARM_DESC(iordy_mask, "Use IORDY if available"); 89 90 static int ht6560a; 91 module_param(ht6560a, int, 0); 92 MODULE_PARM_DESC(ht6560a, "HT 6560A on primary 1, second 2, both 3"); 93 94 static int ht6560b; 95 module_param(ht6560b, int, 0); 96 MODULE_PARM_DESC(ht6560b, "HT 6560B on primary 1, secondary 2, both 3"); 97 98 static int opti82c611a; 99 module_param(opti82c611a, int, 0); 100 MODULE_PARM_DESC(opti82c611a, 101 "Opti 82c611A on primary 1, secondary 2, both 3"); 102 103 static int opti82c46x; 104 module_param(opti82c46x, int, 0); 105 MODULE_PARM_DESC(opti82c46x, 106 "Opti 82c465MV on primary 1, secondary 2, both 3"); 107 108 #ifdef CONFIG_PATA_QDI_MODULE 109 static int qdi = 1; 110 #else 111 static int qdi; 112 #endif 113 module_param(qdi, int, 0); 114 MODULE_PARM_DESC(qdi, "Set to probe QDI controllers"); 115 116 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE 117 static int winbond = 1; 118 #else 119 static int winbond; 120 #endif 121 module_param(winbond, int, 0); 122 MODULE_PARM_DESC(winbond, 123 "Set to probe Winbond controllers, " 124 "give I/O port if non standard"); 125 126 127 enum controller { 128 BIOS = 0, 129 SNOOP = 1, 130 PDC20230 = 2, 131 HT6560A = 3, 132 HT6560B = 4, 133 OPTI611A = 5, 134 OPTI46X = 6, 135 QDI6500 = 7, 136 QDI6580 = 8, 137 QDI6580DP = 9, /* Dual channel mode is different */ 138 W83759A = 10, 139 140 UNKNOWN = -1 141 }; 142 143 struct legacy_data { 144 unsigned long timing; 145 u8 clock[2]; 146 u8 last; 147 int fast; 148 enum controller type; 149 struct platform_device *platform_dev; 150 }; 151 152 struct legacy_probe { 153 unsigned char *name; 154 unsigned long port; 155 unsigned int irq; 156 unsigned int slot; 157 enum controller type; 158 unsigned long private; 159 }; 160 161 struct legacy_controller { 162 const char *name; 163 struct ata_port_operations *ops; 164 unsigned int pio_mask; 165 unsigned int flags; 166 unsigned int pflags; 167 int (*setup)(struct platform_device *, struct legacy_probe *probe, 168 struct legacy_data *data); 169 }; 170 171 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; 172 173 static struct legacy_probe probe_list[NR_HOST]; 174 static struct legacy_data legacy_data[NR_HOST]; 175 static struct ata_host *legacy_host[NR_HOST]; 176 static int nr_legacy_host; 177 178 179 /** 180 * legacy_probe_add - Add interface to probe list 181 * @port: Controller port 182 * @irq: IRQ number 183 * @type: Controller type 184 * @private: Controller specific info 185 * 186 * Add an entry into the probe list for ATA controllers. This is used 187 * to add the default ISA slots and then to build up the table 188 * further according to other ISA/VLB/Weird device scans 189 * 190 * An I/O port list is used to keep ordering stable and sane, as we 191 * don't have any good way to talk about ordering otherwise 192 */ 193 194 static int legacy_probe_add(unsigned long port, unsigned int irq, 195 enum controller type, unsigned long private) 196 { 197 struct legacy_probe *lp = &probe_list[0]; 198 int i; 199 struct legacy_probe *free = NULL; 200 201 for (i = 0; i < NR_HOST; i++) { 202 if (lp->port == 0 && free == NULL) 203 free = lp; 204 /* Matching port, or the correct slot for ordering */ 205 if (lp->port == port || legacy_port[i] == port) { 206 if (!(probe_mask & 1 << i)) 207 return -1; 208 free = lp; 209 break; 210 } 211 lp++; 212 } 213 if (free == NULL) { 214 printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); 215 return -1; 216 } 217 /* Fill in the entry for later probing */ 218 free->port = port; 219 free->irq = irq; 220 free->type = type; 221 free->private = private; 222 return 0; 223 } 224 225 226 /** 227 * legacy_set_mode - mode setting 228 * @link: IDE link 229 * @unused: Device that failed when error is returned 230 * 231 * Use a non standard set_mode function. We don't want to be tuned. 232 * 233 * The BIOS configured everything. Our job is not to fiddle. Just use 234 * whatever PIO the hardware is using and leave it at that. When we 235 * get some kind of nice user driven API for control then we can 236 * expand on this as per hdparm in the base kernel. 237 */ 238 239 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) 240 { 241 struct ata_device *dev; 242 243 ata_for_each_dev(dev, link, ENABLED) { 244 ata_dev_info(dev, "configured for PIO\n"); 245 dev->pio_mode = XFER_PIO_0; 246 dev->xfer_mode = XFER_PIO_0; 247 dev->xfer_shift = ATA_SHIFT_PIO; 248 dev->flags |= ATA_DFLAG_PIO; 249 } 250 return 0; 251 } 252 253 static struct scsi_host_template legacy_sht = { 254 ATA_PIO_SHT(DRV_NAME), 255 }; 256 257 static const struct ata_port_operations legacy_base_port_ops = { 258 .inherits = &ata_sff_port_ops, 259 .cable_detect = ata_cable_40wire, 260 }; 261 262 /* 263 * These ops are used if the user indicates the hardware 264 * snoops the commands to decide on the mode and handles the 265 * mode selection "magically" itself. Several legacy controllers 266 * do this. The mode range can be set if it is not 0x1F by setting 267 * pio_mask as well. 268 */ 269 270 static struct ata_port_operations simple_port_ops = { 271 .inherits = &legacy_base_port_ops, 272 .sff_data_xfer = ata_sff_data_xfer32, 273 }; 274 275 static struct ata_port_operations legacy_port_ops = { 276 .inherits = &legacy_base_port_ops, 277 .sff_data_xfer = ata_sff_data_xfer32, 278 .set_mode = legacy_set_mode, 279 }; 280 281 /* 282 * Promise 20230C and 20620 support 283 * 284 * This controller supports PIO0 to PIO2. We set PIO timings 285 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA 286 * support is weird being DMA to controller and PIO'd to the host 287 * and not supported. 288 */ 289 290 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) 291 { 292 int tries = 5; 293 int pio = adev->pio_mode - XFER_PIO_0; 294 u8 rt; 295 unsigned long flags; 296 297 /* Safe as UP only. Force I/Os to occur together */ 298 299 local_irq_save(flags); 300 301 /* Unlock the control interface */ 302 do { 303 inb(0x1F5); 304 outb(inb(0x1F2) | 0x80, 0x1F2); 305 inb(0x1F2); 306 inb(0x3F6); 307 inb(0x3F6); 308 inb(0x1F2); 309 inb(0x1F2); 310 } 311 while ((inb(0x1F2) & 0x80) && --tries); 312 313 local_irq_restore(flags); 314 315 outb(inb(0x1F4) & 0x07, 0x1F4); 316 317 rt = inb(0x1F3); 318 rt &= 0x07 << (3 * adev->devno); 319 if (pio) 320 rt |= (1 + 3 * pio) << (3 * adev->devno); 321 322 udelay(100); 323 outb(inb(0x1F2) | 0x01, 0x1F2); 324 udelay(100); 325 inb(0x1F5); 326 327 } 328 329 static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc, 330 unsigned char *buf, unsigned int buflen, int rw) 331 { 332 struct ata_device *dev = qc->dev; 333 struct ata_port *ap = dev->link->ap; 334 int slop = buflen & 3; 335 336 /* 32bit I/O capable *and* we need to write a whole number of dwords */ 337 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) 338 && (ap->pflags & ATA_PFLAG_PIO32)) { 339 unsigned long flags; 340 341 local_irq_save(flags); 342 343 /* Perform the 32bit I/O synchronization sequence */ 344 ioread8(ap->ioaddr.nsect_addr); 345 ioread8(ap->ioaddr.nsect_addr); 346 ioread8(ap->ioaddr.nsect_addr); 347 348 /* Now the data */ 349 if (rw == READ) 350 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 351 else 352 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 353 354 if (unlikely(slop)) { 355 __le32 pad; 356 if (rw == READ) { 357 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 358 memcpy(buf + buflen - slop, &pad, slop); 359 } else { 360 memcpy(&pad, buf + buflen - slop, slop); 361 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 362 } 363 buflen += 4 - slop; 364 } 365 local_irq_restore(flags); 366 } else 367 buflen = ata_sff_data_xfer32(qc, buf, buflen, rw); 368 369 return buflen; 370 } 371 372 static struct ata_port_operations pdc20230_port_ops = { 373 .inherits = &legacy_base_port_ops, 374 .set_piomode = pdc20230_set_piomode, 375 .sff_data_xfer = pdc_data_xfer_vlb, 376 }; 377 378 /* 379 * Holtek 6560A support 380 * 381 * This controller supports PIO0 to PIO2 (no IORDY even though higher 382 * timings can be loaded). 383 */ 384 385 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) 386 { 387 u8 active, recover; 388 struct ata_timing t; 389 390 /* Get the timing data in cycles. For now play safe at 50Mhz */ 391 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 392 393 active = clamp_val(t.active, 2, 15); 394 recover = clamp_val(t.recover, 4, 15); 395 396 inb(0x3E6); 397 inb(0x3E6); 398 inb(0x3E6); 399 inb(0x3E6); 400 401 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 402 ioread8(ap->ioaddr.status_addr); 403 } 404 405 static struct ata_port_operations ht6560a_port_ops = { 406 .inherits = &legacy_base_port_ops, 407 .set_piomode = ht6560a_set_piomode, 408 }; 409 410 /* 411 * Holtek 6560B support 412 * 413 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO 414 * setting unless we see an ATAPI device in which case we force it off. 415 * 416 * FIXME: need to implement 2nd channel support. 417 */ 418 419 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) 420 { 421 u8 active, recover; 422 struct ata_timing t; 423 424 /* Get the timing data in cycles. For now play safe at 50Mhz */ 425 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 426 427 active = clamp_val(t.active, 2, 15); 428 recover = clamp_val(t.recover, 2, 16) & 0x0F; 429 430 inb(0x3E6); 431 inb(0x3E6); 432 inb(0x3E6); 433 inb(0x3E6); 434 435 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 436 437 if (adev->class != ATA_DEV_ATA) { 438 u8 rconf = inb(0x3E6); 439 if (rconf & 0x24) { 440 rconf &= ~0x24; 441 outb(rconf, 0x3E6); 442 } 443 } 444 ioread8(ap->ioaddr.status_addr); 445 } 446 447 static struct ata_port_operations ht6560b_port_ops = { 448 .inherits = &legacy_base_port_ops, 449 .set_piomode = ht6560b_set_piomode, 450 }; 451 452 /* 453 * Opti core chipset helpers 454 */ 455 456 /** 457 * opti_syscfg - read OPTI chipset configuration 458 * @reg: Configuration register to read 459 * 460 * Returns the value of an OPTI system board configuration register. 461 */ 462 463 static u8 opti_syscfg(u8 reg) 464 { 465 unsigned long flags; 466 u8 r; 467 468 /* Uniprocessor chipset and must force cycles adjancent */ 469 local_irq_save(flags); 470 outb(reg, 0x22); 471 r = inb(0x24); 472 local_irq_restore(flags); 473 return r; 474 } 475 476 /* 477 * Opti 82C611A 478 * 479 * This controller supports PIO0 to PIO3. 480 */ 481 482 static void opti82c611a_set_piomode(struct ata_port *ap, 483 struct ata_device *adev) 484 { 485 u8 active, recover, setup; 486 struct ata_timing t; 487 struct ata_device *pair = ata_dev_pair(adev); 488 int clock; 489 int khz[4] = { 50000, 40000, 33000, 25000 }; 490 u8 rc; 491 492 /* Enter configuration mode */ 493 ioread16(ap->ioaddr.error_addr); 494 ioread16(ap->ioaddr.error_addr); 495 iowrite8(3, ap->ioaddr.nsect_addr); 496 497 /* Read VLB clock strapping */ 498 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; 499 500 /* Get the timing data in cycles */ 501 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 502 503 /* Setup timing is shared */ 504 if (pair) { 505 struct ata_timing tp; 506 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 507 508 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 509 } 510 511 active = clamp_val(t.active, 2, 17) - 2; 512 recover = clamp_val(t.recover, 1, 16) - 1; 513 setup = clamp_val(t.setup, 1, 4) - 1; 514 515 /* Select the right timing bank for write timing */ 516 rc = ioread8(ap->ioaddr.lbal_addr); 517 rc &= 0x7F; 518 rc |= (adev->devno << 7); 519 iowrite8(rc, ap->ioaddr.lbal_addr); 520 521 /* Write the timings */ 522 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 523 524 /* Select the right bank for read timings, also 525 load the shared timings for address */ 526 rc = ioread8(ap->ioaddr.device_addr); 527 rc &= 0xC0; 528 rc |= adev->devno; /* Index select */ 529 rc |= (setup << 4) | 0x04; 530 iowrite8(rc, ap->ioaddr.device_addr); 531 532 /* Load the read timings */ 533 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 534 535 /* Ensure the timing register mode is right */ 536 rc = ioread8(ap->ioaddr.lbal_addr); 537 rc &= 0x73; 538 rc |= 0x84; 539 iowrite8(rc, ap->ioaddr.lbal_addr); 540 541 /* Exit command mode */ 542 iowrite8(0x83, ap->ioaddr.nsect_addr); 543 } 544 545 546 static struct ata_port_operations opti82c611a_port_ops = { 547 .inherits = &legacy_base_port_ops, 548 .set_piomode = opti82c611a_set_piomode, 549 }; 550 551 /* 552 * Opti 82C465MV 553 * 554 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB 555 * version is dual channel but doesn't have a lot of unique registers. 556 */ 557 558 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) 559 { 560 u8 active, recover, setup; 561 struct ata_timing t; 562 struct ata_device *pair = ata_dev_pair(adev); 563 int clock; 564 int khz[4] = { 50000, 40000, 33000, 25000 }; 565 u8 rc; 566 u8 sysclk; 567 568 /* Get the clock */ 569 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */ 570 571 /* Enter configuration mode */ 572 ioread16(ap->ioaddr.error_addr); 573 ioread16(ap->ioaddr.error_addr); 574 iowrite8(3, ap->ioaddr.nsect_addr); 575 576 /* Read VLB clock strapping */ 577 clock = 1000000000 / khz[sysclk]; 578 579 /* Get the timing data in cycles */ 580 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 581 582 /* Setup timing is shared */ 583 if (pair) { 584 struct ata_timing tp; 585 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 586 587 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 588 } 589 590 active = clamp_val(t.active, 2, 17) - 2; 591 recover = clamp_val(t.recover, 1, 16) - 1; 592 setup = clamp_val(t.setup, 1, 4) - 1; 593 594 /* Select the right timing bank for write timing */ 595 rc = ioread8(ap->ioaddr.lbal_addr); 596 rc &= 0x7F; 597 rc |= (adev->devno << 7); 598 iowrite8(rc, ap->ioaddr.lbal_addr); 599 600 /* Write the timings */ 601 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 602 603 /* Select the right bank for read timings, also 604 load the shared timings for address */ 605 rc = ioread8(ap->ioaddr.device_addr); 606 rc &= 0xC0; 607 rc |= adev->devno; /* Index select */ 608 rc |= (setup << 4) | 0x04; 609 iowrite8(rc, ap->ioaddr.device_addr); 610 611 /* Load the read timings */ 612 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 613 614 /* Ensure the timing register mode is right */ 615 rc = ioread8(ap->ioaddr.lbal_addr); 616 rc &= 0x73; 617 rc |= 0x84; 618 iowrite8(rc, ap->ioaddr.lbal_addr); 619 620 /* Exit command mode */ 621 iowrite8(0x83, ap->ioaddr.nsect_addr); 622 623 /* We need to know this for quad device on the MVB */ 624 ap->host->private_data = ap; 625 } 626 627 /** 628 * opti82c46x_qc_issue - command issue 629 * @qc: command pending 630 * 631 * Called when the libata layer is about to issue a command. We wrap 632 * this interface so that we can load the correct ATA timings. The 633 * MVB has a single set of timing registers and these are shared 634 * across channels. As there are two registers we really ought to 635 * track the last two used values as a sort of register window. For 636 * now we just reload on a channel switch. On the single channel 637 * setup this condition never fires so we do nothing extra. 638 * 639 * FIXME: dual channel needs ->serialize support 640 */ 641 642 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) 643 { 644 struct ata_port *ap = qc->ap; 645 struct ata_device *adev = qc->dev; 646 647 /* If timings are set and for the wrong channel (2nd test is 648 due to a libata shortcoming and will eventually go I hope) */ 649 if (ap->host->private_data != ap->host 650 && ap->host->private_data != NULL) 651 opti82c46x_set_piomode(ap, adev); 652 653 return ata_sff_qc_issue(qc); 654 } 655 656 static struct ata_port_operations opti82c46x_port_ops = { 657 .inherits = &legacy_base_port_ops, 658 .set_piomode = opti82c46x_set_piomode, 659 .qc_issue = opti82c46x_qc_issue, 660 }; 661 662 /** 663 * qdi65x0_set_piomode - PIO setup for QDI65x0 664 * @ap: Port 665 * @adev: Device 666 * 667 * In single channel mode the 6580 has one clock per device and we can 668 * avoid the requirement to clock switch. We also have to load the timing 669 * into the right clock according to whether we are master or slave. 670 * 671 * In dual channel mode the 6580 has one clock per channel and we have 672 * to software clockswitch in qc_issue. 673 */ 674 675 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev) 676 { 677 struct ata_timing t; 678 struct legacy_data *ld_qdi = ap->host->private_data; 679 int active, recovery; 680 u8 timing; 681 682 /* Get the timing data in cycles */ 683 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 684 685 if (ld_qdi->fast) { 686 active = 8 - clamp_val(t.active, 1, 8); 687 recovery = 18 - clamp_val(t.recover, 3, 18); 688 } else { 689 active = 9 - clamp_val(t.active, 2, 9); 690 recovery = 15 - clamp_val(t.recover, 0, 15); 691 } 692 timing = (recovery << 4) | active | 0x08; 693 ld_qdi->clock[adev->devno] = timing; 694 695 if (ld_qdi->type == QDI6580) 696 outb(timing, ld_qdi->timing + 2 * adev->devno); 697 else 698 outb(timing, ld_qdi->timing + 2 * ap->port_no); 699 700 /* Clear the FIFO */ 701 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA) 702 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); 703 } 704 705 /** 706 * qdi_qc_issue - command issue 707 * @qc: command pending 708 * 709 * Called when the libata layer is about to issue a command. We wrap 710 * this interface so that we can load the correct ATA timings. 711 */ 712 713 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) 714 { 715 struct ata_port *ap = qc->ap; 716 struct ata_device *adev = qc->dev; 717 struct legacy_data *ld_qdi = ap->host->private_data; 718 719 if (ld_qdi->clock[adev->devno] != ld_qdi->last) { 720 if (adev->pio_mode) { 721 ld_qdi->last = ld_qdi->clock[adev->devno]; 722 outb(ld_qdi->clock[adev->devno], ld_qdi->timing + 723 2 * ap->port_no); 724 } 725 } 726 return ata_sff_qc_issue(qc); 727 } 728 729 static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc, 730 unsigned char *buf, 731 unsigned int buflen, int rw) 732 { 733 struct ata_device *adev = qc->dev; 734 struct ata_port *ap = adev->link->ap; 735 int slop = buflen & 3; 736 737 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) 738 && (ap->pflags & ATA_PFLAG_PIO32)) { 739 if (rw == WRITE) 740 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 741 else 742 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 743 744 if (unlikely(slop)) { 745 __le32 pad; 746 if (rw == WRITE) { 747 memcpy(&pad, buf + buflen - slop, slop); 748 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 749 } else { 750 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 751 memcpy(buf + buflen - slop, &pad, slop); 752 } 753 } 754 return (buflen + 3) & ~3; 755 } else 756 return ata_sff_data_xfer(qc, buf, buflen, rw); 757 } 758 759 static int qdi_port(struct platform_device *dev, 760 struct legacy_probe *lp, struct legacy_data *ld) 761 { 762 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) 763 return -EBUSY; 764 ld->timing = lp->private; 765 return 0; 766 } 767 768 static struct ata_port_operations qdi6500_port_ops = { 769 .inherits = &legacy_base_port_ops, 770 .set_piomode = qdi65x0_set_piomode, 771 .qc_issue = qdi_qc_issue, 772 .sff_data_xfer = vlb32_data_xfer, 773 }; 774 775 static struct ata_port_operations qdi6580_port_ops = { 776 .inherits = &legacy_base_port_ops, 777 .set_piomode = qdi65x0_set_piomode, 778 .sff_data_xfer = vlb32_data_xfer, 779 }; 780 781 static struct ata_port_operations qdi6580dp_port_ops = { 782 .inherits = &legacy_base_port_ops, 783 .set_piomode = qdi65x0_set_piomode, 784 .qc_issue = qdi_qc_issue, 785 .sff_data_xfer = vlb32_data_xfer, 786 }; 787 788 static DEFINE_SPINLOCK(winbond_lock); 789 790 static void winbond_writecfg(unsigned long port, u8 reg, u8 val) 791 { 792 unsigned long flags; 793 spin_lock_irqsave(&winbond_lock, flags); 794 outb(reg, port + 0x01); 795 outb(val, port + 0x02); 796 spin_unlock_irqrestore(&winbond_lock, flags); 797 } 798 799 static u8 winbond_readcfg(unsigned long port, u8 reg) 800 { 801 u8 val; 802 803 unsigned long flags; 804 spin_lock_irqsave(&winbond_lock, flags); 805 outb(reg, port + 0x01); 806 val = inb(port + 0x02); 807 spin_unlock_irqrestore(&winbond_lock, flags); 808 809 return val; 810 } 811 812 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) 813 { 814 struct ata_timing t; 815 struct legacy_data *ld_winbond = ap->host->private_data; 816 int active, recovery; 817 u8 reg; 818 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); 819 820 reg = winbond_readcfg(ld_winbond->timing, 0x81); 821 822 /* Get the timing data in cycles */ 823 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ 824 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 825 else 826 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 827 828 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; 829 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; 830 timing = (active << 4) | recovery; 831 winbond_writecfg(ld_winbond->timing, timing, reg); 832 833 /* Load the setup timing */ 834 835 reg = 0x35; 836 if (adev->class != ATA_DEV_ATA) 837 reg |= 0x08; /* FIFO off */ 838 if (!ata_pio_need_iordy(adev)) 839 reg |= 0x02; /* IORDY off */ 840 reg |= (clamp_val(t.setup, 0, 3) << 6); 841 winbond_writecfg(ld_winbond->timing, timing + 1, reg); 842 } 843 844 static int winbond_port(struct platform_device *dev, 845 struct legacy_probe *lp, struct legacy_data *ld) 846 { 847 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) 848 return -EBUSY; 849 ld->timing = lp->private; 850 return 0; 851 } 852 853 static struct ata_port_operations winbond_port_ops = { 854 .inherits = &legacy_base_port_ops, 855 .set_piomode = winbond_set_piomode, 856 .sff_data_xfer = vlb32_data_xfer, 857 }; 858 859 static struct legacy_controller controllers[] = { 860 {"BIOS", &legacy_port_ops, ATA_PIO4, 861 ATA_FLAG_NO_IORDY, 0, NULL }, 862 {"Snooping", &simple_port_ops, ATA_PIO4, 863 0, 0, NULL }, 864 {"PDC20230", &pdc20230_port_ops, ATA_PIO2, 865 ATA_FLAG_NO_IORDY, 866 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, 867 {"HT6560A", &ht6560a_port_ops, ATA_PIO2, 868 ATA_FLAG_NO_IORDY, 0, NULL }, 869 {"HT6560B", &ht6560b_port_ops, ATA_PIO4, 870 ATA_FLAG_NO_IORDY, 0, NULL }, 871 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3, 872 0, 0, NULL }, 873 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3, 874 0, 0, NULL }, 875 {"QDI6500", &qdi6500_port_ops, ATA_PIO2, 876 ATA_FLAG_NO_IORDY, 877 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 878 {"QDI6580", &qdi6580_port_ops, ATA_PIO4, 879 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 880 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4, 881 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 882 {"W83759A", &winbond_port_ops, ATA_PIO4, 883 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, 884 winbond_port } 885 }; 886 887 /** 888 * probe_chip_type - Discover controller 889 * @probe: Probe entry to check 890 * 891 * Probe an ATA port and identify the type of controller. We don't 892 * check if the controller appears to be driveless at this point. 893 */ 894 895 static __init int probe_chip_type(struct legacy_probe *probe) 896 { 897 int mask = 1 << probe->slot; 898 899 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { 900 u8 reg = winbond_readcfg(winbond, 0x81); 901 reg |= 0x80; /* jumpered mode off */ 902 winbond_writecfg(winbond, 0x81, reg); 903 reg = winbond_readcfg(winbond, 0x83); 904 reg |= 0xF0; /* local control */ 905 winbond_writecfg(winbond, 0x83, reg); 906 reg = winbond_readcfg(winbond, 0x85); 907 reg |= 0xF0; /* programmable timing */ 908 winbond_writecfg(winbond, 0x85, reg); 909 910 reg = winbond_readcfg(winbond, 0x81); 911 912 if (reg & mask) 913 return W83759A; 914 } 915 if (probe->port == 0x1F0) { 916 unsigned long flags; 917 local_irq_save(flags); 918 /* Probes */ 919 outb(inb(0x1F2) | 0x80, 0x1F2); 920 inb(0x1F5); 921 inb(0x1F2); 922 inb(0x3F6); 923 inb(0x3F6); 924 inb(0x1F2); 925 inb(0x1F2); 926 927 if ((inb(0x1F2) & 0x80) == 0) { 928 /* PDC20230c or 20630 ? */ 929 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" 930 " detected.\n"); 931 udelay(100); 932 inb(0x1F5); 933 local_irq_restore(flags); 934 return PDC20230; 935 } else { 936 outb(0x55, 0x1F2); 937 inb(0x1F2); 938 inb(0x1F2); 939 if (inb(0x1F2) == 0x00) 940 printk(KERN_INFO "PDC20230-B VLB ATA " 941 "controller detected.\n"); 942 local_irq_restore(flags); 943 return BIOS; 944 } 945 } 946 947 if (ht6560a & mask) 948 return HT6560A; 949 if (ht6560b & mask) 950 return HT6560B; 951 if (opti82c611a & mask) 952 return OPTI611A; 953 if (opti82c46x & mask) 954 return OPTI46X; 955 if (autospeed & mask) 956 return SNOOP; 957 return BIOS; 958 } 959 960 961 /** 962 * legacy_init_one - attach a legacy interface 963 * @probe: probe record 964 * 965 * Register an ISA bus IDE interface. Such interfaces are PIO and we 966 * assume do not support IRQ sharing. 967 */ 968 969 static __init int legacy_init_one(struct legacy_probe *probe) 970 { 971 struct legacy_controller *controller = &controllers[probe->type]; 972 int pio_modes = controller->pio_mask; 973 unsigned long io = probe->port; 974 u32 mask = (1 << probe->slot); 975 struct ata_port_operations *ops = controller->ops; 976 struct legacy_data *ld = &legacy_data[probe->slot]; 977 struct ata_host *host = NULL; 978 struct ata_port *ap; 979 struct platform_device *pdev; 980 struct ata_device *dev; 981 void __iomem *io_addr, *ctrl_addr; 982 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; 983 int ret; 984 985 iordy |= controller->flags; 986 987 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); 988 if (IS_ERR(pdev)) 989 return PTR_ERR(pdev); 990 991 ret = -EBUSY; 992 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || 993 devm_request_region(&pdev->dev, io + 0x0206, 1, 994 "pata_legacy") == NULL) 995 goto fail; 996 997 ret = -ENOMEM; 998 io_addr = devm_ioport_map(&pdev->dev, io, 8); 999 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); 1000 if (!io_addr || !ctrl_addr) 1001 goto fail; 1002 ld->type = probe->type; 1003 if (controller->setup) 1004 if (controller->setup(pdev, probe, ld) < 0) 1005 goto fail; 1006 host = ata_host_alloc(&pdev->dev, 1); 1007 if (!host) 1008 goto fail; 1009 ap = host->ports[0]; 1010 1011 ap->ops = ops; 1012 ap->pio_mask = pio_modes; 1013 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; 1014 ap->pflags |= controller->pflags; 1015 ap->ioaddr.cmd_addr = io_addr; 1016 ap->ioaddr.altstatus_addr = ctrl_addr; 1017 ap->ioaddr.ctl_addr = ctrl_addr; 1018 ata_sff_std_ports(&ap->ioaddr); 1019 ap->host->private_data = ld; 1020 1021 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); 1022 1023 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, 1024 &legacy_sht); 1025 if (ret) 1026 goto fail; 1027 async_synchronize_full(); 1028 ld->platform_dev = pdev; 1029 1030 /* Nothing found means we drop the port as its probably not there */ 1031 1032 ret = -ENODEV; 1033 ata_for_each_dev(dev, &ap->link, ALL) { 1034 if (!ata_dev_absent(dev)) { 1035 legacy_host[probe->slot] = host; 1036 ld->platform_dev = pdev; 1037 return 0; 1038 } 1039 } 1040 ata_host_detach(host); 1041 fail: 1042 platform_device_unregister(pdev); 1043 return ret; 1044 } 1045 1046 /** 1047 * legacy_check_special_cases - ATA special cases 1048 * @p: PCI device to check 1049 * @primary: set this if we find an ATA master 1050 * @secondary: set this if we find an ATA secondary 1051 * 1052 * A small number of vendors implemented early PCI ATA interfaces 1053 * on bridge logic without the ATA interface being PCI visible. 1054 * Where we have a matching PCI driver we must skip the relevant 1055 * device here. If we don't know about it then the legacy driver 1056 * is the right driver anyway. 1057 */ 1058 1059 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, 1060 int *secondary) 1061 { 1062 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ 1063 if (p->vendor == 0x1078 && p->device == 0x0000) { 1064 *primary = *secondary = 1; 1065 return; 1066 } 1067 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ 1068 if (p->vendor == 0x1078 && p->device == 0x0002) { 1069 *primary = *secondary = 1; 1070 return; 1071 } 1072 /* Intel MPIIX - PIO ATA on non PCI side of bridge */ 1073 if (p->vendor == 0x8086 && p->device == 0x1234) { 1074 u16 r; 1075 pci_read_config_word(p, 0x6C, &r); 1076 if (r & 0x8000) { 1077 /* ATA port enabled */ 1078 if (r & 0x4000) 1079 *secondary = 1; 1080 else 1081 *primary = 1; 1082 } 1083 return; 1084 } 1085 } 1086 1087 static __init void probe_opti_vlb(void) 1088 { 1089 /* If an OPTI 82C46X is present find out where the channels are */ 1090 static const char *optis[4] = { 1091 "3/463MV", "5MV", 1092 "5MVA", "5MVB" 1093 }; 1094 u8 chans = 1; 1095 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; 1096 1097 opti82c46x = 3; /* Assume master and slave first */ 1098 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", 1099 optis[ctrl]); 1100 if (ctrl == 3) 1101 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; 1102 ctrl = opti_syscfg(0xAC); 1103 /* Check enabled and this port is the 465MV port. On the 1104 MVB we may have two channels */ 1105 if (ctrl & 8) { 1106 if (chans == 2) { 1107 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1108 legacy_probe_add(0x170, 15, OPTI46X, 0); 1109 } 1110 if (ctrl & 4) 1111 legacy_probe_add(0x170, 15, OPTI46X, 0); 1112 else 1113 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1114 } else 1115 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1116 } 1117 1118 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) 1119 { 1120 static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; 1121 /* Check card type */ 1122 if ((r & 0xF0) == 0xC0) { 1123 /* QD6500: single channel */ 1124 if (r & 8) 1125 /* Disabled ? */ 1126 return; 1127 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1128 QDI6500, port); 1129 } 1130 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { 1131 /* QD6580: dual channel */ 1132 if (!request_region(port + 2 , 2, "pata_qdi")) { 1133 release_region(port, 2); 1134 return; 1135 } 1136 res = inb(port + 3); 1137 /* Single channel mode ? */ 1138 if (res & 1) 1139 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1140 QDI6580, port); 1141 else { /* Dual channel mode */ 1142 legacy_probe_add(0x1F0, 14, QDI6580DP, port); 1143 /* port + 0x02, r & 0x04 */ 1144 legacy_probe_add(0x170, 15, QDI6580DP, port + 2); 1145 } 1146 release_region(port + 2, 2); 1147 } 1148 } 1149 1150 static __init void probe_qdi_vlb(void) 1151 { 1152 unsigned long flags; 1153 static const unsigned long qd_port[2] = { 0x30, 0xB0 }; 1154 int i; 1155 1156 /* 1157 * Check each possible QD65xx base address 1158 */ 1159 1160 for (i = 0; i < 2; i++) { 1161 unsigned long port = qd_port[i]; 1162 u8 r, res; 1163 1164 1165 if (request_region(port, 2, "pata_qdi")) { 1166 /* Check for a card */ 1167 local_irq_save(flags); 1168 /* I have no h/w that needs this delay but it 1169 is present in the historic code */ 1170 r = inb(port); 1171 udelay(1); 1172 outb(0x19, port); 1173 udelay(1); 1174 res = inb(port); 1175 udelay(1); 1176 outb(r, port); 1177 udelay(1); 1178 local_irq_restore(flags); 1179 1180 /* Fail */ 1181 if (res == 0x19) { 1182 release_region(port, 2); 1183 continue; 1184 } 1185 /* Passes the presence test */ 1186 r = inb(port + 1); 1187 udelay(1); 1188 /* Check port agrees with port set */ 1189 if ((r & 2) >> 1 == i) 1190 qdi65_identify_port(r, res, port); 1191 release_region(port, 2); 1192 } 1193 } 1194 } 1195 1196 /** 1197 * legacy_init - attach legacy interfaces 1198 * 1199 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. 1200 * Right now we do not scan the ide0 and ide1 address but should do so 1201 * for non PCI systems or systems with no PCI IDE legacy mode devices. 1202 * If you fix that note there are special cases to consider like VLB 1203 * drivers and CS5510/20. 1204 */ 1205 1206 static __init int legacy_init(void) 1207 { 1208 int i; 1209 int ct = 0; 1210 int primary = 0; 1211 int secondary = 0; 1212 int pci_present = 0; 1213 struct legacy_probe *pl = &probe_list[0]; 1214 int slot = 0; 1215 1216 struct pci_dev *p = NULL; 1217 1218 for_each_pci_dev(p) { 1219 int r; 1220 /* Check for any overlap of the system ATA mappings. Native 1221 mode controllers stuck on these addresses or some devices 1222 in 'raid' mode won't be found by the storage class test */ 1223 for (r = 0; r < 6; r++) { 1224 if (pci_resource_start(p, r) == 0x1f0) 1225 primary = 1; 1226 if (pci_resource_start(p, r) == 0x170) 1227 secondary = 1; 1228 } 1229 /* Check for special cases */ 1230 legacy_check_special_cases(p, &primary, &secondary); 1231 1232 /* If PCI bus is present then don't probe for tertiary 1233 legacy ports */ 1234 pci_present = 1; 1235 } 1236 1237 if (winbond == 1) 1238 winbond = 0x130; /* Default port, alt is 1B0 */ 1239 1240 if (primary == 0 || all) 1241 legacy_probe_add(0x1F0, 14, UNKNOWN, 0); 1242 if (secondary == 0 || all) 1243 legacy_probe_add(0x170, 15, UNKNOWN, 0); 1244 1245 if (probe_all || !pci_present) { 1246 /* ISA/VLB extra ports */ 1247 legacy_probe_add(0x1E8, 11, UNKNOWN, 0); 1248 legacy_probe_add(0x168, 10, UNKNOWN, 0); 1249 legacy_probe_add(0x1E0, 8, UNKNOWN, 0); 1250 legacy_probe_add(0x160, 12, UNKNOWN, 0); 1251 } 1252 1253 if (opti82c46x) 1254 probe_opti_vlb(); 1255 if (qdi) 1256 probe_qdi_vlb(); 1257 1258 for (i = 0; i < NR_HOST; i++, pl++) { 1259 if (pl->port == 0) 1260 continue; 1261 if (pl->type == UNKNOWN) 1262 pl->type = probe_chip_type(pl); 1263 pl->slot = slot++; 1264 if (legacy_init_one(pl) == 0) 1265 ct++; 1266 } 1267 if (ct != 0) 1268 return 0; 1269 return -ENODEV; 1270 } 1271 1272 static __exit void legacy_exit(void) 1273 { 1274 int i; 1275 1276 for (i = 0; i < nr_legacy_host; i++) { 1277 struct legacy_data *ld = &legacy_data[i]; 1278 ata_host_detach(legacy_host[i]); 1279 platform_device_unregister(ld->platform_dev); 1280 } 1281 } 1282 1283 MODULE_AUTHOR("Alan Cox"); 1284 MODULE_DESCRIPTION("low-level driver for legacy ATA"); 1285 MODULE_LICENSE("GPL"); 1286 MODULE_VERSION(DRV_VERSION); 1287 MODULE_ALIAS("pata_qdi"); 1288 MODULE_ALIAS("pata_winbond"); 1289 1290 module_init(legacy_init); 1291 module_exit(legacy_exit); 1292