1 /* 2 * pata-legacy.c - Legacy port PATA/SATA controller driver. 3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2, or (at your option) 8 * any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; see the file COPYING. If not, write to 17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * An ATA driver for the legacy ATA ports. 20 * 21 * Data Sources: 22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com 23 * HT6560 series: 24 * Promise 20230/20620: 25 * http://www.ryston.cz/petr/vlb/pdc20230b.html 26 * http://www.ryston.cz/petr/vlb/pdc20230c.html 27 * http://www.ryston.cz/petr/vlb/pdc20630.html 28 * 29 * Unsupported but docs exist: 30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 31 * 32 * This driver handles legacy (that is "ISA/VLB side") IDE ports found 33 * on PC class systems. There are three hybrid devices that are exceptions 34 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and 35 * the MPIIX where the tuning is PCI side but the IDE is "ISA side". 36 * 37 * Specific support is included for the ht6560a/ht6560b/opti82c611a/ 38 * opti82c465mv/promise 20230c/20630/winbond83759A 39 * 40 * Use the autospeed and pio_mask options with: 41 * Appian ADI/2 aka CLPD7220 or AIC25VL01. 42 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with 43 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, 44 * Winbond W83759A, Promise PDC20230-B 45 * 46 * For now use autospeed and pio_mask as above with the W83759A. This may 47 * change. 48 * 49 */ 50 51 #include <linux/kernel.h> 52 #include <linux/module.h> 53 #include <linux/pci.h> 54 #include <linux/init.h> 55 #include <linux/blkdev.h> 56 #include <linux/delay.h> 57 #include <scsi/scsi_host.h> 58 #include <linux/ata.h> 59 #include <linux/libata.h> 60 #include <linux/platform_device.h> 61 62 #define DRV_NAME "pata_legacy" 63 #define DRV_VERSION "0.6.5" 64 65 #define NR_HOST 6 66 67 static int all; 68 module_param(all, int, 0444); 69 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); 70 71 struct legacy_data { 72 unsigned long timing; 73 u8 clock[2]; 74 u8 last; 75 int fast; 76 struct platform_device *platform_dev; 77 78 }; 79 80 enum controller { 81 BIOS = 0, 82 SNOOP = 1, 83 PDC20230 = 2, 84 HT6560A = 3, 85 HT6560B = 4, 86 OPTI611A = 5, 87 OPTI46X = 6, 88 QDI6500 = 7, 89 QDI6580 = 8, 90 QDI6580DP = 9, /* Dual channel mode is different */ 91 W83759A = 10, 92 93 UNKNOWN = -1 94 }; 95 96 97 struct legacy_probe { 98 unsigned char *name; 99 unsigned long port; 100 unsigned int irq; 101 unsigned int slot; 102 enum controller type; 103 unsigned long private; 104 }; 105 106 struct legacy_controller { 107 const char *name; 108 struct ata_port_operations *ops; 109 unsigned int pio_mask; 110 unsigned int flags; 111 int (*setup)(struct platform_device *, struct legacy_probe *probe, 112 struct legacy_data *data); 113 }; 114 115 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; 116 117 static struct legacy_probe probe_list[NR_HOST]; 118 static struct legacy_data legacy_data[NR_HOST]; 119 static struct ata_host *legacy_host[NR_HOST]; 120 static int nr_legacy_host; 121 122 123 static int probe_all; /* Set to check all ISA port ranges */ 124 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ 125 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ 126 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ 127 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ 128 static int qdi; /* Set to probe QDI controllers */ 129 static int winbond; /* Set to probe Winbond controllers, 130 give I/O port if non stdanard */ 131 static int autospeed; /* Chip present which snoops speed changes */ 132 static int pio_mask = 0x1F; /* PIO range for autospeed devices */ 133 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ 134 135 /** 136 * legacy_probe_add - Add interface to probe list 137 * @port: Controller port 138 * @irq: IRQ number 139 * @type: Controller type 140 * @private: Controller specific info 141 * 142 * Add an entry into the probe list for ATA controllers. This is used 143 * to add the default ISA slots and then to build up the table 144 * further according to other ISA/VLB/Weird device scans 145 * 146 * An I/O port list is used to keep ordering stable and sane, as we 147 * don't have any good way to talk about ordering otherwise 148 */ 149 150 static int legacy_probe_add(unsigned long port, unsigned int irq, 151 enum controller type, unsigned long private) 152 { 153 struct legacy_probe *lp = &probe_list[0]; 154 int i; 155 struct legacy_probe *free = NULL; 156 157 for (i = 0; i < NR_HOST; i++) { 158 if (lp->port == 0 && free == NULL) 159 free = lp; 160 /* Matching port, or the correct slot for ordering */ 161 if (lp->port == port || legacy_port[i] == port) { 162 free = lp; 163 break; 164 } 165 lp++; 166 } 167 if (free == NULL) { 168 printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); 169 return -1; 170 } 171 /* Fill in the entry for later probing */ 172 free->port = port; 173 free->irq = irq; 174 free->type = type; 175 free->private = private; 176 return 0; 177 } 178 179 180 /** 181 * legacy_set_mode - mode setting 182 * @link: IDE link 183 * @unused: Device that failed when error is returned 184 * 185 * Use a non standard set_mode function. We don't want to be tuned. 186 * 187 * The BIOS configured everything. Our job is not to fiddle. Just use 188 * whatever PIO the hardware is using and leave it at that. When we 189 * get some kind of nice user driven API for control then we can 190 * expand on this as per hdparm in the base kernel. 191 */ 192 193 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) 194 { 195 struct ata_device *dev; 196 197 ata_link_for_each_dev(dev, link) { 198 if (ata_dev_enabled(dev)) { 199 ata_dev_printk(dev, KERN_INFO, 200 "configured for PIO\n"); 201 dev->pio_mode = XFER_PIO_0; 202 dev->xfer_mode = XFER_PIO_0; 203 dev->xfer_shift = ATA_SHIFT_PIO; 204 dev->flags |= ATA_DFLAG_PIO; 205 } 206 } 207 return 0; 208 } 209 210 static struct scsi_host_template legacy_sht = { 211 .module = THIS_MODULE, 212 .name = DRV_NAME, 213 .ioctl = ata_scsi_ioctl, 214 .queuecommand = ata_scsi_queuecmd, 215 .can_queue = ATA_DEF_QUEUE, 216 .this_id = ATA_SHT_THIS_ID, 217 .sg_tablesize = LIBATA_MAX_PRD, 218 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 219 .emulated = ATA_SHT_EMULATED, 220 .use_clustering = ATA_SHT_USE_CLUSTERING, 221 .proc_name = DRV_NAME, 222 .dma_boundary = ATA_DMA_BOUNDARY, 223 .slave_configure = ata_scsi_slave_config, 224 .slave_destroy = ata_scsi_slave_destroy, 225 .bios_param = ata_std_bios_param, 226 }; 227 228 /* 229 * These ops are used if the user indicates the hardware 230 * snoops the commands to decide on the mode and handles the 231 * mode selection "magically" itself. Several legacy controllers 232 * do this. The mode range can be set if it is not 0x1F by setting 233 * pio_mask as well. 234 */ 235 236 static struct ata_port_operations simple_port_ops = { 237 .tf_load = ata_tf_load, 238 .tf_read = ata_tf_read, 239 .check_status = ata_check_status, 240 .exec_command = ata_exec_command, 241 .dev_select = ata_std_dev_select, 242 243 .freeze = ata_bmdma_freeze, 244 .thaw = ata_bmdma_thaw, 245 .error_handler = ata_bmdma_error_handler, 246 .post_internal_cmd = ata_bmdma_post_internal_cmd, 247 .cable_detect = ata_cable_40wire, 248 249 .qc_prep = ata_qc_prep, 250 .qc_issue = ata_qc_issue_prot, 251 252 .data_xfer = ata_data_xfer_noirq, 253 254 .irq_handler = ata_interrupt, 255 .irq_clear = ata_bmdma_irq_clear, 256 .irq_on = ata_irq_on, 257 258 .port_start = ata_sff_port_start, 259 }; 260 261 static struct ata_port_operations legacy_port_ops = { 262 .set_mode = legacy_set_mode, 263 264 .tf_load = ata_tf_load, 265 .tf_read = ata_tf_read, 266 .check_status = ata_check_status, 267 .exec_command = ata_exec_command, 268 .dev_select = ata_std_dev_select, 269 .cable_detect = ata_cable_40wire, 270 271 .freeze = ata_bmdma_freeze, 272 .thaw = ata_bmdma_thaw, 273 .error_handler = ata_bmdma_error_handler, 274 .post_internal_cmd = ata_bmdma_post_internal_cmd, 275 276 .qc_prep = ata_qc_prep, 277 .qc_issue = ata_qc_issue_prot, 278 279 .data_xfer = ata_data_xfer_noirq, 280 281 .irq_handler = ata_interrupt, 282 .irq_clear = ata_bmdma_irq_clear, 283 .irq_on = ata_irq_on, 284 285 .port_start = ata_sff_port_start, 286 }; 287 288 /* 289 * Promise 20230C and 20620 support 290 * 291 * This controller supports PIO0 to PIO2. We set PIO timings 292 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA 293 * support is weird being DMA to controller and PIO'd to the host 294 * and not supported. 295 */ 296 297 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) 298 { 299 int tries = 5; 300 int pio = adev->pio_mode - XFER_PIO_0; 301 u8 rt; 302 unsigned long flags; 303 304 /* Safe as UP only. Force I/Os to occur together */ 305 306 local_irq_save(flags); 307 308 /* Unlock the control interface */ 309 do { 310 inb(0x1F5); 311 outb(inb(0x1F2) | 0x80, 0x1F2); 312 inb(0x1F2); 313 inb(0x3F6); 314 inb(0x3F6); 315 inb(0x1F2); 316 inb(0x1F2); 317 } 318 while ((inb(0x1F2) & 0x80) && --tries); 319 320 local_irq_restore(flags); 321 322 outb(inb(0x1F4) & 0x07, 0x1F4); 323 324 rt = inb(0x1F3); 325 rt &= 0x07 << (3 * adev->devno); 326 if (pio) 327 rt |= (1 + 3 * pio) << (3 * adev->devno); 328 329 udelay(100); 330 outb(inb(0x1F2) | 0x01, 0x1F2); 331 udelay(100); 332 inb(0x1F5); 333 334 } 335 336 static unsigned int pdc_data_xfer_vlb(struct ata_device *dev, 337 unsigned char *buf, unsigned int buflen, int rw) 338 { 339 if (ata_id_has_dword_io(dev->id)) { 340 struct ata_port *ap = dev->link->ap; 341 int slop = buflen & 3; 342 unsigned long flags; 343 344 local_irq_save(flags); 345 346 /* Perform the 32bit I/O synchronization sequence */ 347 ioread8(ap->ioaddr.nsect_addr); 348 ioread8(ap->ioaddr.nsect_addr); 349 ioread8(ap->ioaddr.nsect_addr); 350 351 /* Now the data */ 352 if (rw == READ) 353 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 354 else 355 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 356 357 if (unlikely(slop)) { 358 u32 pad; 359 if (rw == READ) { 360 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 361 memcpy(buf + buflen - slop, &pad, slop); 362 } else { 363 memcpy(&pad, buf + buflen - slop, slop); 364 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 365 } 366 buflen += 4 - slop; 367 } 368 local_irq_restore(flags); 369 } else 370 buflen = ata_data_xfer_noirq(dev, buf, buflen, rw); 371 372 return buflen; 373 } 374 375 static struct ata_port_operations pdc20230_port_ops = { 376 .set_piomode = pdc20230_set_piomode, 377 378 .tf_load = ata_tf_load, 379 .tf_read = ata_tf_read, 380 .check_status = ata_check_status, 381 .exec_command = ata_exec_command, 382 .dev_select = ata_std_dev_select, 383 384 .freeze = ata_bmdma_freeze, 385 .thaw = ata_bmdma_thaw, 386 .error_handler = ata_bmdma_error_handler, 387 .post_internal_cmd = ata_bmdma_post_internal_cmd, 388 .cable_detect = ata_cable_40wire, 389 390 .qc_prep = ata_qc_prep, 391 .qc_issue = ata_qc_issue_prot, 392 393 .data_xfer = pdc_data_xfer_vlb, 394 395 .irq_handler = ata_interrupt, 396 .irq_clear = ata_bmdma_irq_clear, 397 .irq_on = ata_irq_on, 398 399 .port_start = ata_sff_port_start, 400 }; 401 402 /* 403 * Holtek 6560A support 404 * 405 * This controller supports PIO0 to PIO2 (no IORDY even though higher 406 * timings can be loaded). 407 */ 408 409 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) 410 { 411 u8 active, recover; 412 struct ata_timing t; 413 414 /* Get the timing data in cycles. For now play safe at 50Mhz */ 415 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 416 417 active = FIT(t.active, 2, 15); 418 recover = FIT(t.recover, 4, 15); 419 420 inb(0x3E6); 421 inb(0x3E6); 422 inb(0x3E6); 423 inb(0x3E6); 424 425 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 426 ioread8(ap->ioaddr.status_addr); 427 } 428 429 static struct ata_port_operations ht6560a_port_ops = { 430 .set_piomode = ht6560a_set_piomode, 431 432 .tf_load = ata_tf_load, 433 .tf_read = ata_tf_read, 434 .check_status = ata_check_status, 435 .exec_command = ata_exec_command, 436 .dev_select = ata_std_dev_select, 437 438 .freeze = ata_bmdma_freeze, 439 .thaw = ata_bmdma_thaw, 440 .error_handler = ata_bmdma_error_handler, 441 .post_internal_cmd = ata_bmdma_post_internal_cmd, 442 .cable_detect = ata_cable_40wire, 443 444 .qc_prep = ata_qc_prep, 445 .qc_issue = ata_qc_issue_prot, 446 447 .data_xfer = ata_data_xfer, /* Check vlb/noirq */ 448 449 .irq_handler = ata_interrupt, 450 .irq_clear = ata_bmdma_irq_clear, 451 .irq_on = ata_irq_on, 452 453 .port_start = ata_sff_port_start, 454 }; 455 456 /* 457 * Holtek 6560B support 458 * 459 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO 460 * setting unless we see an ATAPI device in which case we force it off. 461 * 462 * FIXME: need to implement 2nd channel support. 463 */ 464 465 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) 466 { 467 u8 active, recover; 468 struct ata_timing t; 469 470 /* Get the timing data in cycles. For now play safe at 50Mhz */ 471 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 472 473 active = FIT(t.active, 2, 15); 474 recover = FIT(t.recover, 2, 16); 475 recover &= 0x15; 476 477 inb(0x3E6); 478 inb(0x3E6); 479 inb(0x3E6); 480 inb(0x3E6); 481 482 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 483 484 if (adev->class != ATA_DEV_ATA) { 485 u8 rconf = inb(0x3E6); 486 if (rconf & 0x24) { 487 rconf &= ~0x24; 488 outb(rconf, 0x3E6); 489 } 490 } 491 ioread8(ap->ioaddr.status_addr); 492 } 493 494 static struct ata_port_operations ht6560b_port_ops = { 495 .set_piomode = ht6560b_set_piomode, 496 497 .tf_load = ata_tf_load, 498 .tf_read = ata_tf_read, 499 .check_status = ata_check_status, 500 .exec_command = ata_exec_command, 501 .dev_select = ata_std_dev_select, 502 503 .freeze = ata_bmdma_freeze, 504 .thaw = ata_bmdma_thaw, 505 .error_handler = ata_bmdma_error_handler, 506 .post_internal_cmd = ata_bmdma_post_internal_cmd, 507 .cable_detect = ata_cable_40wire, 508 509 .qc_prep = ata_qc_prep, 510 .qc_issue = ata_qc_issue_prot, 511 512 .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */ 513 514 .irq_handler = ata_interrupt, 515 .irq_clear = ata_bmdma_irq_clear, 516 .irq_on = ata_irq_on, 517 518 .port_start = ata_sff_port_start, 519 }; 520 521 /* 522 * Opti core chipset helpers 523 */ 524 525 /** 526 * opti_syscfg - read OPTI chipset configuration 527 * @reg: Configuration register to read 528 * 529 * Returns the value of an OPTI system board configuration register. 530 */ 531 532 static u8 opti_syscfg(u8 reg) 533 { 534 unsigned long flags; 535 u8 r; 536 537 /* Uniprocessor chipset and must force cycles adjancent */ 538 local_irq_save(flags); 539 outb(reg, 0x22); 540 r = inb(0x24); 541 local_irq_restore(flags); 542 return r; 543 } 544 545 /* 546 * Opti 82C611A 547 * 548 * This controller supports PIO0 to PIO3. 549 */ 550 551 static void opti82c611a_set_piomode(struct ata_port *ap, 552 struct ata_device *adev) 553 { 554 u8 active, recover, setup; 555 struct ata_timing t; 556 struct ata_device *pair = ata_dev_pair(adev); 557 int clock; 558 int khz[4] = { 50000, 40000, 33000, 25000 }; 559 u8 rc; 560 561 /* Enter configuration mode */ 562 ioread16(ap->ioaddr.error_addr); 563 ioread16(ap->ioaddr.error_addr); 564 iowrite8(3, ap->ioaddr.nsect_addr); 565 566 /* Read VLB clock strapping */ 567 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; 568 569 /* Get the timing data in cycles */ 570 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 571 572 /* Setup timing is shared */ 573 if (pair) { 574 struct ata_timing tp; 575 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 576 577 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 578 } 579 580 active = FIT(t.active, 2, 17) - 2; 581 recover = FIT(t.recover, 1, 16) - 1; 582 setup = FIT(t.setup, 1, 4) - 1; 583 584 /* Select the right timing bank for write timing */ 585 rc = ioread8(ap->ioaddr.lbal_addr); 586 rc &= 0x7F; 587 rc |= (adev->devno << 7); 588 iowrite8(rc, ap->ioaddr.lbal_addr); 589 590 /* Write the timings */ 591 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 592 593 /* Select the right bank for read timings, also 594 load the shared timings for address */ 595 rc = ioread8(ap->ioaddr.device_addr); 596 rc &= 0xC0; 597 rc |= adev->devno; /* Index select */ 598 rc |= (setup << 4) | 0x04; 599 iowrite8(rc, ap->ioaddr.device_addr); 600 601 /* Load the read timings */ 602 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 603 604 /* Ensure the timing register mode is right */ 605 rc = ioread8(ap->ioaddr.lbal_addr); 606 rc &= 0x73; 607 rc |= 0x84; 608 iowrite8(rc, ap->ioaddr.lbal_addr); 609 610 /* Exit command mode */ 611 iowrite8(0x83, ap->ioaddr.nsect_addr); 612 } 613 614 615 static struct ata_port_operations opti82c611a_port_ops = { 616 .set_piomode = opti82c611a_set_piomode, 617 618 .tf_load = ata_tf_load, 619 .tf_read = ata_tf_read, 620 .check_status = ata_check_status, 621 .exec_command = ata_exec_command, 622 .dev_select = ata_std_dev_select, 623 624 .freeze = ata_bmdma_freeze, 625 .thaw = ata_bmdma_thaw, 626 .error_handler = ata_bmdma_error_handler, 627 .post_internal_cmd = ata_bmdma_post_internal_cmd, 628 .cable_detect = ata_cable_40wire, 629 630 .qc_prep = ata_qc_prep, 631 .qc_issue = ata_qc_issue_prot, 632 633 .data_xfer = ata_data_xfer, 634 635 .irq_handler = ata_interrupt, 636 .irq_clear = ata_bmdma_irq_clear, 637 .irq_on = ata_irq_on, 638 639 .port_start = ata_sff_port_start, 640 }; 641 642 /* 643 * Opti 82C465MV 644 * 645 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB 646 * version is dual channel but doesn't have a lot of unique registers. 647 */ 648 649 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) 650 { 651 u8 active, recover, setup; 652 struct ata_timing t; 653 struct ata_device *pair = ata_dev_pair(adev); 654 int clock; 655 int khz[4] = { 50000, 40000, 33000, 25000 }; 656 u8 rc; 657 u8 sysclk; 658 659 /* Get the clock */ 660 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ 661 662 /* Enter configuration mode */ 663 ioread16(ap->ioaddr.error_addr); 664 ioread16(ap->ioaddr.error_addr); 665 iowrite8(3, ap->ioaddr.nsect_addr); 666 667 /* Read VLB clock strapping */ 668 clock = 1000000000 / khz[sysclk]; 669 670 /* Get the timing data in cycles */ 671 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 672 673 /* Setup timing is shared */ 674 if (pair) { 675 struct ata_timing tp; 676 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 677 678 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 679 } 680 681 active = FIT(t.active, 2, 17) - 2; 682 recover = FIT(t.recover, 1, 16) - 1; 683 setup = FIT(t.setup, 1, 4) - 1; 684 685 /* Select the right timing bank for write timing */ 686 rc = ioread8(ap->ioaddr.lbal_addr); 687 rc &= 0x7F; 688 rc |= (adev->devno << 7); 689 iowrite8(rc, ap->ioaddr.lbal_addr); 690 691 /* Write the timings */ 692 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 693 694 /* Select the right bank for read timings, also 695 load the shared timings for address */ 696 rc = ioread8(ap->ioaddr.device_addr); 697 rc &= 0xC0; 698 rc |= adev->devno; /* Index select */ 699 rc |= (setup << 4) | 0x04; 700 iowrite8(rc, ap->ioaddr.device_addr); 701 702 /* Load the read timings */ 703 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 704 705 /* Ensure the timing register mode is right */ 706 rc = ioread8(ap->ioaddr.lbal_addr); 707 rc &= 0x73; 708 rc |= 0x84; 709 iowrite8(rc, ap->ioaddr.lbal_addr); 710 711 /* Exit command mode */ 712 iowrite8(0x83, ap->ioaddr.nsect_addr); 713 714 /* We need to know this for quad device on the MVB */ 715 ap->host->private_data = ap; 716 } 717 718 /** 719 * opt82c465mv_qc_issue_prot - command issue 720 * @qc: command pending 721 * 722 * Called when the libata layer is about to issue a command. We wrap 723 * this interface so that we can load the correct ATA timings. The 724 * MVB has a single set of timing registers and these are shared 725 * across channels. As there are two registers we really ought to 726 * track the last two used values as a sort of register window. For 727 * now we just reload on a channel switch. On the single channel 728 * setup this condition never fires so we do nothing extra. 729 * 730 * FIXME: dual channel needs ->serialize support 731 */ 732 733 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc) 734 { 735 struct ata_port *ap = qc->ap; 736 struct ata_device *adev = qc->dev; 737 738 /* If timings are set and for the wrong channel (2nd test is 739 due to a libata shortcoming and will eventually go I hope) */ 740 if (ap->host->private_data != ap->host 741 && ap->host->private_data != NULL) 742 opti82c46x_set_piomode(ap, adev); 743 744 return ata_qc_issue_prot(qc); 745 } 746 747 static struct ata_port_operations opti82c46x_port_ops = { 748 .set_piomode = opti82c46x_set_piomode, 749 750 .tf_load = ata_tf_load, 751 .tf_read = ata_tf_read, 752 .check_status = ata_check_status, 753 .exec_command = ata_exec_command, 754 .dev_select = ata_std_dev_select, 755 756 .freeze = ata_bmdma_freeze, 757 .thaw = ata_bmdma_thaw, 758 .error_handler = ata_bmdma_error_handler, 759 .post_internal_cmd = ata_bmdma_post_internal_cmd, 760 .cable_detect = ata_cable_40wire, 761 762 .qc_prep = ata_qc_prep, 763 .qc_issue = opti82c46x_qc_issue_prot, 764 765 .data_xfer = ata_data_xfer, 766 767 .irq_handler = ata_interrupt, 768 .irq_clear = ata_bmdma_irq_clear, 769 .irq_on = ata_irq_on, 770 771 .port_start = ata_sff_port_start, 772 }; 773 774 static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev) 775 { 776 struct ata_timing t; 777 struct legacy_data *qdi = ap->host->private_data; 778 int active, recovery; 779 u8 timing; 780 781 /* Get the timing data in cycles */ 782 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 783 784 if (qdi->fast) { 785 active = 8 - FIT(t.active, 1, 8); 786 recovery = 18 - FIT(t.recover, 3, 18); 787 } else { 788 active = 9 - FIT(t.active, 2, 9); 789 recovery = 15 - FIT(t.recover, 0, 15); 790 } 791 timing = (recovery << 4) | active | 0x08; 792 793 qdi->clock[adev->devno] = timing; 794 795 outb(timing, qdi->timing); 796 } 797 798 /** 799 * qdi6580dp_set_piomode - PIO setup for dual channel 800 * @ap: Port 801 * @adev: Device 802 * @irq: interrupt line 803 * 804 * In dual channel mode the 6580 has one clock per channel and we have 805 * to software clockswitch in qc_issue_prot. 806 */ 807 808 static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev) 809 { 810 struct ata_timing t; 811 struct legacy_data *qdi = ap->host->private_data; 812 int active, recovery; 813 u8 timing; 814 815 /* Get the timing data in cycles */ 816 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 817 818 if (qdi->fast) { 819 active = 8 - FIT(t.active, 1, 8); 820 recovery = 18 - FIT(t.recover, 3, 18); 821 } else { 822 active = 9 - FIT(t.active, 2, 9); 823 recovery = 15 - FIT(t.recover, 0, 15); 824 } 825 timing = (recovery << 4) | active | 0x08; 826 827 qdi->clock[adev->devno] = timing; 828 829 outb(timing, qdi->timing + 2 * ap->port_no); 830 /* Clear the FIFO */ 831 if (adev->class != ATA_DEV_ATA) 832 outb(0x5F, qdi->timing + 3); 833 } 834 835 /** 836 * qdi6580_set_piomode - PIO setup for single channel 837 * @ap: Port 838 * @adev: Device 839 * 840 * In single channel mode the 6580 has one clock per device and we can 841 * avoid the requirement to clock switch. We also have to load the timing 842 * into the right clock according to whether we are master or slave. 843 */ 844 845 static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev) 846 { 847 struct ata_timing t; 848 struct legacy_data *qdi = ap->host->private_data; 849 int active, recovery; 850 u8 timing; 851 852 /* Get the timing data in cycles */ 853 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 854 855 if (qdi->fast) { 856 active = 8 - FIT(t.active, 1, 8); 857 recovery = 18 - FIT(t.recover, 3, 18); 858 } else { 859 active = 9 - FIT(t.active, 2, 9); 860 recovery = 15 - FIT(t.recover, 0, 15); 861 } 862 timing = (recovery << 4) | active | 0x08; 863 qdi->clock[adev->devno] = timing; 864 outb(timing, qdi->timing + 2 * adev->devno); 865 /* Clear the FIFO */ 866 if (adev->class != ATA_DEV_ATA) 867 outb(0x5F, qdi->timing + 3); 868 } 869 870 /** 871 * qdi_qc_issue_prot - command issue 872 * @qc: command pending 873 * 874 * Called when the libata layer is about to issue a command. We wrap 875 * this interface so that we can load the correct ATA timings. 876 */ 877 878 static unsigned int qdi_qc_issue_prot(struct ata_queued_cmd *qc) 879 { 880 struct ata_port *ap = qc->ap; 881 struct ata_device *adev = qc->dev; 882 struct legacy_data *qdi = ap->host->private_data; 883 884 if (qdi->clock[adev->devno] != qdi->last) { 885 if (adev->pio_mode) { 886 qdi->last = qdi->clock[adev->devno]; 887 outb(qdi->clock[adev->devno], qdi->timing + 888 2 * ap->port_no); 889 } 890 } 891 return ata_qc_issue_prot(qc); 892 } 893 894 static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf, 895 unsigned int buflen, int rw) 896 { 897 struct ata_port *ap = adev->link->ap; 898 int slop = buflen & 3; 899 900 if (ata_id_has_dword_io(adev->id)) { 901 if (rw == WRITE) 902 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 903 else 904 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 905 906 if (unlikely(slop)) { 907 u32 pad; 908 if (rw == WRITE) { 909 memcpy(&pad, buf + buflen - slop, slop); 910 pad = le32_to_cpu(pad); 911 iowrite32(pad, ap->ioaddr.data_addr); 912 } else { 913 pad = ioread32(ap->ioaddr.data_addr); 914 pad = cpu_to_le32(pad); 915 memcpy(buf + buflen - slop, &pad, slop); 916 } 917 } 918 return (buflen + 3) & ~3; 919 } else 920 return ata_data_xfer(adev, buf, buflen, rw); 921 } 922 923 static int qdi_port(struct platform_device *dev, 924 struct legacy_probe *lp, struct legacy_data *ld) 925 { 926 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) 927 return -EBUSY; 928 ld->timing = lp->private; 929 return 0; 930 } 931 932 static struct ata_port_operations qdi6500_port_ops = { 933 .set_piomode = qdi6500_set_piomode, 934 935 .tf_load = ata_tf_load, 936 .tf_read = ata_tf_read, 937 .check_status = ata_check_status, 938 .exec_command = ata_exec_command, 939 .dev_select = ata_std_dev_select, 940 941 .freeze = ata_bmdma_freeze, 942 .thaw = ata_bmdma_thaw, 943 .error_handler = ata_bmdma_error_handler, 944 .post_internal_cmd = ata_bmdma_post_internal_cmd, 945 .cable_detect = ata_cable_40wire, 946 947 .qc_prep = ata_qc_prep, 948 .qc_issue = qdi_qc_issue_prot, 949 950 .data_xfer = vlb32_data_xfer, 951 952 .irq_handler = ata_interrupt, 953 .irq_clear = ata_bmdma_irq_clear, 954 .irq_on = ata_irq_on, 955 956 .port_start = ata_sff_port_start, 957 }; 958 959 static struct ata_port_operations qdi6580_port_ops = { 960 .set_piomode = qdi6580_set_piomode, 961 962 .tf_load = ata_tf_load, 963 .tf_read = ata_tf_read, 964 .check_status = ata_check_status, 965 .exec_command = ata_exec_command, 966 .dev_select = ata_std_dev_select, 967 968 .freeze = ata_bmdma_freeze, 969 .thaw = ata_bmdma_thaw, 970 .error_handler = ata_bmdma_error_handler, 971 .post_internal_cmd = ata_bmdma_post_internal_cmd, 972 .cable_detect = ata_cable_40wire, 973 974 .qc_prep = ata_qc_prep, 975 .qc_issue = ata_qc_issue_prot, 976 977 .data_xfer = vlb32_data_xfer, 978 979 .irq_handler = ata_interrupt, 980 .irq_clear = ata_bmdma_irq_clear, 981 .irq_on = ata_irq_on, 982 983 .port_start = ata_sff_port_start, 984 }; 985 986 static struct ata_port_operations qdi6580dp_port_ops = { 987 .set_piomode = qdi6580dp_set_piomode, 988 989 .tf_load = ata_tf_load, 990 .tf_read = ata_tf_read, 991 .check_status = ata_check_status, 992 .exec_command = ata_exec_command, 993 .dev_select = ata_std_dev_select, 994 995 .freeze = ata_bmdma_freeze, 996 .thaw = ata_bmdma_thaw, 997 .error_handler = ata_bmdma_error_handler, 998 .post_internal_cmd = ata_bmdma_post_internal_cmd, 999 .cable_detect = ata_cable_40wire, 1000 1001 .qc_prep = ata_qc_prep, 1002 .qc_issue = qdi_qc_issue_prot, 1003 1004 .data_xfer = vlb32_data_xfer, 1005 1006 .irq_handler = ata_interrupt, 1007 .irq_clear = ata_bmdma_irq_clear, 1008 .irq_on = ata_irq_on, 1009 1010 .port_start = ata_sff_port_start, 1011 }; 1012 1013 static DEFINE_SPINLOCK(winbond_lock); 1014 1015 static void winbond_writecfg(unsigned long port, u8 reg, u8 val) 1016 { 1017 unsigned long flags; 1018 spin_lock_irqsave(&winbond_lock, flags); 1019 outb(reg, port + 0x01); 1020 outb(val, port + 0x02); 1021 spin_unlock_irqrestore(&winbond_lock, flags); 1022 } 1023 1024 static u8 winbond_readcfg(unsigned long port, u8 reg) 1025 { 1026 u8 val; 1027 1028 unsigned long flags; 1029 spin_lock_irqsave(&winbond_lock, flags); 1030 outb(reg, port + 0x01); 1031 val = inb(port + 0x02); 1032 spin_unlock_irqrestore(&winbond_lock, flags); 1033 1034 return val; 1035 } 1036 1037 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) 1038 { 1039 struct ata_timing t; 1040 struct legacy_data *winbond = ap->host->private_data; 1041 int active, recovery; 1042 u8 reg; 1043 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); 1044 1045 reg = winbond_readcfg(winbond->timing, 0x81); 1046 1047 /* Get the timing data in cycles */ 1048 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ 1049 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 1050 else 1051 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 1052 1053 active = (FIT(t.active, 3, 17) - 1) & 0x0F; 1054 recovery = (FIT(t.recover, 1, 15) + 1) & 0x0F; 1055 timing = (active << 4) | recovery; 1056 winbond_writecfg(winbond->timing, timing, reg); 1057 1058 /* Load the setup timing */ 1059 1060 reg = 0x35; 1061 if (adev->class != ATA_DEV_ATA) 1062 reg |= 0x08; /* FIFO off */ 1063 if (!ata_pio_need_iordy(adev)) 1064 reg |= 0x02; /* IORDY off */ 1065 reg |= (FIT(t.setup, 0, 3) << 6); 1066 winbond_writecfg(winbond->timing, timing + 1, reg); 1067 } 1068 1069 static int winbond_port(struct platform_device *dev, 1070 struct legacy_probe *lp, struct legacy_data *ld) 1071 { 1072 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) 1073 return -EBUSY; 1074 ld->timing = lp->private; 1075 return 0; 1076 } 1077 1078 static struct ata_port_operations winbond_port_ops = { 1079 .set_piomode = winbond_set_piomode, 1080 1081 .tf_load = ata_tf_load, 1082 .tf_read = ata_tf_read, 1083 .check_status = ata_check_status, 1084 .exec_command = ata_exec_command, 1085 .dev_select = ata_std_dev_select, 1086 1087 .freeze = ata_bmdma_freeze, 1088 .thaw = ata_bmdma_thaw, 1089 .error_handler = ata_bmdma_error_handler, 1090 .post_internal_cmd = ata_bmdma_post_internal_cmd, 1091 .cable_detect = ata_cable_40wire, 1092 1093 .qc_prep = ata_qc_prep, 1094 .qc_issue = ata_qc_issue_prot, 1095 1096 .data_xfer = vlb32_data_xfer, 1097 1098 .irq_clear = ata_bmdma_irq_clear, 1099 .irq_on = ata_irq_on, 1100 1101 .port_start = ata_sff_port_start, 1102 }; 1103 1104 static struct legacy_controller controllers[] = { 1105 {"BIOS", &legacy_port_ops, 0x1F, 1106 ATA_FLAG_NO_IORDY, NULL }, 1107 {"Snooping", &simple_port_ops, 0x1F, 1108 0 , NULL }, 1109 {"PDC20230", &pdc20230_port_ops, 0x7, 1110 ATA_FLAG_NO_IORDY, NULL }, 1111 {"HT6560A", &ht6560a_port_ops, 0x07, 1112 ATA_FLAG_NO_IORDY, NULL }, 1113 {"HT6560B", &ht6560b_port_ops, 0x1F, 1114 ATA_FLAG_NO_IORDY, NULL }, 1115 {"OPTI82C611A", &opti82c611a_port_ops, 0x0F, 1116 0 , NULL }, 1117 {"OPTI82C46X", &opti82c46x_port_ops, 0x0F, 1118 0 , NULL }, 1119 {"QDI6500", &qdi6500_port_ops, 0x07, 1120 ATA_FLAG_NO_IORDY, qdi_port }, 1121 {"QDI6580", &qdi6580_port_ops, 0x1F, 1122 0 , qdi_port }, 1123 {"QDI6580DP", &qdi6580dp_port_ops, 0x1F, 1124 0 , qdi_port }, 1125 {"W83759A", &winbond_port_ops, 0x1F, 1126 0 , winbond_port } 1127 }; 1128 1129 /** 1130 * probe_chip_type - Discover controller 1131 * @probe: Probe entry to check 1132 * 1133 * Probe an ATA port and identify the type of controller. We don't 1134 * check if the controller appears to be driveless at this point. 1135 */ 1136 1137 static __init int probe_chip_type(struct legacy_probe *probe) 1138 { 1139 int mask = 1 << probe->slot; 1140 1141 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { 1142 u8 reg = winbond_readcfg(winbond, 0x81); 1143 reg |= 0x80; /* jumpered mode off */ 1144 winbond_writecfg(winbond, 0x81, reg); 1145 reg = winbond_readcfg(winbond, 0x83); 1146 reg |= 0xF0; /* local control */ 1147 winbond_writecfg(winbond, 0x83, reg); 1148 reg = winbond_readcfg(winbond, 0x85); 1149 reg |= 0xF0; /* programmable timing */ 1150 winbond_writecfg(winbond, 0x85, reg); 1151 1152 reg = winbond_readcfg(winbond, 0x81); 1153 1154 if (reg & mask) 1155 return W83759A; 1156 } 1157 if (probe->port == 0x1F0) { 1158 unsigned long flags; 1159 local_irq_save(flags); 1160 /* Probes */ 1161 outb(inb(0x1F2) | 0x80, 0x1F2); 1162 inb(0x1F5); 1163 inb(0x1F2); 1164 inb(0x3F6); 1165 inb(0x3F6); 1166 inb(0x1F2); 1167 inb(0x1F2); 1168 1169 if ((inb(0x1F2) & 0x80) == 0) { 1170 /* PDC20230c or 20630 ? */ 1171 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" 1172 " detected.\n"); 1173 udelay(100); 1174 inb(0x1F5); 1175 local_irq_restore(flags); 1176 return PDC20230; 1177 } else { 1178 outb(0x55, 0x1F2); 1179 inb(0x1F2); 1180 inb(0x1F2); 1181 if (inb(0x1F2) == 0x00) 1182 printk(KERN_INFO "PDC20230-B VLB ATA " 1183 "controller detected.\n"); 1184 local_irq_restore(flags); 1185 return BIOS; 1186 } 1187 local_irq_restore(flags); 1188 } 1189 1190 if (ht6560a & mask) 1191 return HT6560A; 1192 if (ht6560b & mask) 1193 return HT6560B; 1194 if (opti82c611a & mask) 1195 return OPTI611A; 1196 if (opti82c46x & mask) 1197 return OPTI46X; 1198 if (autospeed & mask) 1199 return SNOOP; 1200 return BIOS; 1201 } 1202 1203 1204 /** 1205 * legacy_init_one - attach a legacy interface 1206 * @pl: probe record 1207 * 1208 * Register an ISA bus IDE interface. Such interfaces are PIO and we 1209 * assume do not support IRQ sharing. 1210 */ 1211 1212 static __init int legacy_init_one(struct legacy_probe *probe) 1213 { 1214 struct legacy_controller *controller = &controllers[probe->type]; 1215 int pio_modes = controller->pio_mask; 1216 unsigned long io = probe->port; 1217 u32 mask = (1 << probe->slot); 1218 struct ata_port_operations *ops = controller->ops; 1219 struct legacy_data *ld = &legacy_data[probe->slot]; 1220 struct ata_host *host = NULL; 1221 struct ata_port *ap; 1222 struct platform_device *pdev; 1223 struct ata_device *dev; 1224 void __iomem *io_addr, *ctrl_addr; 1225 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; 1226 int ret; 1227 1228 iordy |= controller->flags; 1229 1230 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); 1231 if (IS_ERR(pdev)) 1232 return PTR_ERR(pdev); 1233 1234 ret = -EBUSY; 1235 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || 1236 devm_request_region(&pdev->dev, io + 0x0206, 1, 1237 "pata_legacy") == NULL) 1238 goto fail; 1239 1240 ret = -ENOMEM; 1241 io_addr = devm_ioport_map(&pdev->dev, io, 8); 1242 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); 1243 if (!io_addr || !ctrl_addr) 1244 goto fail; 1245 if (controller->setup) 1246 if (controller->setup(pdev, probe, ld) < 0) 1247 goto fail; 1248 host = ata_host_alloc(&pdev->dev, 1); 1249 if (!host) 1250 goto fail; 1251 ap = host->ports[0]; 1252 1253 ap->ops = ops; 1254 ap->pio_mask = pio_modes; 1255 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; 1256 ap->ioaddr.cmd_addr = io_addr; 1257 ap->ioaddr.altstatus_addr = ctrl_addr; 1258 ap->ioaddr.ctl_addr = ctrl_addr; 1259 ata_std_ports(&ap->ioaddr); 1260 ap->host->private_data = ld; 1261 1262 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); 1263 1264 ret = ata_host_activate(host, probe->irq, ata_interrupt, 0, 1265 &legacy_sht); 1266 if (ret) 1267 goto fail; 1268 ld->platform_dev = pdev; 1269 1270 /* Nothing found means we drop the port as its probably not there */ 1271 1272 ret = -ENODEV; 1273 ata_link_for_each_dev(dev, &ap->link) { 1274 if (!ata_dev_absent(dev)) { 1275 legacy_host[probe->slot] = host; 1276 ld->platform_dev = pdev; 1277 return 0; 1278 } 1279 } 1280 fail: 1281 if (host) 1282 ata_host_detach(host); 1283 platform_device_unregister(pdev); 1284 return ret; 1285 } 1286 1287 /** 1288 * legacy_check_special_cases - ATA special cases 1289 * @p: PCI device to check 1290 * @master: set this if we find an ATA master 1291 * @master: set this if we find an ATA secondary 1292 * 1293 * A small number of vendors implemented early PCI ATA interfaces 1294 * on bridge logic without the ATA interface being PCI visible. 1295 * Where we have a matching PCI driver we must skip the relevant 1296 * device here. If we don't know about it then the legacy driver 1297 * is the right driver anyway. 1298 */ 1299 1300 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, 1301 int *secondary) 1302 { 1303 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ 1304 if (p->vendor == 0x1078 && p->device == 0x0000) { 1305 *primary = *secondary = 1; 1306 return; 1307 } 1308 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ 1309 if (p->vendor == 0x1078 && p->device == 0x0002) { 1310 *primary = *secondary = 1; 1311 return; 1312 } 1313 /* Intel MPIIX - PIO ATA on non PCI side of bridge */ 1314 if (p->vendor == 0x8086 && p->device == 0x1234) { 1315 u16 r; 1316 pci_read_config_word(p, 0x6C, &r); 1317 if (r & 0x8000) { 1318 /* ATA port enabled */ 1319 if (r & 0x4000) 1320 *secondary = 1; 1321 else 1322 *primary = 1; 1323 } 1324 return; 1325 } 1326 } 1327 1328 static __init void probe_opti_vlb(void) 1329 { 1330 /* If an OPTI 82C46X is present find out where the channels are */ 1331 static const char *optis[4] = { 1332 "3/463MV", "5MV", 1333 "5MVA", "5MVB" 1334 }; 1335 u8 chans = 1; 1336 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; 1337 1338 opti82c46x = 3; /* Assume master and slave first */ 1339 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", 1340 optis[ctrl]); 1341 if (ctrl == 3) 1342 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; 1343 ctrl = opti_syscfg(0xAC); 1344 /* Check enabled and this port is the 465MV port. On the 1345 MVB we may have two channels */ 1346 if (ctrl & 8) { 1347 if (chans == 2) { 1348 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1349 legacy_probe_add(0x170, 15, OPTI46X, 0); 1350 } 1351 if (ctrl & 4) 1352 legacy_probe_add(0x170, 15, OPTI46X, 0); 1353 else 1354 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1355 } else 1356 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1357 } 1358 1359 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) 1360 { 1361 static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; 1362 /* Check card type */ 1363 if ((r & 0xF0) == 0xC0) { 1364 /* QD6500: single channel */ 1365 if (r & 8) 1366 /* Disabled ? */ 1367 return; 1368 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1369 QDI6500, port); 1370 } 1371 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { 1372 /* QD6580: dual channel */ 1373 if (!request_region(port + 2 , 2, "pata_qdi")) { 1374 release_region(port, 2); 1375 return; 1376 } 1377 res = inb(port + 3); 1378 /* Single channel mode ? */ 1379 if (res & 1) 1380 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1381 QDI6580, port); 1382 else { /* Dual channel mode */ 1383 legacy_probe_add(0x1F0, 14, QDI6580DP, port); 1384 /* port + 0x02, r & 0x04 */ 1385 legacy_probe_add(0x170, 15, QDI6580DP, port + 2); 1386 } 1387 release_region(port + 2, 2); 1388 } 1389 } 1390 1391 static __init void probe_qdi_vlb(void) 1392 { 1393 unsigned long flags; 1394 static const unsigned long qd_port[2] = { 0x30, 0xB0 }; 1395 int i; 1396 1397 /* 1398 * Check each possible QD65xx base address 1399 */ 1400 1401 for (i = 0; i < 2; i++) { 1402 unsigned long port = qd_port[i]; 1403 u8 r, res; 1404 1405 1406 if (request_region(port, 2, "pata_qdi")) { 1407 /* Check for a card */ 1408 local_irq_save(flags); 1409 /* I have no h/w that needs this delay but it 1410 is present in the historic code */ 1411 r = inb(port); 1412 udelay(1); 1413 outb(0x19, port); 1414 udelay(1); 1415 res = inb(port); 1416 udelay(1); 1417 outb(r, port); 1418 udelay(1); 1419 local_irq_restore(flags); 1420 1421 /* Fail */ 1422 if (res == 0x19) { 1423 release_region(port, 2); 1424 continue; 1425 } 1426 /* Passes the presence test */ 1427 r = inb(port + 1); 1428 udelay(1); 1429 /* Check port agrees with port set */ 1430 if ((r & 2) >> 1 == i) 1431 qdi65_identify_port(r, res, port); 1432 release_region(port, 2); 1433 } 1434 } 1435 } 1436 1437 /** 1438 * legacy_init - attach legacy interfaces 1439 * 1440 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. 1441 * Right now we do not scan the ide0 and ide1 address but should do so 1442 * for non PCI systems or systems with no PCI IDE legacy mode devices. 1443 * If you fix that note there are special cases to consider like VLB 1444 * drivers and CS5510/20. 1445 */ 1446 1447 static __init int legacy_init(void) 1448 { 1449 int i; 1450 int ct = 0; 1451 int primary = 0; 1452 int secondary = 0; 1453 int pci_present = 0; 1454 struct legacy_probe *pl = &probe_list[0]; 1455 int slot = 0; 1456 1457 struct pci_dev *p = NULL; 1458 1459 for_each_pci_dev(p) { 1460 int r; 1461 /* Check for any overlap of the system ATA mappings. Native 1462 mode controllers stuck on these addresses or some devices 1463 in 'raid' mode won't be found by the storage class test */ 1464 for (r = 0; r < 6; r++) { 1465 if (pci_resource_start(p, r) == 0x1f0) 1466 primary = 1; 1467 if (pci_resource_start(p, r) == 0x170) 1468 secondary = 1; 1469 } 1470 /* Check for special cases */ 1471 legacy_check_special_cases(p, &primary, &secondary); 1472 1473 /* If PCI bus is present then don't probe for tertiary 1474 legacy ports */ 1475 pci_present = 1; 1476 } 1477 1478 if (winbond == 1) 1479 winbond = 0x130; /* Default port, alt is 1B0 */ 1480 1481 if (primary == 0 || all) 1482 legacy_probe_add(0x1F0, 14, UNKNOWN, 0); 1483 if (secondary == 0 || all) 1484 legacy_probe_add(0x170, 15, UNKNOWN, 0); 1485 1486 if (probe_all || !pci_present) { 1487 /* ISA/VLB extra ports */ 1488 legacy_probe_add(0x1E8, 11, UNKNOWN, 0); 1489 legacy_probe_add(0x168, 10, UNKNOWN, 0); 1490 legacy_probe_add(0x1E0, 8, UNKNOWN, 0); 1491 legacy_probe_add(0x160, 12, UNKNOWN, 0); 1492 } 1493 1494 if (opti82c46x) 1495 probe_opti_vlb(); 1496 if (qdi) 1497 probe_qdi_vlb(); 1498 1499 for (i = 0; i < NR_HOST; i++, pl++) { 1500 if (pl->port == 0) 1501 continue; 1502 if (pl->type == UNKNOWN) 1503 pl->type = probe_chip_type(pl); 1504 pl->slot = slot++; 1505 if (legacy_init_one(pl) == 0) 1506 ct++; 1507 } 1508 if (ct != 0) 1509 return 0; 1510 return -ENODEV; 1511 } 1512 1513 static __exit void legacy_exit(void) 1514 { 1515 int i; 1516 1517 for (i = 0; i < nr_legacy_host; i++) { 1518 struct legacy_data *ld = &legacy_data[i]; 1519 ata_host_detach(legacy_host[i]); 1520 platform_device_unregister(ld->platform_dev); 1521 } 1522 } 1523 1524 MODULE_AUTHOR("Alan Cox"); 1525 MODULE_DESCRIPTION("low-level driver for legacy ATA"); 1526 MODULE_LICENSE("GPL"); 1527 MODULE_VERSION(DRV_VERSION); 1528 1529 module_param(probe_all, int, 0); 1530 module_param(autospeed, int, 0); 1531 module_param(ht6560a, int, 0); 1532 module_param(ht6560b, int, 0); 1533 module_param(opti82c611a, int, 0); 1534 module_param(opti82c46x, int, 0); 1535 module_param(qdi, int, 0); 1536 module_param(pio_mask, int, 0); 1537 module_param(iordy_mask, int, 0); 1538 1539 module_init(legacy_init); 1540 module_exit(legacy_exit); 1541