1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * pata-legacy.c - Legacy port PATA/SATA controller driver. 4 * Copyright 2005/2006 Red Hat, all rights reserved. 5 * 6 * An ATA driver for the legacy ATA ports. 7 * 8 * Data Sources: 9 * Opti 82C465/82C611 support: Data sheets at opti-inc.com 10 * HT6560 series: 11 * Promise 20230/20620: 12 * http://www.ryston.cz/petr/vlb/pdc20230b.html 13 * http://www.ryston.cz/petr/vlb/pdc20230c.html 14 * http://www.ryston.cz/petr/vlb/pdc20630.html 15 * QDI65x0: 16 * http://www.ryston.cz/petr/vlb/qd6500.html 17 * http://www.ryston.cz/petr/vlb/qd6580.html 18 * 19 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c 20 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by 21 * Samuel Thibault <samuel.thibault@ens-lyon.org> 22 * 23 * Unsupported but docs exist: 24 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 25 * 26 * This driver handles legacy (that is "ISA/VLB side") IDE ports found 27 * on PC class systems. There are three hybrid devices that are exceptions 28 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and 29 * the MPIIX where the tuning is PCI side but the IDE is "ISA side". 30 * 31 * Specific support is included for the ht6560a/ht6560b/opti82c611a/ 32 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A 33 * 34 * Support for the Winbond 83759A when operating in advanced mode. 35 * Multichip mode is not currently supported. 36 * 37 * Use the autospeed and pio_mask options with: 38 * Appian ADI/2 aka CLPD7220 or AIC25VL01. 39 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with 40 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, 41 * Winbond W83759A, Promise PDC20230-B 42 * 43 * For now use autospeed and pio_mask as above with the W83759A. This may 44 * change. 45 */ 46 47 #include <linux/async.h> 48 #include <linux/kernel.h> 49 #include <linux/module.h> 50 #include <linux/pci.h> 51 #include <linux/init.h> 52 #include <linux/blkdev.h> 53 #include <linux/delay.h> 54 #include <scsi/scsi_host.h> 55 #include <linux/ata.h> 56 #include <linux/libata.h> 57 #include <linux/platform_device.h> 58 59 #define DRV_NAME "pata_legacy" 60 #define DRV_VERSION "0.6.5" 61 62 #define NR_HOST 6 63 64 static int all; 65 module_param(all, int, 0444); 66 MODULE_PARM_DESC(all, 67 "Set to probe unclaimed pri/sec ISA port ranges even if PCI"); 68 69 static int probe_all; 70 module_param(probe_all, int, 0); 71 MODULE_PARM_DESC(probe_all, 72 "Set to probe tertiary+ ISA port ranges even if PCI"); 73 74 static int probe_mask = ~0; 75 module_param(probe_mask, int, 0); 76 MODULE_PARM_DESC(probe_mask, "Probe mask for legacy ISA PATA ports"); 77 78 static int autospeed; 79 module_param(autospeed, int, 0); 80 MODULE_PARM_DESC(autospeed, "Chip present that snoops speed changes"); 81 82 static int pio_mask = ATA_PIO4; 83 module_param(pio_mask, int, 0); 84 MODULE_PARM_DESC(pio_mask, "PIO range for autospeed devices"); 85 86 static int iordy_mask = 0xFFFFFFFF; 87 module_param(iordy_mask, int, 0); 88 MODULE_PARM_DESC(iordy_mask, "Use IORDY if available"); 89 90 static int ht6560a; 91 module_param(ht6560a, int, 0); 92 MODULE_PARM_DESC(ht6560a, "HT 6560A on primary 1, second 2, both 3"); 93 94 static int ht6560b; 95 module_param(ht6560b, int, 0); 96 MODULE_PARM_DESC(ht6560b, "HT 6560B on primary 1, secondary 2, both 3"); 97 98 static int opti82c611a; 99 module_param(opti82c611a, int, 0); 100 MODULE_PARM_DESC(opti82c611a, 101 "Opti 82c611A on primary 1, secondary 2, both 3"); 102 103 static int opti82c46x; 104 module_param(opti82c46x, int, 0); 105 MODULE_PARM_DESC(opti82c46x, 106 "Opti 82c465MV on primary 1, secondary 2, both 3"); 107 108 #ifdef CONFIG_PATA_QDI_MODULE 109 static int qdi = 1; 110 #else 111 static int qdi; 112 #endif 113 module_param(qdi, int, 0); 114 MODULE_PARM_DESC(qdi, "Set to probe QDI controllers"); 115 116 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE 117 static int winbond = 1; 118 #else 119 static int winbond; 120 #endif 121 module_param(winbond, int, 0); 122 MODULE_PARM_DESC(winbond, 123 "Set to probe Winbond controllers, " 124 "give I/O port if non standard"); 125 126 127 enum controller { 128 BIOS = 0, 129 SNOOP = 1, 130 PDC20230 = 2, 131 HT6560A = 3, 132 HT6560B = 4, 133 OPTI611A = 5, 134 OPTI46X = 6, 135 QDI6500 = 7, 136 QDI6580 = 8, 137 QDI6580DP = 9, /* Dual channel mode is different */ 138 W83759A = 10, 139 140 UNKNOWN = -1 141 }; 142 143 struct legacy_data { 144 unsigned long timing; 145 u8 clock[2]; 146 u8 last; 147 int fast; 148 enum controller type; 149 struct platform_device *platform_dev; 150 }; 151 152 struct legacy_probe { 153 unsigned char *name; 154 unsigned long port; 155 unsigned int irq; 156 unsigned int slot; 157 enum controller type; 158 unsigned long private; 159 }; 160 161 struct legacy_controller { 162 const char *name; 163 struct ata_port_operations *ops; 164 unsigned int pio_mask; 165 unsigned int flags; 166 unsigned int pflags; 167 int (*setup)(struct platform_device *, struct legacy_probe *probe, 168 struct legacy_data *data); 169 }; 170 171 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; 172 173 static struct legacy_probe probe_list[NR_HOST]; 174 static struct legacy_data legacy_data[NR_HOST]; 175 static struct ata_host *legacy_host[NR_HOST]; 176 static int nr_legacy_host; 177 178 179 /** 180 * legacy_probe_add - Add interface to probe list 181 * @port: Controller port 182 * @irq: IRQ number 183 * @type: Controller type 184 * @private: Controller specific info 185 * 186 * Add an entry into the probe list for ATA controllers. This is used 187 * to add the default ISA slots and then to build up the table 188 * further according to other ISA/VLB/Weird device scans 189 * 190 * An I/O port list is used to keep ordering stable and sane, as we 191 * don't have any good way to talk about ordering otherwise 192 */ 193 194 static int legacy_probe_add(unsigned long port, unsigned int irq, 195 enum controller type, unsigned long private) 196 { 197 struct legacy_probe *lp = &probe_list[0]; 198 int i; 199 struct legacy_probe *free = NULL; 200 201 for (i = 0; i < NR_HOST; i++) { 202 if (lp->port == 0 && free == NULL) 203 free = lp; 204 /* Matching port, or the correct slot for ordering */ 205 if (lp->port == port || legacy_port[i] == port) { 206 if (!(probe_mask & 1 << i)) 207 return -1; 208 free = lp; 209 break; 210 } 211 lp++; 212 } 213 if (free == NULL) { 214 printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); 215 return -1; 216 } 217 /* Fill in the entry for later probing */ 218 free->port = port; 219 free->irq = irq; 220 free->type = type; 221 free->private = private; 222 return 0; 223 } 224 225 226 /** 227 * legacy_set_mode - mode setting 228 * @link: IDE link 229 * @unused: Device that failed when error is returned 230 * 231 * Use a non standard set_mode function. We don't want to be tuned. 232 * 233 * The BIOS configured everything. Our job is not to fiddle. Just use 234 * whatever PIO the hardware is using and leave it at that. When we 235 * get some kind of nice user driven API for control then we can 236 * expand on this as per hdparm in the base kernel. 237 */ 238 239 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) 240 { 241 struct ata_device *dev; 242 243 ata_for_each_dev(dev, link, ENABLED) { 244 ata_dev_info(dev, "configured for PIO\n"); 245 dev->pio_mode = XFER_PIO_0; 246 dev->xfer_mode = XFER_PIO_0; 247 dev->xfer_shift = ATA_SHIFT_PIO; 248 dev->flags |= ATA_DFLAG_PIO; 249 } 250 return 0; 251 } 252 253 static struct scsi_host_template legacy_sht = { 254 ATA_PIO_SHT(DRV_NAME), 255 }; 256 257 static const struct ata_port_operations legacy_base_port_ops = { 258 .inherits = &ata_sff_port_ops, 259 .cable_detect = ata_cable_40wire, 260 }; 261 262 /* 263 * These ops are used if the user indicates the hardware 264 * snoops the commands to decide on the mode and handles the 265 * mode selection "magically" itself. Several legacy controllers 266 * do this. The mode range can be set if it is not 0x1F by setting 267 * pio_mask as well. 268 */ 269 270 static struct ata_port_operations simple_port_ops = { 271 .inherits = &legacy_base_port_ops, 272 .sff_data_xfer = ata_sff_data_xfer32, 273 }; 274 275 static struct ata_port_operations legacy_port_ops = { 276 .inherits = &legacy_base_port_ops, 277 .sff_data_xfer = ata_sff_data_xfer32, 278 .set_mode = legacy_set_mode, 279 }; 280 281 /* 282 * Promise 20230C and 20620 support 283 * 284 * This controller supports PIO0 to PIO2. We set PIO timings 285 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA 286 * support is weird being DMA to controller and PIO'd to the host 287 * and not supported. 288 */ 289 290 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) 291 { 292 int tries = 5; 293 int pio = adev->pio_mode - XFER_PIO_0; 294 u8 rt; 295 unsigned long flags; 296 297 /* Safe as UP only. Force I/Os to occur together */ 298 299 local_irq_save(flags); 300 301 /* Unlock the control interface */ 302 do { 303 inb(0x1F5); 304 outb(inb(0x1F2) | 0x80, 0x1F2); 305 inb(0x1F2); 306 inb(0x3F6); 307 inb(0x3F6); 308 inb(0x1F2); 309 inb(0x1F2); 310 } 311 while ((inb(0x1F2) & 0x80) && --tries); 312 313 local_irq_restore(flags); 314 315 outb(inb(0x1F4) & 0x07, 0x1F4); 316 317 rt = inb(0x1F3); 318 rt &= 0x07 << (3 * adev->devno); 319 if (pio) 320 rt |= (1 + 3 * pio) << (3 * adev->devno); 321 322 udelay(100); 323 outb(inb(0x1F2) | 0x01, 0x1F2); 324 udelay(100); 325 inb(0x1F5); 326 327 } 328 329 static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc, 330 unsigned char *buf, unsigned int buflen, int rw) 331 { 332 struct ata_device *dev = qc->dev; 333 struct ata_port *ap = dev->link->ap; 334 int slop = buflen & 3; 335 336 /* 32bit I/O capable *and* we need to write a whole number of dwords */ 337 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) 338 && (ap->pflags & ATA_PFLAG_PIO32)) { 339 unsigned long flags; 340 341 local_irq_save(flags); 342 343 /* Perform the 32bit I/O synchronization sequence */ 344 ioread8(ap->ioaddr.nsect_addr); 345 ioread8(ap->ioaddr.nsect_addr); 346 ioread8(ap->ioaddr.nsect_addr); 347 348 /* Now the data */ 349 if (rw == READ) 350 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 351 else 352 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 353 354 if (unlikely(slop)) { 355 __le32 pad = 0; 356 357 if (rw == READ) { 358 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 359 memcpy(buf + buflen - slop, &pad, slop); 360 } else { 361 memcpy(&pad, buf + buflen - slop, slop); 362 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 363 } 364 buflen += 4 - slop; 365 } 366 local_irq_restore(flags); 367 } else 368 buflen = ata_sff_data_xfer32(qc, buf, buflen, rw); 369 370 return buflen; 371 } 372 373 static struct ata_port_operations pdc20230_port_ops = { 374 .inherits = &legacy_base_port_ops, 375 .set_piomode = pdc20230_set_piomode, 376 .sff_data_xfer = pdc_data_xfer_vlb, 377 }; 378 379 /* 380 * Holtek 6560A support 381 * 382 * This controller supports PIO0 to PIO2 (no IORDY even though higher 383 * timings can be loaded). 384 */ 385 386 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) 387 { 388 u8 active, recover; 389 struct ata_timing t; 390 391 /* Get the timing data in cycles. For now play safe at 50Mhz */ 392 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 393 394 active = clamp_val(t.active, 2, 15); 395 recover = clamp_val(t.recover, 4, 15); 396 397 inb(0x3E6); 398 inb(0x3E6); 399 inb(0x3E6); 400 inb(0x3E6); 401 402 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 403 ioread8(ap->ioaddr.status_addr); 404 } 405 406 static struct ata_port_operations ht6560a_port_ops = { 407 .inherits = &legacy_base_port_ops, 408 .set_piomode = ht6560a_set_piomode, 409 }; 410 411 /* 412 * Holtek 6560B support 413 * 414 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO 415 * setting unless we see an ATAPI device in which case we force it off. 416 * 417 * FIXME: need to implement 2nd channel support. 418 */ 419 420 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) 421 { 422 u8 active, recover; 423 struct ata_timing t; 424 425 /* Get the timing data in cycles. For now play safe at 50Mhz */ 426 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 427 428 active = clamp_val(t.active, 2, 15); 429 recover = clamp_val(t.recover, 2, 16) & 0x0F; 430 431 inb(0x3E6); 432 inb(0x3E6); 433 inb(0x3E6); 434 inb(0x3E6); 435 436 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 437 438 if (adev->class != ATA_DEV_ATA) { 439 u8 rconf = inb(0x3E6); 440 if (rconf & 0x24) { 441 rconf &= ~0x24; 442 outb(rconf, 0x3E6); 443 } 444 } 445 ioread8(ap->ioaddr.status_addr); 446 } 447 448 static struct ata_port_operations ht6560b_port_ops = { 449 .inherits = &legacy_base_port_ops, 450 .set_piomode = ht6560b_set_piomode, 451 }; 452 453 /* 454 * Opti core chipset helpers 455 */ 456 457 /** 458 * opti_syscfg - read OPTI chipset configuration 459 * @reg: Configuration register to read 460 * 461 * Returns the value of an OPTI system board configuration register. 462 */ 463 464 static u8 opti_syscfg(u8 reg) 465 { 466 unsigned long flags; 467 u8 r; 468 469 /* Uniprocessor chipset and must force cycles adjancent */ 470 local_irq_save(flags); 471 outb(reg, 0x22); 472 r = inb(0x24); 473 local_irq_restore(flags); 474 return r; 475 } 476 477 /* 478 * Opti 82C611A 479 * 480 * This controller supports PIO0 to PIO3. 481 */ 482 483 static void opti82c611a_set_piomode(struct ata_port *ap, 484 struct ata_device *adev) 485 { 486 u8 active, recover, setup; 487 struct ata_timing t; 488 struct ata_device *pair = ata_dev_pair(adev); 489 int clock; 490 int khz[4] = { 50000, 40000, 33000, 25000 }; 491 u8 rc; 492 493 /* Enter configuration mode */ 494 ioread16(ap->ioaddr.error_addr); 495 ioread16(ap->ioaddr.error_addr); 496 iowrite8(3, ap->ioaddr.nsect_addr); 497 498 /* Read VLB clock strapping */ 499 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; 500 501 /* Get the timing data in cycles */ 502 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 503 504 /* Setup timing is shared */ 505 if (pair) { 506 struct ata_timing tp; 507 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 508 509 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 510 } 511 512 active = clamp_val(t.active, 2, 17) - 2; 513 recover = clamp_val(t.recover, 1, 16) - 1; 514 setup = clamp_val(t.setup, 1, 4) - 1; 515 516 /* Select the right timing bank for write timing */ 517 rc = ioread8(ap->ioaddr.lbal_addr); 518 rc &= 0x7F; 519 rc |= (adev->devno << 7); 520 iowrite8(rc, ap->ioaddr.lbal_addr); 521 522 /* Write the timings */ 523 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 524 525 /* Select the right bank for read timings, also 526 load the shared timings for address */ 527 rc = ioread8(ap->ioaddr.device_addr); 528 rc &= 0xC0; 529 rc |= adev->devno; /* Index select */ 530 rc |= (setup << 4) | 0x04; 531 iowrite8(rc, ap->ioaddr.device_addr); 532 533 /* Load the read timings */ 534 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 535 536 /* Ensure the timing register mode is right */ 537 rc = ioread8(ap->ioaddr.lbal_addr); 538 rc &= 0x73; 539 rc |= 0x84; 540 iowrite8(rc, ap->ioaddr.lbal_addr); 541 542 /* Exit command mode */ 543 iowrite8(0x83, ap->ioaddr.nsect_addr); 544 } 545 546 547 static struct ata_port_operations opti82c611a_port_ops = { 548 .inherits = &legacy_base_port_ops, 549 .set_piomode = opti82c611a_set_piomode, 550 }; 551 552 /* 553 * Opti 82C465MV 554 * 555 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB 556 * version is dual channel but doesn't have a lot of unique registers. 557 */ 558 559 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) 560 { 561 u8 active, recover, setup; 562 struct ata_timing t; 563 struct ata_device *pair = ata_dev_pair(adev); 564 int clock; 565 int khz[4] = { 50000, 40000, 33000, 25000 }; 566 u8 rc; 567 u8 sysclk; 568 569 /* Get the clock */ 570 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */ 571 572 /* Enter configuration mode */ 573 ioread16(ap->ioaddr.error_addr); 574 ioread16(ap->ioaddr.error_addr); 575 iowrite8(3, ap->ioaddr.nsect_addr); 576 577 /* Read VLB clock strapping */ 578 clock = 1000000000 / khz[sysclk]; 579 580 /* Get the timing data in cycles */ 581 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 582 583 /* Setup timing is shared */ 584 if (pair) { 585 struct ata_timing tp; 586 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 587 588 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 589 } 590 591 active = clamp_val(t.active, 2, 17) - 2; 592 recover = clamp_val(t.recover, 1, 16) - 1; 593 setup = clamp_val(t.setup, 1, 4) - 1; 594 595 /* Select the right timing bank for write timing */ 596 rc = ioread8(ap->ioaddr.lbal_addr); 597 rc &= 0x7F; 598 rc |= (adev->devno << 7); 599 iowrite8(rc, ap->ioaddr.lbal_addr); 600 601 /* Write the timings */ 602 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 603 604 /* Select the right bank for read timings, also 605 load the shared timings for address */ 606 rc = ioread8(ap->ioaddr.device_addr); 607 rc &= 0xC0; 608 rc |= adev->devno; /* Index select */ 609 rc |= (setup << 4) | 0x04; 610 iowrite8(rc, ap->ioaddr.device_addr); 611 612 /* Load the read timings */ 613 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 614 615 /* Ensure the timing register mode is right */ 616 rc = ioread8(ap->ioaddr.lbal_addr); 617 rc &= 0x73; 618 rc |= 0x84; 619 iowrite8(rc, ap->ioaddr.lbal_addr); 620 621 /* Exit command mode */ 622 iowrite8(0x83, ap->ioaddr.nsect_addr); 623 624 /* We need to know this for quad device on the MVB */ 625 ap->host->private_data = ap; 626 } 627 628 /** 629 * opti82c46x_qc_issue - command issue 630 * @qc: command pending 631 * 632 * Called when the libata layer is about to issue a command. We wrap 633 * this interface so that we can load the correct ATA timings. The 634 * MVB has a single set of timing registers and these are shared 635 * across channels. As there are two registers we really ought to 636 * track the last two used values as a sort of register window. For 637 * now we just reload on a channel switch. On the single channel 638 * setup this condition never fires so we do nothing extra. 639 * 640 * FIXME: dual channel needs ->serialize support 641 */ 642 643 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) 644 { 645 struct ata_port *ap = qc->ap; 646 struct ata_device *adev = qc->dev; 647 648 /* If timings are set and for the wrong channel (2nd test is 649 due to a libata shortcoming and will eventually go I hope) */ 650 if (ap->host->private_data != ap->host 651 && ap->host->private_data != NULL) 652 opti82c46x_set_piomode(ap, adev); 653 654 return ata_sff_qc_issue(qc); 655 } 656 657 static struct ata_port_operations opti82c46x_port_ops = { 658 .inherits = &legacy_base_port_ops, 659 .set_piomode = opti82c46x_set_piomode, 660 .qc_issue = opti82c46x_qc_issue, 661 }; 662 663 /** 664 * qdi65x0_set_piomode - PIO setup for QDI65x0 665 * @ap: Port 666 * @adev: Device 667 * 668 * In single channel mode the 6580 has one clock per device and we can 669 * avoid the requirement to clock switch. We also have to load the timing 670 * into the right clock according to whether we are master or slave. 671 * 672 * In dual channel mode the 6580 has one clock per channel and we have 673 * to software clockswitch in qc_issue. 674 */ 675 676 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev) 677 { 678 struct ata_timing t; 679 struct legacy_data *ld_qdi = ap->host->private_data; 680 int active, recovery; 681 u8 timing; 682 683 /* Get the timing data in cycles */ 684 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 685 686 if (ld_qdi->fast) { 687 active = 8 - clamp_val(t.active, 1, 8); 688 recovery = 18 - clamp_val(t.recover, 3, 18); 689 } else { 690 active = 9 - clamp_val(t.active, 2, 9); 691 recovery = 15 - clamp_val(t.recover, 0, 15); 692 } 693 timing = (recovery << 4) | active | 0x08; 694 ld_qdi->clock[adev->devno] = timing; 695 696 if (ld_qdi->type == QDI6580) 697 outb(timing, ld_qdi->timing + 2 * adev->devno); 698 else 699 outb(timing, ld_qdi->timing + 2 * ap->port_no); 700 701 /* Clear the FIFO */ 702 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA) 703 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); 704 } 705 706 /** 707 * qdi_qc_issue - command issue 708 * @qc: command pending 709 * 710 * Called when the libata layer is about to issue a command. We wrap 711 * this interface so that we can load the correct ATA timings. 712 */ 713 714 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) 715 { 716 struct ata_port *ap = qc->ap; 717 struct ata_device *adev = qc->dev; 718 struct legacy_data *ld_qdi = ap->host->private_data; 719 720 if (ld_qdi->clock[adev->devno] != ld_qdi->last) { 721 if (adev->pio_mode) { 722 ld_qdi->last = ld_qdi->clock[adev->devno]; 723 outb(ld_qdi->clock[adev->devno], ld_qdi->timing + 724 2 * ap->port_no); 725 } 726 } 727 return ata_sff_qc_issue(qc); 728 } 729 730 static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc, 731 unsigned char *buf, 732 unsigned int buflen, int rw) 733 { 734 struct ata_device *adev = qc->dev; 735 struct ata_port *ap = adev->link->ap; 736 int slop = buflen & 3; 737 738 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) 739 && (ap->pflags & ATA_PFLAG_PIO32)) { 740 if (rw == WRITE) 741 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 742 else 743 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 744 745 if (unlikely(slop)) { 746 __le32 pad = 0; 747 748 if (rw == WRITE) { 749 memcpy(&pad, buf + buflen - slop, slop); 750 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 751 } else { 752 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 753 memcpy(buf + buflen - slop, &pad, slop); 754 } 755 } 756 return (buflen + 3) & ~3; 757 } else 758 return ata_sff_data_xfer(qc, buf, buflen, rw); 759 } 760 761 static int qdi_port(struct platform_device *dev, 762 struct legacy_probe *lp, struct legacy_data *ld) 763 { 764 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) 765 return -EBUSY; 766 ld->timing = lp->private; 767 return 0; 768 } 769 770 static struct ata_port_operations qdi6500_port_ops = { 771 .inherits = &legacy_base_port_ops, 772 .set_piomode = qdi65x0_set_piomode, 773 .qc_issue = qdi_qc_issue, 774 .sff_data_xfer = vlb32_data_xfer, 775 }; 776 777 static struct ata_port_operations qdi6580_port_ops = { 778 .inherits = &legacy_base_port_ops, 779 .set_piomode = qdi65x0_set_piomode, 780 .sff_data_xfer = vlb32_data_xfer, 781 }; 782 783 static struct ata_port_operations qdi6580dp_port_ops = { 784 .inherits = &legacy_base_port_ops, 785 .set_piomode = qdi65x0_set_piomode, 786 .qc_issue = qdi_qc_issue, 787 .sff_data_xfer = vlb32_data_xfer, 788 }; 789 790 static DEFINE_SPINLOCK(winbond_lock); 791 792 static void winbond_writecfg(unsigned long port, u8 reg, u8 val) 793 { 794 unsigned long flags; 795 spin_lock_irqsave(&winbond_lock, flags); 796 outb(reg, port + 0x01); 797 outb(val, port + 0x02); 798 spin_unlock_irqrestore(&winbond_lock, flags); 799 } 800 801 static u8 winbond_readcfg(unsigned long port, u8 reg) 802 { 803 u8 val; 804 805 unsigned long flags; 806 spin_lock_irqsave(&winbond_lock, flags); 807 outb(reg, port + 0x01); 808 val = inb(port + 0x02); 809 spin_unlock_irqrestore(&winbond_lock, flags); 810 811 return val; 812 } 813 814 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) 815 { 816 struct ata_timing t; 817 struct legacy_data *ld_winbond = ap->host->private_data; 818 int active, recovery; 819 u8 reg; 820 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); 821 822 reg = winbond_readcfg(ld_winbond->timing, 0x81); 823 824 /* Get the timing data in cycles */ 825 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ 826 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 827 else 828 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 829 830 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; 831 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; 832 timing = (active << 4) | recovery; 833 winbond_writecfg(ld_winbond->timing, timing, reg); 834 835 /* Load the setup timing */ 836 837 reg = 0x35; 838 if (adev->class != ATA_DEV_ATA) 839 reg |= 0x08; /* FIFO off */ 840 if (!ata_pio_need_iordy(adev)) 841 reg |= 0x02; /* IORDY off */ 842 reg |= (clamp_val(t.setup, 0, 3) << 6); 843 winbond_writecfg(ld_winbond->timing, timing + 1, reg); 844 } 845 846 static int winbond_port(struct platform_device *dev, 847 struct legacy_probe *lp, struct legacy_data *ld) 848 { 849 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) 850 return -EBUSY; 851 ld->timing = lp->private; 852 return 0; 853 } 854 855 static struct ata_port_operations winbond_port_ops = { 856 .inherits = &legacy_base_port_ops, 857 .set_piomode = winbond_set_piomode, 858 .sff_data_xfer = vlb32_data_xfer, 859 }; 860 861 static struct legacy_controller controllers[] = { 862 {"BIOS", &legacy_port_ops, ATA_PIO4, 863 ATA_FLAG_NO_IORDY, 0, NULL }, 864 {"Snooping", &simple_port_ops, ATA_PIO4, 865 0, 0, NULL }, 866 {"PDC20230", &pdc20230_port_ops, ATA_PIO2, 867 ATA_FLAG_NO_IORDY, 868 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, 869 {"HT6560A", &ht6560a_port_ops, ATA_PIO2, 870 ATA_FLAG_NO_IORDY, 0, NULL }, 871 {"HT6560B", &ht6560b_port_ops, ATA_PIO4, 872 ATA_FLAG_NO_IORDY, 0, NULL }, 873 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3, 874 0, 0, NULL }, 875 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3, 876 0, 0, NULL }, 877 {"QDI6500", &qdi6500_port_ops, ATA_PIO2, 878 ATA_FLAG_NO_IORDY, 879 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 880 {"QDI6580", &qdi6580_port_ops, ATA_PIO4, 881 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 882 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4, 883 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 884 {"W83759A", &winbond_port_ops, ATA_PIO4, 885 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, 886 winbond_port } 887 }; 888 889 /** 890 * probe_chip_type - Discover controller 891 * @probe: Probe entry to check 892 * 893 * Probe an ATA port and identify the type of controller. We don't 894 * check if the controller appears to be driveless at this point. 895 */ 896 897 static __init int probe_chip_type(struct legacy_probe *probe) 898 { 899 int mask = 1 << probe->slot; 900 901 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { 902 u8 reg = winbond_readcfg(winbond, 0x81); 903 reg |= 0x80; /* jumpered mode off */ 904 winbond_writecfg(winbond, 0x81, reg); 905 reg = winbond_readcfg(winbond, 0x83); 906 reg |= 0xF0; /* local control */ 907 winbond_writecfg(winbond, 0x83, reg); 908 reg = winbond_readcfg(winbond, 0x85); 909 reg |= 0xF0; /* programmable timing */ 910 winbond_writecfg(winbond, 0x85, reg); 911 912 reg = winbond_readcfg(winbond, 0x81); 913 914 if (reg & mask) 915 return W83759A; 916 } 917 if (probe->port == 0x1F0) { 918 unsigned long flags; 919 local_irq_save(flags); 920 /* Probes */ 921 outb(inb(0x1F2) | 0x80, 0x1F2); 922 inb(0x1F5); 923 inb(0x1F2); 924 inb(0x3F6); 925 inb(0x3F6); 926 inb(0x1F2); 927 inb(0x1F2); 928 929 if ((inb(0x1F2) & 0x80) == 0) { 930 /* PDC20230c or 20630 ? */ 931 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" 932 " detected.\n"); 933 udelay(100); 934 inb(0x1F5); 935 local_irq_restore(flags); 936 return PDC20230; 937 } else { 938 outb(0x55, 0x1F2); 939 inb(0x1F2); 940 inb(0x1F2); 941 if (inb(0x1F2) == 0x00) 942 printk(KERN_INFO "PDC20230-B VLB ATA " 943 "controller detected.\n"); 944 local_irq_restore(flags); 945 return BIOS; 946 } 947 } 948 949 if (ht6560a & mask) 950 return HT6560A; 951 if (ht6560b & mask) 952 return HT6560B; 953 if (opti82c611a & mask) 954 return OPTI611A; 955 if (opti82c46x & mask) 956 return OPTI46X; 957 if (autospeed & mask) 958 return SNOOP; 959 return BIOS; 960 } 961 962 963 /** 964 * legacy_init_one - attach a legacy interface 965 * @probe: probe record 966 * 967 * Register an ISA bus IDE interface. Such interfaces are PIO and we 968 * assume do not support IRQ sharing. 969 */ 970 971 static __init int legacy_init_one(struct legacy_probe *probe) 972 { 973 struct legacy_controller *controller = &controllers[probe->type]; 974 int pio_modes = controller->pio_mask; 975 unsigned long io = probe->port; 976 u32 mask = (1 << probe->slot); 977 struct ata_port_operations *ops = controller->ops; 978 struct legacy_data *ld = &legacy_data[probe->slot]; 979 struct ata_host *host = NULL; 980 struct ata_port *ap; 981 struct platform_device *pdev; 982 struct ata_device *dev; 983 void __iomem *io_addr, *ctrl_addr; 984 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; 985 int ret; 986 987 iordy |= controller->flags; 988 989 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); 990 if (IS_ERR(pdev)) 991 return PTR_ERR(pdev); 992 993 ret = -EBUSY; 994 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || 995 devm_request_region(&pdev->dev, io + 0x0206, 1, 996 "pata_legacy") == NULL) 997 goto fail; 998 999 ret = -ENOMEM; 1000 io_addr = devm_ioport_map(&pdev->dev, io, 8); 1001 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); 1002 if (!io_addr || !ctrl_addr) 1003 goto fail; 1004 ld->type = probe->type; 1005 if (controller->setup) 1006 if (controller->setup(pdev, probe, ld) < 0) 1007 goto fail; 1008 host = ata_host_alloc(&pdev->dev, 1); 1009 if (!host) 1010 goto fail; 1011 ap = host->ports[0]; 1012 1013 ap->ops = ops; 1014 ap->pio_mask = pio_modes; 1015 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; 1016 ap->pflags |= controller->pflags; 1017 ap->ioaddr.cmd_addr = io_addr; 1018 ap->ioaddr.altstatus_addr = ctrl_addr; 1019 ap->ioaddr.ctl_addr = ctrl_addr; 1020 ata_sff_std_ports(&ap->ioaddr); 1021 ap->host->private_data = ld; 1022 1023 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); 1024 1025 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, 1026 &legacy_sht); 1027 if (ret) 1028 goto fail; 1029 async_synchronize_full(); 1030 ld->platform_dev = pdev; 1031 1032 /* Nothing found means we drop the port as its probably not there */ 1033 1034 ret = -ENODEV; 1035 ata_for_each_dev(dev, &ap->link, ALL) { 1036 if (!ata_dev_absent(dev)) { 1037 legacy_host[probe->slot] = host; 1038 ld->platform_dev = pdev; 1039 return 0; 1040 } 1041 } 1042 ata_host_detach(host); 1043 fail: 1044 platform_device_unregister(pdev); 1045 return ret; 1046 } 1047 1048 /** 1049 * legacy_check_special_cases - ATA special cases 1050 * @p: PCI device to check 1051 * @primary: set this if we find an ATA master 1052 * @secondary: set this if we find an ATA secondary 1053 * 1054 * A small number of vendors implemented early PCI ATA interfaces 1055 * on bridge logic without the ATA interface being PCI visible. 1056 * Where we have a matching PCI driver we must skip the relevant 1057 * device here. If we don't know about it then the legacy driver 1058 * is the right driver anyway. 1059 */ 1060 1061 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, 1062 int *secondary) 1063 { 1064 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ 1065 if (p->vendor == 0x1078 && p->device == 0x0000) { 1066 *primary = *secondary = 1; 1067 return; 1068 } 1069 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ 1070 if (p->vendor == 0x1078 && p->device == 0x0002) { 1071 *primary = *secondary = 1; 1072 return; 1073 } 1074 /* Intel MPIIX - PIO ATA on non PCI side of bridge */ 1075 if (p->vendor == 0x8086 && p->device == 0x1234) { 1076 u16 r; 1077 pci_read_config_word(p, 0x6C, &r); 1078 if (r & 0x8000) { 1079 /* ATA port enabled */ 1080 if (r & 0x4000) 1081 *secondary = 1; 1082 else 1083 *primary = 1; 1084 } 1085 return; 1086 } 1087 } 1088 1089 static __init void probe_opti_vlb(void) 1090 { 1091 /* If an OPTI 82C46X is present find out where the channels are */ 1092 static const char *optis[4] = { 1093 "3/463MV", "5MV", 1094 "5MVA", "5MVB" 1095 }; 1096 u8 chans = 1; 1097 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; 1098 1099 opti82c46x = 3; /* Assume master and slave first */ 1100 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", 1101 optis[ctrl]); 1102 if (ctrl == 3) 1103 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; 1104 ctrl = opti_syscfg(0xAC); 1105 /* Check enabled and this port is the 465MV port. On the 1106 MVB we may have two channels */ 1107 if (ctrl & 8) { 1108 if (chans == 2) { 1109 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1110 legacy_probe_add(0x170, 15, OPTI46X, 0); 1111 } 1112 if (ctrl & 4) 1113 legacy_probe_add(0x170, 15, OPTI46X, 0); 1114 else 1115 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1116 } else 1117 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1118 } 1119 1120 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) 1121 { 1122 static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; 1123 /* Check card type */ 1124 if ((r & 0xF0) == 0xC0) { 1125 /* QD6500: single channel */ 1126 if (r & 8) 1127 /* Disabled ? */ 1128 return; 1129 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1130 QDI6500, port); 1131 } 1132 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { 1133 /* QD6580: dual channel */ 1134 if (!request_region(port + 2 , 2, "pata_qdi")) { 1135 release_region(port, 2); 1136 return; 1137 } 1138 res = inb(port + 3); 1139 /* Single channel mode ? */ 1140 if (res & 1) 1141 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1142 QDI6580, port); 1143 else { /* Dual channel mode */ 1144 legacy_probe_add(0x1F0, 14, QDI6580DP, port); 1145 /* port + 0x02, r & 0x04 */ 1146 legacy_probe_add(0x170, 15, QDI6580DP, port + 2); 1147 } 1148 release_region(port + 2, 2); 1149 } 1150 } 1151 1152 static __init void probe_qdi_vlb(void) 1153 { 1154 unsigned long flags; 1155 static const unsigned long qd_port[2] = { 0x30, 0xB0 }; 1156 int i; 1157 1158 /* 1159 * Check each possible QD65xx base address 1160 */ 1161 1162 for (i = 0; i < 2; i++) { 1163 unsigned long port = qd_port[i]; 1164 u8 r, res; 1165 1166 1167 if (request_region(port, 2, "pata_qdi")) { 1168 /* Check for a card */ 1169 local_irq_save(flags); 1170 /* I have no h/w that needs this delay but it 1171 is present in the historic code */ 1172 r = inb(port); 1173 udelay(1); 1174 outb(0x19, port); 1175 udelay(1); 1176 res = inb(port); 1177 udelay(1); 1178 outb(r, port); 1179 udelay(1); 1180 local_irq_restore(flags); 1181 1182 /* Fail */ 1183 if (res == 0x19) { 1184 release_region(port, 2); 1185 continue; 1186 } 1187 /* Passes the presence test */ 1188 r = inb(port + 1); 1189 udelay(1); 1190 /* Check port agrees with port set */ 1191 if ((r & 2) >> 1 == i) 1192 qdi65_identify_port(r, res, port); 1193 release_region(port, 2); 1194 } 1195 } 1196 } 1197 1198 /** 1199 * legacy_init - attach legacy interfaces 1200 * 1201 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. 1202 * Right now we do not scan the ide0 and ide1 address but should do so 1203 * for non PCI systems or systems with no PCI IDE legacy mode devices. 1204 * If you fix that note there are special cases to consider like VLB 1205 * drivers and CS5510/20. 1206 */ 1207 1208 static __init int legacy_init(void) 1209 { 1210 int i; 1211 int ct = 0; 1212 int primary = 0; 1213 int secondary = 0; 1214 int pci_present = 0; 1215 struct legacy_probe *pl = &probe_list[0]; 1216 int slot = 0; 1217 1218 struct pci_dev *p = NULL; 1219 1220 for_each_pci_dev(p) { 1221 int r; 1222 /* Check for any overlap of the system ATA mappings. Native 1223 mode controllers stuck on these addresses or some devices 1224 in 'raid' mode won't be found by the storage class test */ 1225 for (r = 0; r < 6; r++) { 1226 if (pci_resource_start(p, r) == 0x1f0) 1227 primary = 1; 1228 if (pci_resource_start(p, r) == 0x170) 1229 secondary = 1; 1230 } 1231 /* Check for special cases */ 1232 legacy_check_special_cases(p, &primary, &secondary); 1233 1234 /* If PCI bus is present then don't probe for tertiary 1235 legacy ports */ 1236 pci_present = 1; 1237 } 1238 1239 if (winbond == 1) 1240 winbond = 0x130; /* Default port, alt is 1B0 */ 1241 1242 if (primary == 0 || all) 1243 legacy_probe_add(0x1F0, 14, UNKNOWN, 0); 1244 if (secondary == 0 || all) 1245 legacy_probe_add(0x170, 15, UNKNOWN, 0); 1246 1247 if (probe_all || !pci_present) { 1248 /* ISA/VLB extra ports */ 1249 legacy_probe_add(0x1E8, 11, UNKNOWN, 0); 1250 legacy_probe_add(0x168, 10, UNKNOWN, 0); 1251 legacy_probe_add(0x1E0, 8, UNKNOWN, 0); 1252 legacy_probe_add(0x160, 12, UNKNOWN, 0); 1253 } 1254 1255 if (opti82c46x) 1256 probe_opti_vlb(); 1257 if (qdi) 1258 probe_qdi_vlb(); 1259 1260 for (i = 0; i < NR_HOST; i++, pl++) { 1261 if (pl->port == 0) 1262 continue; 1263 if (pl->type == UNKNOWN) 1264 pl->type = probe_chip_type(pl); 1265 pl->slot = slot++; 1266 if (legacy_init_one(pl) == 0) 1267 ct++; 1268 } 1269 if (ct != 0) 1270 return 0; 1271 return -ENODEV; 1272 } 1273 1274 static __exit void legacy_exit(void) 1275 { 1276 int i; 1277 1278 for (i = 0; i < nr_legacy_host; i++) { 1279 struct legacy_data *ld = &legacy_data[i]; 1280 ata_host_detach(legacy_host[i]); 1281 platform_device_unregister(ld->platform_dev); 1282 } 1283 } 1284 1285 MODULE_AUTHOR("Alan Cox"); 1286 MODULE_DESCRIPTION("low-level driver for legacy ATA"); 1287 MODULE_LICENSE("GPL"); 1288 MODULE_VERSION(DRV_VERSION); 1289 MODULE_ALIAS("pata_qdi"); 1290 MODULE_ALIAS("pata_winbond"); 1291 1292 module_init(legacy_init); 1293 module_exit(legacy_exit); 1294