1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * EP93XX PATA controller driver. 4 * 5 * Copyright (c) 2012, Metasoft s.c. 6 * Rafal Prylowski <prylowski@metasoft.pl> 7 * 8 * Based on pata_scc.c, pata_icside.c and on earlier version of EP93XX 9 * PATA driver by Lennert Buytenhek and Alessandro Zummo. 10 * Read/Write timings, resource management and other improvements 11 * from driver by Joao Ramos and Bartlomiej Zolnierkiewicz. 12 * DMA engine support based on spi-ep93xx.c by Mika Westerberg. 13 * 14 * Original copyrights: 15 * 16 * Support for Cirrus Logic's EP93xx (EP9312, EP9315) CPUs 17 * PATA host controller driver. 18 * 19 * Copyright (c) 2009, Bartlomiej Zolnierkiewicz 20 * 21 * Heavily based on the ep93xx-ide.c driver: 22 * 23 * Copyright (c) 2009, Joao Ramos <joao.ramos@inov.pt> 24 * INESC Inovacao (INOV) 25 * 26 * EP93XX PATA controller driver. 27 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> 28 * 29 * An ATA driver for the Cirrus Logic EP93xx PATA controller. 30 * 31 * Based on an earlier version by Alessandro Zummo, which is: 32 * Copyright (C) 2006 Tower Technologies 33 */ 34 35 #include <linux/err.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/blkdev.h> 39 #include <scsi/scsi_host.h> 40 #include <linux/ata.h> 41 #include <linux/libata.h> 42 #include <linux/platform_device.h> 43 #include <linux/sys_soc.h> 44 #include <linux/delay.h> 45 #include <linux/dmaengine.h> 46 #include <linux/ktime.h> 47 #include <linux/mod_devicetable.h> 48 49 #include <linux/soc/cirrus/ep93xx.h> 50 51 #define DRV_NAME "ep93xx-ide" 52 #define DRV_VERSION "1.0" 53 54 enum { 55 /* IDE Control Register */ 56 IDECTRL = 0x00, 57 IDECTRL_CS0N = (1 << 0), 58 IDECTRL_CS1N = (1 << 1), 59 IDECTRL_DIORN = (1 << 5), 60 IDECTRL_DIOWN = (1 << 6), 61 IDECTRL_INTRQ = (1 << 9), 62 IDECTRL_IORDY = (1 << 10), 63 /* 64 * the device IDE register to be accessed is selected through 65 * IDECTRL register's specific bitfields 'DA', 'CS1N' and 'CS0N': 66 * b4 b3 b2 b1 b0 67 * A2 A1 A0 CS1N CS0N 68 * the values filled in this structure allows the value to be directly 69 * ORed to the IDECTRL register, hence giving directly the A[2:0] and 70 * CS1N/CS0N values for each IDE register. 71 * The values correspond to the transformation: 72 * ((real IDE address) << 2) | CS1N value << 1 | CS0N value 73 */ 74 IDECTRL_ADDR_CMD = 0 + 2, /* CS1 */ 75 IDECTRL_ADDR_DATA = (ATA_REG_DATA << 2) + 2, 76 IDECTRL_ADDR_ERROR = (ATA_REG_ERR << 2) + 2, 77 IDECTRL_ADDR_FEATURE = (ATA_REG_FEATURE << 2) + 2, 78 IDECTRL_ADDR_NSECT = (ATA_REG_NSECT << 2) + 2, 79 IDECTRL_ADDR_LBAL = (ATA_REG_LBAL << 2) + 2, 80 IDECTRL_ADDR_LBAM = (ATA_REG_LBAM << 2) + 2, 81 IDECTRL_ADDR_LBAH = (ATA_REG_LBAH << 2) + 2, 82 IDECTRL_ADDR_DEVICE = (ATA_REG_DEVICE << 2) + 2, 83 IDECTRL_ADDR_STATUS = (ATA_REG_STATUS << 2) + 2, 84 IDECTRL_ADDR_COMMAND = (ATA_REG_CMD << 2) + 2, 85 IDECTRL_ADDR_ALTSTATUS = (0x06 << 2) + 1, /* CS0 */ 86 IDECTRL_ADDR_CTL = (0x06 << 2) + 1, /* CS0 */ 87 88 /* IDE Configuration Register */ 89 IDECFG = 0x04, 90 IDECFG_IDEEN = (1 << 0), 91 IDECFG_PIO = (1 << 1), 92 IDECFG_MDMA = (1 << 2), 93 IDECFG_UDMA = (1 << 3), 94 IDECFG_MODE_SHIFT = 4, 95 IDECFG_MODE_MASK = (0xf << 4), 96 IDECFG_WST_SHIFT = 8, 97 IDECFG_WST_MASK = (0x3 << 8), 98 99 /* MDMA Operation Register */ 100 IDEMDMAOP = 0x08, 101 102 /* UDMA Operation Register */ 103 IDEUDMAOP = 0x0c, 104 IDEUDMAOP_UEN = (1 << 0), 105 IDEUDMAOP_RWOP = (1 << 1), 106 107 /* PIO/MDMA/UDMA Data Registers */ 108 IDEDATAOUT = 0x10, 109 IDEDATAIN = 0x14, 110 IDEMDMADATAOUT = 0x18, 111 IDEMDMADATAIN = 0x1c, 112 IDEUDMADATAOUT = 0x20, 113 IDEUDMADATAIN = 0x24, 114 115 /* UDMA Status Register */ 116 IDEUDMASTS = 0x28, 117 IDEUDMASTS_DMAIDE = (1 << 16), 118 IDEUDMASTS_INTIDE = (1 << 17), 119 IDEUDMASTS_SBUSY = (1 << 18), 120 IDEUDMASTS_NDO = (1 << 24), 121 IDEUDMASTS_NDI = (1 << 25), 122 IDEUDMASTS_N4X = (1 << 26), 123 124 /* UDMA Debug Status Register */ 125 IDEUDMADEBUG = 0x2c, 126 }; 127 128 struct ep93xx_pata_data { 129 struct platform_device *pdev; 130 void __iomem *ide_base; 131 struct ata_timing t; 132 bool iordy; 133 134 unsigned long udma_in_phys; 135 unsigned long udma_out_phys; 136 137 struct dma_chan *dma_rx_channel; 138 struct dma_chan *dma_tx_channel; 139 }; 140 141 static void ep93xx_pata_clear_regs(void __iomem *base) 142 { 143 writel(IDECTRL_CS0N | IDECTRL_CS1N | IDECTRL_DIORN | 144 IDECTRL_DIOWN, base + IDECTRL); 145 146 writel(0, base + IDECFG); 147 writel(0, base + IDEMDMAOP); 148 writel(0, base + IDEUDMAOP); 149 writel(0, base + IDEDATAOUT); 150 writel(0, base + IDEDATAIN); 151 writel(0, base + IDEMDMADATAOUT); 152 writel(0, base + IDEMDMADATAIN); 153 writel(0, base + IDEUDMADATAOUT); 154 writel(0, base + IDEUDMADATAIN); 155 writel(0, base + IDEUDMADEBUG); 156 } 157 158 static bool ep93xx_pata_check_iordy(void __iomem *base) 159 { 160 return !!(readl(base + IDECTRL) & IDECTRL_IORDY); 161 } 162 163 /* 164 * According to EP93xx User's Guide, WST field of IDECFG specifies number 165 * of HCLK cycles to hold the data bus after a PIO write operation. 166 * It should be programmed to guarantee following delays: 167 * 168 * PIO Mode [ns] 169 * 0 30 170 * 1 20 171 * 2 15 172 * 3 10 173 * 4 5 174 * 175 * Maximum possible value for HCLK is 100MHz. 176 */ 177 static int ep93xx_pata_get_wst(int pio_mode) 178 { 179 int val; 180 181 if (pio_mode == 0) 182 val = 3; 183 else if (pio_mode < 3) 184 val = 2; 185 else 186 val = 1; 187 188 return val << IDECFG_WST_SHIFT; 189 } 190 191 static void ep93xx_pata_enable_pio(void __iomem *base, int pio_mode) 192 { 193 writel(IDECFG_IDEEN | IDECFG_PIO | 194 ep93xx_pata_get_wst(pio_mode) | 195 (pio_mode << IDECFG_MODE_SHIFT), base + IDECFG); 196 } 197 198 /* 199 * Based on delay loop found in mach-pxa/mp900.c. 200 * 201 * Single iteration should take 5 cpu cycles. This is 25ns assuming the 202 * fastest ep93xx cpu speed (200MHz) and is better optimized for PIO4 timings 203 * than eg. 20ns. 204 */ 205 static void ep93xx_pata_delay(unsigned long count) 206 { 207 #ifdef CONFIG_ARM 208 __asm__ volatile ( 209 "0:\n" 210 "mov r0, r0\n" 211 "subs %0, %1, #1\n" 212 "bge 0b\n" 213 : "=r" (count) 214 : "0" (count) 215 ); 216 #else 217 while (count--) 218 cpu_relax(); 219 #endif 220 } 221 222 static unsigned long ep93xx_pata_wait_for_iordy(void __iomem *base, 223 unsigned long t2) 224 { 225 /* 226 * According to ATA specification, IORDY pin can be first sampled 227 * tA = 35ns after activation of DIOR-/DIOW-. Maximum IORDY pulse 228 * width is tB = 1250ns. 229 * 230 * We are already t2 delay loop iterations after activation of 231 * DIOR-/DIOW-, so we set timeout to (1250 + 35) / 25 - t2 additional 232 * delay loop iterations. 233 */ 234 unsigned long start = (1250 + 35) / 25 - t2; 235 unsigned long counter = start; 236 237 while (!ep93xx_pata_check_iordy(base) && counter--) 238 ep93xx_pata_delay(1); 239 return start - counter; 240 } 241 242 /* common part at start of ep93xx_pata_read/write() */ 243 static void ep93xx_pata_rw_begin(void __iomem *base, unsigned long addr, 244 unsigned long t1) 245 { 246 writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL); 247 ep93xx_pata_delay(t1); 248 } 249 250 /* common part at end of ep93xx_pata_read/write() */ 251 static void ep93xx_pata_rw_end(void __iomem *base, unsigned long addr, 252 bool iordy, unsigned long t0, unsigned long t2, 253 unsigned long t2i) 254 { 255 ep93xx_pata_delay(t2); 256 /* lengthen t2 if needed */ 257 if (iordy) 258 t2 += ep93xx_pata_wait_for_iordy(base, t2); 259 writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL); 260 if (t0 > t2 && t0 - t2 > t2i) 261 ep93xx_pata_delay(t0 - t2); 262 else 263 ep93xx_pata_delay(t2i); 264 } 265 266 static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data, 267 unsigned long addr, 268 bool reg) 269 { 270 void __iomem *base = drv_data->ide_base; 271 const struct ata_timing *t = &drv_data->t; 272 unsigned long t0 = reg ? t->cyc8b : t->cycle; 273 unsigned long t2 = reg ? t->act8b : t->active; 274 unsigned long t2i = reg ? t->rec8b : t->recover; 275 276 ep93xx_pata_rw_begin(base, addr, t->setup); 277 writel(IDECTRL_DIOWN | addr, base + IDECTRL); 278 /* 279 * The IDEDATAIN register is loaded from the DD pins at the positive 280 * edge of the DIORN signal. (EP93xx UG p27-14) 281 */ 282 ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i); 283 return readl(base + IDEDATAIN); 284 } 285 286 /* IDE register read */ 287 static u16 ep93xx_pata_read_reg(struct ep93xx_pata_data *drv_data, 288 unsigned long addr) 289 { 290 return ep93xx_pata_read(drv_data, addr, true); 291 } 292 293 /* PIO data read */ 294 static u16 ep93xx_pata_read_data(struct ep93xx_pata_data *drv_data, 295 unsigned long addr) 296 { 297 return ep93xx_pata_read(drv_data, addr, false); 298 } 299 300 static void ep93xx_pata_write(struct ep93xx_pata_data *drv_data, 301 u16 value, unsigned long addr, 302 bool reg) 303 { 304 void __iomem *base = drv_data->ide_base; 305 const struct ata_timing *t = &drv_data->t; 306 unsigned long t0 = reg ? t->cyc8b : t->cycle; 307 unsigned long t2 = reg ? t->act8b : t->active; 308 unsigned long t2i = reg ? t->rec8b : t->recover; 309 310 ep93xx_pata_rw_begin(base, addr, t->setup); 311 /* 312 * Value from IDEDATAOUT register is driven onto the DD pins when 313 * DIOWN is low. (EP93xx UG p27-13) 314 */ 315 writel(value, base + IDEDATAOUT); 316 writel(IDECTRL_DIORN | addr, base + IDECTRL); 317 ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i); 318 } 319 320 /* IDE register write */ 321 static void ep93xx_pata_write_reg(struct ep93xx_pata_data *drv_data, 322 u16 value, unsigned long addr) 323 { 324 ep93xx_pata_write(drv_data, value, addr, true); 325 } 326 327 /* PIO data write */ 328 static void ep93xx_pata_write_data(struct ep93xx_pata_data *drv_data, 329 u16 value, unsigned long addr) 330 { 331 ep93xx_pata_write(drv_data, value, addr, false); 332 } 333 334 static void ep93xx_pata_set_piomode(struct ata_port *ap, 335 struct ata_device *adev) 336 { 337 struct ep93xx_pata_data *drv_data = ap->host->private_data; 338 struct ata_device *pair = ata_dev_pair(adev); 339 /* 340 * Calculate timings for the delay loop, assuming ep93xx cpu speed 341 * is 200MHz (maximum possible for ep93xx). If actual cpu speed is 342 * slower, we will wait a bit longer in each delay. 343 * Additional division of cpu speed by 5, because single iteration 344 * of our delay loop takes 5 cpu cycles (25ns). 345 */ 346 unsigned long T = 1000000 / (200 / 5); 347 348 ata_timing_compute(adev, adev->pio_mode, &drv_data->t, T, 0); 349 if (pair && pair->pio_mode) { 350 struct ata_timing t; 351 ata_timing_compute(pair, pair->pio_mode, &t, T, 0); 352 ata_timing_merge(&t, &drv_data->t, &drv_data->t, 353 ATA_TIMING_SETUP | ATA_TIMING_8BIT); 354 } 355 drv_data->iordy = ata_pio_need_iordy(adev); 356 357 ep93xx_pata_enable_pio(drv_data->ide_base, 358 adev->pio_mode - XFER_PIO_0); 359 } 360 361 /* Note: original code is ata_sff_check_status */ 362 static u8 ep93xx_pata_check_status(struct ata_port *ap) 363 { 364 struct ep93xx_pata_data *drv_data = ap->host->private_data; 365 366 return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_STATUS); 367 } 368 369 static u8 ep93xx_pata_check_altstatus(struct ata_port *ap) 370 { 371 struct ep93xx_pata_data *drv_data = ap->host->private_data; 372 373 return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_ALTSTATUS); 374 } 375 376 /* Note: original code is ata_sff_tf_load */ 377 static void ep93xx_pata_tf_load(struct ata_port *ap, 378 const struct ata_taskfile *tf) 379 { 380 struct ep93xx_pata_data *drv_data = ap->host->private_data; 381 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 382 383 if (tf->ctl != ap->last_ctl) { 384 ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL); 385 ap->last_ctl = tf->ctl; 386 ata_wait_idle(ap); 387 } 388 389 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 390 ep93xx_pata_write_reg(drv_data, tf->hob_feature, 391 IDECTRL_ADDR_FEATURE); 392 ep93xx_pata_write_reg(drv_data, tf->hob_nsect, 393 IDECTRL_ADDR_NSECT); 394 ep93xx_pata_write_reg(drv_data, tf->hob_lbal, 395 IDECTRL_ADDR_LBAL); 396 ep93xx_pata_write_reg(drv_data, tf->hob_lbam, 397 IDECTRL_ADDR_LBAM); 398 ep93xx_pata_write_reg(drv_data, tf->hob_lbah, 399 IDECTRL_ADDR_LBAH); 400 } 401 402 if (is_addr) { 403 ep93xx_pata_write_reg(drv_data, tf->feature, 404 IDECTRL_ADDR_FEATURE); 405 ep93xx_pata_write_reg(drv_data, tf->nsect, IDECTRL_ADDR_NSECT); 406 ep93xx_pata_write_reg(drv_data, tf->lbal, IDECTRL_ADDR_LBAL); 407 ep93xx_pata_write_reg(drv_data, tf->lbam, IDECTRL_ADDR_LBAM); 408 ep93xx_pata_write_reg(drv_data, tf->lbah, IDECTRL_ADDR_LBAH); 409 } 410 411 if (tf->flags & ATA_TFLAG_DEVICE) 412 ep93xx_pata_write_reg(drv_data, tf->device, 413 IDECTRL_ADDR_DEVICE); 414 415 ata_wait_idle(ap); 416 } 417 418 /* Note: original code is ata_sff_tf_read */ 419 static void ep93xx_pata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 420 { 421 struct ep93xx_pata_data *drv_data = ap->host->private_data; 422 423 tf->status = ep93xx_pata_check_status(ap); 424 tf->error = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_FEATURE); 425 tf->nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT); 426 tf->lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL); 427 tf->lbam = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAM); 428 tf->lbah = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAH); 429 tf->device = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DEVICE); 430 431 if (tf->flags & ATA_TFLAG_LBA48) { 432 ep93xx_pata_write_reg(drv_data, tf->ctl | ATA_HOB, 433 IDECTRL_ADDR_CTL); 434 tf->hob_feature = ep93xx_pata_read_reg(drv_data, 435 IDECTRL_ADDR_FEATURE); 436 tf->hob_nsect = ep93xx_pata_read_reg(drv_data, 437 IDECTRL_ADDR_NSECT); 438 tf->hob_lbal = ep93xx_pata_read_reg(drv_data, 439 IDECTRL_ADDR_LBAL); 440 tf->hob_lbam = ep93xx_pata_read_reg(drv_data, 441 IDECTRL_ADDR_LBAM); 442 tf->hob_lbah = ep93xx_pata_read_reg(drv_data, 443 IDECTRL_ADDR_LBAH); 444 ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL); 445 ap->last_ctl = tf->ctl; 446 } 447 } 448 449 /* Note: original code is ata_sff_exec_command */ 450 static void ep93xx_pata_exec_command(struct ata_port *ap, 451 const struct ata_taskfile *tf) 452 { 453 struct ep93xx_pata_data *drv_data = ap->host->private_data; 454 455 ep93xx_pata_write_reg(drv_data, tf->command, 456 IDECTRL_ADDR_COMMAND); 457 ata_sff_pause(ap); 458 } 459 460 /* Note: original code is ata_sff_dev_select */ 461 static void ep93xx_pata_dev_select(struct ata_port *ap, unsigned int device) 462 { 463 struct ep93xx_pata_data *drv_data = ap->host->private_data; 464 u8 tmp = ATA_DEVICE_OBS; 465 466 if (device != 0) 467 tmp |= ATA_DEV1; 468 469 ep93xx_pata_write_reg(drv_data, tmp, IDECTRL_ADDR_DEVICE); 470 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 471 } 472 473 /* Note: original code is ata_sff_set_devctl */ 474 static void ep93xx_pata_set_devctl(struct ata_port *ap, u8 ctl) 475 { 476 struct ep93xx_pata_data *drv_data = ap->host->private_data; 477 478 ep93xx_pata_write_reg(drv_data, ctl, IDECTRL_ADDR_CTL); 479 } 480 481 /* Note: original code is ata_sff_data_xfer */ 482 static unsigned int ep93xx_pata_data_xfer(struct ata_queued_cmd *qc, 483 unsigned char *buf, 484 unsigned int buflen, int rw) 485 { 486 struct ata_port *ap = qc->dev->link->ap; 487 struct ep93xx_pata_data *drv_data = ap->host->private_data; 488 u16 *data = (u16 *)buf; 489 unsigned int words = buflen >> 1; 490 491 /* Transfer multiple of 2 bytes */ 492 while (words--) 493 if (rw == READ) 494 *data++ = cpu_to_le16( 495 ep93xx_pata_read_data( 496 drv_data, IDECTRL_ADDR_DATA)); 497 else 498 ep93xx_pata_write_data(drv_data, le16_to_cpu(*data++), 499 IDECTRL_ADDR_DATA); 500 501 /* Transfer trailing 1 byte, if any. */ 502 if (unlikely(buflen & 0x01)) { 503 unsigned char pad[2] = { }; 504 505 buf += buflen - 1; 506 507 if (rw == READ) { 508 *pad = cpu_to_le16( 509 ep93xx_pata_read_data( 510 drv_data, IDECTRL_ADDR_DATA)); 511 *buf = pad[0]; 512 } else { 513 pad[0] = *buf; 514 ep93xx_pata_write_data(drv_data, le16_to_cpu(*pad), 515 IDECTRL_ADDR_DATA); 516 } 517 words++; 518 } 519 520 return words << 1; 521 } 522 523 /* Note: original code is ata_devchk */ 524 static bool ep93xx_pata_device_is_present(struct ata_port *ap, 525 unsigned int device) 526 { 527 struct ep93xx_pata_data *drv_data = ap->host->private_data; 528 u8 nsect, lbal; 529 530 ap->ops->sff_dev_select(ap, device); 531 532 ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT); 533 ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL); 534 535 ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_NSECT); 536 ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_LBAL); 537 538 ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT); 539 ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL); 540 541 nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT); 542 lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL); 543 544 if ((nsect == 0x55) && (lbal == 0xaa)) 545 return true; 546 547 return false; 548 } 549 550 /* Note: original code is ata_sff_wait_after_reset */ 551 static int ep93xx_pata_wait_after_reset(struct ata_link *link, 552 unsigned int devmask, 553 unsigned long deadline) 554 { 555 struct ata_port *ap = link->ap; 556 struct ep93xx_pata_data *drv_data = ap->host->private_data; 557 unsigned int dev0 = devmask & (1 << 0); 558 unsigned int dev1 = devmask & (1 << 1); 559 int rc, ret = 0; 560 561 ata_msleep(ap, ATA_WAIT_AFTER_RESET); 562 563 /* always check readiness of the master device */ 564 rc = ata_sff_wait_ready(link, deadline); 565 /* 566 * -ENODEV means the odd clown forgot the D7 pulldown resistor 567 * and TF status is 0xff, bail out on it too. 568 */ 569 if (rc) 570 return rc; 571 572 /* 573 * if device 1 was found in ata_devchk, wait for register 574 * access briefly, then wait for BSY to clear. 575 */ 576 if (dev1) { 577 int i; 578 579 ap->ops->sff_dev_select(ap, 1); 580 581 /* 582 * Wait for register access. Some ATAPI devices fail 583 * to set nsect/lbal after reset, so don't waste too 584 * much time on it. We're gonna wait for !BSY anyway. 585 */ 586 for (i = 0; i < 2; i++) { 587 u8 nsect, lbal; 588 589 nsect = ep93xx_pata_read_reg(drv_data, 590 IDECTRL_ADDR_NSECT); 591 lbal = ep93xx_pata_read_reg(drv_data, 592 IDECTRL_ADDR_LBAL); 593 if (nsect == 1 && lbal == 1) 594 break; 595 msleep(50); /* give drive a breather */ 596 } 597 598 rc = ata_sff_wait_ready(link, deadline); 599 if (rc) { 600 if (rc != -ENODEV) 601 return rc; 602 ret = rc; 603 } 604 } 605 /* is all this really necessary? */ 606 ap->ops->sff_dev_select(ap, 0); 607 if (dev1) 608 ap->ops->sff_dev_select(ap, 1); 609 if (dev0) 610 ap->ops->sff_dev_select(ap, 0); 611 612 return ret; 613 } 614 615 /* Note: original code is ata_bus_softreset */ 616 static int ep93xx_pata_bus_softreset(struct ata_port *ap, unsigned int devmask, 617 unsigned long deadline) 618 { 619 struct ep93xx_pata_data *drv_data = ap->host->private_data; 620 621 ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL); 622 udelay(20); /* FIXME: flush */ 623 ep93xx_pata_write_reg(drv_data, ap->ctl | ATA_SRST, IDECTRL_ADDR_CTL); 624 udelay(20); /* FIXME: flush */ 625 ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL); 626 ap->last_ctl = ap->ctl; 627 628 return ep93xx_pata_wait_after_reset(&ap->link, devmask, deadline); 629 } 630 631 static void ep93xx_pata_release_dma(struct ep93xx_pata_data *drv_data) 632 { 633 if (drv_data->dma_rx_channel) { 634 dma_release_channel(drv_data->dma_rx_channel); 635 drv_data->dma_rx_channel = NULL; 636 } 637 if (drv_data->dma_tx_channel) { 638 dma_release_channel(drv_data->dma_tx_channel); 639 drv_data->dma_tx_channel = NULL; 640 } 641 } 642 643 static int ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data) 644 { 645 struct platform_device *pdev = drv_data->pdev; 646 struct device *dev = &pdev->dev; 647 dma_cap_mask_t mask; 648 struct dma_slave_config conf; 649 int ret; 650 651 dma_cap_zero(mask); 652 dma_cap_set(DMA_SLAVE, mask); 653 654 /* 655 * Request two channels for IDE. Another possibility would be 656 * to request only one channel, and reprogram it's direction at 657 * start of new transfer. 658 */ 659 drv_data->dma_rx_channel = dma_request_chan(dev, "rx"); 660 if (IS_ERR(drv_data->dma_rx_channel)) 661 return dev_err_probe(dev, PTR_ERR(drv_data->dma_rx_channel), 662 "rx DMA setup failed\n"); 663 664 drv_data->dma_tx_channel = dma_request_chan(&pdev->dev, "tx"); 665 if (IS_ERR(drv_data->dma_tx_channel)) { 666 ret = dev_err_probe(dev, PTR_ERR(drv_data->dma_tx_channel), 667 "tx DMA setup failed\n"); 668 goto fail_release_rx; 669 } 670 671 /* Configure receive channel direction and source address */ 672 memset(&conf, 0, sizeof(conf)); 673 conf.direction = DMA_DEV_TO_MEM; 674 conf.src_addr = drv_data->udma_in_phys; 675 conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 676 ret = dmaengine_slave_config(drv_data->dma_rx_channel, &conf); 677 if (ret) { 678 dev_err_probe(dev, ret, "failed to configure rx dma channel"); 679 goto fail_release_dma; 680 } 681 682 /* Configure transmit channel direction and destination address */ 683 memset(&conf, 0, sizeof(conf)); 684 conf.direction = DMA_MEM_TO_DEV; 685 conf.dst_addr = drv_data->udma_out_phys; 686 conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 687 ret = dmaengine_slave_config(drv_data->dma_tx_channel, &conf); 688 if (ret) { 689 dev_err_probe(dev, ret, "failed to configure tx dma channel"); 690 goto fail_release_dma; 691 } 692 693 return 0; 694 695 fail_release_rx: 696 dma_release_channel(drv_data->dma_rx_channel); 697 fail_release_dma: 698 ep93xx_pata_release_dma(drv_data); 699 700 return ret; 701 } 702 703 static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc) 704 { 705 struct dma_async_tx_descriptor *txd; 706 struct ep93xx_pata_data *drv_data = qc->ap->host->private_data; 707 void __iomem *base = drv_data->ide_base; 708 struct ata_device *adev = qc->dev; 709 u32 v = qc->dma_dir == DMA_TO_DEVICE ? IDEUDMAOP_RWOP : 0; 710 struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE 711 ? drv_data->dma_tx_channel : drv_data->dma_rx_channel; 712 713 txd = dmaengine_prep_slave_sg(channel, qc->sg, qc->n_elem, qc->dma_dir, 714 DMA_CTRL_ACK); 715 if (!txd) { 716 dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n"); 717 return; 718 } 719 txd->callback = NULL; 720 txd->callback_param = NULL; 721 722 if (dmaengine_submit(txd) < 0) { 723 dev_err(qc->ap->dev, "failed to submit dma transfer\n"); 724 return; 725 } 726 dma_async_issue_pending(channel); 727 728 /* 729 * When enabling UDMA operation, IDEUDMAOP register needs to be 730 * programmed in three step sequence: 731 * 1) set or clear the RWOP bit, 732 * 2) perform dummy read of the register, 733 * 3) set the UEN bit. 734 */ 735 writel(v, base + IDEUDMAOP); 736 readl(base + IDEUDMAOP); 737 writel(v | IDEUDMAOP_UEN, base + IDEUDMAOP); 738 739 writel(IDECFG_IDEEN | IDECFG_UDMA | 740 ((adev->xfer_mode - XFER_UDMA_0) << IDECFG_MODE_SHIFT), 741 base + IDECFG); 742 } 743 744 static void ep93xx_pata_dma_stop(struct ata_queued_cmd *qc) 745 { 746 struct ep93xx_pata_data *drv_data = qc->ap->host->private_data; 747 void __iomem *base = drv_data->ide_base; 748 749 /* terminate all dma transfers, if not yet finished */ 750 dmaengine_terminate_all(drv_data->dma_rx_channel); 751 dmaengine_terminate_all(drv_data->dma_tx_channel); 752 753 /* 754 * To properly stop IDE-DMA, IDEUDMAOP register must to be cleared 755 * and IDECTRL register must be set to default value. 756 */ 757 writel(0, base + IDEUDMAOP); 758 writel(readl(base + IDECTRL) | IDECTRL_DIOWN | IDECTRL_DIORN | 759 IDECTRL_CS0N | IDECTRL_CS1N, base + IDECTRL); 760 761 ep93xx_pata_enable_pio(drv_data->ide_base, 762 qc->dev->pio_mode - XFER_PIO_0); 763 764 ata_sff_dma_pause(qc->ap); 765 } 766 767 static void ep93xx_pata_dma_setup(struct ata_queued_cmd *qc) 768 { 769 qc->ap->ops->sff_exec_command(qc->ap, &qc->tf); 770 } 771 772 static u8 ep93xx_pata_dma_status(struct ata_port *ap) 773 { 774 struct ep93xx_pata_data *drv_data = ap->host->private_data; 775 u32 val = readl(drv_data->ide_base + IDEUDMASTS); 776 777 /* 778 * UDMA Status Register bits: 779 * 780 * DMAIDE - DMA request signal from UDMA state machine, 781 * INTIDE - INT line generated by UDMA because of errors in the 782 * state machine, 783 * SBUSY - UDMA state machine busy, not in idle state, 784 * NDO - error for data-out not completed, 785 * NDI - error for data-in not completed, 786 * N4X - error for data transferred not multiplies of four 787 * 32-bit words. 788 * (EP93xx UG p27-17) 789 */ 790 if (val & IDEUDMASTS_NDO || val & IDEUDMASTS_NDI || 791 val & IDEUDMASTS_N4X || val & IDEUDMASTS_INTIDE) 792 return ATA_DMA_ERR; 793 794 /* read INTRQ (INT[3]) pin input state */ 795 if (readl(drv_data->ide_base + IDECTRL) & IDECTRL_INTRQ) 796 return ATA_DMA_INTR; 797 798 if (val & IDEUDMASTS_SBUSY || val & IDEUDMASTS_DMAIDE) 799 return ATA_DMA_ACTIVE; 800 801 return 0; 802 } 803 804 /* Note: original code is ata_sff_softreset */ 805 static int ep93xx_pata_softreset(struct ata_link *al, unsigned int *classes, 806 unsigned long deadline) 807 { 808 struct ata_port *ap = al->ap; 809 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; 810 unsigned int devmask = 0; 811 int rc; 812 u8 err; 813 814 /* determine if device 0/1 are present */ 815 if (ep93xx_pata_device_is_present(ap, 0)) 816 devmask |= (1 << 0); 817 if (slave_possible && ep93xx_pata_device_is_present(ap, 1)) 818 devmask |= (1 << 1); 819 820 /* select device 0 again */ 821 ap->ops->sff_dev_select(al->ap, 0); 822 823 /* issue bus reset */ 824 rc = ep93xx_pata_bus_softreset(ap, devmask, deadline); 825 /* if link is ocuppied, -ENODEV too is an error */ 826 if (rc && (rc != -ENODEV || sata_scr_valid(al))) { 827 ata_link_err(al, "SRST failed (errno=%d)\n", rc); 828 return rc; 829 } 830 831 /* determine by signature whether we have ATA or ATAPI devices */ 832 classes[0] = ata_sff_dev_classify(&al->device[0], devmask & (1 << 0), 833 &err); 834 if (slave_possible && err != 0x81) 835 classes[1] = ata_sff_dev_classify(&al->device[1], 836 devmask & (1 << 1), &err); 837 838 return 0; 839 } 840 841 /* Note: original code is ata_sff_drain_fifo */ 842 static void ep93xx_pata_drain_fifo(struct ata_queued_cmd *qc) 843 { 844 int count; 845 struct ata_port *ap; 846 struct ep93xx_pata_data *drv_data; 847 848 /* We only need to flush incoming data when a command was running */ 849 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) 850 return; 851 852 ap = qc->ap; 853 drv_data = ap->host->private_data; 854 /* Drain up to 64K of data before we give up this recovery method */ 855 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) 856 && count < 65536; count += 2) 857 ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DATA); 858 859 if (count) 860 ata_port_dbg(ap, "drained %d bytes to clear DRQ.\n", count); 861 862 } 863 864 static int ep93xx_pata_port_start(struct ata_port *ap) 865 { 866 struct ep93xx_pata_data *drv_data = ap->host->private_data; 867 868 /* 869 * Set timings to safe values at startup (= number of ns from ATA 870 * specification), we'll switch to properly calculated values later. 871 */ 872 drv_data->t = *ata_timing_find_mode(XFER_PIO_0); 873 return 0; 874 } 875 876 static const struct scsi_host_template ep93xx_pata_sht = { 877 ATA_BASE_SHT(DRV_NAME), 878 /* ep93xx dma implementation limit */ 879 .sg_tablesize = 32, 880 /* ep93xx dma can't transfer 65536 bytes at once */ 881 .dma_boundary = 0x7fff, 882 }; 883 884 static struct ata_port_operations ep93xx_pata_port_ops = { 885 .inherits = &ata_bmdma_port_ops, 886 887 .reset.softreset = ep93xx_pata_softreset, 888 .reset.hardreset = ATA_OP_NULL, 889 890 .sff_dev_select = ep93xx_pata_dev_select, 891 .sff_set_devctl = ep93xx_pata_set_devctl, 892 .sff_check_status = ep93xx_pata_check_status, 893 .sff_check_altstatus = ep93xx_pata_check_altstatus, 894 .sff_tf_load = ep93xx_pata_tf_load, 895 .sff_tf_read = ep93xx_pata_tf_read, 896 .sff_exec_command = ep93xx_pata_exec_command, 897 .sff_data_xfer = ep93xx_pata_data_xfer, 898 .sff_drain_fifo = ep93xx_pata_drain_fifo, 899 .sff_irq_clear = ATA_OP_NULL, 900 901 .set_piomode = ep93xx_pata_set_piomode, 902 903 .bmdma_setup = ep93xx_pata_dma_setup, 904 .bmdma_start = ep93xx_pata_dma_start, 905 .bmdma_stop = ep93xx_pata_dma_stop, 906 .bmdma_status = ep93xx_pata_dma_status, 907 908 .cable_detect = ata_cable_unknown, 909 .port_start = ep93xx_pata_port_start, 910 }; 911 912 static const struct soc_device_attribute ep93xx_soc_table[] = { 913 { .revision = "E1", .data = (void *)ATA_UDMA3 }, 914 { .revision = "E2", .data = (void *)ATA_UDMA4 }, 915 { /* sentinel */ } 916 }; 917 918 static int ep93xx_pata_probe(struct platform_device *pdev) 919 { 920 struct ep93xx_pata_data *drv_data; 921 struct ata_host *host; 922 struct ata_port *ap; 923 int irq; 924 struct resource *mem_res; 925 void __iomem *ide_base; 926 int err; 927 928 /* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */ 929 irq = platform_get_irq(pdev, 0); 930 if (irq < 0) 931 return irq; 932 933 ide_base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); 934 if (IS_ERR(ide_base)) 935 return PTR_ERR(ide_base); 936 937 drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL); 938 if (!drv_data) 939 return -ENOMEM; 940 941 drv_data->pdev = pdev; 942 drv_data->ide_base = ide_base; 943 drv_data->udma_in_phys = mem_res->start + IDEUDMADATAIN; 944 drv_data->udma_out_phys = mem_res->start + IDEUDMADATAOUT; 945 err = ep93xx_pata_dma_init(drv_data); 946 if (err) 947 return err; 948 949 /* allocate host */ 950 host = ata_host_alloc(&pdev->dev, 1); 951 if (!host) { 952 err = -ENOMEM; 953 goto err_rel_dma; 954 } 955 956 ep93xx_pata_clear_regs(ide_base); 957 958 host->private_data = drv_data; 959 960 ap = host->ports[0]; 961 ap->dev = &pdev->dev; 962 ap->ops = &ep93xx_pata_port_ops; 963 ap->flags |= ATA_FLAG_SLAVE_POSS; 964 ap->pio_mask = ATA_PIO4; 965 966 /* 967 * Maximum UDMA modes: 968 * EP931x rev.E0 - UDMA2 969 * EP931x rev.E1 - UDMA3 970 * EP931x rev.E2 - UDMA4 971 * 972 * MWDMA support was removed from EP931x rev.E2, 973 * so this driver supports only UDMA modes. 974 */ 975 if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) { 976 const struct soc_device_attribute *match; 977 978 match = soc_device_match(ep93xx_soc_table); 979 if (match) 980 ap->udma_mask = (unsigned long) match->data; 981 else 982 ap->udma_mask = ATA_UDMA2; 983 } 984 985 /* defaults, pio 0 */ 986 ep93xx_pata_enable_pio(ide_base, 0); 987 988 dev_info(&pdev->dev, "version " DRV_VERSION "\n"); 989 990 /* activate host */ 991 err = ata_host_activate(host, irq, ata_bmdma_interrupt, 0, 992 &ep93xx_pata_sht); 993 if (err == 0) 994 return 0; 995 996 err_rel_dma: 997 ep93xx_pata_release_dma(drv_data); 998 return err; 999 } 1000 1001 static void ep93xx_pata_remove(struct platform_device *pdev) 1002 { 1003 struct ata_host *host = platform_get_drvdata(pdev); 1004 struct ep93xx_pata_data *drv_data = host->private_data; 1005 1006 ata_host_detach(host); 1007 ep93xx_pata_release_dma(drv_data); 1008 ep93xx_pata_clear_regs(drv_data->ide_base); 1009 } 1010 1011 static const struct of_device_id ep93xx_pata_of_ids[] = { 1012 { .compatible = "cirrus,ep9312-pata" }, 1013 { /* sentinel */ } 1014 }; 1015 MODULE_DEVICE_TABLE(of, ep93xx_pata_of_ids); 1016 1017 static struct platform_driver ep93xx_pata_platform_driver = { 1018 .driver = { 1019 .name = DRV_NAME, 1020 .of_match_table = ep93xx_pata_of_ids, 1021 }, 1022 .probe = ep93xx_pata_probe, 1023 .remove = ep93xx_pata_remove, 1024 }; 1025 1026 module_platform_driver(ep93xx_pata_platform_driver); 1027 1028 MODULE_AUTHOR("Alessandro Zummo, Lennert Buytenhek, Joao Ramos, " 1029 "Bartlomiej Zolnierkiewicz, Rafal Prylowski"); 1030 MODULE_DESCRIPTION("low-level driver for cirrus ep93xx IDE controller"); 1031 MODULE_LICENSE("GPL"); 1032 MODULE_VERSION(DRV_VERSION); 1033 MODULE_ALIAS("platform:pata_ep93xx"); 1034