1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * EP93XX PATA controller driver. 4 * 5 * Copyright (c) 2012, Metasoft s.c. 6 * Rafal Prylowski <prylowski@metasoft.pl> 7 * 8 * Based on pata_scc.c, pata_icside.c and on earlier version of EP93XX 9 * PATA driver by Lennert Buytenhek and Alessandro Zummo. 10 * Read/Write timings, resource management and other improvements 11 * from driver by Joao Ramos and Bartlomiej Zolnierkiewicz. 12 * DMA engine support based on spi-ep93xx.c by Mika Westerberg. 13 * 14 * Original copyrights: 15 * 16 * Support for Cirrus Logic's EP93xx (EP9312, EP9315) CPUs 17 * PATA host controller driver. 18 * 19 * Copyright (c) 2009, Bartlomiej Zolnierkiewicz 20 * 21 * Heavily based on the ep93xx-ide.c driver: 22 * 23 * Copyright (c) 2009, Joao Ramos <joao.ramos@inov.pt> 24 * INESC Inovacao (INOV) 25 * 26 * EP93XX PATA controller driver. 27 * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> 28 * 29 * An ATA driver for the Cirrus Logic EP93xx PATA controller. 30 * 31 * Based on an earlier version by Alessandro Zummo, which is: 32 * Copyright (C) 2006 Tower Technologies 33 */ 34 35 #include <linux/err.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/blkdev.h> 39 #include <scsi/scsi_host.h> 40 #include <linux/ata.h> 41 #include <linux/libata.h> 42 #include <linux/platform_device.h> 43 #include <linux/sys_soc.h> 44 #include <linux/delay.h> 45 #include <linux/dmaengine.h> 46 #include <linux/ktime.h> 47 48 #include <linux/soc/cirrus/ep93xx.h> 49 50 #define DRV_NAME "ep93xx-ide" 51 #define DRV_VERSION "1.0" 52 53 enum { 54 /* IDE Control Register */ 55 IDECTRL = 0x00, 56 IDECTRL_CS0N = (1 << 0), 57 IDECTRL_CS1N = (1 << 1), 58 IDECTRL_DIORN = (1 << 5), 59 IDECTRL_DIOWN = (1 << 6), 60 IDECTRL_INTRQ = (1 << 9), 61 IDECTRL_IORDY = (1 << 10), 62 /* 63 * the device IDE register to be accessed is selected through 64 * IDECTRL register's specific bitfields 'DA', 'CS1N' and 'CS0N': 65 * b4 b3 b2 b1 b0 66 * A2 A1 A0 CS1N CS0N 67 * the values filled in this structure allows the value to be directly 68 * ORed to the IDECTRL register, hence giving directly the A[2:0] and 69 * CS1N/CS0N values for each IDE register. 70 * The values correspond to the transformation: 71 * ((real IDE address) << 2) | CS1N value << 1 | CS0N value 72 */ 73 IDECTRL_ADDR_CMD = 0 + 2, /* CS1 */ 74 IDECTRL_ADDR_DATA = (ATA_REG_DATA << 2) + 2, 75 IDECTRL_ADDR_ERROR = (ATA_REG_ERR << 2) + 2, 76 IDECTRL_ADDR_FEATURE = (ATA_REG_FEATURE << 2) + 2, 77 IDECTRL_ADDR_NSECT = (ATA_REG_NSECT << 2) + 2, 78 IDECTRL_ADDR_LBAL = (ATA_REG_LBAL << 2) + 2, 79 IDECTRL_ADDR_LBAM = (ATA_REG_LBAM << 2) + 2, 80 IDECTRL_ADDR_LBAH = (ATA_REG_LBAH << 2) + 2, 81 IDECTRL_ADDR_DEVICE = (ATA_REG_DEVICE << 2) + 2, 82 IDECTRL_ADDR_STATUS = (ATA_REG_STATUS << 2) + 2, 83 IDECTRL_ADDR_COMMAND = (ATA_REG_CMD << 2) + 2, 84 IDECTRL_ADDR_ALTSTATUS = (0x06 << 2) + 1, /* CS0 */ 85 IDECTRL_ADDR_CTL = (0x06 << 2) + 1, /* CS0 */ 86 87 /* IDE Configuration Register */ 88 IDECFG = 0x04, 89 IDECFG_IDEEN = (1 << 0), 90 IDECFG_PIO = (1 << 1), 91 IDECFG_MDMA = (1 << 2), 92 IDECFG_UDMA = (1 << 3), 93 IDECFG_MODE_SHIFT = 4, 94 IDECFG_MODE_MASK = (0xf << 4), 95 IDECFG_WST_SHIFT = 8, 96 IDECFG_WST_MASK = (0x3 << 8), 97 98 /* MDMA Operation Register */ 99 IDEMDMAOP = 0x08, 100 101 /* UDMA Operation Register */ 102 IDEUDMAOP = 0x0c, 103 IDEUDMAOP_UEN = (1 << 0), 104 IDEUDMAOP_RWOP = (1 << 1), 105 106 /* PIO/MDMA/UDMA Data Registers */ 107 IDEDATAOUT = 0x10, 108 IDEDATAIN = 0x14, 109 IDEMDMADATAOUT = 0x18, 110 IDEMDMADATAIN = 0x1c, 111 IDEUDMADATAOUT = 0x20, 112 IDEUDMADATAIN = 0x24, 113 114 /* UDMA Status Register */ 115 IDEUDMASTS = 0x28, 116 IDEUDMASTS_DMAIDE = (1 << 16), 117 IDEUDMASTS_INTIDE = (1 << 17), 118 IDEUDMASTS_SBUSY = (1 << 18), 119 IDEUDMASTS_NDO = (1 << 24), 120 IDEUDMASTS_NDI = (1 << 25), 121 IDEUDMASTS_N4X = (1 << 26), 122 123 /* UDMA Debug Status Register */ 124 IDEUDMADEBUG = 0x2c, 125 }; 126 127 struct ep93xx_pata_data { 128 struct platform_device *pdev; 129 void __iomem *ide_base; 130 struct ata_timing t; 131 bool iordy; 132 133 unsigned long udma_in_phys; 134 unsigned long udma_out_phys; 135 136 struct dma_chan *dma_rx_channel; 137 struct dma_chan *dma_tx_channel; 138 }; 139 140 static void ep93xx_pata_clear_regs(void __iomem *base) 141 { 142 writel(IDECTRL_CS0N | IDECTRL_CS1N | IDECTRL_DIORN | 143 IDECTRL_DIOWN, base + IDECTRL); 144 145 writel(0, base + IDECFG); 146 writel(0, base + IDEMDMAOP); 147 writel(0, base + IDEUDMAOP); 148 writel(0, base + IDEDATAOUT); 149 writel(0, base + IDEDATAIN); 150 writel(0, base + IDEMDMADATAOUT); 151 writel(0, base + IDEMDMADATAIN); 152 writel(0, base + IDEUDMADATAOUT); 153 writel(0, base + IDEUDMADATAIN); 154 writel(0, base + IDEUDMADEBUG); 155 } 156 157 static bool ep93xx_pata_check_iordy(void __iomem *base) 158 { 159 return !!(readl(base + IDECTRL) & IDECTRL_IORDY); 160 } 161 162 /* 163 * According to EP93xx User's Guide, WST field of IDECFG specifies number 164 * of HCLK cycles to hold the data bus after a PIO write operation. 165 * It should be programmed to guarantee following delays: 166 * 167 * PIO Mode [ns] 168 * 0 30 169 * 1 20 170 * 2 15 171 * 3 10 172 * 4 5 173 * 174 * Maximum possible value for HCLK is 100MHz. 175 */ 176 static int ep93xx_pata_get_wst(int pio_mode) 177 { 178 int val; 179 180 if (pio_mode == 0) 181 val = 3; 182 else if (pio_mode < 3) 183 val = 2; 184 else 185 val = 1; 186 187 return val << IDECFG_WST_SHIFT; 188 } 189 190 static void ep93xx_pata_enable_pio(void __iomem *base, int pio_mode) 191 { 192 writel(IDECFG_IDEEN | IDECFG_PIO | 193 ep93xx_pata_get_wst(pio_mode) | 194 (pio_mode << IDECFG_MODE_SHIFT), base + IDECFG); 195 } 196 197 /* 198 * Based on delay loop found in mach-pxa/mp900.c. 199 * 200 * Single iteration should take 5 cpu cycles. This is 25ns assuming the 201 * fastest ep93xx cpu speed (200MHz) and is better optimized for PIO4 timings 202 * than eg. 20ns. 203 */ 204 static void ep93xx_pata_delay(unsigned long count) 205 { 206 #ifdef CONFIG_ARM 207 __asm__ volatile ( 208 "0:\n" 209 "mov r0, r0\n" 210 "subs %0, %1, #1\n" 211 "bge 0b\n" 212 : "=r" (count) 213 : "0" (count) 214 ); 215 #else 216 while (count--) 217 cpu_relax(); 218 #endif 219 } 220 221 static unsigned long ep93xx_pata_wait_for_iordy(void __iomem *base, 222 unsigned long t2) 223 { 224 /* 225 * According to ATA specification, IORDY pin can be first sampled 226 * tA = 35ns after activation of DIOR-/DIOW-. Maximum IORDY pulse 227 * width is tB = 1250ns. 228 * 229 * We are already t2 delay loop iterations after activation of 230 * DIOR-/DIOW-, so we set timeout to (1250 + 35) / 25 - t2 additional 231 * delay loop iterations. 232 */ 233 unsigned long start = (1250 + 35) / 25 - t2; 234 unsigned long counter = start; 235 236 while (!ep93xx_pata_check_iordy(base) && counter--) 237 ep93xx_pata_delay(1); 238 return start - counter; 239 } 240 241 /* common part at start of ep93xx_pata_read/write() */ 242 static void ep93xx_pata_rw_begin(void __iomem *base, unsigned long addr, 243 unsigned long t1) 244 { 245 writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL); 246 ep93xx_pata_delay(t1); 247 } 248 249 /* common part at end of ep93xx_pata_read/write() */ 250 static void ep93xx_pata_rw_end(void __iomem *base, unsigned long addr, 251 bool iordy, unsigned long t0, unsigned long t2, 252 unsigned long t2i) 253 { 254 ep93xx_pata_delay(t2); 255 /* lengthen t2 if needed */ 256 if (iordy) 257 t2 += ep93xx_pata_wait_for_iordy(base, t2); 258 writel(IDECTRL_DIOWN | IDECTRL_DIORN | addr, base + IDECTRL); 259 if (t0 > t2 && t0 - t2 > t2i) 260 ep93xx_pata_delay(t0 - t2); 261 else 262 ep93xx_pata_delay(t2i); 263 } 264 265 static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data, 266 unsigned long addr, 267 bool reg) 268 { 269 void __iomem *base = drv_data->ide_base; 270 const struct ata_timing *t = &drv_data->t; 271 unsigned long t0 = reg ? t->cyc8b : t->cycle; 272 unsigned long t2 = reg ? t->act8b : t->active; 273 unsigned long t2i = reg ? t->rec8b : t->recover; 274 275 ep93xx_pata_rw_begin(base, addr, t->setup); 276 writel(IDECTRL_DIOWN | addr, base + IDECTRL); 277 /* 278 * The IDEDATAIN register is loaded from the DD pins at the positive 279 * edge of the DIORN signal. (EP93xx UG p27-14) 280 */ 281 ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i); 282 return readl(base + IDEDATAIN); 283 } 284 285 /* IDE register read */ 286 static u16 ep93xx_pata_read_reg(struct ep93xx_pata_data *drv_data, 287 unsigned long addr) 288 { 289 return ep93xx_pata_read(drv_data, addr, true); 290 } 291 292 /* PIO data read */ 293 static u16 ep93xx_pata_read_data(struct ep93xx_pata_data *drv_data, 294 unsigned long addr) 295 { 296 return ep93xx_pata_read(drv_data, addr, false); 297 } 298 299 static void ep93xx_pata_write(struct ep93xx_pata_data *drv_data, 300 u16 value, unsigned long addr, 301 bool reg) 302 { 303 void __iomem *base = drv_data->ide_base; 304 const struct ata_timing *t = &drv_data->t; 305 unsigned long t0 = reg ? t->cyc8b : t->cycle; 306 unsigned long t2 = reg ? t->act8b : t->active; 307 unsigned long t2i = reg ? t->rec8b : t->recover; 308 309 ep93xx_pata_rw_begin(base, addr, t->setup); 310 /* 311 * Value from IDEDATAOUT register is driven onto the DD pins when 312 * DIOWN is low. (EP93xx UG p27-13) 313 */ 314 writel(value, base + IDEDATAOUT); 315 writel(IDECTRL_DIORN | addr, base + IDECTRL); 316 ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i); 317 } 318 319 /* IDE register write */ 320 static void ep93xx_pata_write_reg(struct ep93xx_pata_data *drv_data, 321 u16 value, unsigned long addr) 322 { 323 ep93xx_pata_write(drv_data, value, addr, true); 324 } 325 326 /* PIO data write */ 327 static void ep93xx_pata_write_data(struct ep93xx_pata_data *drv_data, 328 u16 value, unsigned long addr) 329 { 330 ep93xx_pata_write(drv_data, value, addr, false); 331 } 332 333 static void ep93xx_pata_set_piomode(struct ata_port *ap, 334 struct ata_device *adev) 335 { 336 struct ep93xx_pata_data *drv_data = ap->host->private_data; 337 struct ata_device *pair = ata_dev_pair(adev); 338 /* 339 * Calculate timings for the delay loop, assuming ep93xx cpu speed 340 * is 200MHz (maximum possible for ep93xx). If actual cpu speed is 341 * slower, we will wait a bit longer in each delay. 342 * Additional division of cpu speed by 5, because single iteration 343 * of our delay loop takes 5 cpu cycles (25ns). 344 */ 345 unsigned long T = 1000000 / (200 / 5); 346 347 ata_timing_compute(adev, adev->pio_mode, &drv_data->t, T, 0); 348 if (pair && pair->pio_mode) { 349 struct ata_timing t; 350 ata_timing_compute(pair, pair->pio_mode, &t, T, 0); 351 ata_timing_merge(&t, &drv_data->t, &drv_data->t, 352 ATA_TIMING_SETUP | ATA_TIMING_8BIT); 353 } 354 drv_data->iordy = ata_pio_need_iordy(adev); 355 356 ep93xx_pata_enable_pio(drv_data->ide_base, 357 adev->pio_mode - XFER_PIO_0); 358 } 359 360 /* Note: original code is ata_sff_check_status */ 361 static u8 ep93xx_pata_check_status(struct ata_port *ap) 362 { 363 struct ep93xx_pata_data *drv_data = ap->host->private_data; 364 365 return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_STATUS); 366 } 367 368 static u8 ep93xx_pata_check_altstatus(struct ata_port *ap) 369 { 370 struct ep93xx_pata_data *drv_data = ap->host->private_data; 371 372 return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_ALTSTATUS); 373 } 374 375 /* Note: original code is ata_sff_tf_load */ 376 static void ep93xx_pata_tf_load(struct ata_port *ap, 377 const struct ata_taskfile *tf) 378 { 379 struct ep93xx_pata_data *drv_data = ap->host->private_data; 380 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 381 382 if (tf->ctl != ap->last_ctl) { 383 ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL); 384 ap->last_ctl = tf->ctl; 385 ata_wait_idle(ap); 386 } 387 388 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 389 ep93xx_pata_write_reg(drv_data, tf->hob_feature, 390 IDECTRL_ADDR_FEATURE); 391 ep93xx_pata_write_reg(drv_data, tf->hob_nsect, 392 IDECTRL_ADDR_NSECT); 393 ep93xx_pata_write_reg(drv_data, tf->hob_lbal, 394 IDECTRL_ADDR_LBAL); 395 ep93xx_pata_write_reg(drv_data, tf->hob_lbam, 396 IDECTRL_ADDR_LBAM); 397 ep93xx_pata_write_reg(drv_data, tf->hob_lbah, 398 IDECTRL_ADDR_LBAH); 399 } 400 401 if (is_addr) { 402 ep93xx_pata_write_reg(drv_data, tf->feature, 403 IDECTRL_ADDR_FEATURE); 404 ep93xx_pata_write_reg(drv_data, tf->nsect, IDECTRL_ADDR_NSECT); 405 ep93xx_pata_write_reg(drv_data, tf->lbal, IDECTRL_ADDR_LBAL); 406 ep93xx_pata_write_reg(drv_data, tf->lbam, IDECTRL_ADDR_LBAM); 407 ep93xx_pata_write_reg(drv_data, tf->lbah, IDECTRL_ADDR_LBAH); 408 } 409 410 if (tf->flags & ATA_TFLAG_DEVICE) 411 ep93xx_pata_write_reg(drv_data, tf->device, 412 IDECTRL_ADDR_DEVICE); 413 414 ata_wait_idle(ap); 415 } 416 417 /* Note: original code is ata_sff_tf_read */ 418 static void ep93xx_pata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 419 { 420 struct ep93xx_pata_data *drv_data = ap->host->private_data; 421 422 tf->status = ep93xx_pata_check_status(ap); 423 tf->error = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_FEATURE); 424 tf->nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT); 425 tf->lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL); 426 tf->lbam = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAM); 427 tf->lbah = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAH); 428 tf->device = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DEVICE); 429 430 if (tf->flags & ATA_TFLAG_LBA48) { 431 ep93xx_pata_write_reg(drv_data, tf->ctl | ATA_HOB, 432 IDECTRL_ADDR_CTL); 433 tf->hob_feature = ep93xx_pata_read_reg(drv_data, 434 IDECTRL_ADDR_FEATURE); 435 tf->hob_nsect = ep93xx_pata_read_reg(drv_data, 436 IDECTRL_ADDR_NSECT); 437 tf->hob_lbal = ep93xx_pata_read_reg(drv_data, 438 IDECTRL_ADDR_LBAL); 439 tf->hob_lbam = ep93xx_pata_read_reg(drv_data, 440 IDECTRL_ADDR_LBAM); 441 tf->hob_lbah = ep93xx_pata_read_reg(drv_data, 442 IDECTRL_ADDR_LBAH); 443 ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL); 444 ap->last_ctl = tf->ctl; 445 } 446 } 447 448 /* Note: original code is ata_sff_exec_command */ 449 static void ep93xx_pata_exec_command(struct ata_port *ap, 450 const struct ata_taskfile *tf) 451 { 452 struct ep93xx_pata_data *drv_data = ap->host->private_data; 453 454 ep93xx_pata_write_reg(drv_data, tf->command, 455 IDECTRL_ADDR_COMMAND); 456 ata_sff_pause(ap); 457 } 458 459 /* Note: original code is ata_sff_dev_select */ 460 static void ep93xx_pata_dev_select(struct ata_port *ap, unsigned int device) 461 { 462 struct ep93xx_pata_data *drv_data = ap->host->private_data; 463 u8 tmp = ATA_DEVICE_OBS; 464 465 if (device != 0) 466 tmp |= ATA_DEV1; 467 468 ep93xx_pata_write_reg(drv_data, tmp, IDECTRL_ADDR_DEVICE); 469 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 470 } 471 472 /* Note: original code is ata_sff_set_devctl */ 473 static void ep93xx_pata_set_devctl(struct ata_port *ap, u8 ctl) 474 { 475 struct ep93xx_pata_data *drv_data = ap->host->private_data; 476 477 ep93xx_pata_write_reg(drv_data, ctl, IDECTRL_ADDR_CTL); 478 } 479 480 /* Note: original code is ata_sff_data_xfer */ 481 static unsigned int ep93xx_pata_data_xfer(struct ata_queued_cmd *qc, 482 unsigned char *buf, 483 unsigned int buflen, int rw) 484 { 485 struct ata_port *ap = qc->dev->link->ap; 486 struct ep93xx_pata_data *drv_data = ap->host->private_data; 487 u16 *data = (u16 *)buf; 488 unsigned int words = buflen >> 1; 489 490 /* Transfer multiple of 2 bytes */ 491 while (words--) 492 if (rw == READ) 493 *data++ = cpu_to_le16( 494 ep93xx_pata_read_data( 495 drv_data, IDECTRL_ADDR_DATA)); 496 else 497 ep93xx_pata_write_data(drv_data, le16_to_cpu(*data++), 498 IDECTRL_ADDR_DATA); 499 500 /* Transfer trailing 1 byte, if any. */ 501 if (unlikely(buflen & 0x01)) { 502 unsigned char pad[2] = { }; 503 504 buf += buflen - 1; 505 506 if (rw == READ) { 507 *pad = cpu_to_le16( 508 ep93xx_pata_read_data( 509 drv_data, IDECTRL_ADDR_DATA)); 510 *buf = pad[0]; 511 } else { 512 pad[0] = *buf; 513 ep93xx_pata_write_data(drv_data, le16_to_cpu(*pad), 514 IDECTRL_ADDR_DATA); 515 } 516 words++; 517 } 518 519 return words << 1; 520 } 521 522 /* Note: original code is ata_devchk */ 523 static bool ep93xx_pata_device_is_present(struct ata_port *ap, 524 unsigned int device) 525 { 526 struct ep93xx_pata_data *drv_data = ap->host->private_data; 527 u8 nsect, lbal; 528 529 ap->ops->sff_dev_select(ap, device); 530 531 ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT); 532 ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL); 533 534 ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_NSECT); 535 ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_LBAL); 536 537 ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT); 538 ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL); 539 540 nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT); 541 lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL); 542 543 if ((nsect == 0x55) && (lbal == 0xaa)) 544 return true; 545 546 return false; 547 } 548 549 /* Note: original code is ata_sff_wait_after_reset */ 550 static int ep93xx_pata_wait_after_reset(struct ata_link *link, 551 unsigned int devmask, 552 unsigned long deadline) 553 { 554 struct ata_port *ap = link->ap; 555 struct ep93xx_pata_data *drv_data = ap->host->private_data; 556 unsigned int dev0 = devmask & (1 << 0); 557 unsigned int dev1 = devmask & (1 << 1); 558 int rc, ret = 0; 559 560 ata_msleep(ap, ATA_WAIT_AFTER_RESET); 561 562 /* always check readiness of the master device */ 563 rc = ata_sff_wait_ready(link, deadline); 564 /* 565 * -ENODEV means the odd clown forgot the D7 pulldown resistor 566 * and TF status is 0xff, bail out on it too. 567 */ 568 if (rc) 569 return rc; 570 571 /* 572 * if device 1 was found in ata_devchk, wait for register 573 * access briefly, then wait for BSY to clear. 574 */ 575 if (dev1) { 576 int i; 577 578 ap->ops->sff_dev_select(ap, 1); 579 580 /* 581 * Wait for register access. Some ATAPI devices fail 582 * to set nsect/lbal after reset, so don't waste too 583 * much time on it. We're gonna wait for !BSY anyway. 584 */ 585 for (i = 0; i < 2; i++) { 586 u8 nsect, lbal; 587 588 nsect = ep93xx_pata_read_reg(drv_data, 589 IDECTRL_ADDR_NSECT); 590 lbal = ep93xx_pata_read_reg(drv_data, 591 IDECTRL_ADDR_LBAL); 592 if (nsect == 1 && lbal == 1) 593 break; 594 msleep(50); /* give drive a breather */ 595 } 596 597 rc = ata_sff_wait_ready(link, deadline); 598 if (rc) { 599 if (rc != -ENODEV) 600 return rc; 601 ret = rc; 602 } 603 } 604 /* is all this really necessary? */ 605 ap->ops->sff_dev_select(ap, 0); 606 if (dev1) 607 ap->ops->sff_dev_select(ap, 1); 608 if (dev0) 609 ap->ops->sff_dev_select(ap, 0); 610 611 return ret; 612 } 613 614 /* Note: original code is ata_bus_softreset */ 615 static int ep93xx_pata_bus_softreset(struct ata_port *ap, unsigned int devmask, 616 unsigned long deadline) 617 { 618 struct ep93xx_pata_data *drv_data = ap->host->private_data; 619 620 ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL); 621 udelay(20); /* FIXME: flush */ 622 ep93xx_pata_write_reg(drv_data, ap->ctl | ATA_SRST, IDECTRL_ADDR_CTL); 623 udelay(20); /* FIXME: flush */ 624 ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL); 625 ap->last_ctl = ap->ctl; 626 627 return ep93xx_pata_wait_after_reset(&ap->link, devmask, deadline); 628 } 629 630 static void ep93xx_pata_release_dma(struct ep93xx_pata_data *drv_data) 631 { 632 if (drv_data->dma_rx_channel) { 633 dma_release_channel(drv_data->dma_rx_channel); 634 drv_data->dma_rx_channel = NULL; 635 } 636 if (drv_data->dma_tx_channel) { 637 dma_release_channel(drv_data->dma_tx_channel); 638 drv_data->dma_tx_channel = NULL; 639 } 640 } 641 642 static int ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data) 643 { 644 struct platform_device *pdev = drv_data->pdev; 645 struct device *dev = &pdev->dev; 646 dma_cap_mask_t mask; 647 struct dma_slave_config conf; 648 int ret; 649 650 dma_cap_zero(mask); 651 dma_cap_set(DMA_SLAVE, mask); 652 653 /* 654 * Request two channels for IDE. Another possibility would be 655 * to request only one channel, and reprogram it's direction at 656 * start of new transfer. 657 */ 658 drv_data->dma_rx_channel = dma_request_chan(dev, "rx"); 659 if (IS_ERR(drv_data->dma_rx_channel)) { 660 ret = PTR_ERR(drv_data->dma_rx_channel); 661 drv_data->dma_rx_channel = NULL; 662 if (ret == -EPROBE_DEFER) 663 return ret; 664 dev_warn(dev, "rx DMA unavailable, using PIO\n"); 665 return 0; 666 } 667 668 drv_data->dma_tx_channel = dma_request_chan(&pdev->dev, "tx"); 669 if (IS_ERR(drv_data->dma_tx_channel)) { 670 ret = PTR_ERR(drv_data->dma_tx_channel); 671 drv_data->dma_tx_channel = NULL; 672 if (ret == -EPROBE_DEFER) 673 goto fail_release_rx; 674 dev_warn(dev, "tx DMA unavailable, using PIO\n"); 675 goto fail_release_rx; 676 } 677 678 /* Configure receive channel direction and source address */ 679 memset(&conf, 0, sizeof(conf)); 680 conf.direction = DMA_DEV_TO_MEM; 681 conf.src_addr = drv_data->udma_in_phys; 682 conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 683 ret = dmaengine_slave_config(drv_data->dma_rx_channel, &conf); 684 if (ret) { 685 dev_warn(dev, "failed to configure rx dma channel, using PIO\n"); 686 goto fail_release_dma; 687 } 688 689 /* Configure transmit channel direction and destination address */ 690 memset(&conf, 0, sizeof(conf)); 691 conf.direction = DMA_MEM_TO_DEV; 692 conf.dst_addr = drv_data->udma_out_phys; 693 conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 694 ret = dmaengine_slave_config(drv_data->dma_tx_channel, &conf); 695 if (ret) { 696 dev_warn(dev, "failed to configure tx dma channel, using PIO\n"); 697 goto fail_release_dma; 698 } 699 700 return 0; 701 702 fail_release_rx: 703 dma_release_channel(drv_data->dma_rx_channel); 704 drv_data->dma_rx_channel = NULL; 705 if (ret == -EPROBE_DEFER) 706 return ret; 707 return 0; 708 709 fail_release_dma: 710 ep93xx_pata_release_dma(drv_data); 711 return 0; 712 } 713 714 static void ep93xx_pata_dma_start(struct ata_queued_cmd *qc) 715 { 716 struct dma_async_tx_descriptor *txd; 717 struct ep93xx_pata_data *drv_data = qc->ap->host->private_data; 718 void __iomem *base = drv_data->ide_base; 719 struct ata_device *adev = qc->dev; 720 u32 v = qc->dma_dir == DMA_TO_DEVICE ? IDEUDMAOP_RWOP : 0; 721 struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE 722 ? drv_data->dma_tx_channel : drv_data->dma_rx_channel; 723 724 txd = dmaengine_prep_slave_sg(channel, qc->sg, qc->n_elem, qc->dma_dir, 725 DMA_CTRL_ACK); 726 if (!txd) { 727 dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n"); 728 return; 729 } 730 txd->callback = NULL; 731 txd->callback_param = NULL; 732 733 if (dmaengine_submit(txd) < 0) { 734 dev_err(qc->ap->dev, "failed to submit dma transfer\n"); 735 return; 736 } 737 dma_async_issue_pending(channel); 738 739 /* 740 * When enabling UDMA operation, IDEUDMAOP register needs to be 741 * programmed in three step sequence: 742 * 1) set or clear the RWOP bit, 743 * 2) perform dummy read of the register, 744 * 3) set the UEN bit. 745 */ 746 writel(v, base + IDEUDMAOP); 747 readl(base + IDEUDMAOP); 748 writel(v | IDEUDMAOP_UEN, base + IDEUDMAOP); 749 750 writel(IDECFG_IDEEN | IDECFG_UDMA | 751 ((adev->xfer_mode - XFER_UDMA_0) << IDECFG_MODE_SHIFT), 752 base + IDECFG); 753 } 754 755 static void ep93xx_pata_dma_stop(struct ata_queued_cmd *qc) 756 { 757 struct ep93xx_pata_data *drv_data = qc->ap->host->private_data; 758 void __iomem *base = drv_data->ide_base; 759 760 /* terminate all dma transfers, if not yet finished */ 761 dmaengine_terminate_all(drv_data->dma_rx_channel); 762 dmaengine_terminate_all(drv_data->dma_tx_channel); 763 764 /* 765 * To properly stop IDE-DMA, IDEUDMAOP register must to be cleared 766 * and IDECTRL register must be set to default value. 767 */ 768 writel(0, base + IDEUDMAOP); 769 writel(readl(base + IDECTRL) | IDECTRL_DIOWN | IDECTRL_DIORN | 770 IDECTRL_CS0N | IDECTRL_CS1N, base + IDECTRL); 771 772 ep93xx_pata_enable_pio(drv_data->ide_base, 773 qc->dev->pio_mode - XFER_PIO_0); 774 775 ata_sff_dma_pause(qc->ap); 776 } 777 778 static void ep93xx_pata_dma_setup(struct ata_queued_cmd *qc) 779 { 780 qc->ap->ops->sff_exec_command(qc->ap, &qc->tf); 781 } 782 783 static u8 ep93xx_pata_dma_status(struct ata_port *ap) 784 { 785 struct ep93xx_pata_data *drv_data = ap->host->private_data; 786 u32 val = readl(drv_data->ide_base + IDEUDMASTS); 787 788 /* 789 * UDMA Status Register bits: 790 * 791 * DMAIDE - DMA request signal from UDMA state machine, 792 * INTIDE - INT line generated by UDMA because of errors in the 793 * state machine, 794 * SBUSY - UDMA state machine busy, not in idle state, 795 * NDO - error for data-out not completed, 796 * NDI - error for data-in not completed, 797 * N4X - error for data transferred not multiplies of four 798 * 32-bit words. 799 * (EP93xx UG p27-17) 800 */ 801 if (val & IDEUDMASTS_NDO || val & IDEUDMASTS_NDI || 802 val & IDEUDMASTS_N4X || val & IDEUDMASTS_INTIDE) 803 return ATA_DMA_ERR; 804 805 /* read INTRQ (INT[3]) pin input state */ 806 if (readl(drv_data->ide_base + IDECTRL) & IDECTRL_INTRQ) 807 return ATA_DMA_INTR; 808 809 if (val & IDEUDMASTS_SBUSY || val & IDEUDMASTS_DMAIDE) 810 return ATA_DMA_ACTIVE; 811 812 return 0; 813 } 814 815 /* Note: original code is ata_sff_softreset */ 816 static int ep93xx_pata_softreset(struct ata_link *al, unsigned int *classes, 817 unsigned long deadline) 818 { 819 struct ata_port *ap = al->ap; 820 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; 821 unsigned int devmask = 0; 822 int rc; 823 u8 err; 824 825 /* determine if device 0/1 are present */ 826 if (ep93xx_pata_device_is_present(ap, 0)) 827 devmask |= (1 << 0); 828 if (slave_possible && ep93xx_pata_device_is_present(ap, 1)) 829 devmask |= (1 << 1); 830 831 /* select device 0 again */ 832 ap->ops->sff_dev_select(al->ap, 0); 833 834 /* issue bus reset */ 835 rc = ep93xx_pata_bus_softreset(ap, devmask, deadline); 836 /* if link is ocuppied, -ENODEV too is an error */ 837 if (rc && (rc != -ENODEV || sata_scr_valid(al))) { 838 ata_link_err(al, "SRST failed (errno=%d)\n", rc); 839 return rc; 840 } 841 842 /* determine by signature whether we have ATA or ATAPI devices */ 843 classes[0] = ata_sff_dev_classify(&al->device[0], devmask & (1 << 0), 844 &err); 845 if (slave_possible && err != 0x81) 846 classes[1] = ata_sff_dev_classify(&al->device[1], 847 devmask & (1 << 1), &err); 848 849 return 0; 850 } 851 852 /* Note: original code is ata_sff_drain_fifo */ 853 static void ep93xx_pata_drain_fifo(struct ata_queued_cmd *qc) 854 { 855 int count; 856 struct ata_port *ap; 857 struct ep93xx_pata_data *drv_data; 858 859 /* We only need to flush incoming data when a command was running */ 860 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) 861 return; 862 863 ap = qc->ap; 864 drv_data = ap->host->private_data; 865 /* Drain up to 64K of data before we give up this recovery method */ 866 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) 867 && count < 65536; count += 2) 868 ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DATA); 869 870 if (count) 871 ata_port_dbg(ap, "drained %d bytes to clear DRQ.\n", count); 872 873 } 874 875 static int ep93xx_pata_port_start(struct ata_port *ap) 876 { 877 struct ep93xx_pata_data *drv_data = ap->host->private_data; 878 879 /* 880 * Set timings to safe values at startup (= number of ns from ATA 881 * specification), we'll switch to properly calculated values later. 882 */ 883 drv_data->t = *ata_timing_find_mode(XFER_PIO_0); 884 return 0; 885 } 886 887 static const struct scsi_host_template ep93xx_pata_sht = { 888 ATA_BASE_SHT(DRV_NAME), 889 /* ep93xx dma implementation limit */ 890 .sg_tablesize = 32, 891 /* ep93xx dma can't transfer 65536 bytes at once */ 892 .dma_boundary = 0x7fff, 893 }; 894 895 static struct ata_port_operations ep93xx_pata_port_ops = { 896 .inherits = &ata_bmdma_port_ops, 897 898 .reset.softreset = ep93xx_pata_softreset, 899 .reset.hardreset = ATA_OP_NULL, 900 901 .sff_dev_select = ep93xx_pata_dev_select, 902 .sff_set_devctl = ep93xx_pata_set_devctl, 903 .sff_check_status = ep93xx_pata_check_status, 904 .sff_check_altstatus = ep93xx_pata_check_altstatus, 905 .sff_tf_load = ep93xx_pata_tf_load, 906 .sff_tf_read = ep93xx_pata_tf_read, 907 .sff_exec_command = ep93xx_pata_exec_command, 908 .sff_data_xfer = ep93xx_pata_data_xfer, 909 .sff_drain_fifo = ep93xx_pata_drain_fifo, 910 .sff_irq_clear = ATA_OP_NULL, 911 912 .set_piomode = ep93xx_pata_set_piomode, 913 914 .bmdma_setup = ep93xx_pata_dma_setup, 915 .bmdma_start = ep93xx_pata_dma_start, 916 .bmdma_stop = ep93xx_pata_dma_stop, 917 .bmdma_status = ep93xx_pata_dma_status, 918 919 .cable_detect = ata_cable_unknown, 920 .port_start = ep93xx_pata_port_start, 921 }; 922 923 static const struct soc_device_attribute ep93xx_soc_table[] = { 924 { .revision = "E1", .data = (void *)ATA_UDMA3 }, 925 { .revision = "E2", .data = (void *)ATA_UDMA4 }, 926 { /* sentinel */ } 927 }; 928 929 static int ep93xx_pata_probe(struct platform_device *pdev) 930 { 931 struct ep93xx_pata_data *drv_data; 932 struct ata_host *host; 933 struct ata_port *ap; 934 int irq; 935 struct resource *mem_res; 936 void __iomem *ide_base; 937 int err; 938 939 /* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */ 940 irq = platform_get_irq(pdev, 0); 941 if (irq < 0) 942 return irq; 943 944 ide_base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); 945 if (IS_ERR(ide_base)) 946 return PTR_ERR(ide_base); 947 948 drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL); 949 if (!drv_data) 950 return -ENOMEM; 951 952 drv_data->pdev = pdev; 953 drv_data->ide_base = ide_base; 954 drv_data->udma_in_phys = mem_res->start + IDEUDMADATAIN; 955 drv_data->udma_out_phys = mem_res->start + IDEUDMADATAOUT; 956 err = ep93xx_pata_dma_init(drv_data); 957 if (err) 958 return err; 959 960 /* allocate host */ 961 host = ata_host_alloc(&pdev->dev, 1); 962 if (!host) { 963 err = -ENOMEM; 964 goto err_rel_dma; 965 } 966 967 ep93xx_pata_clear_regs(ide_base); 968 969 host->private_data = drv_data; 970 971 ap = host->ports[0]; 972 ap->dev = &pdev->dev; 973 ap->ops = &ep93xx_pata_port_ops; 974 ap->flags |= ATA_FLAG_SLAVE_POSS; 975 ap->pio_mask = ATA_PIO4; 976 977 /* 978 * Maximum UDMA modes: 979 * EP931x rev.E0 - UDMA2 980 * EP931x rev.E1 - UDMA3 981 * EP931x rev.E2 - UDMA4 982 * 983 * MWDMA support was removed from EP931x rev.E2, 984 * so this driver supports only UDMA modes. 985 */ 986 if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) { 987 const struct soc_device_attribute *match; 988 989 match = soc_device_match(ep93xx_soc_table); 990 if (match) 991 ap->udma_mask = (unsigned long) match->data; 992 else 993 ap->udma_mask = ATA_UDMA2; 994 } 995 996 /* defaults, pio 0 */ 997 ep93xx_pata_enable_pio(ide_base, 0); 998 999 dev_info(&pdev->dev, "version " DRV_VERSION "\n"); 1000 1001 /* activate host */ 1002 err = ata_host_activate(host, irq, ata_bmdma_interrupt, 0, 1003 &ep93xx_pata_sht); 1004 if (err == 0) 1005 return 0; 1006 1007 err_rel_dma: 1008 ep93xx_pata_release_dma(drv_data); 1009 return err; 1010 } 1011 1012 static void ep93xx_pata_remove(struct platform_device *pdev) 1013 { 1014 struct ata_host *host = platform_get_drvdata(pdev); 1015 struct ep93xx_pata_data *drv_data = host->private_data; 1016 1017 ata_host_detach(host); 1018 ep93xx_pata_release_dma(drv_data); 1019 ep93xx_pata_clear_regs(drv_data->ide_base); 1020 } 1021 1022 static const struct of_device_id ep93xx_pata_of_ids[] = { 1023 { .compatible = "cirrus,ep9312-pata" }, 1024 { /* sentinel */ } 1025 }; 1026 MODULE_DEVICE_TABLE(of, ep93xx_pata_of_ids); 1027 1028 static struct platform_driver ep93xx_pata_platform_driver = { 1029 .driver = { 1030 .name = DRV_NAME, 1031 .of_match_table = ep93xx_pata_of_ids, 1032 }, 1033 .probe = ep93xx_pata_probe, 1034 .remove = ep93xx_pata_remove, 1035 }; 1036 1037 module_platform_driver(ep93xx_pata_platform_driver); 1038 1039 MODULE_AUTHOR("Alessandro Zummo, Lennert Buytenhek, Joao Ramos, " 1040 "Bartlomiej Zolnierkiewicz, Rafal Prylowski"); 1041 MODULE_DESCRIPTION("low-level driver for cirrus ep93xx IDE controller"); 1042 MODULE_LICENSE("GPL"); 1043 MODULE_VERSION(DRV_VERSION); 1044 MODULE_ALIAS("platform:pata_ep93xx"); 1045