1 /* 2 * pata_efar.c - EFAR PIIX clone controller driver 3 * 4 * (C) 2005 Red Hat 5 * 6 * Some parts based on ata_piix.c by Jeff Garzik and others. 7 * 8 * The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later 9 * Intel ICH controllers the EFAR widened the UDMA mode register bits 10 * and doesn't require the funky clock selection. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/init.h> 17 #include <linux/blkdev.h> 18 #include <linux/delay.h> 19 #include <linux/device.h> 20 #include <scsi/scsi_host.h> 21 #include <linux/libata.h> 22 #include <linux/ata.h> 23 24 #define DRV_NAME "pata_efar" 25 #define DRV_VERSION "0.4.4" 26 27 /** 28 * efar_pre_reset - Enable bits 29 * @link: ATA link 30 * @deadline: deadline jiffies for the operation 31 * 32 * Perform cable detection for the EFAR ATA interface. This is 33 * different to the PIIX arrangement 34 */ 35 36 static int efar_pre_reset(struct ata_link *link, unsigned long deadline) 37 { 38 static const struct pci_bits efar_enable_bits[] = { 39 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 40 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 41 }; 42 struct ata_port *ap = link->ap; 43 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 44 45 if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no])) 46 return -ENOENT; 47 48 return ata_sff_prereset(link, deadline); 49 } 50 51 /** 52 * efar_cable_detect - check for 40/80 pin 53 * @ap: Port 54 * 55 * Perform cable detection for the EFAR ATA interface. This is 56 * different to the PIIX arrangement 57 */ 58 59 static int efar_cable_detect(struct ata_port *ap) 60 { 61 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 62 u8 tmp; 63 64 pci_read_config_byte(pdev, 0x47, &tmp); 65 if (tmp & (2 >> ap->port_no)) 66 return ATA_CBL_PATA40; 67 return ATA_CBL_PATA80; 68 } 69 70 /** 71 * efar_set_piomode - Initialize host controller PATA PIO timings 72 * @ap: Port whose timings we are configuring 73 * @adev: um 74 * 75 * Set PIO mode for device, in host controller PCI config space. 76 * 77 * LOCKING: 78 * None (inherited from caller). 79 */ 80 81 static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev) 82 { 83 unsigned int pio = adev->pio_mode - XFER_PIO_0; 84 struct pci_dev *dev = to_pci_dev(ap->host->dev); 85 unsigned int idetm_port= ap->port_no ? 0x42 : 0x40; 86 u16 idetm_data; 87 int control = 0; 88 89 /* 90 * See Intel Document 298600-004 for the timing programing rules 91 * for PIIX/ICH. The EFAR is a clone so very similar 92 */ 93 94 static const /* ISP RTC */ 95 u8 timings[][2] = { { 0, 0 }, 96 { 0, 0 }, 97 { 1, 0 }, 98 { 2, 1 }, 99 { 2, 3 }, }; 100 101 if (pio > 2) 102 control |= 1; /* TIME1 enable */ 103 if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */ 104 control |= 2; /* IE enable */ 105 /* Intel specifies that the PPE functionality is for disk only */ 106 if (adev->class == ATA_DEV_ATA) 107 control |= 4; /* PPE enable */ 108 109 pci_read_config_word(dev, idetm_port, &idetm_data); 110 111 /* Enable PPE, IE and TIME as appropriate */ 112 113 if (adev->devno == 0) { 114 idetm_data &= 0xCCF0; 115 idetm_data |= control; 116 idetm_data |= (timings[pio][0] << 12) | 117 (timings[pio][1] << 8); 118 } else { 119 int shift = 4 * ap->port_no; 120 u8 slave_data; 121 122 idetm_data &= 0xCC0F; 123 idetm_data |= (control << 4); 124 125 /* Slave timing in separate register */ 126 pci_read_config_byte(dev, 0x44, &slave_data); 127 slave_data &= 0x0F << shift; 128 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift; 129 pci_write_config_byte(dev, 0x44, slave_data); 130 } 131 132 idetm_data |= 0x4000; /* Ensure SITRE is enabled */ 133 pci_write_config_word(dev, idetm_port, idetm_data); 134 } 135 136 /** 137 * efar_set_dmamode - Initialize host controller PATA DMA timings 138 * @ap: Port whose timings we are configuring 139 * @adev: Device to program 140 * 141 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 142 * 143 * LOCKING: 144 * None (inherited from caller). 145 */ 146 147 static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev) 148 { 149 struct pci_dev *dev = to_pci_dev(ap->host->dev); 150 u8 master_port = ap->port_no ? 0x42 : 0x40; 151 u16 master_data; 152 u8 speed = adev->dma_mode; 153 int devid = adev->devno + 2 * ap->port_no; 154 u8 udma_enable; 155 156 static const /* ISP RTC */ 157 u8 timings[][2] = { { 0, 0 }, 158 { 0, 0 }, 159 { 1, 0 }, 160 { 2, 1 }, 161 { 2, 3 }, }; 162 163 pci_read_config_word(dev, master_port, &master_data); 164 pci_read_config_byte(dev, 0x48, &udma_enable); 165 166 if (speed >= XFER_UDMA_0) { 167 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 168 u16 udma_timing; 169 170 udma_enable |= (1 << devid); 171 172 /* Load the UDMA mode number */ 173 pci_read_config_word(dev, 0x4A, &udma_timing); 174 udma_timing &= ~(7 << (4 * devid)); 175 udma_timing |= udma << (4 * devid); 176 pci_write_config_word(dev, 0x4A, udma_timing); 177 } else { 178 /* 179 * MWDMA is driven by the PIO timings. We must also enable 180 * IORDY unconditionally along with TIME1. PPE has already 181 * been set when the PIO timing was set. 182 */ 183 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 184 unsigned int control; 185 u8 slave_data; 186 const unsigned int needed_pio[3] = { 187 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 188 }; 189 int pio = needed_pio[mwdma] - XFER_PIO_0; 190 191 control = 3; /* IORDY|TIME1 */ 192 193 /* If the drive MWDMA is faster than it can do PIO then 194 we must force PIO into PIO0 */ 195 196 if (adev->pio_mode < needed_pio[mwdma]) 197 /* Enable DMA timing only */ 198 control |= 8; /* PIO cycles in PIO0 */ 199 200 if (adev->devno) { /* Slave */ 201 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 202 master_data |= control << 4; 203 pci_read_config_byte(dev, 0x44, &slave_data); 204 slave_data &= (0x0F + 0xE1 * ap->port_no); 205 /* Load the matching timing */ 206 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 207 pci_write_config_byte(dev, 0x44, slave_data); 208 } else { /* Master */ 209 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 210 and master timing bits */ 211 master_data |= control; 212 master_data |= 213 (timings[pio][0] << 12) | 214 (timings[pio][1] << 8); 215 } 216 udma_enable &= ~(1 << devid); 217 pci_write_config_word(dev, master_port, master_data); 218 } 219 pci_write_config_byte(dev, 0x48, udma_enable); 220 } 221 222 static struct scsi_host_template efar_sht = { 223 ATA_BMDMA_SHT(DRV_NAME), 224 }; 225 226 static struct ata_port_operations efar_ops = { 227 .inherits = &ata_bmdma_port_ops, 228 .cable_detect = efar_cable_detect, 229 .set_piomode = efar_set_piomode, 230 .set_dmamode = efar_set_dmamode, 231 .prereset = efar_pre_reset, 232 }; 233 234 235 /** 236 * efar_init_one - Register EFAR ATA PCI device with kernel services 237 * @pdev: PCI device to register 238 * @ent: Entry in efar_pci_tbl matching with @pdev 239 * 240 * Called from kernel PCI layer. 241 * 242 * LOCKING: 243 * Inherited from PCI layer (may sleep). 244 * 245 * RETURNS: 246 * Zero on success, or -ERRNO value. 247 */ 248 249 static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 250 { 251 static int printed_version; 252 static const struct ata_port_info info = { 253 .flags = ATA_FLAG_SLAVE_POSS, 254 .pio_mask = ATA_PIO4, 255 .mwdma_mask = ATA_MWDMA2, 256 .udma_mask = ATA_UDMA4, 257 .port_ops = &efar_ops, 258 }; 259 const struct ata_port_info *ppi[] = { &info, NULL }; 260 261 if (!printed_version++) 262 dev_printk(KERN_DEBUG, &pdev->dev, 263 "version " DRV_VERSION "\n"); 264 265 return ata_pci_sff_init_one(pdev, ppi, &efar_sht, NULL); 266 } 267 268 static const struct pci_device_id efar_pci_tbl[] = { 269 { PCI_VDEVICE(EFAR, 0x9130), }, 270 271 { } /* terminate list */ 272 }; 273 274 static struct pci_driver efar_pci_driver = { 275 .name = DRV_NAME, 276 .id_table = efar_pci_tbl, 277 .probe = efar_init_one, 278 .remove = ata_pci_remove_one, 279 #ifdef CONFIG_PM 280 .suspend = ata_pci_device_suspend, 281 .resume = ata_pci_device_resume, 282 #endif 283 }; 284 285 static int __init efar_init(void) 286 { 287 return pci_register_driver(&efar_pci_driver); 288 } 289 290 static void __exit efar_exit(void) 291 { 292 pci_unregister_driver(&efar_pci_driver); 293 } 294 295 module_init(efar_init); 296 module_exit(efar_exit); 297 298 MODULE_AUTHOR("Alan Cox"); 299 MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones"); 300 MODULE_LICENSE("GPL"); 301 MODULE_DEVICE_TABLE(pci, efar_pci_tbl); 302 MODULE_VERSION(DRV_VERSION); 303 304