1 /* 2 * pata-cs5530.c - CS5530 PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * based upon cs5530.c by Mark Lord. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * 21 * Loosely based on the piix & svwks drivers. 22 * 23 * Documentation: 24 * Available from AMD web site. 25 */ 26 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/init.h> 31 #include <linux/blkdev.h> 32 #include <linux/delay.h> 33 #include <scsi/scsi_host.h> 34 #include <linux/libata.h> 35 #include <linux/dmi.h> 36 37 #define DRV_NAME "pata_cs5530" 38 #define DRV_VERSION "0.7.1" 39 40 /** 41 * cs5530_set_piomode - PIO setup 42 * @ap: ATA interface 43 * @adev: device on the interface 44 * 45 * Set our PIO requirements. This is fairly simple on the CS5530 46 * chips. 47 */ 48 49 static void cs5530_set_piomode(struct ata_port *ap, struct ata_device *adev) 50 { 51 static const unsigned int cs5530_pio_timings[2][5] = { 52 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, 53 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010} 54 }; 55 unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no; 56 u32 tuning; 57 int format; 58 59 /* Find out which table to use */ 60 tuning = inl(base + 0x04); 61 format = (tuning & 0x80000000UL) ? 1 : 0; 62 63 /* Now load the right timing register */ 64 if (adev->devno) 65 base += 0x08; 66 67 outl(cs5530_pio_timings[format][adev->pio_mode - XFER_PIO_0], base); 68 } 69 70 /** 71 * cs5530_set_dmamode - DMA timing setup 72 * @ap: ATA interface 73 * @adev: Device being configured 74 * 75 * We cannot mix MWDMA and UDMA without reloading timings each switch 76 * master to slave. We track the last DMA setup in order to minimise 77 * reloads. 78 */ 79 80 static void cs5530_set_dmamode(struct ata_port *ap, struct ata_device *adev) 81 { 82 unsigned long base = ( ap->ioaddr.bmdma_addr & ~0x0F) + 0x20 + 0x10 * ap->port_no; 83 u32 tuning, timing = 0; 84 u8 reg; 85 86 /* Find out which table to use */ 87 tuning = inl(base + 0x04); 88 89 switch(adev->dma_mode) { 90 case XFER_UDMA_0: 91 timing = 0x00921250;break; 92 case XFER_UDMA_1: 93 timing = 0x00911140;break; 94 case XFER_UDMA_2: 95 timing = 0x00911030;break; 96 case XFER_MW_DMA_0: 97 timing = 0x00077771;break; 98 case XFER_MW_DMA_1: 99 timing = 0x00012121;break; 100 case XFER_MW_DMA_2: 101 timing = 0x00002020;break; 102 default: 103 BUG(); 104 } 105 /* Merge in the PIO format bit */ 106 timing |= (tuning & 0x80000000UL); 107 if (adev->devno == 0) /* Master */ 108 outl(timing, base + 0x04); 109 else { 110 if (timing & 0x00100000) 111 tuning |= 0x00100000; /* UDMA for both */ 112 else 113 tuning &= ~0x00100000; /* MWDMA for both */ 114 outl(tuning, base + 0x04); 115 outl(timing, base + 0x0C); 116 } 117 118 /* Set the DMA capable bit in the BMDMA area */ 119 reg = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 120 reg |= (1 << (5 + adev->devno)); 121 outb(reg, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 122 123 /* Remember the last DMA setup we did */ 124 125 ap->private_data = adev; 126 } 127 128 /** 129 * cs5530_qc_issue_prot - command issue 130 * @qc: command pending 131 * 132 * Called when the libata layer is about to issue a command. We wrap 133 * this interface so that we can load the correct ATA timings if 134 * neccessary. Specifically we have a problem that there is only 135 * one MWDMA/UDMA bit. 136 */ 137 138 static unsigned int cs5530_qc_issue_prot(struct ata_queued_cmd *qc) 139 { 140 struct ata_port *ap = qc->ap; 141 struct ata_device *adev = qc->dev; 142 struct ata_device *prev = ap->private_data; 143 144 /* See if the DMA settings could be wrong */ 145 if (adev->dma_mode != 0 && adev != prev && prev != NULL) { 146 /* Maybe, but do the channels match MWDMA/UDMA ? */ 147 if ((adev->dma_mode >= XFER_UDMA_0 && prev->dma_mode < XFER_UDMA_0) || 148 (adev->dma_mode < XFER_UDMA_0 && prev->dma_mode >= XFER_UDMA_0)) 149 /* Switch the mode bits */ 150 cs5530_set_dmamode(ap, adev); 151 } 152 153 return ata_qc_issue_prot(qc); 154 } 155 156 static int cs5530_pre_reset(struct ata_port *ap) 157 { 158 ap->cbl = ATA_CBL_PATA40; 159 return ata_std_prereset(ap); 160 } 161 162 static void cs5530_error_handler(struct ata_port *ap) 163 { 164 return ata_bmdma_drive_eh(ap, cs5530_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 165 } 166 167 168 static struct scsi_host_template cs5530_sht = { 169 .module = THIS_MODULE, 170 .name = DRV_NAME, 171 .ioctl = ata_scsi_ioctl, 172 .queuecommand = ata_scsi_queuecmd, 173 .can_queue = ATA_DEF_QUEUE, 174 .this_id = ATA_SHT_THIS_ID, 175 .sg_tablesize = LIBATA_MAX_PRD, 176 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 177 .emulated = ATA_SHT_EMULATED, 178 .use_clustering = ATA_SHT_USE_CLUSTERING, 179 .proc_name = DRV_NAME, 180 .dma_boundary = ATA_DMA_BOUNDARY, 181 .slave_configure = ata_scsi_slave_config, 182 .slave_destroy = ata_scsi_slave_destroy, 183 .bios_param = ata_std_bios_param, 184 .resume = ata_scsi_device_resume, 185 .suspend = ata_scsi_device_suspend, 186 }; 187 188 static struct ata_port_operations cs5530_port_ops = { 189 .port_disable = ata_port_disable, 190 .set_piomode = cs5530_set_piomode, 191 .set_dmamode = cs5530_set_dmamode, 192 .mode_filter = ata_pci_default_filter, 193 194 .tf_load = ata_tf_load, 195 .tf_read = ata_tf_read, 196 .check_status = ata_check_status, 197 .exec_command = ata_exec_command, 198 .dev_select = ata_std_dev_select, 199 200 .bmdma_setup = ata_bmdma_setup, 201 .bmdma_start = ata_bmdma_start, 202 .bmdma_stop = ata_bmdma_stop, 203 .bmdma_status = ata_bmdma_status, 204 205 .freeze = ata_bmdma_freeze, 206 .thaw = ata_bmdma_thaw, 207 .error_handler = cs5530_error_handler, 208 .post_internal_cmd = ata_bmdma_post_internal_cmd, 209 210 .qc_prep = ata_qc_prep, 211 .qc_issue = cs5530_qc_issue_prot, 212 213 .data_xfer = ata_pio_data_xfer, 214 215 .irq_handler = ata_interrupt, 216 .irq_clear = ata_bmdma_irq_clear, 217 218 .port_start = ata_port_start, 219 .port_stop = ata_port_stop, 220 .host_stop = ata_host_stop 221 }; 222 223 static struct dmi_system_id palmax_dmi_table[] = { 224 { 225 .ident = "Palmax PD1100", 226 .matches = { 227 DMI_MATCH(DMI_SYS_VENDOR, "Cyrix"), 228 DMI_MATCH(DMI_PRODUCT_NAME, "Caddis"), 229 }, 230 }, 231 { } 232 }; 233 234 static int cs5530_is_palmax(void) 235 { 236 if (dmi_check_system(palmax_dmi_table)) { 237 printk(KERN_INFO "Palmax PD1100: Disabling DMA on docking port.\n"); 238 return 1; 239 } 240 return 0; 241 } 242 243 244 /** 245 * cs5530_init_chip - Chipset init 246 * 247 * Perform the chip initialisation work that is shared between both 248 * setup and resume paths 249 */ 250 251 static int cs5530_init_chip(void) 252 { 253 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL, *dev = NULL; 254 255 while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) { 256 switch (dev->device) { 257 case PCI_DEVICE_ID_CYRIX_PCI_MASTER: 258 master_0 = pci_dev_get(dev); 259 break; 260 case PCI_DEVICE_ID_CYRIX_5530_LEGACY: 261 cs5530_0 = pci_dev_get(dev); 262 break; 263 } 264 } 265 if (!master_0) { 266 printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n"); 267 goto fail_put; 268 } 269 if (!cs5530_0) { 270 printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n"); 271 goto fail_put; 272 } 273 274 pci_set_master(cs5530_0); 275 pci_set_mwi(cs5530_0); 276 277 /* 278 * Set PCI CacheLineSize to 16-bytes: 279 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530 280 * 281 * Note: This value is constant because the 5530 is only a Geode companion 282 */ 283 284 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04); 285 286 /* 287 * Disable trapping of UDMA register accesses (Win98 hack): 288 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530 289 */ 290 291 pci_write_config_word(cs5530_0, 0xd0, 0x5006); 292 293 /* 294 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus: 295 * The other settings are what is necessary to get the register 296 * into a sane state for IDE DMA operation. 297 */ 298 299 pci_write_config_byte(master_0, 0x40, 0x1e); 300 301 /* 302 * Set max PCI burst size (16-bytes seems to work best): 303 * 16bytes: set bit-1 at 0x41 (reg value of 0x16) 304 * all others: clear bit-1 at 0x41, and do: 305 * 128bytes: OR 0x00 at 0x41 306 * 256bytes: OR 0x04 at 0x41 307 * 512bytes: OR 0x08 at 0x41 308 * 1024bytes: OR 0x0c at 0x41 309 */ 310 311 pci_write_config_byte(master_0, 0x41, 0x14); 312 313 /* 314 * These settings are necessary to get the chip 315 * into a sane state for IDE DMA operation. 316 */ 317 318 pci_write_config_byte(master_0, 0x42, 0x00); 319 pci_write_config_byte(master_0, 0x43, 0xc1); 320 321 pci_dev_put(master_0); 322 pci_dev_put(cs5530_0); 323 return 0; 324 fail_put: 325 if (master_0) 326 pci_dev_put(master_0); 327 if (cs5530_0) 328 pci_dev_put(cs5530_0); 329 return -ENODEV; 330 } 331 332 /** 333 * cs5530_init_one - Initialise a CS5530 334 * @dev: PCI device 335 * @id: Entry in match table 336 * 337 * Install a driver for the newly found CS5530 companion chip. Most of 338 * this is just housekeeping. We have to set the chip up correctly and 339 * turn off various bits of emulation magic. 340 */ 341 342 static int cs5530_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 343 { 344 static struct ata_port_info info = { 345 .sht = &cs5530_sht, 346 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, 347 .pio_mask = 0x1f, 348 .mwdma_mask = 0x07, 349 .udma_mask = 0x07, 350 .port_ops = &cs5530_port_ops 351 }; 352 /* The docking connector doesn't do UDMA, and it seems not MWDMA */ 353 static struct ata_port_info info_palmax_secondary = { 354 .sht = &cs5530_sht, 355 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, 356 .pio_mask = 0x1f, 357 .port_ops = &cs5530_port_ops 358 }; 359 static struct ata_port_info *port_info[2] = { &info, &info }; 360 361 /* Chip initialisation */ 362 if (cs5530_init_chip()) 363 return -ENODEV; 364 365 if (cs5530_is_palmax()) 366 port_info[1] = &info_palmax_secondary; 367 368 /* Now kick off ATA set up */ 369 return ata_pci_init_one(pdev, port_info, 2); 370 } 371 372 static int cs5530_reinit_one(struct pci_dev *pdev) 373 { 374 /* If we fail on resume we are doomed */ 375 if (cs5530_init_chip()) 376 BUG(); 377 return ata_pci_device_resume(pdev); 378 } 379 380 static const struct pci_device_id cs5530[] = { 381 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), }, 382 383 { }, 384 }; 385 386 static struct pci_driver cs5530_pci_driver = { 387 .name = DRV_NAME, 388 .id_table = cs5530, 389 .probe = cs5530_init_one, 390 .remove = ata_pci_remove_one, 391 .suspend = ata_pci_device_suspend, 392 .resume = cs5530_reinit_one, 393 }; 394 395 static int __init cs5530_init(void) 396 { 397 return pci_register_driver(&cs5530_pci_driver); 398 } 399 400 static void __exit cs5530_exit(void) 401 { 402 pci_unregister_driver(&cs5530_pci_driver); 403 } 404 405 MODULE_AUTHOR("Alan Cox"); 406 MODULE_DESCRIPTION("low-level driver for the Cyrix/NS/AMD 5530"); 407 MODULE_LICENSE("GPL"); 408 MODULE_DEVICE_TABLE(pci, cs5530); 409 MODULE_VERSION(DRV_VERSION); 410 411 module_init(cs5530_init); 412 module_exit(cs5530_exit); 413