1 /* 2 * pata_cmd64x.c - CMD64x PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@lxorguk.ukuu.org.uk> 5 * 6 * Based upon 7 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002 8 * 9 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines. 10 * Note, this driver is not used at all on other systems because 11 * there the "BIOS" has done all of the following already. 12 * Due to massive hardware bugs, UltraDMA is only supported 13 * on the 646U2 and not on the 646U. 14 * 15 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) 16 * Copyright (C) 1998 David S. Miller (davem@redhat.com) 17 * 18 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 19 * 20 * TODO 21 * Testing work 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/init.h> 28 #include <linux/blkdev.h> 29 #include <linux/delay.h> 30 #include <scsi/scsi_host.h> 31 #include <linux/libata.h> 32 33 #define DRV_NAME "pata_cmd64x" 34 #define DRV_VERSION "0.3.1" 35 36 /* 37 * CMD64x specific registers definition. 38 */ 39 40 enum { 41 CFR = 0x50, 42 CFR_INTR_CH0 = 0x02, 43 CNTRL = 0x51, 44 CNTRL_DIS_RA0 = 0x40, 45 CNTRL_DIS_RA1 = 0x80, 46 CNTRL_ENA_2ND = 0x08, 47 CMDTIM = 0x52, 48 ARTTIM0 = 0x53, 49 DRWTIM0 = 0x54, 50 ARTTIM1 = 0x55, 51 DRWTIM1 = 0x56, 52 ARTTIM23 = 0x57, 53 ARTTIM23_DIS_RA2 = 0x04, 54 ARTTIM23_DIS_RA3 = 0x08, 55 ARTTIM23_INTR_CH1 = 0x10, 56 ARTTIM2 = 0x57, 57 ARTTIM3 = 0x57, 58 DRWTIM23 = 0x58, 59 DRWTIM2 = 0x58, 60 BRST = 0x59, 61 DRWTIM3 = 0x5b, 62 BMIDECR0 = 0x70, 63 MRDMODE = 0x71, 64 MRDMODE_INTR_CH0 = 0x04, 65 MRDMODE_INTR_CH1 = 0x08, 66 MRDMODE_BLK_CH0 = 0x10, 67 MRDMODE_BLK_CH1 = 0x20, 68 BMIDESR0 = 0x72, 69 UDIDETCR0 = 0x73, 70 DTPR0 = 0x74, 71 BMIDECR1 = 0x78, 72 BMIDECSR = 0x79, 73 BMIDESR1 = 0x7A, 74 UDIDETCR1 = 0x7B, 75 DTPR1 = 0x7C 76 }; 77 78 static int cmd648_cable_detect(struct ata_port *ap) 79 { 80 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 81 u8 r; 82 83 /* Check cable detect bits */ 84 pci_read_config_byte(pdev, BMIDECSR, &r); 85 if (r & (1 << ap->port_no)) 86 return ATA_CBL_PATA80; 87 return ATA_CBL_PATA40; 88 } 89 90 /** 91 * cmd64x_set_piomode - set PIO and MWDMA timing 92 * @ap: ATA interface 93 * @adev: ATA device 94 * @mode: mode 95 * 96 * Called to do the PIO and MWDMA mode setup. 97 */ 98 99 static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode) 100 { 101 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 102 struct ata_timing t; 103 const unsigned long T = 1000000 / 33; 104 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 }; 105 106 u8 reg; 107 108 /* Port layout is not logical so use a table */ 109 const u8 arttim_port[2][2] = { 110 { ARTTIM0, ARTTIM1 }, 111 { ARTTIM23, ARTTIM23 } 112 }; 113 const u8 drwtim_port[2][2] = { 114 { DRWTIM0, DRWTIM1 }, 115 { DRWTIM2, DRWTIM3 } 116 }; 117 118 int arttim = arttim_port[ap->port_no][adev->devno]; 119 int drwtim = drwtim_port[ap->port_no][adev->devno]; 120 121 /* ata_timing_compute is smart and will produce timings for MWDMA 122 that don't violate the drives PIO capabilities. */ 123 if (ata_timing_compute(adev, mode, &t, T, 0) < 0) { 124 printk(KERN_ERR DRV_NAME ": mode computation failed.\n"); 125 return; 126 } 127 if (ap->port_no) { 128 /* Slave has shared address setup */ 129 struct ata_device *pair = ata_dev_pair(adev); 130 131 if (pair) { 132 struct ata_timing tp; 133 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0); 134 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 135 } 136 } 137 138 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n", 139 t.active, t.recover, t.setup); 140 if (t.recover > 16) { 141 t.active += t.recover - 16; 142 t.recover = 16; 143 } 144 if (t.active > 16) 145 t.active = 16; 146 147 /* Now convert the clocks into values we can actually stuff into 148 the chip */ 149 150 if (t.recover > 1) 151 t.recover--; 152 else 153 t.recover = 15; 154 155 if (t.setup > 4) 156 t.setup = 0xC0; 157 else 158 t.setup = setup_data[t.setup]; 159 160 t.active &= 0x0F; /* 0 = 16 */ 161 162 /* Load setup timing */ 163 pci_read_config_byte(pdev, arttim, ®); 164 reg &= 0x3F; 165 reg |= t.setup; 166 pci_write_config_byte(pdev, arttim, reg); 167 168 /* Load active/recovery */ 169 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover); 170 } 171 172 /** 173 * cmd64x_set_piomode - set initial PIO mode data 174 * @ap: ATA interface 175 * @adev: ATA device 176 * 177 * Used when configuring the devices ot set the PIO timings. All the 178 * actual work is done by the PIO/MWDMA setting helper 179 */ 180 181 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev) 182 { 183 cmd64x_set_timing(ap, adev, adev->pio_mode); 184 } 185 186 /** 187 * cmd64x_set_dmamode - set initial DMA mode data 188 * @ap: ATA interface 189 * @adev: ATA device 190 * 191 * Called to do the DMA mode setup. 192 */ 193 194 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev) 195 { 196 static const u8 udma_data[] = { 197 0x30, 0x20, 0x10, 0x20, 0x10, 0x00 198 }; 199 200 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 201 u8 regU, regD; 202 203 int pciU = UDIDETCR0 + 8 * ap->port_no; 204 int pciD = BMIDESR0 + 8 * ap->port_no; 205 int shift = 2 * adev->devno; 206 207 pci_read_config_byte(pdev, pciD, ®D); 208 pci_read_config_byte(pdev, pciU, ®U); 209 210 /* DMA bits off */ 211 regD &= ~(0x20 << adev->devno); 212 /* DMA control bits */ 213 regU &= ~(0x30 << shift); 214 /* DMA timing bits */ 215 regU &= ~(0x05 << adev->devno); 216 217 if (adev->dma_mode >= XFER_UDMA_0) { 218 /* Merge the timing value */ 219 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift; 220 /* Merge the control bits */ 221 regU |= 1 << adev->devno; /* UDMA on */ 222 if (adev->dma_mode > 2) /* 15nS timing */ 223 regU |= 4 << adev->devno; 224 } else { 225 regU &= ~ (1 << adev->devno); /* UDMA off */ 226 cmd64x_set_timing(ap, adev, adev->dma_mode); 227 } 228 229 regD |= 0x20 << adev->devno; 230 231 pci_write_config_byte(pdev, pciU, regU); 232 pci_write_config_byte(pdev, pciD, regD); 233 } 234 235 /** 236 * cmd648_dma_stop - DMA stop callback 237 * @qc: Command in progress 238 * 239 * DMA has completed. 240 */ 241 242 static void cmd648_bmdma_stop(struct ata_queued_cmd *qc) 243 { 244 struct ata_port *ap = qc->ap; 245 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 246 u8 dma_intr; 247 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0; 248 int dma_reg = ap->port_no ? ARTTIM2 : CFR; 249 250 ata_bmdma_stop(qc); 251 252 pci_read_config_byte(pdev, dma_reg, &dma_intr); 253 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask); 254 } 255 256 /** 257 * cmd64x_bmdma_stop - DMA stop callback 258 * @qc: Command in progress 259 * 260 * Track the completion of live DMA commands and clear the 261 * host->private_data DMA tracking flag as we do. 262 */ 263 264 static void cmd64x_bmdma_stop(struct ata_queued_cmd *qc) 265 { 266 struct ata_port *ap = qc->ap; 267 ata_bmdma_stop(qc); 268 WARN_ON(ap->host->private_data != ap); 269 ap->host->private_data = NULL; 270 } 271 272 /** 273 * cmd64x_qc_defer - Defer logic for chip limits 274 * @qc: queued command 275 * 276 * Decide whether we can issue the command. Called under the host lock. 277 */ 278 279 static int cmd64x_qc_defer(struct ata_queued_cmd *qc) 280 { 281 struct ata_host *host = qc->ap->host; 282 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no]; 283 int rc; 284 int dma = 0; 285 286 /* Apply the ATA rules first */ 287 rc = ata_std_qc_defer(qc); 288 if (rc) 289 return rc; 290 291 if (qc->tf.protocol == ATAPI_PROT_DMA || 292 qc->tf.protocol == ATA_PROT_DMA) 293 dma = 1; 294 295 /* If the other port is not live then issue the command */ 296 if (alt == NULL || !alt->qc_active) { 297 if (dma) 298 host->private_data = qc->ap; 299 return 0; 300 } 301 /* If there is a live DMA command then wait */ 302 if (host->private_data != NULL) 303 return ATA_DEFER_PORT; 304 if (dma) 305 /* Cannot overlap our DMA command */ 306 return ATA_DEFER_PORT; 307 return 0; 308 } 309 310 /** 311 * cmd64x_interrupt - ATA host interrupt handler 312 * @irq: irq line (unused) 313 * @dev_instance: pointer to our ata_host information structure 314 * 315 * Our interrupt handler for PCI IDE devices. Calls 316 * ata_sff_host_intr() for each port that is flagging an IRQ. We cannot 317 * use the defaults as we need to avoid touching status/altstatus during 318 * a DMA. 319 * 320 * LOCKING: 321 * Obtains host lock during operation. 322 * 323 * RETURNS: 324 * IRQ_NONE or IRQ_HANDLED. 325 */ 326 irqreturn_t cmd64x_interrupt(int irq, void *dev_instance) 327 { 328 struct ata_host *host = dev_instance; 329 struct pci_dev *pdev = to_pci_dev(host->dev); 330 unsigned int i; 331 unsigned int handled = 0; 332 unsigned long flags; 333 static const u8 irq_reg[2] = { CFR, ARTTIM23 }; 334 static const u8 irq_mask[2] = { 1 << 2, 1 << 4 }; 335 336 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ 337 spin_lock_irqsave(&host->lock, flags); 338 339 for (i = 0; i < host->n_ports; i++) { 340 struct ata_port *ap; 341 u8 reg; 342 343 pci_read_config_byte(pdev, irq_reg[i], ®); 344 ap = host->ports[i]; 345 if (ap && (reg & irq_mask[i]) && 346 !(ap->flags & ATA_FLAG_DISABLED)) { 347 struct ata_queued_cmd *qc; 348 349 qc = ata_qc_from_tag(ap, ap->link.active_tag); 350 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && 351 (qc->flags & ATA_QCFLAG_ACTIVE)) 352 handled |= ata_sff_host_intr(ap, qc); 353 } 354 } 355 356 spin_unlock_irqrestore(&host->lock, flags); 357 358 return IRQ_RETVAL(handled); 359 } 360 static struct scsi_host_template cmd64x_sht = { 361 ATA_BMDMA_SHT(DRV_NAME), 362 }; 363 364 static const struct ata_port_operations cmd64x_base_ops = { 365 .inherits = &ata_bmdma_port_ops, 366 .set_piomode = cmd64x_set_piomode, 367 .set_dmamode = cmd64x_set_dmamode, 368 .bmdma_stop = cmd64x_bmdma_stop, 369 .qc_defer = cmd64x_qc_defer, 370 }; 371 372 static struct ata_port_operations cmd64x_port_ops = { 373 .inherits = &cmd64x_base_ops, 374 .cable_detect = ata_cable_40wire, 375 }; 376 377 static struct ata_port_operations cmd646r1_port_ops = { 378 .inherits = &cmd64x_base_ops, 379 .cable_detect = ata_cable_40wire, 380 }; 381 382 static struct ata_port_operations cmd648_port_ops = { 383 .inherits = &cmd64x_base_ops, 384 .bmdma_stop = cmd648_bmdma_stop, 385 .cable_detect = cmd648_cable_detect, 386 .qc_defer = ata_std_qc_defer 387 }; 388 389 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 390 { 391 static const struct ata_port_info cmd_info[6] = { 392 { /* CMD 643 - no UDMA */ 393 .flags = ATA_FLAG_SLAVE_POSS, 394 .pio_mask = ATA_PIO4, 395 .mwdma_mask = ATA_MWDMA2, 396 .port_ops = &cmd64x_port_ops 397 }, 398 { /* CMD 646 with broken UDMA */ 399 .flags = ATA_FLAG_SLAVE_POSS, 400 .pio_mask = ATA_PIO4, 401 .mwdma_mask = ATA_MWDMA2, 402 .port_ops = &cmd64x_port_ops 403 }, 404 { /* CMD 646 with working UDMA */ 405 .flags = ATA_FLAG_SLAVE_POSS, 406 .pio_mask = ATA_PIO4, 407 .mwdma_mask = ATA_MWDMA2, 408 .udma_mask = ATA_UDMA2, 409 .port_ops = &cmd64x_port_ops 410 }, 411 { /* CMD 646 rev 1 */ 412 .flags = ATA_FLAG_SLAVE_POSS, 413 .pio_mask = ATA_PIO4, 414 .mwdma_mask = ATA_MWDMA2, 415 .port_ops = &cmd646r1_port_ops 416 }, 417 { /* CMD 648 */ 418 .flags = ATA_FLAG_SLAVE_POSS, 419 .pio_mask = ATA_PIO4, 420 .mwdma_mask = ATA_MWDMA2, 421 .udma_mask = ATA_UDMA4, 422 .port_ops = &cmd648_port_ops 423 }, 424 { /* CMD 649 */ 425 .flags = ATA_FLAG_SLAVE_POSS, 426 .pio_mask = ATA_PIO4, 427 .mwdma_mask = ATA_MWDMA2, 428 .udma_mask = ATA_UDMA5, 429 .port_ops = &cmd648_port_ops 430 } 431 }; 432 const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL }; 433 u8 mrdmode; 434 int rc; 435 struct ata_host *host; 436 437 rc = pcim_enable_device(pdev); 438 if (rc) 439 return rc; 440 441 if (id->driver_data == 0) /* 643 */ 442 ata_pci_bmdma_clear_simplex(pdev); 443 444 if (pdev->device == PCI_DEVICE_ID_CMD_646) { 445 /* Does UDMA work ? */ 446 if (pdev->revision > 4) 447 ppi[0] = &cmd_info[2]; 448 /* Early rev with other problems ? */ 449 else if (pdev->revision == 1) 450 ppi[0] = &cmd_info[3]; 451 } 452 453 454 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 455 pci_read_config_byte(pdev, MRDMODE, &mrdmode); 456 mrdmode &= ~ 0x30; /* IRQ set up */ 457 mrdmode |= 0x02; /* Memory read line enable */ 458 pci_write_config_byte(pdev, MRDMODE, mrdmode); 459 460 /* PPC specific fixup copied from old driver */ 461 #ifdef CONFIG_PPC 462 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 463 #endif 464 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 465 if (rc) 466 return rc; 467 /* We use this pointer to track the AP which has DMA running */ 468 host->private_data = NULL; 469 470 pci_set_master(pdev); 471 return ata_pci_sff_activate_host(host, cmd64x_interrupt, &cmd64x_sht); 472 } 473 474 #ifdef CONFIG_PM 475 static int cmd64x_reinit_one(struct pci_dev *pdev) 476 { 477 struct ata_host *host = dev_get_drvdata(&pdev->dev); 478 u8 mrdmode; 479 int rc; 480 481 rc = ata_pci_device_do_resume(pdev); 482 if (rc) 483 return rc; 484 485 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64); 486 pci_read_config_byte(pdev, MRDMODE, &mrdmode); 487 mrdmode &= ~ 0x30; /* IRQ set up */ 488 mrdmode |= 0x02; /* Memory read line enable */ 489 pci_write_config_byte(pdev, MRDMODE, mrdmode); 490 #ifdef CONFIG_PPC 491 pci_write_config_byte(pdev, UDIDETCR0, 0xF0); 492 #endif 493 ata_host_resume(host); 494 return 0; 495 } 496 #endif 497 498 static const struct pci_device_id cmd64x[] = { 499 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 }, 500 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 }, 501 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 }, 502 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 }, 503 504 { }, 505 }; 506 507 static struct pci_driver cmd64x_pci_driver = { 508 .name = DRV_NAME, 509 .id_table = cmd64x, 510 .probe = cmd64x_init_one, 511 .remove = ata_pci_remove_one, 512 #ifdef CONFIG_PM 513 .suspend = ata_pci_device_suspend, 514 .resume = cmd64x_reinit_one, 515 #endif 516 }; 517 518 static int __init cmd64x_init(void) 519 { 520 return pci_register_driver(&cmd64x_pci_driver); 521 } 522 523 static void __exit cmd64x_exit(void) 524 { 525 pci_unregister_driver(&cmd64x_pci_driver); 526 } 527 528 MODULE_AUTHOR("Alan Cox"); 529 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers"); 530 MODULE_LICENSE("GPL"); 531 MODULE_DEVICE_TABLE(pci, cmd64x); 532 MODULE_VERSION(DRV_VERSION); 533 534 module_init(cmd64x_init); 535 module_exit(cmd64x_exit); 536