1 /* 2 * pata_amd.c - AMD PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * Based on pata-sil680. Errata information is taken from data sheets 7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are 8 * claimed by sata-nv.c. 9 * 10 * TODO: 11 * Variable system clock when/if it makes sense 12 * Power management on ports 13 * 14 * 15 * Documentation publically available. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <scsi/scsi_host.h> 25 #include <linux/libata.h> 26 27 #define DRV_NAME "pata_amd" 28 #define DRV_VERSION "0.3.8" 29 30 /** 31 * timing_setup - shared timing computation and load 32 * @ap: ATA port being set up 33 * @adev: drive being configured 34 * @offset: port offset 35 * @speed: target speed 36 * @clock: clock multiplier (number of times 33MHz for this part) 37 * 38 * Perform the actual timing set up for Nvidia or AMD PATA devices. 39 * The actual devices vary so they all call into this helper function 40 * providing the clock multipler and offset (because AMD and Nvidia put 41 * the ports at different locations). 42 */ 43 44 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock) 45 { 46 static const unsigned char amd_cyc2udma[] = { 47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 48 }; 49 50 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 51 struct ata_device *peer = ata_dev_pair(adev); 52 int dn = ap->port_no * 2 + adev->devno; 53 struct ata_timing at, apeer; 54 int T, UT; 55 const int amd_clock = 33333; /* KHz. */ 56 u8 t; 57 58 T = 1000000000 / amd_clock; 59 UT = T / min_t(int, max_t(int, clock, 1), 2); 60 61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) { 62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed); 63 return; 64 } 65 66 if (peer) { 67 /* This may be over conservative */ 68 if (peer->dma_mode) { 69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT); 70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 71 } 72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT); 73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 74 } 75 76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1; 77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15; 78 79 /* 80 * Now do the setup work 81 */ 82 83 /* Configure the address set up timing */ 84 pci_read_config_byte(pdev, offset + 0x0C, &t); 85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1)); 86 pci_write_config_byte(pdev, offset + 0x0C , t); 87 88 /* Configure the 8bit I/O timing */ 89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)), 90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1)); 91 92 /* Drive timing */ 93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn), 94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1)); 95 96 switch (clock) { 97 case 1: 98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03; 99 break; 100 101 case 2: 102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03; 103 break; 104 105 case 3: 106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03; 107 break; 108 109 case 4: 110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03; 111 break; 112 113 default: 114 return; 115 } 116 117 /* UDMA timing */ 118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t); 119 } 120 121 /** 122 * amd_probe_init - perform reset handling 123 * @ap: ATA port 124 * 125 * Reset sequence checking enable bits to see which ports are 126 * active. 127 */ 128 129 static int amd_pre_reset(struct ata_port *ap) 130 { 131 static const struct pci_bits amd_enable_bits[] = { 132 { 0x40, 1, 0x02, 0x02 }, 133 { 0x40, 1, 0x01, 0x01 } 134 }; 135 136 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 137 138 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) 139 return -ENOENT; 140 141 return ata_std_prereset(ap); 142 143 } 144 145 static void amd_error_handler(struct ata_port *ap) 146 { 147 return ata_bmdma_drive_eh(ap, amd_pre_reset, 148 ata_std_softreset, NULL, 149 ata_std_postreset); 150 } 151 152 static int amd_cable_detect(struct ata_port *ap) 153 { 154 static const u32 bitmask[2] = {0x03, 0x0C}; 155 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 156 u8 ata66; 157 158 pci_read_config_byte(pdev, 0x42, &ata66); 159 if (ata66 & bitmask[ap->port_no]) 160 return ATA_CBL_PATA80; 161 return ATA_CBL_PATA40; 162 } 163 164 /** 165 * amd33_set_piomode - set initial PIO mode data 166 * @ap: ATA interface 167 * @adev: ATA device 168 * 169 * Program the AMD registers for PIO mode. 170 */ 171 172 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev) 173 { 174 timing_setup(ap, adev, 0x40, adev->pio_mode, 1); 175 } 176 177 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev) 178 { 179 timing_setup(ap, adev, 0x40, adev->pio_mode, 2); 180 } 181 182 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev) 183 { 184 timing_setup(ap, adev, 0x40, adev->pio_mode, 3); 185 } 186 187 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev) 188 { 189 timing_setup(ap, adev, 0x40, adev->pio_mode, 4); 190 } 191 192 /** 193 * amd33_set_dmamode - set initial DMA mode data 194 * @ap: ATA interface 195 * @adev: ATA device 196 * 197 * Program the MWDMA/UDMA modes for the AMD and Nvidia 198 * chipset. 199 */ 200 201 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev) 202 { 203 timing_setup(ap, adev, 0x40, adev->dma_mode, 1); 204 } 205 206 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev) 207 { 208 timing_setup(ap, adev, 0x40, adev->dma_mode, 2); 209 } 210 211 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 212 { 213 timing_setup(ap, adev, 0x40, adev->dma_mode, 3); 214 } 215 216 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 217 { 218 timing_setup(ap, adev, 0x40, adev->dma_mode, 4); 219 } 220 221 222 /** 223 * nv_probe_init - cable detection 224 * @ap: ATA port 225 * 226 * Perform cable detection. The BIOS stores this in PCI config 227 * space for us. 228 */ 229 230 static int nv_pre_reset(struct ata_port *ap) { 231 static const struct pci_bits nv_enable_bits[] = { 232 { 0x50, 1, 0x02, 0x02 }, 233 { 0x50, 1, 0x01, 0x01 } 234 }; 235 236 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 237 238 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no])) 239 return -ENOENT; 240 241 return ata_std_prereset(ap); 242 } 243 244 static void nv_error_handler(struct ata_port *ap) 245 { 246 ata_bmdma_drive_eh(ap, nv_pre_reset, 247 ata_std_softreset, NULL, 248 ata_std_postreset); 249 } 250 251 static int nv_cable_detect(struct ata_port *ap) 252 { 253 static const u8 bitmask[2] = {0x03, 0x0C}; 254 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 255 u8 ata66; 256 u16 udma; 257 int cbl; 258 259 pci_read_config_byte(pdev, 0x52, &ata66); 260 if (ata66 & bitmask[ap->port_no]) 261 cbl = ATA_CBL_PATA80; 262 else 263 cbl = ATA_CBL_PATA40; 264 265 /* We now have to double check because the Nvidia boxes BIOS 266 doesn't always set the cable bits but does set mode bits */ 267 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma); 268 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400) 269 cbl = ATA_CBL_PATA80; 270 return cbl; 271 } 272 273 /** 274 * nv100_set_piomode - set initial PIO mode data 275 * @ap: ATA interface 276 * @adev: ATA device 277 * 278 * Program the AMD registers for PIO mode. 279 */ 280 281 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev) 282 { 283 timing_setup(ap, adev, 0x50, adev->pio_mode, 3); 284 } 285 286 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev) 287 { 288 timing_setup(ap, adev, 0x50, adev->pio_mode, 4); 289 } 290 291 /** 292 * nv100_set_dmamode - set initial DMA mode data 293 * @ap: ATA interface 294 * @adev: ATA device 295 * 296 * Program the MWDMA/UDMA modes for the AMD and Nvidia 297 * chipset. 298 */ 299 300 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 301 { 302 timing_setup(ap, adev, 0x50, adev->dma_mode, 3); 303 } 304 305 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 306 { 307 timing_setup(ap, adev, 0x50, adev->dma_mode, 4); 308 } 309 310 static struct scsi_host_template amd_sht = { 311 .module = THIS_MODULE, 312 .name = DRV_NAME, 313 .ioctl = ata_scsi_ioctl, 314 .queuecommand = ata_scsi_queuecmd, 315 .can_queue = ATA_DEF_QUEUE, 316 .this_id = ATA_SHT_THIS_ID, 317 .sg_tablesize = LIBATA_MAX_PRD, 318 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 319 .emulated = ATA_SHT_EMULATED, 320 .use_clustering = ATA_SHT_USE_CLUSTERING, 321 .proc_name = DRV_NAME, 322 .dma_boundary = ATA_DMA_BOUNDARY, 323 .slave_configure = ata_scsi_slave_config, 324 .slave_destroy = ata_scsi_slave_destroy, 325 .bios_param = ata_std_bios_param, 326 #ifdef CONFIG_PM 327 .resume = ata_scsi_device_resume, 328 .suspend = ata_scsi_device_suspend, 329 #endif 330 }; 331 332 static struct ata_port_operations amd33_port_ops = { 333 .port_disable = ata_port_disable, 334 .set_piomode = amd33_set_piomode, 335 .set_dmamode = amd33_set_dmamode, 336 .mode_filter = ata_pci_default_filter, 337 .tf_load = ata_tf_load, 338 .tf_read = ata_tf_read, 339 .check_status = ata_check_status, 340 .exec_command = ata_exec_command, 341 .dev_select = ata_std_dev_select, 342 343 .freeze = ata_bmdma_freeze, 344 .thaw = ata_bmdma_thaw, 345 .error_handler = amd_error_handler, 346 .post_internal_cmd = ata_bmdma_post_internal_cmd, 347 .cable_detect = ata_cable_40wire, 348 349 .bmdma_setup = ata_bmdma_setup, 350 .bmdma_start = ata_bmdma_start, 351 .bmdma_stop = ata_bmdma_stop, 352 .bmdma_status = ata_bmdma_status, 353 354 .qc_prep = ata_qc_prep, 355 .qc_issue = ata_qc_issue_prot, 356 357 .data_xfer = ata_data_xfer, 358 359 .irq_handler = ata_interrupt, 360 .irq_clear = ata_bmdma_irq_clear, 361 .irq_on = ata_irq_on, 362 .irq_ack = ata_irq_ack, 363 364 .port_start = ata_port_start, 365 }; 366 367 static struct ata_port_operations amd66_port_ops = { 368 .port_disable = ata_port_disable, 369 .set_piomode = amd66_set_piomode, 370 .set_dmamode = amd66_set_dmamode, 371 .mode_filter = ata_pci_default_filter, 372 .tf_load = ata_tf_load, 373 .tf_read = ata_tf_read, 374 .check_status = ata_check_status, 375 .exec_command = ata_exec_command, 376 .dev_select = ata_std_dev_select, 377 378 .freeze = ata_bmdma_freeze, 379 .thaw = ata_bmdma_thaw, 380 .error_handler = amd_error_handler, 381 .post_internal_cmd = ata_bmdma_post_internal_cmd, 382 .cable_detect = ata_cable_unknown, 383 384 .bmdma_setup = ata_bmdma_setup, 385 .bmdma_start = ata_bmdma_start, 386 .bmdma_stop = ata_bmdma_stop, 387 .bmdma_status = ata_bmdma_status, 388 389 .qc_prep = ata_qc_prep, 390 .qc_issue = ata_qc_issue_prot, 391 392 .data_xfer = ata_data_xfer, 393 394 .irq_handler = ata_interrupt, 395 .irq_clear = ata_bmdma_irq_clear, 396 .irq_on = ata_irq_on, 397 .irq_ack = ata_irq_ack, 398 399 .port_start = ata_port_start, 400 }; 401 402 static struct ata_port_operations amd100_port_ops = { 403 .port_disable = ata_port_disable, 404 .set_piomode = amd100_set_piomode, 405 .set_dmamode = amd100_set_dmamode, 406 .mode_filter = ata_pci_default_filter, 407 .tf_load = ata_tf_load, 408 .tf_read = ata_tf_read, 409 .check_status = ata_check_status, 410 .exec_command = ata_exec_command, 411 .dev_select = ata_std_dev_select, 412 413 .freeze = ata_bmdma_freeze, 414 .thaw = ata_bmdma_thaw, 415 .error_handler = amd_error_handler, 416 .post_internal_cmd = ata_bmdma_post_internal_cmd, 417 .cable_detect = ata_cable_unknown, 418 419 .bmdma_setup = ata_bmdma_setup, 420 .bmdma_start = ata_bmdma_start, 421 .bmdma_stop = ata_bmdma_stop, 422 .bmdma_status = ata_bmdma_status, 423 424 .qc_prep = ata_qc_prep, 425 .qc_issue = ata_qc_issue_prot, 426 427 .data_xfer = ata_data_xfer, 428 429 .irq_handler = ata_interrupt, 430 .irq_clear = ata_bmdma_irq_clear, 431 .irq_on = ata_irq_on, 432 .irq_ack = ata_irq_ack, 433 434 .port_start = ata_port_start, 435 }; 436 437 static struct ata_port_operations amd133_port_ops = { 438 .port_disable = ata_port_disable, 439 .set_piomode = amd133_set_piomode, 440 .set_dmamode = amd133_set_dmamode, 441 .mode_filter = ata_pci_default_filter, 442 .tf_load = ata_tf_load, 443 .tf_read = ata_tf_read, 444 .check_status = ata_check_status, 445 .exec_command = ata_exec_command, 446 .dev_select = ata_std_dev_select, 447 448 .freeze = ata_bmdma_freeze, 449 .thaw = ata_bmdma_thaw, 450 .error_handler = amd_error_handler, 451 .post_internal_cmd = ata_bmdma_post_internal_cmd, 452 .cable_detect = amd_cable_detect, 453 454 .bmdma_setup = ata_bmdma_setup, 455 .bmdma_start = ata_bmdma_start, 456 .bmdma_stop = ata_bmdma_stop, 457 .bmdma_status = ata_bmdma_status, 458 459 .qc_prep = ata_qc_prep, 460 .qc_issue = ata_qc_issue_prot, 461 462 .data_xfer = ata_data_xfer, 463 464 .irq_handler = ata_interrupt, 465 .irq_clear = ata_bmdma_irq_clear, 466 .irq_on = ata_irq_on, 467 .irq_ack = ata_irq_ack, 468 469 .port_start = ata_port_start, 470 }; 471 472 static struct ata_port_operations nv100_port_ops = { 473 .port_disable = ata_port_disable, 474 .set_piomode = nv100_set_piomode, 475 .set_dmamode = nv100_set_dmamode, 476 .mode_filter = ata_pci_default_filter, 477 .tf_load = ata_tf_load, 478 .tf_read = ata_tf_read, 479 .check_status = ata_check_status, 480 .exec_command = ata_exec_command, 481 .dev_select = ata_std_dev_select, 482 483 .freeze = ata_bmdma_freeze, 484 .thaw = ata_bmdma_thaw, 485 .error_handler = nv_error_handler, 486 .post_internal_cmd = ata_bmdma_post_internal_cmd, 487 .cable_detect = nv_cable_detect, 488 489 .bmdma_setup = ata_bmdma_setup, 490 .bmdma_start = ata_bmdma_start, 491 .bmdma_stop = ata_bmdma_stop, 492 .bmdma_status = ata_bmdma_status, 493 494 .qc_prep = ata_qc_prep, 495 .qc_issue = ata_qc_issue_prot, 496 497 .data_xfer = ata_data_xfer, 498 499 .irq_handler = ata_interrupt, 500 .irq_clear = ata_bmdma_irq_clear, 501 .irq_on = ata_irq_on, 502 .irq_ack = ata_irq_ack, 503 504 .port_start = ata_port_start, 505 }; 506 507 static struct ata_port_operations nv133_port_ops = { 508 .port_disable = ata_port_disable, 509 .set_piomode = nv133_set_piomode, 510 .set_dmamode = nv133_set_dmamode, 511 .mode_filter = ata_pci_default_filter, 512 .tf_load = ata_tf_load, 513 .tf_read = ata_tf_read, 514 .check_status = ata_check_status, 515 .exec_command = ata_exec_command, 516 .dev_select = ata_std_dev_select, 517 518 .freeze = ata_bmdma_freeze, 519 .thaw = ata_bmdma_thaw, 520 .error_handler = nv_error_handler, 521 .post_internal_cmd = ata_bmdma_post_internal_cmd, 522 .cable_detect = nv_cable_detect, 523 524 .bmdma_setup = ata_bmdma_setup, 525 .bmdma_start = ata_bmdma_start, 526 .bmdma_stop = ata_bmdma_stop, 527 .bmdma_status = ata_bmdma_status, 528 529 .qc_prep = ata_qc_prep, 530 .qc_issue = ata_qc_issue_prot, 531 532 .data_xfer = ata_data_xfer, 533 534 .irq_handler = ata_interrupt, 535 .irq_clear = ata_bmdma_irq_clear, 536 .irq_on = ata_irq_on, 537 .irq_ack = ata_irq_ack, 538 539 .port_start = ata_port_start, 540 }; 541 542 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 543 { 544 static struct ata_port_info info[10] = { 545 { /* 0: AMD 7401 */ 546 .sht = &amd_sht, 547 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 548 .pio_mask = 0x1f, 549 .mwdma_mask = 0x07, /* No SWDMA */ 550 .udma_mask = 0x07, /* UDMA 33 */ 551 .port_ops = &amd33_port_ops 552 }, 553 { /* 1: Early AMD7409 - no swdma */ 554 .sht = &amd_sht, 555 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 556 .pio_mask = 0x1f, 557 .mwdma_mask = 0x07, 558 .udma_mask = 0x1f, /* UDMA 66 */ 559 .port_ops = &amd66_port_ops 560 }, 561 { /* 2: AMD 7409, no swdma errata */ 562 .sht = &amd_sht, 563 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 564 .pio_mask = 0x1f, 565 .mwdma_mask = 0x07, 566 .udma_mask = 0x1f, /* UDMA 66 */ 567 .port_ops = &amd66_port_ops 568 }, 569 { /* 3: AMD 7411 */ 570 .sht = &amd_sht, 571 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 572 .pio_mask = 0x1f, 573 .mwdma_mask = 0x07, 574 .udma_mask = 0x3f, /* UDMA 100 */ 575 .port_ops = &amd100_port_ops 576 }, 577 { /* 4: AMD 7441 */ 578 .sht = &amd_sht, 579 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 580 .pio_mask = 0x1f, 581 .mwdma_mask = 0x07, 582 .udma_mask = 0x3f, /* UDMA 100 */ 583 .port_ops = &amd100_port_ops 584 }, 585 { /* 5: AMD 8111*/ 586 .sht = &amd_sht, 587 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 588 .pio_mask = 0x1f, 589 .mwdma_mask = 0x07, 590 .udma_mask = 0x7f, /* UDMA 133, no swdma */ 591 .port_ops = &amd133_port_ops 592 }, 593 { /* 6: AMD 8111 UDMA 100 (Serenade) */ 594 .sht = &amd_sht, 595 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 596 .pio_mask = 0x1f, 597 .mwdma_mask = 0x07, 598 .udma_mask = 0x3f, /* UDMA 100, no swdma */ 599 .port_ops = &amd133_port_ops 600 }, 601 { /* 7: Nvidia Nforce */ 602 .sht = &amd_sht, 603 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 604 .pio_mask = 0x1f, 605 .mwdma_mask = 0x07, 606 .udma_mask = 0x3f, /* UDMA 100 */ 607 .port_ops = &nv100_port_ops 608 }, 609 { /* 8: Nvidia Nforce2 and later */ 610 .sht = &amd_sht, 611 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 612 .pio_mask = 0x1f, 613 .mwdma_mask = 0x07, 614 .udma_mask = 0x7f, /* UDMA 133, no swdma */ 615 .port_ops = &nv133_port_ops 616 }, 617 { /* 9: AMD CS5536 (Geode companion) */ 618 .sht = &amd_sht, 619 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 620 .pio_mask = 0x1f, 621 .mwdma_mask = 0x07, 622 .udma_mask = 0x3f, /* UDMA 100 */ 623 .port_ops = &amd100_port_ops 624 } 625 }; 626 static struct ata_port_info *port_info[2]; 627 static int printed_version; 628 int type = id->driver_data; 629 u8 rev; 630 u8 fifo; 631 632 if (!printed_version++) 633 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 634 635 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 636 pci_read_config_byte(pdev, 0x41, &fifo); 637 638 /* Check for AMD7409 without swdma errata and if found adjust type */ 639 if (type == 1 && rev > 0x7) 640 type = 2; 641 642 /* Check for AMD7411 */ 643 if (type == 3) 644 /* FIFO is broken */ 645 pci_write_config_byte(pdev, 0x41, fifo & 0x0F); 646 else 647 pci_write_config_byte(pdev, 0x41, fifo | 0xF0); 648 649 /* Serenade ? */ 650 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD && 651 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) 652 type = 6; /* UDMA 100 only */ 653 654 if (type < 3) 655 ata_pci_clear_simplex(pdev); 656 657 /* And fire it up */ 658 659 port_info[0] = port_info[1] = &info[type]; 660 return ata_pci_init_one(pdev, port_info, 2); 661 } 662 663 #ifdef CONFIG_PM 664 static int amd_reinit_one(struct pci_dev *pdev) 665 { 666 if (pdev->vendor == PCI_VENDOR_ID_AMD) { 667 u8 fifo; 668 pci_read_config_byte(pdev, 0x41, &fifo); 669 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) 670 /* FIFO is broken */ 671 pci_write_config_byte(pdev, 0x41, fifo & 0x0F); 672 else 673 pci_write_config_byte(pdev, 0x41, fifo | 0xF0); 674 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 || 675 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401) 676 ata_pci_clear_simplex(pdev); 677 } 678 return ata_pci_device_resume(pdev); 679 } 680 #endif 681 682 static const struct pci_device_id amd[] = { 683 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 }, 684 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 }, 685 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 }, 686 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 }, 687 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 }, 688 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 }, 689 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 }, 690 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 }, 691 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 }, 692 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 }, 693 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 }, 694 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 }, 695 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 }, 696 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 }, 697 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 }, 698 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 }, 699 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 }, 700 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 }, 701 702 { }, 703 }; 704 705 static struct pci_driver amd_pci_driver = { 706 .name = DRV_NAME, 707 .id_table = amd, 708 .probe = amd_init_one, 709 .remove = ata_pci_remove_one, 710 #ifdef CONFIG_PM 711 .suspend = ata_pci_device_suspend, 712 .resume = amd_reinit_one, 713 #endif 714 }; 715 716 static int __init amd_init(void) 717 { 718 return pci_register_driver(&amd_pci_driver); 719 } 720 721 static void __exit amd_exit(void) 722 { 723 pci_unregister_driver(&amd_pci_driver); 724 } 725 726 MODULE_AUTHOR("Alan Cox"); 727 MODULE_DESCRIPTION("low-level driver for AMD PATA IDE"); 728 MODULE_LICENSE("GPL"); 729 MODULE_DEVICE_TABLE(pci, amd); 730 MODULE_VERSION(DRV_VERSION); 731 732 module_init(amd_init); 733 module_exit(amd_exit); 734