1 /* 2 * pata_amd.c - AMD PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * Based on pata-sil680. Errata information is taken from data sheets 7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are 8 * claimed by sata-nv.c. 9 * 10 * TODO: 11 * Variable system clock when/if it makes sense 12 * Power management on ports 13 * 14 * 15 * Documentation publically available. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pci.h> 21 #include <linux/init.h> 22 #include <linux/blkdev.h> 23 #include <linux/delay.h> 24 #include <scsi/scsi_host.h> 25 #include <linux/libata.h> 26 27 #define DRV_NAME "pata_amd" 28 #define DRV_VERSION "0.2.7" 29 30 /** 31 * timing_setup - shared timing computation and load 32 * @ap: ATA port being set up 33 * @adev: drive being configured 34 * @offset: port offset 35 * @speed: target speed 36 * @clock: clock multiplier (number of times 33MHz for this part) 37 * 38 * Perform the actual timing set up for Nvidia or AMD PATA devices. 39 * The actual devices vary so they all call into this helper function 40 * providing the clock multipler and offset (because AMD and Nvidia put 41 * the ports at different locations). 42 */ 43 44 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock) 45 { 46 static const unsigned char amd_cyc2udma[] = { 47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 48 }; 49 50 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 51 struct ata_device *peer = ata_dev_pair(adev); 52 int dn = ap->port_no * 2 + adev->devno; 53 struct ata_timing at, apeer; 54 int T, UT; 55 const int amd_clock = 33333; /* KHz. */ 56 u8 t; 57 58 T = 1000000000 / amd_clock; 59 UT = T / min_t(int, max_t(int, clock, 1), 2); 60 61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) { 62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed); 63 return; 64 } 65 66 if (peer) { 67 /* This may be over conservative */ 68 if (peer->dma_mode) { 69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT); 70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 71 } 72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT); 73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 74 } 75 76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1; 77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15; 78 79 /* 80 * Now do the setup work 81 */ 82 83 /* Configure the address set up timing */ 84 pci_read_config_byte(pdev, offset + 0x0C, &t); 85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1)); 86 pci_write_config_byte(pdev, offset + 0x0C , t); 87 88 /* Configure the 8bit I/O timing */ 89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)), 90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1)); 91 92 /* Drive timing */ 93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn), 94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1)); 95 96 switch (clock) { 97 case 1: 98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03; 99 break; 100 101 case 2: 102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03; 103 break; 104 105 case 3: 106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03; 107 break; 108 109 case 4: 110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03; 111 break; 112 113 default: 114 return; 115 } 116 117 /* UDMA timing */ 118 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t); 119 } 120 121 /** 122 * amd_probe_init - cable detection 123 * @ap: ATA port 124 * 125 * Perform cable detection. The BIOS stores this in PCI config 126 * space for us. 127 */ 128 129 static int amd_pre_reset(struct ata_port *ap) 130 { 131 static const u32 bitmask[2] = {0x03, 0xC0}; 132 static const struct pci_bits amd_enable_bits[] = { 133 { 0x40, 1, 0x02, 0x02 }, 134 { 0x40, 1, 0x01, 0x01 } 135 }; 136 137 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 138 u8 ata66; 139 140 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) 141 return -ENOENT; 142 143 pci_read_config_byte(pdev, 0x42, &ata66); 144 if (ata66 & bitmask[ap->port_no]) 145 ap->cbl = ATA_CBL_PATA80; 146 else 147 ap->cbl = ATA_CBL_PATA40; 148 return ata_std_prereset(ap); 149 150 } 151 152 static void amd_error_handler(struct ata_port *ap) 153 { 154 return ata_bmdma_drive_eh(ap, amd_pre_reset, 155 ata_std_softreset, NULL, 156 ata_std_postreset); 157 } 158 159 static int amd_early_pre_reset(struct ata_port *ap) 160 { 161 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 162 static struct pci_bits amd_enable_bits[] = { 163 { 0x40, 1, 0x02, 0x02 }, 164 { 0x40, 1, 0x01, 0x01 } 165 }; 166 167 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) 168 return -ENOENT; 169 170 /* No host side cable detection */ 171 ap->cbl = ATA_CBL_PATA80; 172 return ata_std_prereset(ap); 173 174 } 175 176 static void amd_early_error_handler(struct ata_port *ap) 177 { 178 ata_bmdma_drive_eh(ap, amd_early_pre_reset, 179 ata_std_softreset, NULL, 180 ata_std_postreset); 181 } 182 183 /** 184 * amd33_set_piomode - set initial PIO mode data 185 * @ap: ATA interface 186 * @adev: ATA device 187 * 188 * Program the AMD registers for PIO mode. 189 */ 190 191 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev) 192 { 193 timing_setup(ap, adev, 0x40, adev->pio_mode, 1); 194 } 195 196 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev) 197 { 198 timing_setup(ap, adev, 0x40, adev->pio_mode, 2); 199 } 200 201 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev) 202 { 203 timing_setup(ap, adev, 0x40, adev->pio_mode, 3); 204 } 205 206 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev) 207 { 208 timing_setup(ap, adev, 0x40, adev->pio_mode, 4); 209 } 210 211 /** 212 * amd33_set_dmamode - set initial DMA mode data 213 * @ap: ATA interface 214 * @adev: ATA device 215 * 216 * Program the MWDMA/UDMA modes for the AMD and Nvidia 217 * chipset. 218 */ 219 220 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev) 221 { 222 timing_setup(ap, adev, 0x40, adev->dma_mode, 1); 223 } 224 225 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev) 226 { 227 timing_setup(ap, adev, 0x40, adev->dma_mode, 2); 228 } 229 230 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 231 { 232 timing_setup(ap, adev, 0x40, adev->dma_mode, 3); 233 } 234 235 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 236 { 237 timing_setup(ap, adev, 0x40, adev->dma_mode, 4); 238 } 239 240 241 /** 242 * nv_probe_init - cable detection 243 * @ap: ATA port 244 * 245 * Perform cable detection. The BIOS stores this in PCI config 246 * space for us. 247 */ 248 249 static int nv_pre_reset(struct ata_port *ap) { 250 static const u8 bitmask[2] = {0x03, 0xC0}; 251 static const struct pci_bits nv_enable_bits[] = { 252 { 0x50, 1, 0x02, 0x02 }, 253 { 0x50, 1, 0x01, 0x01 } 254 }; 255 256 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 257 u8 ata66; 258 u16 udma; 259 260 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no])) 261 return -ENOENT; 262 263 pci_read_config_byte(pdev, 0x52, &ata66); 264 if (ata66 & bitmask[ap->port_no]) 265 ap->cbl = ATA_CBL_PATA80; 266 else 267 ap->cbl = ATA_CBL_PATA40; 268 269 /* We now have to double check because the Nvidia boxes BIOS 270 doesn't always set the cable bits but does set mode bits */ 271 272 pci_read_config_word(pdev, 0x62 - 2 * ap->port_no, &udma); 273 if ((udma & 0xC4) == 0xC4 || (udma & 0xC400) == 0xC400) 274 ap->cbl = ATA_CBL_PATA80; 275 return ata_std_prereset(ap); 276 } 277 278 static void nv_error_handler(struct ata_port *ap) 279 { 280 ata_bmdma_drive_eh(ap, nv_pre_reset, 281 ata_std_softreset, NULL, 282 ata_std_postreset); 283 } 284 /** 285 * nv100_set_piomode - set initial PIO mode data 286 * @ap: ATA interface 287 * @adev: ATA device 288 * 289 * Program the AMD registers for PIO mode. 290 */ 291 292 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev) 293 { 294 timing_setup(ap, adev, 0x50, adev->pio_mode, 3); 295 } 296 297 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev) 298 { 299 timing_setup(ap, adev, 0x50, adev->pio_mode, 4); 300 } 301 302 /** 303 * nv100_set_dmamode - set initial DMA mode data 304 * @ap: ATA interface 305 * @adev: ATA device 306 * 307 * Program the MWDMA/UDMA modes for the AMD and Nvidia 308 * chipset. 309 */ 310 311 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 312 { 313 timing_setup(ap, adev, 0x50, adev->dma_mode, 3); 314 } 315 316 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 317 { 318 timing_setup(ap, adev, 0x50, adev->dma_mode, 4); 319 } 320 321 static struct scsi_host_template amd_sht = { 322 .module = THIS_MODULE, 323 .name = DRV_NAME, 324 .ioctl = ata_scsi_ioctl, 325 .queuecommand = ata_scsi_queuecmd, 326 .can_queue = ATA_DEF_QUEUE, 327 .this_id = ATA_SHT_THIS_ID, 328 .sg_tablesize = LIBATA_MAX_PRD, 329 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 330 .emulated = ATA_SHT_EMULATED, 331 .use_clustering = ATA_SHT_USE_CLUSTERING, 332 .proc_name = DRV_NAME, 333 .dma_boundary = ATA_DMA_BOUNDARY, 334 .slave_configure = ata_scsi_slave_config, 335 .slave_destroy = ata_scsi_slave_destroy, 336 .bios_param = ata_std_bios_param, 337 .resume = ata_scsi_device_resume, 338 .suspend = ata_scsi_device_suspend, 339 }; 340 341 static struct ata_port_operations amd33_port_ops = { 342 .port_disable = ata_port_disable, 343 .set_piomode = amd33_set_piomode, 344 .set_dmamode = amd33_set_dmamode, 345 .mode_filter = ata_pci_default_filter, 346 .tf_load = ata_tf_load, 347 .tf_read = ata_tf_read, 348 .check_status = ata_check_status, 349 .exec_command = ata_exec_command, 350 .dev_select = ata_std_dev_select, 351 352 .freeze = ata_bmdma_freeze, 353 .thaw = ata_bmdma_thaw, 354 .error_handler = amd_early_error_handler, 355 .post_internal_cmd = ata_bmdma_post_internal_cmd, 356 357 .bmdma_setup = ata_bmdma_setup, 358 .bmdma_start = ata_bmdma_start, 359 .bmdma_stop = ata_bmdma_stop, 360 .bmdma_status = ata_bmdma_status, 361 362 .qc_prep = ata_qc_prep, 363 .qc_issue = ata_qc_issue_prot, 364 365 .data_xfer = ata_pio_data_xfer, 366 367 .irq_handler = ata_interrupt, 368 .irq_clear = ata_bmdma_irq_clear, 369 370 .port_start = ata_port_start, 371 .port_stop = ata_port_stop, 372 .host_stop = ata_host_stop 373 }; 374 375 static struct ata_port_operations amd66_port_ops = { 376 .port_disable = ata_port_disable, 377 .set_piomode = amd66_set_piomode, 378 .set_dmamode = amd66_set_dmamode, 379 .mode_filter = ata_pci_default_filter, 380 .tf_load = ata_tf_load, 381 .tf_read = ata_tf_read, 382 .check_status = ata_check_status, 383 .exec_command = ata_exec_command, 384 .dev_select = ata_std_dev_select, 385 386 .freeze = ata_bmdma_freeze, 387 .thaw = ata_bmdma_thaw, 388 .error_handler = amd_early_error_handler, 389 .post_internal_cmd = ata_bmdma_post_internal_cmd, 390 391 .bmdma_setup = ata_bmdma_setup, 392 .bmdma_start = ata_bmdma_start, 393 .bmdma_stop = ata_bmdma_stop, 394 .bmdma_status = ata_bmdma_status, 395 396 .qc_prep = ata_qc_prep, 397 .qc_issue = ata_qc_issue_prot, 398 399 .data_xfer = ata_pio_data_xfer, 400 401 .irq_handler = ata_interrupt, 402 .irq_clear = ata_bmdma_irq_clear, 403 404 .port_start = ata_port_start, 405 .port_stop = ata_port_stop, 406 .host_stop = ata_host_stop 407 }; 408 409 static struct ata_port_operations amd100_port_ops = { 410 .port_disable = ata_port_disable, 411 .set_piomode = amd100_set_piomode, 412 .set_dmamode = amd100_set_dmamode, 413 .mode_filter = ata_pci_default_filter, 414 .tf_load = ata_tf_load, 415 .tf_read = ata_tf_read, 416 .check_status = ata_check_status, 417 .exec_command = ata_exec_command, 418 .dev_select = ata_std_dev_select, 419 420 .freeze = ata_bmdma_freeze, 421 .thaw = ata_bmdma_thaw, 422 .error_handler = amd_error_handler, 423 .post_internal_cmd = ata_bmdma_post_internal_cmd, 424 425 .bmdma_setup = ata_bmdma_setup, 426 .bmdma_start = ata_bmdma_start, 427 .bmdma_stop = ata_bmdma_stop, 428 .bmdma_status = ata_bmdma_status, 429 430 .qc_prep = ata_qc_prep, 431 .qc_issue = ata_qc_issue_prot, 432 433 .data_xfer = ata_pio_data_xfer, 434 435 .irq_handler = ata_interrupt, 436 .irq_clear = ata_bmdma_irq_clear, 437 438 .port_start = ata_port_start, 439 .port_stop = ata_port_stop, 440 .host_stop = ata_host_stop 441 }; 442 443 static struct ata_port_operations amd133_port_ops = { 444 .port_disable = ata_port_disable, 445 .set_piomode = amd133_set_piomode, 446 .set_dmamode = amd133_set_dmamode, 447 .mode_filter = ata_pci_default_filter, 448 .tf_load = ata_tf_load, 449 .tf_read = ata_tf_read, 450 .check_status = ata_check_status, 451 .exec_command = ata_exec_command, 452 .dev_select = ata_std_dev_select, 453 454 .freeze = ata_bmdma_freeze, 455 .thaw = ata_bmdma_thaw, 456 .error_handler = amd_error_handler, 457 .post_internal_cmd = ata_bmdma_post_internal_cmd, 458 459 .bmdma_setup = ata_bmdma_setup, 460 .bmdma_start = ata_bmdma_start, 461 .bmdma_stop = ata_bmdma_stop, 462 .bmdma_status = ata_bmdma_status, 463 464 .qc_prep = ata_qc_prep, 465 .qc_issue = ata_qc_issue_prot, 466 467 .data_xfer = ata_pio_data_xfer, 468 469 .irq_handler = ata_interrupt, 470 .irq_clear = ata_bmdma_irq_clear, 471 472 .port_start = ata_port_start, 473 .port_stop = ata_port_stop, 474 .host_stop = ata_host_stop 475 }; 476 477 static struct ata_port_operations nv100_port_ops = { 478 .port_disable = ata_port_disable, 479 .set_piomode = nv100_set_piomode, 480 .set_dmamode = nv100_set_dmamode, 481 .mode_filter = ata_pci_default_filter, 482 .tf_load = ata_tf_load, 483 .tf_read = ata_tf_read, 484 .check_status = ata_check_status, 485 .exec_command = ata_exec_command, 486 .dev_select = ata_std_dev_select, 487 488 .freeze = ata_bmdma_freeze, 489 .thaw = ata_bmdma_thaw, 490 .error_handler = nv_error_handler, 491 .post_internal_cmd = ata_bmdma_post_internal_cmd, 492 493 .bmdma_setup = ata_bmdma_setup, 494 .bmdma_start = ata_bmdma_start, 495 .bmdma_stop = ata_bmdma_stop, 496 .bmdma_status = ata_bmdma_status, 497 498 .qc_prep = ata_qc_prep, 499 .qc_issue = ata_qc_issue_prot, 500 501 .data_xfer = ata_pio_data_xfer, 502 503 .irq_handler = ata_interrupt, 504 .irq_clear = ata_bmdma_irq_clear, 505 506 .port_start = ata_port_start, 507 .port_stop = ata_port_stop, 508 .host_stop = ata_host_stop 509 }; 510 511 static struct ata_port_operations nv133_port_ops = { 512 .port_disable = ata_port_disable, 513 .set_piomode = nv133_set_piomode, 514 .set_dmamode = nv133_set_dmamode, 515 .mode_filter = ata_pci_default_filter, 516 .tf_load = ata_tf_load, 517 .tf_read = ata_tf_read, 518 .check_status = ata_check_status, 519 .exec_command = ata_exec_command, 520 .dev_select = ata_std_dev_select, 521 522 .freeze = ata_bmdma_freeze, 523 .thaw = ata_bmdma_thaw, 524 .error_handler = nv_error_handler, 525 .post_internal_cmd = ata_bmdma_post_internal_cmd, 526 527 .bmdma_setup = ata_bmdma_setup, 528 .bmdma_start = ata_bmdma_start, 529 .bmdma_stop = ata_bmdma_stop, 530 .bmdma_status = ata_bmdma_status, 531 532 .qc_prep = ata_qc_prep, 533 .qc_issue = ata_qc_issue_prot, 534 535 .data_xfer = ata_pio_data_xfer, 536 537 .irq_handler = ata_interrupt, 538 .irq_clear = ata_bmdma_irq_clear, 539 540 .port_start = ata_port_start, 541 .port_stop = ata_port_stop, 542 .host_stop = ata_host_stop 543 }; 544 545 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 546 { 547 static struct ata_port_info info[10] = { 548 { /* 0: AMD 7401 */ 549 .sht = &amd_sht, 550 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 551 .pio_mask = 0x1f, 552 .mwdma_mask = 0x07, /* No SWDMA */ 553 .udma_mask = 0x07, /* UDMA 33 */ 554 .port_ops = &amd33_port_ops 555 }, 556 { /* 1: Early AMD7409 - no swdma */ 557 .sht = &amd_sht, 558 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 559 .pio_mask = 0x1f, 560 .mwdma_mask = 0x07, 561 .udma_mask = 0x1f, /* UDMA 66 */ 562 .port_ops = &amd66_port_ops 563 }, 564 { /* 2: AMD 7409, no swdma errata */ 565 .sht = &amd_sht, 566 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 567 .pio_mask = 0x1f, 568 .mwdma_mask = 0x07, 569 .udma_mask = 0x1f, /* UDMA 66 */ 570 .port_ops = &amd66_port_ops 571 }, 572 { /* 3: AMD 7411 */ 573 .sht = &amd_sht, 574 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 575 .pio_mask = 0x1f, 576 .mwdma_mask = 0x07, 577 .udma_mask = 0x3f, /* UDMA 100 */ 578 .port_ops = &amd100_port_ops 579 }, 580 { /* 4: AMD 7441 */ 581 .sht = &amd_sht, 582 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 583 .pio_mask = 0x1f, 584 .mwdma_mask = 0x07, 585 .udma_mask = 0x3f, /* UDMA 100 */ 586 .port_ops = &amd100_port_ops 587 }, 588 { /* 5: AMD 8111*/ 589 .sht = &amd_sht, 590 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 591 .pio_mask = 0x1f, 592 .mwdma_mask = 0x07, 593 .udma_mask = 0x7f, /* UDMA 133, no swdma */ 594 .port_ops = &amd133_port_ops 595 }, 596 { /* 6: AMD 8111 UDMA 100 (Serenade) */ 597 .sht = &amd_sht, 598 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 599 .pio_mask = 0x1f, 600 .mwdma_mask = 0x07, 601 .udma_mask = 0x3f, /* UDMA 100, no swdma */ 602 .port_ops = &amd133_port_ops 603 }, 604 { /* 7: Nvidia Nforce */ 605 .sht = &amd_sht, 606 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 607 .pio_mask = 0x1f, 608 .mwdma_mask = 0x07, 609 .udma_mask = 0x3f, /* UDMA 100 */ 610 .port_ops = &nv100_port_ops 611 }, 612 { /* 8: Nvidia Nforce2 and later */ 613 .sht = &amd_sht, 614 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 615 .pio_mask = 0x1f, 616 .mwdma_mask = 0x07, 617 .udma_mask = 0x7f, /* UDMA 133, no swdma */ 618 .port_ops = &nv133_port_ops 619 }, 620 { /* 9: AMD CS5536 (Geode companion) */ 621 .sht = &amd_sht, 622 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 623 .pio_mask = 0x1f, 624 .mwdma_mask = 0x07, 625 .udma_mask = 0x3f, /* UDMA 100 */ 626 .port_ops = &amd100_port_ops 627 } 628 }; 629 static struct ata_port_info *port_info[2]; 630 static int printed_version; 631 int type = id->driver_data; 632 u8 rev; 633 u8 fifo; 634 635 if (!printed_version++) 636 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 637 638 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 639 pci_read_config_byte(pdev, 0x41, &fifo); 640 641 /* Check for AMD7409 without swdma errata and if found adjust type */ 642 if (type == 1 && rev > 0x7) 643 type = 2; 644 645 /* Check for AMD7411 */ 646 if (type == 3) 647 /* FIFO is broken */ 648 pci_write_config_byte(pdev, 0x41, fifo & 0x0F); 649 else 650 pci_write_config_byte(pdev, 0x41, fifo | 0xF0); 651 652 /* Serenade ? */ 653 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD && 654 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) 655 type = 6; /* UDMA 100 only */ 656 657 if (type < 3) 658 ata_pci_clear_simplex(pdev); 659 660 /* And fire it up */ 661 662 port_info[0] = port_info[1] = &info[type]; 663 return ata_pci_init_one(pdev, port_info, 2); 664 } 665 666 static int amd_reinit_one(struct pci_dev *pdev) 667 { 668 if (pdev->vendor == PCI_VENDOR_ID_AMD) { 669 u8 fifo; 670 pci_read_config_byte(pdev, 0x41, &fifo); 671 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) 672 /* FIFO is broken */ 673 pci_write_config_byte(pdev, 0x41, fifo & 0x0F); 674 else 675 pci_write_config_byte(pdev, 0x41, fifo | 0xF0); 676 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 || 677 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401) 678 ata_pci_clear_simplex(pdev); 679 } 680 return ata_pci_device_resume(pdev); 681 } 682 683 static const struct pci_device_id amd[] = { 684 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 }, 685 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 }, 686 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 }, 687 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 }, 688 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 }, 689 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 }, 690 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 }, 691 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 }, 692 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 }, 693 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 }, 694 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 }, 695 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 }, 696 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 }, 697 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 }, 698 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 }, 699 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 }, 700 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 }, 701 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 }, 702 703 { }, 704 }; 705 706 static struct pci_driver amd_pci_driver = { 707 .name = DRV_NAME, 708 .id_table = amd, 709 .probe = amd_init_one, 710 .remove = ata_pci_remove_one, 711 .suspend = ata_pci_device_suspend, 712 .resume = amd_reinit_one, 713 }; 714 715 static int __init amd_init(void) 716 { 717 return pci_register_driver(&amd_pci_driver); 718 } 719 720 static void __exit amd_exit(void) 721 { 722 pci_unregister_driver(&amd_pci_driver); 723 } 724 725 MODULE_AUTHOR("Alan Cox"); 726 MODULE_DESCRIPTION("low-level driver for AMD PATA IDE"); 727 MODULE_LICENSE("GPL"); 728 MODULE_DEVICE_TABLE(pci, amd); 729 MODULE_VERSION(DRV_VERSION); 730 731 module_init(amd_init); 732 module_exit(amd_exit); 733