1 /* 2 * libata-sff.c - helper library for PCI IDE BMDMA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved. 9 * Copyright 2003-2006 Jeff Garzik 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * 27 * libata documentation is available via 'make {ps|pdf}docs', 28 * as Documentation/DocBook/libata.* 29 * 30 * Hardware documentation available from http://www.t13.org/ and 31 * http://www.sata-io.org/ 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/pci.h> 38 #include <linux/libata.h> 39 #include <linux/highmem.h> 40 41 #include "libata.h" 42 43 static struct workqueue_struct *ata_sff_wq; 44 45 const struct ata_port_operations ata_sff_port_ops = { 46 .inherits = &ata_base_port_ops, 47 48 .qc_prep = ata_noop_qc_prep, 49 .qc_issue = ata_sff_qc_issue, 50 .qc_fill_rtf = ata_sff_qc_fill_rtf, 51 52 .freeze = ata_sff_freeze, 53 .thaw = ata_sff_thaw, 54 .prereset = ata_sff_prereset, 55 .softreset = ata_sff_softreset, 56 .hardreset = sata_sff_hardreset, 57 .postreset = ata_sff_postreset, 58 .error_handler = ata_sff_error_handler, 59 60 .sff_dev_select = ata_sff_dev_select, 61 .sff_check_status = ata_sff_check_status, 62 .sff_tf_load = ata_sff_tf_load, 63 .sff_tf_read = ata_sff_tf_read, 64 .sff_exec_command = ata_sff_exec_command, 65 .sff_data_xfer = ata_sff_data_xfer, 66 .sff_drain_fifo = ata_sff_drain_fifo, 67 68 .lost_interrupt = ata_sff_lost_interrupt, 69 }; 70 EXPORT_SYMBOL_GPL(ata_sff_port_ops); 71 72 /** 73 * ata_sff_check_status - Read device status reg & clear interrupt 74 * @ap: port where the device is 75 * 76 * Reads ATA taskfile status register for currently-selected device 77 * and return its value. This also clears pending interrupts 78 * from this device 79 * 80 * LOCKING: 81 * Inherited from caller. 82 */ 83 u8 ata_sff_check_status(struct ata_port *ap) 84 { 85 return ioread8(ap->ioaddr.status_addr); 86 } 87 EXPORT_SYMBOL_GPL(ata_sff_check_status); 88 89 /** 90 * ata_sff_altstatus - Read device alternate status reg 91 * @ap: port where the device is 92 * 93 * Reads ATA taskfile alternate status register for 94 * currently-selected device and return its value. 95 * 96 * Note: may NOT be used as the check_altstatus() entry in 97 * ata_port_operations. 98 * 99 * LOCKING: 100 * Inherited from caller. 101 */ 102 static u8 ata_sff_altstatus(struct ata_port *ap) 103 { 104 if (ap->ops->sff_check_altstatus) 105 return ap->ops->sff_check_altstatus(ap); 106 107 return ioread8(ap->ioaddr.altstatus_addr); 108 } 109 110 /** 111 * ata_sff_irq_status - Check if the device is busy 112 * @ap: port where the device is 113 * 114 * Determine if the port is currently busy. Uses altstatus 115 * if available in order to avoid clearing shared IRQ status 116 * when finding an IRQ source. Non ctl capable devices don't 117 * share interrupt lines fortunately for us. 118 * 119 * LOCKING: 120 * Inherited from caller. 121 */ 122 static u8 ata_sff_irq_status(struct ata_port *ap) 123 { 124 u8 status; 125 126 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { 127 status = ata_sff_altstatus(ap); 128 /* Not us: We are busy */ 129 if (status & ATA_BUSY) 130 return status; 131 } 132 /* Clear INTRQ latch */ 133 status = ap->ops->sff_check_status(ap); 134 return status; 135 } 136 137 /** 138 * ata_sff_sync - Flush writes 139 * @ap: Port to wait for. 140 * 141 * CAUTION: 142 * If we have an mmio device with no ctl and no altstatus 143 * method this will fail. No such devices are known to exist. 144 * 145 * LOCKING: 146 * Inherited from caller. 147 */ 148 149 static void ata_sff_sync(struct ata_port *ap) 150 { 151 if (ap->ops->sff_check_altstatus) 152 ap->ops->sff_check_altstatus(ap); 153 else if (ap->ioaddr.altstatus_addr) 154 ioread8(ap->ioaddr.altstatus_addr); 155 } 156 157 /** 158 * ata_sff_pause - Flush writes and wait 400nS 159 * @ap: Port to pause for. 160 * 161 * CAUTION: 162 * If we have an mmio device with no ctl and no altstatus 163 * method this will fail. No such devices are known to exist. 164 * 165 * LOCKING: 166 * Inherited from caller. 167 */ 168 169 void ata_sff_pause(struct ata_port *ap) 170 { 171 ata_sff_sync(ap); 172 ndelay(400); 173 } 174 EXPORT_SYMBOL_GPL(ata_sff_pause); 175 176 /** 177 * ata_sff_dma_pause - Pause before commencing DMA 178 * @ap: Port to pause for. 179 * 180 * Perform I/O fencing and ensure sufficient cycle delays occur 181 * for the HDMA1:0 transition 182 */ 183 184 void ata_sff_dma_pause(struct ata_port *ap) 185 { 186 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { 187 /* An altstatus read will cause the needed delay without 188 messing up the IRQ status */ 189 ata_sff_altstatus(ap); 190 return; 191 } 192 /* There are no DMA controllers without ctl. BUG here to ensure 193 we never violate the HDMA1:0 transition timing and risk 194 corruption. */ 195 BUG(); 196 } 197 EXPORT_SYMBOL_GPL(ata_sff_dma_pause); 198 199 /** 200 * ata_sff_busy_sleep - sleep until BSY clears, or timeout 201 * @ap: port containing status register to be polled 202 * @tmout_pat: impatience timeout in msecs 203 * @tmout: overall timeout in msecs 204 * 205 * Sleep until ATA Status register bit BSY clears, 206 * or a timeout occurs. 207 * 208 * LOCKING: 209 * Kernel thread context (may sleep). 210 * 211 * RETURNS: 212 * 0 on success, -errno otherwise. 213 */ 214 int ata_sff_busy_sleep(struct ata_port *ap, 215 unsigned long tmout_pat, unsigned long tmout) 216 { 217 unsigned long timer_start, timeout; 218 u8 status; 219 220 status = ata_sff_busy_wait(ap, ATA_BUSY, 300); 221 timer_start = jiffies; 222 timeout = ata_deadline(timer_start, tmout_pat); 223 while (status != 0xff && (status & ATA_BUSY) && 224 time_before(jiffies, timeout)) { 225 ata_msleep(ap, 50); 226 status = ata_sff_busy_wait(ap, ATA_BUSY, 3); 227 } 228 229 if (status != 0xff && (status & ATA_BUSY)) 230 ata_port_warn(ap, 231 "port is slow to respond, please be patient (Status 0x%x)\n", 232 status); 233 234 timeout = ata_deadline(timer_start, tmout); 235 while (status != 0xff && (status & ATA_BUSY) && 236 time_before(jiffies, timeout)) { 237 ata_msleep(ap, 50); 238 status = ap->ops->sff_check_status(ap); 239 } 240 241 if (status == 0xff) 242 return -ENODEV; 243 244 if (status & ATA_BUSY) { 245 ata_port_err(ap, 246 "port failed to respond (%lu secs, Status 0x%x)\n", 247 DIV_ROUND_UP(tmout, 1000), status); 248 return -EBUSY; 249 } 250 251 return 0; 252 } 253 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); 254 255 static int ata_sff_check_ready(struct ata_link *link) 256 { 257 u8 status = link->ap->ops->sff_check_status(link->ap); 258 259 return ata_check_ready(status); 260 } 261 262 /** 263 * ata_sff_wait_ready - sleep until BSY clears, or timeout 264 * @link: SFF link to wait ready status for 265 * @deadline: deadline jiffies for the operation 266 * 267 * Sleep until ATA Status register bit BSY clears, or timeout 268 * occurs. 269 * 270 * LOCKING: 271 * Kernel thread context (may sleep). 272 * 273 * RETURNS: 274 * 0 on success, -errno otherwise. 275 */ 276 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) 277 { 278 return ata_wait_ready(link, deadline, ata_sff_check_ready); 279 } 280 EXPORT_SYMBOL_GPL(ata_sff_wait_ready); 281 282 /** 283 * ata_sff_set_devctl - Write device control reg 284 * @ap: port where the device is 285 * @ctl: value to write 286 * 287 * Writes ATA taskfile device control register. 288 * 289 * Note: may NOT be used as the sff_set_devctl() entry in 290 * ata_port_operations. 291 * 292 * LOCKING: 293 * Inherited from caller. 294 */ 295 static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl) 296 { 297 if (ap->ops->sff_set_devctl) 298 ap->ops->sff_set_devctl(ap, ctl); 299 else 300 iowrite8(ctl, ap->ioaddr.ctl_addr); 301 } 302 303 /** 304 * ata_sff_dev_select - Select device 0/1 on ATA bus 305 * @ap: ATA channel to manipulate 306 * @device: ATA device (numbered from zero) to select 307 * 308 * Use the method defined in the ATA specification to 309 * make either device 0, or device 1, active on the 310 * ATA channel. Works with both PIO and MMIO. 311 * 312 * May be used as the dev_select() entry in ata_port_operations. 313 * 314 * LOCKING: 315 * caller. 316 */ 317 void ata_sff_dev_select(struct ata_port *ap, unsigned int device) 318 { 319 u8 tmp; 320 321 if (device == 0) 322 tmp = ATA_DEVICE_OBS; 323 else 324 tmp = ATA_DEVICE_OBS | ATA_DEV1; 325 326 iowrite8(tmp, ap->ioaddr.device_addr); 327 ata_sff_pause(ap); /* needed; also flushes, for mmio */ 328 } 329 EXPORT_SYMBOL_GPL(ata_sff_dev_select); 330 331 /** 332 * ata_dev_select - Select device 0/1 on ATA bus 333 * @ap: ATA channel to manipulate 334 * @device: ATA device (numbered from zero) to select 335 * @wait: non-zero to wait for Status register BSY bit to clear 336 * @can_sleep: non-zero if context allows sleeping 337 * 338 * Use the method defined in the ATA specification to 339 * make either device 0, or device 1, active on the 340 * ATA channel. 341 * 342 * This is a high-level version of ata_sff_dev_select(), which 343 * additionally provides the services of inserting the proper 344 * pauses and status polling, where needed. 345 * 346 * LOCKING: 347 * caller. 348 */ 349 static void ata_dev_select(struct ata_port *ap, unsigned int device, 350 unsigned int wait, unsigned int can_sleep) 351 { 352 if (ata_msg_probe(ap)) 353 ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n", 354 device, wait); 355 356 if (wait) 357 ata_wait_idle(ap); 358 359 ap->ops->sff_dev_select(ap, device); 360 361 if (wait) { 362 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) 363 ata_msleep(ap, 150); 364 ata_wait_idle(ap); 365 } 366 } 367 368 /** 369 * ata_sff_irq_on - Enable interrupts on a port. 370 * @ap: Port on which interrupts are enabled. 371 * 372 * Enable interrupts on a legacy IDE device using MMIO or PIO, 373 * wait for idle, clear any pending interrupts. 374 * 375 * Note: may NOT be used as the sff_irq_on() entry in 376 * ata_port_operations. 377 * 378 * LOCKING: 379 * Inherited from caller. 380 */ 381 void ata_sff_irq_on(struct ata_port *ap) 382 { 383 struct ata_ioports *ioaddr = &ap->ioaddr; 384 385 if (ap->ops->sff_irq_on) { 386 ap->ops->sff_irq_on(ap); 387 return; 388 } 389 390 ap->ctl &= ~ATA_NIEN; 391 ap->last_ctl = ap->ctl; 392 393 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr) 394 ata_sff_set_devctl(ap, ap->ctl); 395 ata_wait_idle(ap); 396 397 if (ap->ops->sff_irq_clear) 398 ap->ops->sff_irq_clear(ap); 399 } 400 EXPORT_SYMBOL_GPL(ata_sff_irq_on); 401 402 /** 403 * ata_sff_tf_load - send taskfile registers to host controller 404 * @ap: Port to which output is sent 405 * @tf: ATA taskfile register set 406 * 407 * Outputs ATA taskfile to standard ATA host controller. 408 * 409 * LOCKING: 410 * Inherited from caller. 411 */ 412 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 413 { 414 struct ata_ioports *ioaddr = &ap->ioaddr; 415 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 416 417 if (tf->ctl != ap->last_ctl) { 418 if (ioaddr->ctl_addr) 419 iowrite8(tf->ctl, ioaddr->ctl_addr); 420 ap->last_ctl = tf->ctl; 421 ata_wait_idle(ap); 422 } 423 424 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 425 WARN_ON_ONCE(!ioaddr->ctl_addr); 426 iowrite8(tf->hob_feature, ioaddr->feature_addr); 427 iowrite8(tf->hob_nsect, ioaddr->nsect_addr); 428 iowrite8(tf->hob_lbal, ioaddr->lbal_addr); 429 iowrite8(tf->hob_lbam, ioaddr->lbam_addr); 430 iowrite8(tf->hob_lbah, ioaddr->lbah_addr); 431 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 432 tf->hob_feature, 433 tf->hob_nsect, 434 tf->hob_lbal, 435 tf->hob_lbam, 436 tf->hob_lbah); 437 } 438 439 if (is_addr) { 440 iowrite8(tf->feature, ioaddr->feature_addr); 441 iowrite8(tf->nsect, ioaddr->nsect_addr); 442 iowrite8(tf->lbal, ioaddr->lbal_addr); 443 iowrite8(tf->lbam, ioaddr->lbam_addr); 444 iowrite8(tf->lbah, ioaddr->lbah_addr); 445 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 446 tf->feature, 447 tf->nsect, 448 tf->lbal, 449 tf->lbam, 450 tf->lbah); 451 } 452 453 if (tf->flags & ATA_TFLAG_DEVICE) { 454 iowrite8(tf->device, ioaddr->device_addr); 455 VPRINTK("device 0x%X\n", tf->device); 456 } 457 458 ata_wait_idle(ap); 459 } 460 EXPORT_SYMBOL_GPL(ata_sff_tf_load); 461 462 /** 463 * ata_sff_tf_read - input device's ATA taskfile shadow registers 464 * @ap: Port from which input is read 465 * @tf: ATA taskfile register set for storing input 466 * 467 * Reads ATA taskfile registers for currently-selected device 468 * into @tf. Assumes the device has a fully SFF compliant task file 469 * layout and behaviour. If you device does not (eg has a different 470 * status method) then you will need to provide a replacement tf_read 471 * 472 * LOCKING: 473 * Inherited from caller. 474 */ 475 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 476 { 477 struct ata_ioports *ioaddr = &ap->ioaddr; 478 479 tf->command = ata_sff_check_status(ap); 480 tf->feature = ioread8(ioaddr->error_addr); 481 tf->nsect = ioread8(ioaddr->nsect_addr); 482 tf->lbal = ioread8(ioaddr->lbal_addr); 483 tf->lbam = ioread8(ioaddr->lbam_addr); 484 tf->lbah = ioread8(ioaddr->lbah_addr); 485 tf->device = ioread8(ioaddr->device_addr); 486 487 if (tf->flags & ATA_TFLAG_LBA48) { 488 if (likely(ioaddr->ctl_addr)) { 489 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 490 tf->hob_feature = ioread8(ioaddr->error_addr); 491 tf->hob_nsect = ioread8(ioaddr->nsect_addr); 492 tf->hob_lbal = ioread8(ioaddr->lbal_addr); 493 tf->hob_lbam = ioread8(ioaddr->lbam_addr); 494 tf->hob_lbah = ioread8(ioaddr->lbah_addr); 495 iowrite8(tf->ctl, ioaddr->ctl_addr); 496 ap->last_ctl = tf->ctl; 497 } else 498 WARN_ON_ONCE(1); 499 } 500 } 501 EXPORT_SYMBOL_GPL(ata_sff_tf_read); 502 503 /** 504 * ata_sff_exec_command - issue ATA command to host controller 505 * @ap: port to which command is being issued 506 * @tf: ATA taskfile register set 507 * 508 * Issues ATA command, with proper synchronization with interrupt 509 * handler / other threads. 510 * 511 * LOCKING: 512 * spin_lock_irqsave(host lock) 513 */ 514 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) 515 { 516 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 517 518 iowrite8(tf->command, ap->ioaddr.command_addr); 519 ata_sff_pause(ap); 520 } 521 EXPORT_SYMBOL_GPL(ata_sff_exec_command); 522 523 /** 524 * ata_tf_to_host - issue ATA taskfile to host controller 525 * @ap: port to which command is being issued 526 * @tf: ATA taskfile register set 527 * 528 * Issues ATA taskfile register set to ATA host controller, 529 * with proper synchronization with interrupt handler and 530 * other threads. 531 * 532 * LOCKING: 533 * spin_lock_irqsave(host lock) 534 */ 535 static inline void ata_tf_to_host(struct ata_port *ap, 536 const struct ata_taskfile *tf) 537 { 538 ap->ops->sff_tf_load(ap, tf); 539 ap->ops->sff_exec_command(ap, tf); 540 } 541 542 /** 543 * ata_sff_data_xfer - Transfer data by PIO 544 * @dev: device to target 545 * @buf: data buffer 546 * @buflen: buffer length 547 * @rw: read/write 548 * 549 * Transfer data from/to the device data register by PIO. 550 * 551 * LOCKING: 552 * Inherited from caller. 553 * 554 * RETURNS: 555 * Bytes consumed. 556 */ 557 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, 558 unsigned int buflen, int rw) 559 { 560 struct ata_port *ap = dev->link->ap; 561 void __iomem *data_addr = ap->ioaddr.data_addr; 562 unsigned int words = buflen >> 1; 563 564 /* Transfer multiple of 2 bytes */ 565 if (rw == READ) 566 ioread16_rep(data_addr, buf, words); 567 else 568 iowrite16_rep(data_addr, buf, words); 569 570 /* Transfer trailing byte, if any. */ 571 if (unlikely(buflen & 0x01)) { 572 unsigned char pad[2] = { }; 573 574 /* Point buf to the tail of buffer */ 575 buf += buflen - 1; 576 577 /* 578 * Use io*16_rep() accessors here as well to avoid pointlessly 579 * swapping bytes to and from on the big endian machines... 580 */ 581 if (rw == READ) { 582 ioread16_rep(data_addr, pad, 1); 583 *buf = pad[0]; 584 } else { 585 pad[0] = *buf; 586 iowrite16_rep(data_addr, pad, 1); 587 } 588 words++; 589 } 590 591 return words << 1; 592 } 593 EXPORT_SYMBOL_GPL(ata_sff_data_xfer); 594 595 /** 596 * ata_sff_data_xfer32 - Transfer data by PIO 597 * @dev: device to target 598 * @buf: data buffer 599 * @buflen: buffer length 600 * @rw: read/write 601 * 602 * Transfer data from/to the device data register by PIO using 32bit 603 * I/O operations. 604 * 605 * LOCKING: 606 * Inherited from caller. 607 * 608 * RETURNS: 609 * Bytes consumed. 610 */ 611 612 unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf, 613 unsigned int buflen, int rw) 614 { 615 struct ata_port *ap = dev->link->ap; 616 void __iomem *data_addr = ap->ioaddr.data_addr; 617 unsigned int words = buflen >> 2; 618 int slop = buflen & 3; 619 620 if (!(ap->pflags & ATA_PFLAG_PIO32)) 621 return ata_sff_data_xfer(dev, buf, buflen, rw); 622 623 /* Transfer multiple of 4 bytes */ 624 if (rw == READ) 625 ioread32_rep(data_addr, buf, words); 626 else 627 iowrite32_rep(data_addr, buf, words); 628 629 /* Transfer trailing bytes, if any */ 630 if (unlikely(slop)) { 631 unsigned char pad[4] = { }; 632 633 /* Point buf to the tail of buffer */ 634 buf += buflen - slop; 635 636 /* 637 * Use io*_rep() accessors here as well to avoid pointlessly 638 * swapping bytes to and from on the big endian machines... 639 */ 640 if (rw == READ) { 641 if (slop < 3) 642 ioread16_rep(data_addr, pad, 1); 643 else 644 ioread32_rep(data_addr, pad, 1); 645 memcpy(buf, pad, slop); 646 } else { 647 memcpy(pad, buf, slop); 648 if (slop < 3) 649 iowrite16_rep(data_addr, pad, 1); 650 else 651 iowrite32_rep(data_addr, pad, 1); 652 } 653 } 654 return (buflen + 1) & ~1; 655 } 656 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); 657 658 /** 659 * ata_sff_data_xfer_noirq - Transfer data by PIO 660 * @dev: device to target 661 * @buf: data buffer 662 * @buflen: buffer length 663 * @rw: read/write 664 * 665 * Transfer data from/to the device data register by PIO. Do the 666 * transfer with interrupts disabled. 667 * 668 * LOCKING: 669 * Inherited from caller. 670 * 671 * RETURNS: 672 * Bytes consumed. 673 */ 674 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, 675 unsigned int buflen, int rw) 676 { 677 unsigned long flags; 678 unsigned int consumed; 679 680 local_irq_save(flags); 681 consumed = ata_sff_data_xfer32(dev, buf, buflen, rw); 682 local_irq_restore(flags); 683 684 return consumed; 685 } 686 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); 687 688 /** 689 * ata_pio_sector - Transfer a sector of data. 690 * @qc: Command on going 691 * 692 * Transfer qc->sect_size bytes of data from/to the ATA device. 693 * 694 * LOCKING: 695 * Inherited from caller. 696 */ 697 static void ata_pio_sector(struct ata_queued_cmd *qc) 698 { 699 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); 700 struct ata_port *ap = qc->ap; 701 struct page *page; 702 unsigned int offset; 703 unsigned char *buf; 704 705 if (qc->curbytes == qc->nbytes - qc->sect_size) 706 ap->hsm_task_state = HSM_ST_LAST; 707 708 page = sg_page(qc->cursg); 709 offset = qc->cursg->offset + qc->cursg_ofs; 710 711 /* get the current page and offset */ 712 page = nth_page(page, (offset >> PAGE_SHIFT)); 713 offset %= PAGE_SIZE; 714 715 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); 716 717 if (PageHighMem(page)) { 718 unsigned long flags; 719 720 /* FIXME: use a bounce buffer */ 721 local_irq_save(flags); 722 buf = kmap_atomic(page, KM_IRQ0); 723 724 /* do the actual data transfer */ 725 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, 726 do_write); 727 728 kunmap_atomic(buf, KM_IRQ0); 729 local_irq_restore(flags); 730 } else { 731 buf = page_address(page); 732 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, 733 do_write); 734 } 735 736 if (!do_write && !PageSlab(page)) 737 flush_dcache_page(page); 738 739 qc->curbytes += qc->sect_size; 740 qc->cursg_ofs += qc->sect_size; 741 742 if (qc->cursg_ofs == qc->cursg->length) { 743 qc->cursg = sg_next(qc->cursg); 744 qc->cursg_ofs = 0; 745 } 746 } 747 748 /** 749 * ata_pio_sectors - Transfer one or many sectors. 750 * @qc: Command on going 751 * 752 * Transfer one or many sectors of data from/to the 753 * ATA device for the DRQ request. 754 * 755 * LOCKING: 756 * Inherited from caller. 757 */ 758 static void ata_pio_sectors(struct ata_queued_cmd *qc) 759 { 760 if (is_multi_taskfile(&qc->tf)) { 761 /* READ/WRITE MULTIPLE */ 762 unsigned int nsect; 763 764 WARN_ON_ONCE(qc->dev->multi_count == 0); 765 766 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, 767 qc->dev->multi_count); 768 while (nsect--) 769 ata_pio_sector(qc); 770 } else 771 ata_pio_sector(qc); 772 773 ata_sff_sync(qc->ap); /* flush */ 774 } 775 776 /** 777 * atapi_send_cdb - Write CDB bytes to hardware 778 * @ap: Port to which ATAPI device is attached. 779 * @qc: Taskfile currently active 780 * 781 * When device has indicated its readiness to accept 782 * a CDB, this function is called. Send the CDB. 783 * 784 * LOCKING: 785 * caller. 786 */ 787 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) 788 { 789 /* send SCSI cdb */ 790 DPRINTK("send cdb\n"); 791 WARN_ON_ONCE(qc->dev->cdb_len < 12); 792 793 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); 794 ata_sff_sync(ap); 795 /* FIXME: If the CDB is for DMA do we need to do the transition delay 796 or is bmdma_start guaranteed to do it ? */ 797 switch (qc->tf.protocol) { 798 case ATAPI_PROT_PIO: 799 ap->hsm_task_state = HSM_ST; 800 break; 801 case ATAPI_PROT_NODATA: 802 ap->hsm_task_state = HSM_ST_LAST; 803 break; 804 #ifdef CONFIG_ATA_BMDMA 805 case ATAPI_PROT_DMA: 806 ap->hsm_task_state = HSM_ST_LAST; 807 /* initiate bmdma */ 808 ap->ops->bmdma_start(qc); 809 break; 810 #endif /* CONFIG_ATA_BMDMA */ 811 default: 812 BUG(); 813 } 814 } 815 816 /** 817 * __atapi_pio_bytes - Transfer data from/to the ATAPI device. 818 * @qc: Command on going 819 * @bytes: number of bytes 820 * 821 * Transfer Transfer data from/to the ATAPI device. 822 * 823 * LOCKING: 824 * Inherited from caller. 825 * 826 */ 827 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) 828 { 829 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; 830 struct ata_port *ap = qc->ap; 831 struct ata_device *dev = qc->dev; 832 struct ata_eh_info *ehi = &dev->link->eh_info; 833 struct scatterlist *sg; 834 struct page *page; 835 unsigned char *buf; 836 unsigned int offset, count, consumed; 837 838 next_sg: 839 sg = qc->cursg; 840 if (unlikely(!sg)) { 841 ata_ehi_push_desc(ehi, "unexpected or too much trailing data " 842 "buf=%u cur=%u bytes=%u", 843 qc->nbytes, qc->curbytes, bytes); 844 return -1; 845 } 846 847 page = sg_page(sg); 848 offset = sg->offset + qc->cursg_ofs; 849 850 /* get the current page and offset */ 851 page = nth_page(page, (offset >> PAGE_SHIFT)); 852 offset %= PAGE_SIZE; 853 854 /* don't overrun current sg */ 855 count = min(sg->length - qc->cursg_ofs, bytes); 856 857 /* don't cross page boundaries */ 858 count = min(count, (unsigned int)PAGE_SIZE - offset); 859 860 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); 861 862 if (PageHighMem(page)) { 863 unsigned long flags; 864 865 /* FIXME: use bounce buffer */ 866 local_irq_save(flags); 867 buf = kmap_atomic(page, KM_IRQ0); 868 869 /* do the actual data transfer */ 870 consumed = ap->ops->sff_data_xfer(dev, buf + offset, 871 count, rw); 872 873 kunmap_atomic(buf, KM_IRQ0); 874 local_irq_restore(flags); 875 } else { 876 buf = page_address(page); 877 consumed = ap->ops->sff_data_xfer(dev, buf + offset, 878 count, rw); 879 } 880 881 bytes -= min(bytes, consumed); 882 qc->curbytes += count; 883 qc->cursg_ofs += count; 884 885 if (qc->cursg_ofs == sg->length) { 886 qc->cursg = sg_next(qc->cursg); 887 qc->cursg_ofs = 0; 888 } 889 890 /* 891 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); 892 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN 893 * check correctly as it doesn't know if it is the last request being 894 * made. Somebody should implement a proper sanity check. 895 */ 896 if (bytes) 897 goto next_sg; 898 return 0; 899 } 900 901 /** 902 * atapi_pio_bytes - Transfer data from/to the ATAPI device. 903 * @qc: Command on going 904 * 905 * Transfer Transfer data from/to the ATAPI device. 906 * 907 * LOCKING: 908 * Inherited from caller. 909 */ 910 static void atapi_pio_bytes(struct ata_queued_cmd *qc) 911 { 912 struct ata_port *ap = qc->ap; 913 struct ata_device *dev = qc->dev; 914 struct ata_eh_info *ehi = &dev->link->eh_info; 915 unsigned int ireason, bc_lo, bc_hi, bytes; 916 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; 917 918 /* Abuse qc->result_tf for temp storage of intermediate TF 919 * here to save some kernel stack usage. 920 * For normal completion, qc->result_tf is not relevant. For 921 * error, qc->result_tf is later overwritten by ata_qc_complete(). 922 * So, the correctness of qc->result_tf is not affected. 923 */ 924 ap->ops->sff_tf_read(ap, &qc->result_tf); 925 ireason = qc->result_tf.nsect; 926 bc_lo = qc->result_tf.lbam; 927 bc_hi = qc->result_tf.lbah; 928 bytes = (bc_hi << 8) | bc_lo; 929 930 /* shall be cleared to zero, indicating xfer of data */ 931 if (unlikely(ireason & (1 << 0))) 932 goto atapi_check; 933 934 /* make sure transfer direction matches expected */ 935 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; 936 if (unlikely(do_write != i_write)) 937 goto atapi_check; 938 939 if (unlikely(!bytes)) 940 goto atapi_check; 941 942 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); 943 944 if (unlikely(__atapi_pio_bytes(qc, bytes))) 945 goto err_out; 946 ata_sff_sync(ap); /* flush */ 947 948 return; 949 950 atapi_check: 951 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", 952 ireason, bytes); 953 err_out: 954 qc->err_mask |= AC_ERR_HSM; 955 ap->hsm_task_state = HSM_ST_ERR; 956 } 957 958 /** 959 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. 960 * @ap: the target ata_port 961 * @qc: qc on going 962 * 963 * RETURNS: 964 * 1 if ok in workqueue, 0 otherwise. 965 */ 966 static inline int ata_hsm_ok_in_wq(struct ata_port *ap, 967 struct ata_queued_cmd *qc) 968 { 969 if (qc->tf.flags & ATA_TFLAG_POLLING) 970 return 1; 971 972 if (ap->hsm_task_state == HSM_ST_FIRST) { 973 if (qc->tf.protocol == ATA_PROT_PIO && 974 (qc->tf.flags & ATA_TFLAG_WRITE)) 975 return 1; 976 977 if (ata_is_atapi(qc->tf.protocol) && 978 !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 979 return 1; 980 } 981 982 return 0; 983 } 984 985 /** 986 * ata_hsm_qc_complete - finish a qc running on standard HSM 987 * @qc: Command to complete 988 * @in_wq: 1 if called from workqueue, 0 otherwise 989 * 990 * Finish @qc which is running on standard HSM. 991 * 992 * LOCKING: 993 * If @in_wq is zero, spin_lock_irqsave(host lock). 994 * Otherwise, none on entry and grabs host lock. 995 */ 996 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) 997 { 998 struct ata_port *ap = qc->ap; 999 unsigned long flags; 1000 1001 if (ap->ops->error_handler) { 1002 if (in_wq) { 1003 spin_lock_irqsave(ap->lock, flags); 1004 1005 /* EH might have kicked in while host lock is 1006 * released. 1007 */ 1008 qc = ata_qc_from_tag(ap, qc->tag); 1009 if (qc) { 1010 if (likely(!(qc->err_mask & AC_ERR_HSM))) { 1011 ata_sff_irq_on(ap); 1012 ata_qc_complete(qc); 1013 } else 1014 ata_port_freeze(ap); 1015 } 1016 1017 spin_unlock_irqrestore(ap->lock, flags); 1018 } else { 1019 if (likely(!(qc->err_mask & AC_ERR_HSM))) 1020 ata_qc_complete(qc); 1021 else 1022 ata_port_freeze(ap); 1023 } 1024 } else { 1025 if (in_wq) { 1026 spin_lock_irqsave(ap->lock, flags); 1027 ata_sff_irq_on(ap); 1028 ata_qc_complete(qc); 1029 spin_unlock_irqrestore(ap->lock, flags); 1030 } else 1031 ata_qc_complete(qc); 1032 } 1033 } 1034 1035 /** 1036 * ata_sff_hsm_move - move the HSM to the next state. 1037 * @ap: the target ata_port 1038 * @qc: qc on going 1039 * @status: current device status 1040 * @in_wq: 1 if called from workqueue, 0 otherwise 1041 * 1042 * RETURNS: 1043 * 1 when poll next status needed, 0 otherwise. 1044 */ 1045 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, 1046 u8 status, int in_wq) 1047 { 1048 struct ata_link *link = qc->dev->link; 1049 struct ata_eh_info *ehi = &link->eh_info; 1050 unsigned long flags = 0; 1051 int poll_next; 1052 1053 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0); 1054 1055 /* Make sure ata_sff_qc_issue() does not throw things 1056 * like DMA polling into the workqueue. Notice that 1057 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). 1058 */ 1059 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc)); 1060 1061 fsm_start: 1062 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", 1063 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); 1064 1065 switch (ap->hsm_task_state) { 1066 case HSM_ST_FIRST: 1067 /* Send first data block or PACKET CDB */ 1068 1069 /* If polling, we will stay in the work queue after 1070 * sending the data. Otherwise, interrupt handler 1071 * takes over after sending the data. 1072 */ 1073 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); 1074 1075 /* check device status */ 1076 if (unlikely((status & ATA_DRQ) == 0)) { 1077 /* handle BSY=0, DRQ=0 as error */ 1078 if (likely(status & (ATA_ERR | ATA_DF))) 1079 /* device stops HSM for abort/error */ 1080 qc->err_mask |= AC_ERR_DEV; 1081 else { 1082 /* HSM violation. Let EH handle this */ 1083 ata_ehi_push_desc(ehi, 1084 "ST_FIRST: !(DRQ|ERR|DF)"); 1085 qc->err_mask |= AC_ERR_HSM; 1086 } 1087 1088 ap->hsm_task_state = HSM_ST_ERR; 1089 goto fsm_start; 1090 } 1091 1092 /* Device should not ask for data transfer (DRQ=1) 1093 * when it finds something wrong. 1094 * We ignore DRQ here and stop the HSM by 1095 * changing hsm_task_state to HSM_ST_ERR and 1096 * let the EH abort the command or reset the device. 1097 */ 1098 if (unlikely(status & (ATA_ERR | ATA_DF))) { 1099 /* Some ATAPI tape drives forget to clear the ERR bit 1100 * when doing the next command (mostly request sense). 1101 * We ignore ERR here to workaround and proceed sending 1102 * the CDB. 1103 */ 1104 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { 1105 ata_ehi_push_desc(ehi, "ST_FIRST: " 1106 "DRQ=1 with device error, " 1107 "dev_stat 0x%X", status); 1108 qc->err_mask |= AC_ERR_HSM; 1109 ap->hsm_task_state = HSM_ST_ERR; 1110 goto fsm_start; 1111 } 1112 } 1113 1114 /* Send the CDB (atapi) or the first data block (ata pio out). 1115 * During the state transition, interrupt handler shouldn't 1116 * be invoked before the data transfer is complete and 1117 * hsm_task_state is changed. Hence, the following locking. 1118 */ 1119 if (in_wq) 1120 spin_lock_irqsave(ap->lock, flags); 1121 1122 if (qc->tf.protocol == ATA_PROT_PIO) { 1123 /* PIO data out protocol. 1124 * send first data block. 1125 */ 1126 1127 /* ata_pio_sectors() might change the state 1128 * to HSM_ST_LAST. so, the state is changed here 1129 * before ata_pio_sectors(). 1130 */ 1131 ap->hsm_task_state = HSM_ST; 1132 ata_pio_sectors(qc); 1133 } else 1134 /* send CDB */ 1135 atapi_send_cdb(ap, qc); 1136 1137 if (in_wq) 1138 spin_unlock_irqrestore(ap->lock, flags); 1139 1140 /* if polling, ata_sff_pio_task() handles the rest. 1141 * otherwise, interrupt handler takes over from here. 1142 */ 1143 break; 1144 1145 case HSM_ST: 1146 /* complete command or read/write the data register */ 1147 if (qc->tf.protocol == ATAPI_PROT_PIO) { 1148 /* ATAPI PIO protocol */ 1149 if ((status & ATA_DRQ) == 0) { 1150 /* No more data to transfer or device error. 1151 * Device error will be tagged in HSM_ST_LAST. 1152 */ 1153 ap->hsm_task_state = HSM_ST_LAST; 1154 goto fsm_start; 1155 } 1156 1157 /* Device should not ask for data transfer (DRQ=1) 1158 * when it finds something wrong. 1159 * We ignore DRQ here and stop the HSM by 1160 * changing hsm_task_state to HSM_ST_ERR and 1161 * let the EH abort the command or reset the device. 1162 */ 1163 if (unlikely(status & (ATA_ERR | ATA_DF))) { 1164 ata_ehi_push_desc(ehi, "ST-ATAPI: " 1165 "DRQ=1 with device error, " 1166 "dev_stat 0x%X", status); 1167 qc->err_mask |= AC_ERR_HSM; 1168 ap->hsm_task_state = HSM_ST_ERR; 1169 goto fsm_start; 1170 } 1171 1172 atapi_pio_bytes(qc); 1173 1174 if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) 1175 /* bad ireason reported by device */ 1176 goto fsm_start; 1177 1178 } else { 1179 /* ATA PIO protocol */ 1180 if (unlikely((status & ATA_DRQ) == 0)) { 1181 /* handle BSY=0, DRQ=0 as error */ 1182 if (likely(status & (ATA_ERR | ATA_DF))) { 1183 /* device stops HSM for abort/error */ 1184 qc->err_mask |= AC_ERR_DEV; 1185 1186 /* If diagnostic failed and this is 1187 * IDENTIFY, it's likely a phantom 1188 * device. Mark hint. 1189 */ 1190 if (qc->dev->horkage & 1191 ATA_HORKAGE_DIAGNOSTIC) 1192 qc->err_mask |= 1193 AC_ERR_NODEV_HINT; 1194 } else { 1195 /* HSM violation. Let EH handle this. 1196 * Phantom devices also trigger this 1197 * condition. Mark hint. 1198 */ 1199 ata_ehi_push_desc(ehi, "ST-ATA: " 1200 "DRQ=0 without device error, " 1201 "dev_stat 0x%X", status); 1202 qc->err_mask |= AC_ERR_HSM | 1203 AC_ERR_NODEV_HINT; 1204 } 1205 1206 ap->hsm_task_state = HSM_ST_ERR; 1207 goto fsm_start; 1208 } 1209 1210 /* For PIO reads, some devices may ask for 1211 * data transfer (DRQ=1) alone with ERR=1. 1212 * We respect DRQ here and transfer one 1213 * block of junk data before changing the 1214 * hsm_task_state to HSM_ST_ERR. 1215 * 1216 * For PIO writes, ERR=1 DRQ=1 doesn't make 1217 * sense since the data block has been 1218 * transferred to the device. 1219 */ 1220 if (unlikely(status & (ATA_ERR | ATA_DF))) { 1221 /* data might be corrputed */ 1222 qc->err_mask |= AC_ERR_DEV; 1223 1224 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { 1225 ata_pio_sectors(qc); 1226 status = ata_wait_idle(ap); 1227 } 1228 1229 if (status & (ATA_BUSY | ATA_DRQ)) { 1230 ata_ehi_push_desc(ehi, "ST-ATA: " 1231 "BUSY|DRQ persists on ERR|DF, " 1232 "dev_stat 0x%X", status); 1233 qc->err_mask |= AC_ERR_HSM; 1234 } 1235 1236 /* There are oddball controllers with 1237 * status register stuck at 0x7f and 1238 * lbal/m/h at zero which makes it 1239 * pass all other presence detection 1240 * mechanisms we have. Set NODEV_HINT 1241 * for it. Kernel bz#7241. 1242 */ 1243 if (status == 0x7f) 1244 qc->err_mask |= AC_ERR_NODEV_HINT; 1245 1246 /* ata_pio_sectors() might change the 1247 * state to HSM_ST_LAST. so, the state 1248 * is changed after ata_pio_sectors(). 1249 */ 1250 ap->hsm_task_state = HSM_ST_ERR; 1251 goto fsm_start; 1252 } 1253 1254 ata_pio_sectors(qc); 1255 1256 if (ap->hsm_task_state == HSM_ST_LAST && 1257 (!(qc->tf.flags & ATA_TFLAG_WRITE))) { 1258 /* all data read */ 1259 status = ata_wait_idle(ap); 1260 goto fsm_start; 1261 } 1262 } 1263 1264 poll_next = 1; 1265 break; 1266 1267 case HSM_ST_LAST: 1268 if (unlikely(!ata_ok(status))) { 1269 qc->err_mask |= __ac_err_mask(status); 1270 ap->hsm_task_state = HSM_ST_ERR; 1271 goto fsm_start; 1272 } 1273 1274 /* no more data to transfer */ 1275 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", 1276 ap->print_id, qc->dev->devno, status); 1277 1278 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); 1279 1280 ap->hsm_task_state = HSM_ST_IDLE; 1281 1282 /* complete taskfile transaction */ 1283 ata_hsm_qc_complete(qc, in_wq); 1284 1285 poll_next = 0; 1286 break; 1287 1288 case HSM_ST_ERR: 1289 ap->hsm_task_state = HSM_ST_IDLE; 1290 1291 /* complete taskfile transaction */ 1292 ata_hsm_qc_complete(qc, in_wq); 1293 1294 poll_next = 0; 1295 break; 1296 default: 1297 poll_next = 0; 1298 BUG(); 1299 } 1300 1301 return poll_next; 1302 } 1303 EXPORT_SYMBOL_GPL(ata_sff_hsm_move); 1304 1305 void ata_sff_queue_work(struct work_struct *work) 1306 { 1307 queue_work(ata_sff_wq, work); 1308 } 1309 EXPORT_SYMBOL_GPL(ata_sff_queue_work); 1310 1311 void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay) 1312 { 1313 queue_delayed_work(ata_sff_wq, dwork, delay); 1314 } 1315 EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work); 1316 1317 void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay) 1318 { 1319 struct ata_port *ap = link->ap; 1320 1321 WARN_ON((ap->sff_pio_task_link != NULL) && 1322 (ap->sff_pio_task_link != link)); 1323 ap->sff_pio_task_link = link; 1324 1325 /* may fail if ata_sff_flush_pio_task() in progress */ 1326 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay)); 1327 } 1328 EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task); 1329 1330 void ata_sff_flush_pio_task(struct ata_port *ap) 1331 { 1332 DPRINTK("ENTER\n"); 1333 1334 cancel_delayed_work_sync(&ap->sff_pio_task); 1335 ap->hsm_task_state = HSM_ST_IDLE; 1336 ap->sff_pio_task_link = NULL; 1337 1338 if (ata_msg_ctl(ap)) 1339 ata_port_dbg(ap, "%s: EXIT\n", __func__); 1340 } 1341 1342 static void ata_sff_pio_task(struct work_struct *work) 1343 { 1344 struct ata_port *ap = 1345 container_of(work, struct ata_port, sff_pio_task.work); 1346 struct ata_link *link = ap->sff_pio_task_link; 1347 struct ata_queued_cmd *qc; 1348 u8 status; 1349 int poll_next; 1350 1351 BUG_ON(ap->sff_pio_task_link == NULL); 1352 /* qc can be NULL if timeout occurred */ 1353 qc = ata_qc_from_tag(ap, link->active_tag); 1354 if (!qc) { 1355 ap->sff_pio_task_link = NULL; 1356 return; 1357 } 1358 1359 fsm_start: 1360 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE); 1361 1362 /* 1363 * This is purely heuristic. This is a fast path. 1364 * Sometimes when we enter, BSY will be cleared in 1365 * a chk-status or two. If not, the drive is probably seeking 1366 * or something. Snooze for a couple msecs, then 1367 * chk-status again. If still busy, queue delayed work. 1368 */ 1369 status = ata_sff_busy_wait(ap, ATA_BUSY, 5); 1370 if (status & ATA_BUSY) { 1371 ata_msleep(ap, 2); 1372 status = ata_sff_busy_wait(ap, ATA_BUSY, 10); 1373 if (status & ATA_BUSY) { 1374 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE); 1375 return; 1376 } 1377 } 1378 1379 /* 1380 * hsm_move() may trigger another command to be processed. 1381 * clean the link beforehand. 1382 */ 1383 ap->sff_pio_task_link = NULL; 1384 /* move the HSM */ 1385 poll_next = ata_sff_hsm_move(ap, qc, status, 1); 1386 1387 /* another command or interrupt handler 1388 * may be running at this point. 1389 */ 1390 if (poll_next) 1391 goto fsm_start; 1392 } 1393 1394 /** 1395 * ata_sff_qc_issue - issue taskfile to a SFF controller 1396 * @qc: command to issue to device 1397 * 1398 * This function issues a PIO or NODATA command to a SFF 1399 * controller. 1400 * 1401 * LOCKING: 1402 * spin_lock_irqsave(host lock) 1403 * 1404 * RETURNS: 1405 * Zero on success, AC_ERR_* mask on failure 1406 */ 1407 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) 1408 { 1409 struct ata_port *ap = qc->ap; 1410 struct ata_link *link = qc->dev->link; 1411 1412 /* Use polling pio if the LLD doesn't handle 1413 * interrupt driven pio and atapi CDB interrupt. 1414 */ 1415 if (ap->flags & ATA_FLAG_PIO_POLLING) 1416 qc->tf.flags |= ATA_TFLAG_POLLING; 1417 1418 /* select the device */ 1419 ata_dev_select(ap, qc->dev->devno, 1, 0); 1420 1421 /* start the command */ 1422 switch (qc->tf.protocol) { 1423 case ATA_PROT_NODATA: 1424 if (qc->tf.flags & ATA_TFLAG_POLLING) 1425 ata_qc_set_polling(qc); 1426 1427 ata_tf_to_host(ap, &qc->tf); 1428 ap->hsm_task_state = HSM_ST_LAST; 1429 1430 if (qc->tf.flags & ATA_TFLAG_POLLING) 1431 ata_sff_queue_pio_task(link, 0); 1432 1433 break; 1434 1435 case ATA_PROT_PIO: 1436 if (qc->tf.flags & ATA_TFLAG_POLLING) 1437 ata_qc_set_polling(qc); 1438 1439 ata_tf_to_host(ap, &qc->tf); 1440 1441 if (qc->tf.flags & ATA_TFLAG_WRITE) { 1442 /* PIO data out protocol */ 1443 ap->hsm_task_state = HSM_ST_FIRST; 1444 ata_sff_queue_pio_task(link, 0); 1445 1446 /* always send first data block using the 1447 * ata_sff_pio_task() codepath. 1448 */ 1449 } else { 1450 /* PIO data in protocol */ 1451 ap->hsm_task_state = HSM_ST; 1452 1453 if (qc->tf.flags & ATA_TFLAG_POLLING) 1454 ata_sff_queue_pio_task(link, 0); 1455 1456 /* if polling, ata_sff_pio_task() handles the 1457 * rest. otherwise, interrupt handler takes 1458 * over from here. 1459 */ 1460 } 1461 1462 break; 1463 1464 case ATAPI_PROT_PIO: 1465 case ATAPI_PROT_NODATA: 1466 if (qc->tf.flags & ATA_TFLAG_POLLING) 1467 ata_qc_set_polling(qc); 1468 1469 ata_tf_to_host(ap, &qc->tf); 1470 1471 ap->hsm_task_state = HSM_ST_FIRST; 1472 1473 /* send cdb by polling if no cdb interrupt */ 1474 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || 1475 (qc->tf.flags & ATA_TFLAG_POLLING)) 1476 ata_sff_queue_pio_task(link, 0); 1477 break; 1478 1479 default: 1480 WARN_ON_ONCE(1); 1481 return AC_ERR_SYSTEM; 1482 } 1483 1484 return 0; 1485 } 1486 EXPORT_SYMBOL_GPL(ata_sff_qc_issue); 1487 1488 /** 1489 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read 1490 * @qc: qc to fill result TF for 1491 * 1492 * @qc is finished and result TF needs to be filled. Fill it 1493 * using ->sff_tf_read. 1494 * 1495 * LOCKING: 1496 * spin_lock_irqsave(host lock) 1497 * 1498 * RETURNS: 1499 * true indicating that result TF is successfully filled. 1500 */ 1501 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) 1502 { 1503 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); 1504 return true; 1505 } 1506 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); 1507 1508 static unsigned int ata_sff_idle_irq(struct ata_port *ap) 1509 { 1510 ap->stats.idle_irq++; 1511 1512 #ifdef ATA_IRQ_TRAP 1513 if ((ap->stats.idle_irq % 1000) == 0) { 1514 ap->ops->sff_check_status(ap); 1515 if (ap->ops->sff_irq_clear) 1516 ap->ops->sff_irq_clear(ap); 1517 ata_port_warn(ap, "irq trap\n"); 1518 return 1; 1519 } 1520 #endif 1521 return 0; /* irq not handled */ 1522 } 1523 1524 static unsigned int __ata_sff_port_intr(struct ata_port *ap, 1525 struct ata_queued_cmd *qc, 1526 bool hsmv_on_idle) 1527 { 1528 u8 status; 1529 1530 VPRINTK("ata%u: protocol %d task_state %d\n", 1531 ap->print_id, qc->tf.protocol, ap->hsm_task_state); 1532 1533 /* Check whether we are expecting interrupt in this state */ 1534 switch (ap->hsm_task_state) { 1535 case HSM_ST_FIRST: 1536 /* Some pre-ATAPI-4 devices assert INTRQ 1537 * at this state when ready to receive CDB. 1538 */ 1539 1540 /* Check the ATA_DFLAG_CDB_INTR flag is enough here. 1541 * The flag was turned on only for atapi devices. No 1542 * need to check ata_is_atapi(qc->tf.protocol) again. 1543 */ 1544 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 1545 return ata_sff_idle_irq(ap); 1546 break; 1547 case HSM_ST_IDLE: 1548 return ata_sff_idle_irq(ap); 1549 default: 1550 break; 1551 } 1552 1553 /* check main status, clearing INTRQ if needed */ 1554 status = ata_sff_irq_status(ap); 1555 if (status & ATA_BUSY) { 1556 if (hsmv_on_idle) { 1557 /* BMDMA engine is already stopped, we're screwed */ 1558 qc->err_mask |= AC_ERR_HSM; 1559 ap->hsm_task_state = HSM_ST_ERR; 1560 } else 1561 return ata_sff_idle_irq(ap); 1562 } 1563 1564 /* clear irq events */ 1565 if (ap->ops->sff_irq_clear) 1566 ap->ops->sff_irq_clear(ap); 1567 1568 ata_sff_hsm_move(ap, qc, status, 0); 1569 1570 return 1; /* irq handled */ 1571 } 1572 1573 /** 1574 * ata_sff_port_intr - Handle SFF port interrupt 1575 * @ap: Port on which interrupt arrived (possibly...) 1576 * @qc: Taskfile currently active in engine 1577 * 1578 * Handle port interrupt for given queued command. 1579 * 1580 * LOCKING: 1581 * spin_lock_irqsave(host lock) 1582 * 1583 * RETURNS: 1584 * One if interrupt was handled, zero if not (shared irq). 1585 */ 1586 unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) 1587 { 1588 return __ata_sff_port_intr(ap, qc, false); 1589 } 1590 EXPORT_SYMBOL_GPL(ata_sff_port_intr); 1591 1592 static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance, 1593 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *)) 1594 { 1595 struct ata_host *host = dev_instance; 1596 bool retried = false; 1597 unsigned int i; 1598 unsigned int handled, idle, polling; 1599 unsigned long flags; 1600 1601 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ 1602 spin_lock_irqsave(&host->lock, flags); 1603 1604 retry: 1605 handled = idle = polling = 0; 1606 for (i = 0; i < host->n_ports; i++) { 1607 struct ata_port *ap = host->ports[i]; 1608 struct ata_queued_cmd *qc; 1609 1610 qc = ata_qc_from_tag(ap, ap->link.active_tag); 1611 if (qc) { 1612 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) 1613 handled |= port_intr(ap, qc); 1614 else 1615 polling |= 1 << i; 1616 } else 1617 idle |= 1 << i; 1618 } 1619 1620 /* 1621 * If no port was expecting IRQ but the controller is actually 1622 * asserting IRQ line, nobody cared will ensue. Check IRQ 1623 * pending status if available and clear spurious IRQ. 1624 */ 1625 if (!handled && !retried) { 1626 bool retry = false; 1627 1628 for (i = 0; i < host->n_ports; i++) { 1629 struct ata_port *ap = host->ports[i]; 1630 1631 if (polling & (1 << i)) 1632 continue; 1633 1634 if (!ap->ops->sff_irq_check || 1635 !ap->ops->sff_irq_check(ap)) 1636 continue; 1637 1638 if (idle & (1 << i)) { 1639 ap->ops->sff_check_status(ap); 1640 if (ap->ops->sff_irq_clear) 1641 ap->ops->sff_irq_clear(ap); 1642 } else { 1643 /* clear INTRQ and check if BUSY cleared */ 1644 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY)) 1645 retry |= true; 1646 /* 1647 * With command in flight, we can't do 1648 * sff_irq_clear() w/o racing with completion. 1649 */ 1650 } 1651 } 1652 1653 if (retry) { 1654 retried = true; 1655 goto retry; 1656 } 1657 } 1658 1659 spin_unlock_irqrestore(&host->lock, flags); 1660 1661 return IRQ_RETVAL(handled); 1662 } 1663 1664 /** 1665 * ata_sff_interrupt - Default SFF ATA host interrupt handler 1666 * @irq: irq line (unused) 1667 * @dev_instance: pointer to our ata_host information structure 1668 * 1669 * Default interrupt handler for PCI IDE devices. Calls 1670 * ata_sff_port_intr() for each port that is not disabled. 1671 * 1672 * LOCKING: 1673 * Obtains host lock during operation. 1674 * 1675 * RETURNS: 1676 * IRQ_NONE or IRQ_HANDLED. 1677 */ 1678 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) 1679 { 1680 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr); 1681 } 1682 EXPORT_SYMBOL_GPL(ata_sff_interrupt); 1683 1684 /** 1685 * ata_sff_lost_interrupt - Check for an apparent lost interrupt 1686 * @ap: port that appears to have timed out 1687 * 1688 * Called from the libata error handlers when the core code suspects 1689 * an interrupt has been lost. If it has complete anything we can and 1690 * then return. Interface must support altstatus for this faster 1691 * recovery to occur. 1692 * 1693 * Locking: 1694 * Caller holds host lock 1695 */ 1696 1697 void ata_sff_lost_interrupt(struct ata_port *ap) 1698 { 1699 u8 status; 1700 struct ata_queued_cmd *qc; 1701 1702 /* Only one outstanding command per SFF channel */ 1703 qc = ata_qc_from_tag(ap, ap->link.active_tag); 1704 /* We cannot lose an interrupt on a non-existent or polled command */ 1705 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING) 1706 return; 1707 /* See if the controller thinks it is still busy - if so the command 1708 isn't a lost IRQ but is still in progress */ 1709 status = ata_sff_altstatus(ap); 1710 if (status & ATA_BUSY) 1711 return; 1712 1713 /* There was a command running, we are no longer busy and we have 1714 no interrupt. */ 1715 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n", 1716 status); 1717 /* Run the host interrupt logic as if the interrupt had not been 1718 lost */ 1719 ata_sff_port_intr(ap, qc); 1720 } 1721 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt); 1722 1723 /** 1724 * ata_sff_freeze - Freeze SFF controller port 1725 * @ap: port to freeze 1726 * 1727 * Freeze SFF controller port. 1728 * 1729 * LOCKING: 1730 * Inherited from caller. 1731 */ 1732 void ata_sff_freeze(struct ata_port *ap) 1733 { 1734 ap->ctl |= ATA_NIEN; 1735 ap->last_ctl = ap->ctl; 1736 1737 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) 1738 ata_sff_set_devctl(ap, ap->ctl); 1739 1740 /* Under certain circumstances, some controllers raise IRQ on 1741 * ATA_NIEN manipulation. Also, many controllers fail to mask 1742 * previously pending IRQ on ATA_NIEN assertion. Clear it. 1743 */ 1744 ap->ops->sff_check_status(ap); 1745 1746 if (ap->ops->sff_irq_clear) 1747 ap->ops->sff_irq_clear(ap); 1748 } 1749 EXPORT_SYMBOL_GPL(ata_sff_freeze); 1750 1751 /** 1752 * ata_sff_thaw - Thaw SFF controller port 1753 * @ap: port to thaw 1754 * 1755 * Thaw SFF controller port. 1756 * 1757 * LOCKING: 1758 * Inherited from caller. 1759 */ 1760 void ata_sff_thaw(struct ata_port *ap) 1761 { 1762 /* clear & re-enable interrupts */ 1763 ap->ops->sff_check_status(ap); 1764 if (ap->ops->sff_irq_clear) 1765 ap->ops->sff_irq_clear(ap); 1766 ata_sff_irq_on(ap); 1767 } 1768 EXPORT_SYMBOL_GPL(ata_sff_thaw); 1769 1770 /** 1771 * ata_sff_prereset - prepare SFF link for reset 1772 * @link: SFF link to be reset 1773 * @deadline: deadline jiffies for the operation 1774 * 1775 * SFF link @link is about to be reset. Initialize it. It first 1776 * calls ata_std_prereset() and wait for !BSY if the port is 1777 * being softreset. 1778 * 1779 * LOCKING: 1780 * Kernel thread context (may sleep) 1781 * 1782 * RETURNS: 1783 * 0 on success, -errno otherwise. 1784 */ 1785 int ata_sff_prereset(struct ata_link *link, unsigned long deadline) 1786 { 1787 struct ata_eh_context *ehc = &link->eh_context; 1788 int rc; 1789 1790 rc = ata_std_prereset(link, deadline); 1791 if (rc) 1792 return rc; 1793 1794 /* if we're about to do hardreset, nothing more to do */ 1795 if (ehc->i.action & ATA_EH_HARDRESET) 1796 return 0; 1797 1798 /* wait for !BSY if we don't know that no device is attached */ 1799 if (!ata_link_offline(link)) { 1800 rc = ata_sff_wait_ready(link, deadline); 1801 if (rc && rc != -ENODEV) { 1802 ata_link_warn(link, 1803 "device not ready (errno=%d), forcing hardreset\n", 1804 rc); 1805 ehc->i.action |= ATA_EH_HARDRESET; 1806 } 1807 } 1808 1809 return 0; 1810 } 1811 EXPORT_SYMBOL_GPL(ata_sff_prereset); 1812 1813 /** 1814 * ata_devchk - PATA device presence detection 1815 * @ap: ATA channel to examine 1816 * @device: Device to examine (starting at zero) 1817 * 1818 * This technique was originally described in 1819 * Hale Landis's ATADRVR (www.ata-atapi.com), and 1820 * later found its way into the ATA/ATAPI spec. 1821 * 1822 * Write a pattern to the ATA shadow registers, 1823 * and if a device is present, it will respond by 1824 * correctly storing and echoing back the 1825 * ATA shadow register contents. 1826 * 1827 * LOCKING: 1828 * caller. 1829 */ 1830 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) 1831 { 1832 struct ata_ioports *ioaddr = &ap->ioaddr; 1833 u8 nsect, lbal; 1834 1835 ap->ops->sff_dev_select(ap, device); 1836 1837 iowrite8(0x55, ioaddr->nsect_addr); 1838 iowrite8(0xaa, ioaddr->lbal_addr); 1839 1840 iowrite8(0xaa, ioaddr->nsect_addr); 1841 iowrite8(0x55, ioaddr->lbal_addr); 1842 1843 iowrite8(0x55, ioaddr->nsect_addr); 1844 iowrite8(0xaa, ioaddr->lbal_addr); 1845 1846 nsect = ioread8(ioaddr->nsect_addr); 1847 lbal = ioread8(ioaddr->lbal_addr); 1848 1849 if ((nsect == 0x55) && (lbal == 0xaa)) 1850 return 1; /* we found a device */ 1851 1852 return 0; /* nothing found */ 1853 } 1854 1855 /** 1856 * ata_sff_dev_classify - Parse returned ATA device signature 1857 * @dev: ATA device to classify (starting at zero) 1858 * @present: device seems present 1859 * @r_err: Value of error register on completion 1860 * 1861 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, 1862 * an ATA/ATAPI-defined set of values is placed in the ATA 1863 * shadow registers, indicating the results of device detection 1864 * and diagnostics. 1865 * 1866 * Select the ATA device, and read the values from the ATA shadow 1867 * registers. Then parse according to the Error register value, 1868 * and the spec-defined values examined by ata_dev_classify(). 1869 * 1870 * LOCKING: 1871 * caller. 1872 * 1873 * RETURNS: 1874 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. 1875 */ 1876 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, 1877 u8 *r_err) 1878 { 1879 struct ata_port *ap = dev->link->ap; 1880 struct ata_taskfile tf; 1881 unsigned int class; 1882 u8 err; 1883 1884 ap->ops->sff_dev_select(ap, dev->devno); 1885 1886 memset(&tf, 0, sizeof(tf)); 1887 1888 ap->ops->sff_tf_read(ap, &tf); 1889 err = tf.feature; 1890 if (r_err) 1891 *r_err = err; 1892 1893 /* see if device passed diags: continue and warn later */ 1894 if (err == 0) 1895 /* diagnostic fail : do nothing _YET_ */ 1896 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; 1897 else if (err == 1) 1898 /* do nothing */ ; 1899 else if ((dev->devno == 0) && (err == 0x81)) 1900 /* do nothing */ ; 1901 else 1902 return ATA_DEV_NONE; 1903 1904 /* determine if device is ATA or ATAPI */ 1905 class = ata_dev_classify(&tf); 1906 1907 if (class == ATA_DEV_UNKNOWN) { 1908 /* If the device failed diagnostic, it's likely to 1909 * have reported incorrect device signature too. 1910 * Assume ATA device if the device seems present but 1911 * device signature is invalid with diagnostic 1912 * failure. 1913 */ 1914 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) 1915 class = ATA_DEV_ATA; 1916 else 1917 class = ATA_DEV_NONE; 1918 } else if ((class == ATA_DEV_ATA) && 1919 (ap->ops->sff_check_status(ap) == 0)) 1920 class = ATA_DEV_NONE; 1921 1922 return class; 1923 } 1924 EXPORT_SYMBOL_GPL(ata_sff_dev_classify); 1925 1926 /** 1927 * ata_sff_wait_after_reset - wait for devices to become ready after reset 1928 * @link: SFF link which is just reset 1929 * @devmask: mask of present devices 1930 * @deadline: deadline jiffies for the operation 1931 * 1932 * Wait devices attached to SFF @link to become ready after 1933 * reset. It contains preceding 150ms wait to avoid accessing TF 1934 * status register too early. 1935 * 1936 * LOCKING: 1937 * Kernel thread context (may sleep). 1938 * 1939 * RETURNS: 1940 * 0 on success, -ENODEV if some or all of devices in @devmask 1941 * don't seem to exist. -errno on other errors. 1942 */ 1943 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, 1944 unsigned long deadline) 1945 { 1946 struct ata_port *ap = link->ap; 1947 struct ata_ioports *ioaddr = &ap->ioaddr; 1948 unsigned int dev0 = devmask & (1 << 0); 1949 unsigned int dev1 = devmask & (1 << 1); 1950 int rc, ret = 0; 1951 1952 ata_msleep(ap, ATA_WAIT_AFTER_RESET); 1953 1954 /* always check readiness of the master device */ 1955 rc = ata_sff_wait_ready(link, deadline); 1956 /* -ENODEV means the odd clown forgot the D7 pulldown resistor 1957 * and TF status is 0xff, bail out on it too. 1958 */ 1959 if (rc) 1960 return rc; 1961 1962 /* if device 1 was found in ata_devchk, wait for register 1963 * access briefly, then wait for BSY to clear. 1964 */ 1965 if (dev1) { 1966 int i; 1967 1968 ap->ops->sff_dev_select(ap, 1); 1969 1970 /* Wait for register access. Some ATAPI devices fail 1971 * to set nsect/lbal after reset, so don't waste too 1972 * much time on it. We're gonna wait for !BSY anyway. 1973 */ 1974 for (i = 0; i < 2; i++) { 1975 u8 nsect, lbal; 1976 1977 nsect = ioread8(ioaddr->nsect_addr); 1978 lbal = ioread8(ioaddr->lbal_addr); 1979 if ((nsect == 1) && (lbal == 1)) 1980 break; 1981 ata_msleep(ap, 50); /* give drive a breather */ 1982 } 1983 1984 rc = ata_sff_wait_ready(link, deadline); 1985 if (rc) { 1986 if (rc != -ENODEV) 1987 return rc; 1988 ret = rc; 1989 } 1990 } 1991 1992 /* is all this really necessary? */ 1993 ap->ops->sff_dev_select(ap, 0); 1994 if (dev1) 1995 ap->ops->sff_dev_select(ap, 1); 1996 if (dev0) 1997 ap->ops->sff_dev_select(ap, 0); 1998 1999 return ret; 2000 } 2001 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); 2002 2003 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, 2004 unsigned long deadline) 2005 { 2006 struct ata_ioports *ioaddr = &ap->ioaddr; 2007 2008 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); 2009 2010 /* software reset. causes dev0 to be selected */ 2011 iowrite8(ap->ctl, ioaddr->ctl_addr); 2012 udelay(20); /* FIXME: flush */ 2013 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); 2014 udelay(20); /* FIXME: flush */ 2015 iowrite8(ap->ctl, ioaddr->ctl_addr); 2016 ap->last_ctl = ap->ctl; 2017 2018 /* wait the port to become ready */ 2019 return ata_sff_wait_after_reset(&ap->link, devmask, deadline); 2020 } 2021 2022 /** 2023 * ata_sff_softreset - reset host port via ATA SRST 2024 * @link: ATA link to reset 2025 * @classes: resulting classes of attached devices 2026 * @deadline: deadline jiffies for the operation 2027 * 2028 * Reset host port using ATA SRST. 2029 * 2030 * LOCKING: 2031 * Kernel thread context (may sleep) 2032 * 2033 * RETURNS: 2034 * 0 on success, -errno otherwise. 2035 */ 2036 int ata_sff_softreset(struct ata_link *link, unsigned int *classes, 2037 unsigned long deadline) 2038 { 2039 struct ata_port *ap = link->ap; 2040 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; 2041 unsigned int devmask = 0; 2042 int rc; 2043 u8 err; 2044 2045 DPRINTK("ENTER\n"); 2046 2047 /* determine if device 0/1 are present */ 2048 if (ata_devchk(ap, 0)) 2049 devmask |= (1 << 0); 2050 if (slave_possible && ata_devchk(ap, 1)) 2051 devmask |= (1 << 1); 2052 2053 /* select device 0 again */ 2054 ap->ops->sff_dev_select(ap, 0); 2055 2056 /* issue bus reset */ 2057 DPRINTK("about to softreset, devmask=%x\n", devmask); 2058 rc = ata_bus_softreset(ap, devmask, deadline); 2059 /* if link is occupied, -ENODEV too is an error */ 2060 if (rc && (rc != -ENODEV || sata_scr_valid(link))) { 2061 ata_link_err(link, "SRST failed (errno=%d)\n", rc); 2062 return rc; 2063 } 2064 2065 /* determine by signature whether we have ATA or ATAPI devices */ 2066 classes[0] = ata_sff_dev_classify(&link->device[0], 2067 devmask & (1 << 0), &err); 2068 if (slave_possible && err != 0x81) 2069 classes[1] = ata_sff_dev_classify(&link->device[1], 2070 devmask & (1 << 1), &err); 2071 2072 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); 2073 return 0; 2074 } 2075 EXPORT_SYMBOL_GPL(ata_sff_softreset); 2076 2077 /** 2078 * sata_sff_hardreset - reset host port via SATA phy reset 2079 * @link: link to reset 2080 * @class: resulting class of attached device 2081 * @deadline: deadline jiffies for the operation 2082 * 2083 * SATA phy-reset host port using DET bits of SControl register, 2084 * wait for !BSY and classify the attached device. 2085 * 2086 * LOCKING: 2087 * Kernel thread context (may sleep) 2088 * 2089 * RETURNS: 2090 * 0 on success, -errno otherwise. 2091 */ 2092 int sata_sff_hardreset(struct ata_link *link, unsigned int *class, 2093 unsigned long deadline) 2094 { 2095 struct ata_eh_context *ehc = &link->eh_context; 2096 const unsigned long *timing = sata_ehc_deb_timing(ehc); 2097 bool online; 2098 int rc; 2099 2100 rc = sata_link_hardreset(link, timing, deadline, &online, 2101 ata_sff_check_ready); 2102 if (online) 2103 *class = ata_sff_dev_classify(link->device, 1, NULL); 2104 2105 DPRINTK("EXIT, class=%u\n", *class); 2106 return rc; 2107 } 2108 EXPORT_SYMBOL_GPL(sata_sff_hardreset); 2109 2110 /** 2111 * ata_sff_postreset - SFF postreset callback 2112 * @link: the target SFF ata_link 2113 * @classes: classes of attached devices 2114 * 2115 * This function is invoked after a successful reset. It first 2116 * calls ata_std_postreset() and performs SFF specific postreset 2117 * processing. 2118 * 2119 * LOCKING: 2120 * Kernel thread context (may sleep) 2121 */ 2122 void ata_sff_postreset(struct ata_link *link, unsigned int *classes) 2123 { 2124 struct ata_port *ap = link->ap; 2125 2126 ata_std_postreset(link, classes); 2127 2128 /* is double-select really necessary? */ 2129 if (classes[0] != ATA_DEV_NONE) 2130 ap->ops->sff_dev_select(ap, 1); 2131 if (classes[1] != ATA_DEV_NONE) 2132 ap->ops->sff_dev_select(ap, 0); 2133 2134 /* bail out if no device is present */ 2135 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { 2136 DPRINTK("EXIT, no device\n"); 2137 return; 2138 } 2139 2140 /* set up device control */ 2141 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) { 2142 ata_sff_set_devctl(ap, ap->ctl); 2143 ap->last_ctl = ap->ctl; 2144 } 2145 } 2146 EXPORT_SYMBOL_GPL(ata_sff_postreset); 2147 2148 /** 2149 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers 2150 * @qc: command 2151 * 2152 * Drain the FIFO and device of any stuck data following a command 2153 * failing to complete. In some cases this is necessary before a 2154 * reset will recover the device. 2155 * 2156 */ 2157 2158 void ata_sff_drain_fifo(struct ata_queued_cmd *qc) 2159 { 2160 int count; 2161 struct ata_port *ap; 2162 2163 /* We only need to flush incoming data when a command was running */ 2164 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) 2165 return; 2166 2167 ap = qc->ap; 2168 /* Drain up to 64K of data before we give up this recovery method */ 2169 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) 2170 && count < 65536; count += 2) 2171 ioread16(ap->ioaddr.data_addr); 2172 2173 /* Can become DEBUG later */ 2174 if (count) 2175 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); 2176 2177 } 2178 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo); 2179 2180 /** 2181 * ata_sff_error_handler - Stock error handler for SFF controller 2182 * @ap: port to handle error for 2183 * 2184 * Stock error handler for SFF controller. It can handle both 2185 * PATA and SATA controllers. Many controllers should be able to 2186 * use this EH as-is or with some added handling before and 2187 * after. 2188 * 2189 * LOCKING: 2190 * Kernel thread context (may sleep) 2191 */ 2192 void ata_sff_error_handler(struct ata_port *ap) 2193 { 2194 ata_reset_fn_t softreset = ap->ops->softreset; 2195 ata_reset_fn_t hardreset = ap->ops->hardreset; 2196 struct ata_queued_cmd *qc; 2197 unsigned long flags; 2198 2199 qc = __ata_qc_from_tag(ap, ap->link.active_tag); 2200 if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) 2201 qc = NULL; 2202 2203 spin_lock_irqsave(ap->lock, flags); 2204 2205 /* 2206 * We *MUST* do FIFO draining before we issue a reset as 2207 * several devices helpfully clear their internal state and 2208 * will lock solid if we touch the data port post reset. Pass 2209 * qc in case anyone wants to do different PIO/DMA recovery or 2210 * has per command fixups 2211 */ 2212 if (ap->ops->sff_drain_fifo) 2213 ap->ops->sff_drain_fifo(qc); 2214 2215 spin_unlock_irqrestore(ap->lock, flags); 2216 2217 /* ignore ata_sff_softreset if ctl isn't accessible */ 2218 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) 2219 softreset = NULL; 2220 2221 /* ignore built-in hardresets if SCR access is not available */ 2222 if ((hardreset == sata_std_hardreset || 2223 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link)) 2224 hardreset = NULL; 2225 2226 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, 2227 ap->ops->postreset); 2228 } 2229 EXPORT_SYMBOL_GPL(ata_sff_error_handler); 2230 2231 /** 2232 * ata_sff_std_ports - initialize ioaddr with standard port offsets. 2233 * @ioaddr: IO address structure to be initialized 2234 * 2235 * Utility function which initializes data_addr, error_addr, 2236 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, 2237 * device_addr, status_addr, and command_addr to standard offsets 2238 * relative to cmd_addr. 2239 * 2240 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. 2241 */ 2242 void ata_sff_std_ports(struct ata_ioports *ioaddr) 2243 { 2244 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; 2245 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; 2246 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; 2247 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; 2248 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; 2249 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; 2250 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; 2251 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; 2252 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; 2253 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; 2254 } 2255 EXPORT_SYMBOL_GPL(ata_sff_std_ports); 2256 2257 #ifdef CONFIG_PCI 2258 2259 static int ata_resources_present(struct pci_dev *pdev, int port) 2260 { 2261 int i; 2262 2263 /* Check the PCI resources for this channel are enabled */ 2264 port = port * 2; 2265 for (i = 0; i < 2; i++) { 2266 if (pci_resource_start(pdev, port + i) == 0 || 2267 pci_resource_len(pdev, port + i) == 0) 2268 return 0; 2269 } 2270 return 1; 2271 } 2272 2273 /** 2274 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host 2275 * @host: target ATA host 2276 * 2277 * Acquire native PCI ATA resources for @host and initialize the 2278 * first two ports of @host accordingly. Ports marked dummy are 2279 * skipped and allocation failure makes the port dummy. 2280 * 2281 * Note that native PCI resources are valid even for legacy hosts 2282 * as we fix up pdev resources array early in boot, so this 2283 * function can be used for both native and legacy SFF hosts. 2284 * 2285 * LOCKING: 2286 * Inherited from calling layer (may sleep). 2287 * 2288 * RETURNS: 2289 * 0 if at least one port is initialized, -ENODEV if no port is 2290 * available. 2291 */ 2292 int ata_pci_sff_init_host(struct ata_host *host) 2293 { 2294 struct device *gdev = host->dev; 2295 struct pci_dev *pdev = to_pci_dev(gdev); 2296 unsigned int mask = 0; 2297 int i, rc; 2298 2299 /* request, iomap BARs and init port addresses accordingly */ 2300 for (i = 0; i < 2; i++) { 2301 struct ata_port *ap = host->ports[i]; 2302 int base = i * 2; 2303 void __iomem * const *iomap; 2304 2305 if (ata_port_is_dummy(ap)) 2306 continue; 2307 2308 /* Discard disabled ports. Some controllers show 2309 * their unused channels this way. Disabled ports are 2310 * made dummy. 2311 */ 2312 if (!ata_resources_present(pdev, i)) { 2313 ap->ops = &ata_dummy_port_ops; 2314 continue; 2315 } 2316 2317 rc = pcim_iomap_regions(pdev, 0x3 << base, 2318 dev_driver_string(gdev)); 2319 if (rc) { 2320 dev_warn(gdev, 2321 "failed to request/iomap BARs for port %d (errno=%d)\n", 2322 i, rc); 2323 if (rc == -EBUSY) 2324 pcim_pin_device(pdev); 2325 ap->ops = &ata_dummy_port_ops; 2326 continue; 2327 } 2328 host->iomap = iomap = pcim_iomap_table(pdev); 2329 2330 ap->ioaddr.cmd_addr = iomap[base]; 2331 ap->ioaddr.altstatus_addr = 2332 ap->ioaddr.ctl_addr = (void __iomem *) 2333 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); 2334 ata_sff_std_ports(&ap->ioaddr); 2335 2336 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", 2337 (unsigned long long)pci_resource_start(pdev, base), 2338 (unsigned long long)pci_resource_start(pdev, base + 1)); 2339 2340 mask |= 1 << i; 2341 } 2342 2343 if (!mask) { 2344 dev_err(gdev, "no available native port\n"); 2345 return -ENODEV; 2346 } 2347 2348 return 0; 2349 } 2350 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); 2351 2352 /** 2353 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host 2354 * @pdev: target PCI device 2355 * @ppi: array of port_info, must be enough for two ports 2356 * @r_host: out argument for the initialized ATA host 2357 * 2358 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire 2359 * all PCI resources and initialize it accordingly in one go. 2360 * 2361 * LOCKING: 2362 * Inherited from calling layer (may sleep). 2363 * 2364 * RETURNS: 2365 * 0 on success, -errno otherwise. 2366 */ 2367 int ata_pci_sff_prepare_host(struct pci_dev *pdev, 2368 const struct ata_port_info * const *ppi, 2369 struct ata_host **r_host) 2370 { 2371 struct ata_host *host; 2372 int rc; 2373 2374 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) 2375 return -ENOMEM; 2376 2377 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 2378 if (!host) { 2379 dev_err(&pdev->dev, "failed to allocate ATA host\n"); 2380 rc = -ENOMEM; 2381 goto err_out; 2382 } 2383 2384 rc = ata_pci_sff_init_host(host); 2385 if (rc) 2386 goto err_out; 2387 2388 devres_remove_group(&pdev->dev, NULL); 2389 *r_host = host; 2390 return 0; 2391 2392 err_out: 2393 devres_release_group(&pdev->dev, NULL); 2394 return rc; 2395 } 2396 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); 2397 2398 /** 2399 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it 2400 * @host: target SFF ATA host 2401 * @irq_handler: irq_handler used when requesting IRQ(s) 2402 * @sht: scsi_host_template to use when registering the host 2403 * 2404 * This is the counterpart of ata_host_activate() for SFF ATA 2405 * hosts. This separate helper is necessary because SFF hosts 2406 * use two separate interrupts in legacy mode. 2407 * 2408 * LOCKING: 2409 * Inherited from calling layer (may sleep). 2410 * 2411 * RETURNS: 2412 * 0 on success, -errno otherwise. 2413 */ 2414 int ata_pci_sff_activate_host(struct ata_host *host, 2415 irq_handler_t irq_handler, 2416 struct scsi_host_template *sht) 2417 { 2418 struct device *dev = host->dev; 2419 struct pci_dev *pdev = to_pci_dev(dev); 2420 const char *drv_name = dev_driver_string(host->dev); 2421 int legacy_mode = 0, rc; 2422 2423 rc = ata_host_start(host); 2424 if (rc) 2425 return rc; 2426 2427 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { 2428 u8 tmp8, mask; 2429 2430 /* TODO: What if one channel is in native mode ... */ 2431 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); 2432 mask = (1 << 2) | (1 << 0); 2433 if ((tmp8 & mask) != mask) 2434 legacy_mode = 1; 2435 #if defined(CONFIG_NO_ATA_LEGACY) 2436 /* Some platforms with PCI limits cannot address compat 2437 port space. In that case we punt if their firmware has 2438 left a device in compatibility mode */ 2439 if (legacy_mode) { 2440 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); 2441 return -EOPNOTSUPP; 2442 } 2443 #endif 2444 } 2445 2446 if (!devres_open_group(dev, NULL, GFP_KERNEL)) 2447 return -ENOMEM; 2448 2449 if (!legacy_mode && pdev->irq) { 2450 int i; 2451 2452 rc = devm_request_irq(dev, pdev->irq, irq_handler, 2453 IRQF_SHARED, drv_name, host); 2454 if (rc) 2455 goto out; 2456 2457 for (i = 0; i < 2; i++) { 2458 if (ata_port_is_dummy(host->ports[i])) 2459 continue; 2460 ata_port_desc(host->ports[i], "irq %d", pdev->irq); 2461 } 2462 } else if (legacy_mode) { 2463 if (!ata_port_is_dummy(host->ports[0])) { 2464 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), 2465 irq_handler, IRQF_SHARED, 2466 drv_name, host); 2467 if (rc) 2468 goto out; 2469 2470 ata_port_desc(host->ports[0], "irq %d", 2471 ATA_PRIMARY_IRQ(pdev)); 2472 } 2473 2474 if (!ata_port_is_dummy(host->ports[1])) { 2475 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), 2476 irq_handler, IRQF_SHARED, 2477 drv_name, host); 2478 if (rc) 2479 goto out; 2480 2481 ata_port_desc(host->ports[1], "irq %d", 2482 ATA_SECONDARY_IRQ(pdev)); 2483 } 2484 } 2485 2486 rc = ata_host_register(host, sht); 2487 out: 2488 if (rc == 0) 2489 devres_remove_group(dev, NULL); 2490 else 2491 devres_release_group(dev, NULL); 2492 2493 return rc; 2494 } 2495 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); 2496 2497 static const struct ata_port_info *ata_sff_find_valid_pi( 2498 const struct ata_port_info * const *ppi) 2499 { 2500 int i; 2501 2502 /* look up the first valid port_info */ 2503 for (i = 0; i < 2 && ppi[i]; i++) 2504 if (ppi[i]->port_ops != &ata_dummy_port_ops) 2505 return ppi[i]; 2506 2507 return NULL; 2508 } 2509 2510 static int ata_pci_init_one(struct pci_dev *pdev, 2511 const struct ata_port_info * const *ppi, 2512 struct scsi_host_template *sht, void *host_priv, 2513 int hflags, bool bmdma) 2514 { 2515 struct device *dev = &pdev->dev; 2516 const struct ata_port_info *pi; 2517 struct ata_host *host = NULL; 2518 int rc; 2519 2520 DPRINTK("ENTER\n"); 2521 2522 pi = ata_sff_find_valid_pi(ppi); 2523 if (!pi) { 2524 dev_err(&pdev->dev, "no valid port_info specified\n"); 2525 return -EINVAL; 2526 } 2527 2528 if (!devres_open_group(dev, NULL, GFP_KERNEL)) 2529 return -ENOMEM; 2530 2531 rc = pcim_enable_device(pdev); 2532 if (rc) 2533 goto out; 2534 2535 if (bmdma) 2536 /* prepare and activate BMDMA host */ 2537 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); 2538 else 2539 /* prepare and activate SFF host */ 2540 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 2541 if (rc) 2542 goto out; 2543 host->private_data = host_priv; 2544 host->flags |= hflags; 2545 2546 if (bmdma) { 2547 pci_set_master(pdev); 2548 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); 2549 } else 2550 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); 2551 out: 2552 if (rc == 0) 2553 devres_remove_group(&pdev->dev, NULL); 2554 else 2555 devres_release_group(&pdev->dev, NULL); 2556 2557 return rc; 2558 } 2559 2560 /** 2561 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller 2562 * @pdev: Controller to be initialized 2563 * @ppi: array of port_info, must be enough for two ports 2564 * @sht: scsi_host_template to use when registering the host 2565 * @host_priv: host private_data 2566 * @hflag: host flags 2567 * 2568 * This is a helper function which can be called from a driver's 2569 * xxx_init_one() probe function if the hardware uses traditional 2570 * IDE taskfile registers and is PIO only. 2571 * 2572 * ASSUMPTION: 2573 * Nobody makes a single channel controller that appears solely as 2574 * the secondary legacy port on PCI. 2575 * 2576 * LOCKING: 2577 * Inherited from PCI layer (may sleep). 2578 * 2579 * RETURNS: 2580 * Zero on success, negative on errno-based value on error. 2581 */ 2582 int ata_pci_sff_init_one(struct pci_dev *pdev, 2583 const struct ata_port_info * const *ppi, 2584 struct scsi_host_template *sht, void *host_priv, int hflag) 2585 { 2586 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0); 2587 } 2588 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); 2589 2590 #endif /* CONFIG_PCI */ 2591 2592 /* 2593 * BMDMA support 2594 */ 2595 2596 #ifdef CONFIG_ATA_BMDMA 2597 2598 const struct ata_port_operations ata_bmdma_port_ops = { 2599 .inherits = &ata_sff_port_ops, 2600 2601 .error_handler = ata_bmdma_error_handler, 2602 .post_internal_cmd = ata_bmdma_post_internal_cmd, 2603 2604 .qc_prep = ata_bmdma_qc_prep, 2605 .qc_issue = ata_bmdma_qc_issue, 2606 2607 .sff_irq_clear = ata_bmdma_irq_clear, 2608 .bmdma_setup = ata_bmdma_setup, 2609 .bmdma_start = ata_bmdma_start, 2610 .bmdma_stop = ata_bmdma_stop, 2611 .bmdma_status = ata_bmdma_status, 2612 2613 .port_start = ata_bmdma_port_start, 2614 }; 2615 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); 2616 2617 const struct ata_port_operations ata_bmdma32_port_ops = { 2618 .inherits = &ata_bmdma_port_ops, 2619 2620 .sff_data_xfer = ata_sff_data_xfer32, 2621 .port_start = ata_bmdma_port_start32, 2622 }; 2623 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops); 2624 2625 /** 2626 * ata_bmdma_fill_sg - Fill PCI IDE PRD table 2627 * @qc: Metadata associated with taskfile to be transferred 2628 * 2629 * Fill PCI IDE PRD (scatter-gather) table with segments 2630 * associated with the current disk command. 2631 * 2632 * LOCKING: 2633 * spin_lock_irqsave(host lock) 2634 * 2635 */ 2636 static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc) 2637 { 2638 struct ata_port *ap = qc->ap; 2639 struct ata_bmdma_prd *prd = ap->bmdma_prd; 2640 struct scatterlist *sg; 2641 unsigned int si, pi; 2642 2643 pi = 0; 2644 for_each_sg(qc->sg, sg, qc->n_elem, si) { 2645 u32 addr, offset; 2646 u32 sg_len, len; 2647 2648 /* determine if physical DMA addr spans 64K boundary. 2649 * Note h/w doesn't support 64-bit, so we unconditionally 2650 * truncate dma_addr_t to u32. 2651 */ 2652 addr = (u32) sg_dma_address(sg); 2653 sg_len = sg_dma_len(sg); 2654 2655 while (sg_len) { 2656 offset = addr & 0xffff; 2657 len = sg_len; 2658 if ((offset + sg_len) > 0x10000) 2659 len = 0x10000 - offset; 2660 2661 prd[pi].addr = cpu_to_le32(addr); 2662 prd[pi].flags_len = cpu_to_le32(len & 0xffff); 2663 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); 2664 2665 pi++; 2666 sg_len -= len; 2667 addr += len; 2668 } 2669 } 2670 2671 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 2672 } 2673 2674 /** 2675 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table 2676 * @qc: Metadata associated with taskfile to be transferred 2677 * 2678 * Fill PCI IDE PRD (scatter-gather) table with segments 2679 * associated with the current disk command. Perform the fill 2680 * so that we avoid writing any length 64K records for 2681 * controllers that don't follow the spec. 2682 * 2683 * LOCKING: 2684 * spin_lock_irqsave(host lock) 2685 * 2686 */ 2687 static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc) 2688 { 2689 struct ata_port *ap = qc->ap; 2690 struct ata_bmdma_prd *prd = ap->bmdma_prd; 2691 struct scatterlist *sg; 2692 unsigned int si, pi; 2693 2694 pi = 0; 2695 for_each_sg(qc->sg, sg, qc->n_elem, si) { 2696 u32 addr, offset; 2697 u32 sg_len, len, blen; 2698 2699 /* determine if physical DMA addr spans 64K boundary. 2700 * Note h/w doesn't support 64-bit, so we unconditionally 2701 * truncate dma_addr_t to u32. 2702 */ 2703 addr = (u32) sg_dma_address(sg); 2704 sg_len = sg_dma_len(sg); 2705 2706 while (sg_len) { 2707 offset = addr & 0xffff; 2708 len = sg_len; 2709 if ((offset + sg_len) > 0x10000) 2710 len = 0x10000 - offset; 2711 2712 blen = len & 0xffff; 2713 prd[pi].addr = cpu_to_le32(addr); 2714 if (blen == 0) { 2715 /* Some PATA chipsets like the CS5530 can't 2716 cope with 0x0000 meaning 64K as the spec 2717 says */ 2718 prd[pi].flags_len = cpu_to_le32(0x8000); 2719 blen = 0x8000; 2720 prd[++pi].addr = cpu_to_le32(addr + 0x8000); 2721 } 2722 prd[pi].flags_len = cpu_to_le32(blen); 2723 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); 2724 2725 pi++; 2726 sg_len -= len; 2727 addr += len; 2728 } 2729 } 2730 2731 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); 2732 } 2733 2734 /** 2735 * ata_bmdma_qc_prep - Prepare taskfile for submission 2736 * @qc: Metadata associated with taskfile to be prepared 2737 * 2738 * Prepare ATA taskfile for submission. 2739 * 2740 * LOCKING: 2741 * spin_lock_irqsave(host lock) 2742 */ 2743 void ata_bmdma_qc_prep(struct ata_queued_cmd *qc) 2744 { 2745 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2746 return; 2747 2748 ata_bmdma_fill_sg(qc); 2749 } 2750 EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep); 2751 2752 /** 2753 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission 2754 * @qc: Metadata associated with taskfile to be prepared 2755 * 2756 * Prepare ATA taskfile for submission. 2757 * 2758 * LOCKING: 2759 * spin_lock_irqsave(host lock) 2760 */ 2761 void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc) 2762 { 2763 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) 2764 return; 2765 2766 ata_bmdma_fill_sg_dumb(qc); 2767 } 2768 EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep); 2769 2770 /** 2771 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller 2772 * @qc: command to issue to device 2773 * 2774 * This function issues a PIO, NODATA or DMA command to a 2775 * SFF/BMDMA controller. PIO and NODATA are handled by 2776 * ata_sff_qc_issue(). 2777 * 2778 * LOCKING: 2779 * spin_lock_irqsave(host lock) 2780 * 2781 * RETURNS: 2782 * Zero on success, AC_ERR_* mask on failure 2783 */ 2784 unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc) 2785 { 2786 struct ata_port *ap = qc->ap; 2787 struct ata_link *link = qc->dev->link; 2788 2789 /* defer PIO handling to sff_qc_issue */ 2790 if (!ata_is_dma(qc->tf.protocol)) 2791 return ata_sff_qc_issue(qc); 2792 2793 /* select the device */ 2794 ata_dev_select(ap, qc->dev->devno, 1, 0); 2795 2796 /* start the command */ 2797 switch (qc->tf.protocol) { 2798 case ATA_PROT_DMA: 2799 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); 2800 2801 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ 2802 ap->ops->bmdma_setup(qc); /* set up bmdma */ 2803 ap->ops->bmdma_start(qc); /* initiate bmdma */ 2804 ap->hsm_task_state = HSM_ST_LAST; 2805 break; 2806 2807 case ATAPI_PROT_DMA: 2808 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); 2809 2810 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ 2811 ap->ops->bmdma_setup(qc); /* set up bmdma */ 2812 ap->hsm_task_state = HSM_ST_FIRST; 2813 2814 /* send cdb by polling if no cdb interrupt */ 2815 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 2816 ata_sff_queue_pio_task(link, 0); 2817 break; 2818 2819 default: 2820 WARN_ON(1); 2821 return AC_ERR_SYSTEM; 2822 } 2823 2824 return 0; 2825 } 2826 EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue); 2827 2828 /** 2829 * ata_bmdma_port_intr - Handle BMDMA port interrupt 2830 * @ap: Port on which interrupt arrived (possibly...) 2831 * @qc: Taskfile currently active in engine 2832 * 2833 * Handle port interrupt for given queued command. 2834 * 2835 * LOCKING: 2836 * spin_lock_irqsave(host lock) 2837 * 2838 * RETURNS: 2839 * One if interrupt was handled, zero if not (shared irq). 2840 */ 2841 unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) 2842 { 2843 struct ata_eh_info *ehi = &ap->link.eh_info; 2844 u8 host_stat = 0; 2845 bool bmdma_stopped = false; 2846 unsigned int handled; 2847 2848 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) { 2849 /* check status of DMA engine */ 2850 host_stat = ap->ops->bmdma_status(ap); 2851 VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat); 2852 2853 /* if it's not our irq... */ 2854 if (!(host_stat & ATA_DMA_INTR)) 2855 return ata_sff_idle_irq(ap); 2856 2857 /* before we do anything else, clear DMA-Start bit */ 2858 ap->ops->bmdma_stop(qc); 2859 bmdma_stopped = true; 2860 2861 if (unlikely(host_stat & ATA_DMA_ERR)) { 2862 /* error when transferring data to/from memory */ 2863 qc->err_mask |= AC_ERR_HOST_BUS; 2864 ap->hsm_task_state = HSM_ST_ERR; 2865 } 2866 } 2867 2868 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped); 2869 2870 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) 2871 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); 2872 2873 return handled; 2874 } 2875 EXPORT_SYMBOL_GPL(ata_bmdma_port_intr); 2876 2877 /** 2878 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler 2879 * @irq: irq line (unused) 2880 * @dev_instance: pointer to our ata_host information structure 2881 * 2882 * Default interrupt handler for PCI IDE devices. Calls 2883 * ata_bmdma_port_intr() for each port that is not disabled. 2884 * 2885 * LOCKING: 2886 * Obtains host lock during operation. 2887 * 2888 * RETURNS: 2889 * IRQ_NONE or IRQ_HANDLED. 2890 */ 2891 irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance) 2892 { 2893 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr); 2894 } 2895 EXPORT_SYMBOL_GPL(ata_bmdma_interrupt); 2896 2897 /** 2898 * ata_bmdma_error_handler - Stock error handler for BMDMA controller 2899 * @ap: port to handle error for 2900 * 2901 * Stock error handler for BMDMA controller. It can handle both 2902 * PATA and SATA controllers. Most BMDMA controllers should be 2903 * able to use this EH as-is or with some added handling before 2904 * and after. 2905 * 2906 * LOCKING: 2907 * Kernel thread context (may sleep) 2908 */ 2909 void ata_bmdma_error_handler(struct ata_port *ap) 2910 { 2911 struct ata_queued_cmd *qc; 2912 unsigned long flags; 2913 bool thaw = false; 2914 2915 qc = __ata_qc_from_tag(ap, ap->link.active_tag); 2916 if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) 2917 qc = NULL; 2918 2919 /* reset PIO HSM and stop DMA engine */ 2920 spin_lock_irqsave(ap->lock, flags); 2921 2922 if (qc && ata_is_dma(qc->tf.protocol)) { 2923 u8 host_stat; 2924 2925 host_stat = ap->ops->bmdma_status(ap); 2926 2927 /* BMDMA controllers indicate host bus error by 2928 * setting DMA_ERR bit and timing out. As it wasn't 2929 * really a timeout event, adjust error mask and 2930 * cancel frozen state. 2931 */ 2932 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { 2933 qc->err_mask = AC_ERR_HOST_BUS; 2934 thaw = true; 2935 } 2936 2937 ap->ops->bmdma_stop(qc); 2938 2939 /* if we're gonna thaw, make sure IRQ is clear */ 2940 if (thaw) { 2941 ap->ops->sff_check_status(ap); 2942 if (ap->ops->sff_irq_clear) 2943 ap->ops->sff_irq_clear(ap); 2944 } 2945 } 2946 2947 spin_unlock_irqrestore(ap->lock, flags); 2948 2949 if (thaw) 2950 ata_eh_thaw_port(ap); 2951 2952 ata_sff_error_handler(ap); 2953 } 2954 EXPORT_SYMBOL_GPL(ata_bmdma_error_handler); 2955 2956 /** 2957 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA 2958 * @qc: internal command to clean up 2959 * 2960 * LOCKING: 2961 * Kernel thread context (may sleep) 2962 */ 2963 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) 2964 { 2965 struct ata_port *ap = qc->ap; 2966 unsigned long flags; 2967 2968 if (ata_is_dma(qc->tf.protocol)) { 2969 spin_lock_irqsave(ap->lock, flags); 2970 ap->ops->bmdma_stop(qc); 2971 spin_unlock_irqrestore(ap->lock, flags); 2972 } 2973 } 2974 EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd); 2975 2976 /** 2977 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. 2978 * @ap: Port associated with this ATA transaction. 2979 * 2980 * Clear interrupt and error flags in DMA status register. 2981 * 2982 * May be used as the irq_clear() entry in ata_port_operations. 2983 * 2984 * LOCKING: 2985 * spin_lock_irqsave(host lock) 2986 */ 2987 void ata_bmdma_irq_clear(struct ata_port *ap) 2988 { 2989 void __iomem *mmio = ap->ioaddr.bmdma_addr; 2990 2991 if (!mmio) 2992 return; 2993 2994 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); 2995 } 2996 EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear); 2997 2998 /** 2999 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction 3000 * @qc: Info associated with this ATA transaction. 3001 * 3002 * LOCKING: 3003 * spin_lock_irqsave(host lock) 3004 */ 3005 void ata_bmdma_setup(struct ata_queued_cmd *qc) 3006 { 3007 struct ata_port *ap = qc->ap; 3008 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 3009 u8 dmactl; 3010 3011 /* load PRD table addr. */ 3012 mb(); /* make sure PRD table writes are visible to controller */ 3013 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); 3014 3015 /* specify data direction, triple-check start bit is clear */ 3016 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 3017 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); 3018 if (!rw) 3019 dmactl |= ATA_DMA_WR; 3020 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 3021 3022 /* issue r/w command */ 3023 ap->ops->sff_exec_command(ap, &qc->tf); 3024 } 3025 EXPORT_SYMBOL_GPL(ata_bmdma_setup); 3026 3027 /** 3028 * ata_bmdma_start - Start a PCI IDE BMDMA transaction 3029 * @qc: Info associated with this ATA transaction. 3030 * 3031 * LOCKING: 3032 * spin_lock_irqsave(host lock) 3033 */ 3034 void ata_bmdma_start(struct ata_queued_cmd *qc) 3035 { 3036 struct ata_port *ap = qc->ap; 3037 u8 dmactl; 3038 3039 /* start host DMA transaction */ 3040 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 3041 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 3042 3043 /* Strictly, one may wish to issue an ioread8() here, to 3044 * flush the mmio write. However, control also passes 3045 * to the hardware at this point, and it will interrupt 3046 * us when we are to resume control. So, in effect, 3047 * we don't care when the mmio write flushes. 3048 * Further, a read of the DMA status register _immediately_ 3049 * following the write may not be what certain flaky hardware 3050 * is expected, so I think it is best to not add a readb() 3051 * without first all the MMIO ATA cards/mobos. 3052 * Or maybe I'm just being paranoid. 3053 * 3054 * FIXME: The posting of this write means I/O starts are 3055 * unnecessarily delayed for MMIO 3056 */ 3057 } 3058 EXPORT_SYMBOL_GPL(ata_bmdma_start); 3059 3060 /** 3061 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer 3062 * @qc: Command we are ending DMA for 3063 * 3064 * Clears the ATA_DMA_START flag in the dma control register 3065 * 3066 * May be used as the bmdma_stop() entry in ata_port_operations. 3067 * 3068 * LOCKING: 3069 * spin_lock_irqsave(host lock) 3070 */ 3071 void ata_bmdma_stop(struct ata_queued_cmd *qc) 3072 { 3073 struct ata_port *ap = qc->ap; 3074 void __iomem *mmio = ap->ioaddr.bmdma_addr; 3075 3076 /* clear start/stop bit */ 3077 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, 3078 mmio + ATA_DMA_CMD); 3079 3080 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 3081 ata_sff_dma_pause(ap); 3082 } 3083 EXPORT_SYMBOL_GPL(ata_bmdma_stop); 3084 3085 /** 3086 * ata_bmdma_status - Read PCI IDE BMDMA status 3087 * @ap: Port associated with this ATA transaction. 3088 * 3089 * Read and return BMDMA status register. 3090 * 3091 * May be used as the bmdma_status() entry in ata_port_operations. 3092 * 3093 * LOCKING: 3094 * spin_lock_irqsave(host lock) 3095 */ 3096 u8 ata_bmdma_status(struct ata_port *ap) 3097 { 3098 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 3099 } 3100 EXPORT_SYMBOL_GPL(ata_bmdma_status); 3101 3102 3103 /** 3104 * ata_bmdma_port_start - Set port up for bmdma. 3105 * @ap: Port to initialize 3106 * 3107 * Called just after data structures for each port are 3108 * initialized. Allocates space for PRD table. 3109 * 3110 * May be used as the port_start() entry in ata_port_operations. 3111 * 3112 * LOCKING: 3113 * Inherited from caller. 3114 */ 3115 int ata_bmdma_port_start(struct ata_port *ap) 3116 { 3117 if (ap->mwdma_mask || ap->udma_mask) { 3118 ap->bmdma_prd = 3119 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ, 3120 &ap->bmdma_prd_dma, GFP_KERNEL); 3121 if (!ap->bmdma_prd) 3122 return -ENOMEM; 3123 } 3124 3125 return 0; 3126 } 3127 EXPORT_SYMBOL_GPL(ata_bmdma_port_start); 3128 3129 /** 3130 * ata_bmdma_port_start32 - Set port up for dma. 3131 * @ap: Port to initialize 3132 * 3133 * Called just after data structures for each port are 3134 * initialized. Enables 32bit PIO and allocates space for PRD 3135 * table. 3136 * 3137 * May be used as the port_start() entry in ata_port_operations for 3138 * devices that are capable of 32bit PIO. 3139 * 3140 * LOCKING: 3141 * Inherited from caller. 3142 */ 3143 int ata_bmdma_port_start32(struct ata_port *ap) 3144 { 3145 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; 3146 return ata_bmdma_port_start(ap); 3147 } 3148 EXPORT_SYMBOL_GPL(ata_bmdma_port_start32); 3149 3150 #ifdef CONFIG_PCI 3151 3152 /** 3153 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex 3154 * @pdev: PCI device 3155 * 3156 * Some PCI ATA devices report simplex mode but in fact can be told to 3157 * enter non simplex mode. This implements the necessary logic to 3158 * perform the task on such devices. Calling it on other devices will 3159 * have -undefined- behaviour. 3160 */ 3161 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) 3162 { 3163 unsigned long bmdma = pci_resource_start(pdev, 4); 3164 u8 simplex; 3165 3166 if (bmdma == 0) 3167 return -ENOENT; 3168 3169 simplex = inb(bmdma + 0x02); 3170 outb(simplex & 0x60, bmdma + 0x02); 3171 simplex = inb(bmdma + 0x02); 3172 if (simplex & 0x80) 3173 return -EOPNOTSUPP; 3174 return 0; 3175 } 3176 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); 3177 3178 static void ata_bmdma_nodma(struct ata_host *host, const char *reason) 3179 { 3180 int i; 3181 3182 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason); 3183 3184 for (i = 0; i < 2; i++) { 3185 host->ports[i]->mwdma_mask = 0; 3186 host->ports[i]->udma_mask = 0; 3187 } 3188 } 3189 3190 /** 3191 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host 3192 * @host: target ATA host 3193 * 3194 * Acquire PCI BMDMA resources and initialize @host accordingly. 3195 * 3196 * LOCKING: 3197 * Inherited from calling layer (may sleep). 3198 */ 3199 void ata_pci_bmdma_init(struct ata_host *host) 3200 { 3201 struct device *gdev = host->dev; 3202 struct pci_dev *pdev = to_pci_dev(gdev); 3203 int i, rc; 3204 3205 /* No BAR4 allocation: No DMA */ 3206 if (pci_resource_start(pdev, 4) == 0) { 3207 ata_bmdma_nodma(host, "BAR4 is zero"); 3208 return; 3209 } 3210 3211 /* 3212 * Some controllers require BMDMA region to be initialized 3213 * even if DMA is not in use to clear IRQ status via 3214 * ->sff_irq_clear method. Try to initialize bmdma_addr 3215 * regardless of dma masks. 3216 */ 3217 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 3218 if (rc) 3219 ata_bmdma_nodma(host, "failed to set dma mask"); 3220 if (!rc) { 3221 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 3222 if (rc) 3223 ata_bmdma_nodma(host, 3224 "failed to set consistent dma mask"); 3225 } 3226 3227 /* request and iomap DMA region */ 3228 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); 3229 if (rc) { 3230 ata_bmdma_nodma(host, "failed to request/iomap BAR4"); 3231 return; 3232 } 3233 host->iomap = pcim_iomap_table(pdev); 3234 3235 for (i = 0; i < 2; i++) { 3236 struct ata_port *ap = host->ports[i]; 3237 void __iomem *bmdma = host->iomap[4] + 8 * i; 3238 3239 if (ata_port_is_dummy(ap)) 3240 continue; 3241 3242 ap->ioaddr.bmdma_addr = bmdma; 3243 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && 3244 (ioread8(bmdma + 2) & 0x80)) 3245 host->flags |= ATA_HOST_SIMPLEX; 3246 3247 ata_port_desc(ap, "bmdma 0x%llx", 3248 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); 3249 } 3250 } 3251 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); 3252 3253 /** 3254 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host 3255 * @pdev: target PCI device 3256 * @ppi: array of port_info, must be enough for two ports 3257 * @r_host: out argument for the initialized ATA host 3258 * 3259 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI 3260 * resources and initialize it accordingly in one go. 3261 * 3262 * LOCKING: 3263 * Inherited from calling layer (may sleep). 3264 * 3265 * RETURNS: 3266 * 0 on success, -errno otherwise. 3267 */ 3268 int ata_pci_bmdma_prepare_host(struct pci_dev *pdev, 3269 const struct ata_port_info * const * ppi, 3270 struct ata_host **r_host) 3271 { 3272 int rc; 3273 3274 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host); 3275 if (rc) 3276 return rc; 3277 3278 ata_pci_bmdma_init(*r_host); 3279 return 0; 3280 } 3281 EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host); 3282 3283 /** 3284 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller 3285 * @pdev: Controller to be initialized 3286 * @ppi: array of port_info, must be enough for two ports 3287 * @sht: scsi_host_template to use when registering the host 3288 * @host_priv: host private_data 3289 * @hflags: host flags 3290 * 3291 * This function is similar to ata_pci_sff_init_one() but also 3292 * takes care of BMDMA initialization. 3293 * 3294 * LOCKING: 3295 * Inherited from PCI layer (may sleep). 3296 * 3297 * RETURNS: 3298 * Zero on success, negative on errno-based value on error. 3299 */ 3300 int ata_pci_bmdma_init_one(struct pci_dev *pdev, 3301 const struct ata_port_info * const * ppi, 3302 struct scsi_host_template *sht, void *host_priv, 3303 int hflags) 3304 { 3305 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1); 3306 } 3307 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one); 3308 3309 #endif /* CONFIG_PCI */ 3310 #endif /* CONFIG_ATA_BMDMA */ 3311 3312 /** 3313 * ata_sff_port_init - Initialize SFF/BMDMA ATA port 3314 * @ap: Port to initialize 3315 * 3316 * Called on port allocation to initialize SFF/BMDMA specific 3317 * fields. 3318 * 3319 * LOCKING: 3320 * None. 3321 */ 3322 void ata_sff_port_init(struct ata_port *ap) 3323 { 3324 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task); 3325 ap->ctl = ATA_DEVCTL_OBS; 3326 ap->last_ctl = 0xFF; 3327 } 3328 3329 int __init ata_sff_init(void) 3330 { 3331 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE); 3332 if (!ata_sff_wq) 3333 return -ENOMEM; 3334 3335 return 0; 3336 } 3337 3338 void ata_sff_exit(void) 3339 { 3340 destroy_workqueue(ata_sff_wq); 3341 } 3342