1 /* 2 * libata-bmdma.c - helper library for PCI IDE BMDMA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved. 9 * Copyright 2003-2006 Jeff Garzik 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * 27 * libata documentation is available via 'make {ps|pdf}docs', 28 * as Documentation/DocBook/libata.* 29 * 30 * Hardware documentation available from http://www.t13.org/ and 31 * http://www.sata-io.org/ 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/pci.h> 37 #include <linux/libata.h> 38 39 #include "libata.h" 40 41 /** 42 * ata_irq_on - Enable interrupts on a port. 43 * @ap: Port on which interrupts are enabled. 44 * 45 * Enable interrupts on a legacy IDE device using MMIO or PIO, 46 * wait for idle, clear any pending interrupts. 47 * 48 * LOCKING: 49 * Inherited from caller. 50 */ 51 u8 ata_irq_on(struct ata_port *ap) 52 { 53 struct ata_ioports *ioaddr = &ap->ioaddr; 54 u8 tmp; 55 56 ap->ctl &= ~ATA_NIEN; 57 ap->last_ctl = ap->ctl; 58 59 iowrite8(ap->ctl, ioaddr->ctl_addr); 60 tmp = ata_wait_idle(ap); 61 62 ap->ops->irq_clear(ap); 63 64 return tmp; 65 } 66 67 u8 ata_dummy_irq_on (struct ata_port *ap) { return 0; } 68 69 /** 70 * ata_irq_ack - Acknowledge a device interrupt. 71 * @ap: Port on which interrupts are enabled. 72 * 73 * Wait up to 10 ms for legacy IDE device to become idle (BUSY 74 * or BUSY+DRQ clear). Obtain dma status and port status from 75 * device. Clear the interrupt. Return port status. 76 * 77 * LOCKING: 78 */ 79 80 u8 ata_irq_ack(struct ata_port *ap, unsigned int chk_drq) 81 { 82 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY; 83 u8 host_stat, post_stat, status; 84 85 status = ata_busy_wait(ap, bits, 1000); 86 if (status & bits) 87 if (ata_msg_err(ap)) 88 printk(KERN_ERR "abnormal status 0x%X\n", status); 89 90 /* get controller status; clear intr, err bits */ 91 host_stat = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 92 iowrite8(host_stat | ATA_DMA_INTR | ATA_DMA_ERR, 93 ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 94 95 post_stat = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 96 97 if (ata_msg_intr(ap)) 98 printk(KERN_INFO "%s: irq ack: host_stat 0x%X, new host_stat 0x%X, drv_stat 0x%X\n", 99 __FUNCTION__, 100 host_stat, post_stat, status); 101 102 return status; 103 } 104 105 u8 ata_dummy_irq_ack(struct ata_port *ap, unsigned int chk_drq) { return 0; } 106 107 /** 108 * ata_tf_load - send taskfile registers to host controller 109 * @ap: Port to which output is sent 110 * @tf: ATA taskfile register set 111 * 112 * Outputs ATA taskfile to standard ATA host controller. 113 * 114 * LOCKING: 115 * Inherited from caller. 116 */ 117 118 void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) 119 { 120 struct ata_ioports *ioaddr = &ap->ioaddr; 121 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; 122 123 if (tf->ctl != ap->last_ctl) { 124 iowrite8(tf->ctl, ioaddr->ctl_addr); 125 ap->last_ctl = tf->ctl; 126 ata_wait_idle(ap); 127 } 128 129 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { 130 iowrite8(tf->hob_feature, ioaddr->feature_addr); 131 iowrite8(tf->hob_nsect, ioaddr->nsect_addr); 132 iowrite8(tf->hob_lbal, ioaddr->lbal_addr); 133 iowrite8(tf->hob_lbam, ioaddr->lbam_addr); 134 iowrite8(tf->hob_lbah, ioaddr->lbah_addr); 135 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", 136 tf->hob_feature, 137 tf->hob_nsect, 138 tf->hob_lbal, 139 tf->hob_lbam, 140 tf->hob_lbah); 141 } 142 143 if (is_addr) { 144 iowrite8(tf->feature, ioaddr->feature_addr); 145 iowrite8(tf->nsect, ioaddr->nsect_addr); 146 iowrite8(tf->lbal, ioaddr->lbal_addr); 147 iowrite8(tf->lbam, ioaddr->lbam_addr); 148 iowrite8(tf->lbah, ioaddr->lbah_addr); 149 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", 150 tf->feature, 151 tf->nsect, 152 tf->lbal, 153 tf->lbam, 154 tf->lbah); 155 } 156 157 if (tf->flags & ATA_TFLAG_DEVICE) { 158 iowrite8(tf->device, ioaddr->device_addr); 159 VPRINTK("device 0x%X\n", tf->device); 160 } 161 162 ata_wait_idle(ap); 163 } 164 165 /** 166 * ata_exec_command - issue ATA command to host controller 167 * @ap: port to which command is being issued 168 * @tf: ATA taskfile register set 169 * 170 * Issues ATA command, with proper synchronization with interrupt 171 * handler / other threads. 172 * 173 * LOCKING: 174 * spin_lock_irqsave(host lock) 175 */ 176 void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) 177 { 178 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 179 180 iowrite8(tf->command, ap->ioaddr.command_addr); 181 ata_pause(ap); 182 } 183 184 /** 185 * ata_tf_read - input device's ATA taskfile shadow registers 186 * @ap: Port from which input is read 187 * @tf: ATA taskfile register set for storing input 188 * 189 * Reads ATA taskfile registers for currently-selected device 190 * into @tf. 191 * 192 * LOCKING: 193 * Inherited from caller. 194 */ 195 void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 196 { 197 struct ata_ioports *ioaddr = &ap->ioaddr; 198 199 tf->command = ata_check_status(ap); 200 tf->feature = ioread8(ioaddr->error_addr); 201 tf->nsect = ioread8(ioaddr->nsect_addr); 202 tf->lbal = ioread8(ioaddr->lbal_addr); 203 tf->lbam = ioread8(ioaddr->lbam_addr); 204 tf->lbah = ioread8(ioaddr->lbah_addr); 205 tf->device = ioread8(ioaddr->device_addr); 206 207 if (tf->flags & ATA_TFLAG_LBA48) { 208 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); 209 tf->hob_feature = ioread8(ioaddr->error_addr); 210 tf->hob_nsect = ioread8(ioaddr->nsect_addr); 211 tf->hob_lbal = ioread8(ioaddr->lbal_addr); 212 tf->hob_lbam = ioread8(ioaddr->lbam_addr); 213 tf->hob_lbah = ioread8(ioaddr->lbah_addr); 214 } 215 } 216 217 /** 218 * ata_check_status - Read device status reg & clear interrupt 219 * @ap: port where the device is 220 * 221 * Reads ATA taskfile status register for currently-selected device 222 * and return its value. This also clears pending interrupts 223 * from this device 224 * 225 * LOCKING: 226 * Inherited from caller. 227 */ 228 u8 ata_check_status(struct ata_port *ap) 229 { 230 return ioread8(ap->ioaddr.status_addr); 231 } 232 233 /** 234 * ata_altstatus - Read device alternate status reg 235 * @ap: port where the device is 236 * 237 * Reads ATA taskfile alternate status register for 238 * currently-selected device and return its value. 239 * 240 * Note: may NOT be used as the check_altstatus() entry in 241 * ata_port_operations. 242 * 243 * LOCKING: 244 * Inherited from caller. 245 */ 246 u8 ata_altstatus(struct ata_port *ap) 247 { 248 if (ap->ops->check_altstatus) 249 return ap->ops->check_altstatus(ap); 250 251 return ioread8(ap->ioaddr.altstatus_addr); 252 } 253 254 /** 255 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction 256 * @qc: Info associated with this ATA transaction. 257 * 258 * LOCKING: 259 * spin_lock_irqsave(host lock) 260 */ 261 void ata_bmdma_setup(struct ata_queued_cmd *qc) 262 { 263 struct ata_port *ap = qc->ap; 264 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); 265 u8 dmactl; 266 267 /* load PRD table addr. */ 268 mb(); /* make sure PRD table writes are visible to controller */ 269 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); 270 271 /* specify data direction, triple-check start bit is clear */ 272 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 273 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); 274 if (!rw) 275 dmactl |= ATA_DMA_WR; 276 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 277 278 /* issue r/w command */ 279 ap->ops->exec_command(ap, &qc->tf); 280 } 281 282 /** 283 * ata_bmdma_start - Start a PCI IDE BMDMA transaction 284 * @qc: Info associated with this ATA transaction. 285 * 286 * LOCKING: 287 * spin_lock_irqsave(host lock) 288 */ 289 void ata_bmdma_start (struct ata_queued_cmd *qc) 290 { 291 struct ata_port *ap = qc->ap; 292 u8 dmactl; 293 294 /* start host DMA transaction */ 295 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 296 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 297 298 /* Strictly, one may wish to issue a readb() here, to 299 * flush the mmio write. However, control also passes 300 * to the hardware at this point, and it will interrupt 301 * us when we are to resume control. So, in effect, 302 * we don't care when the mmio write flushes. 303 * Further, a read of the DMA status register _immediately_ 304 * following the write may not be what certain flaky hardware 305 * is expected, so I think it is best to not add a readb() 306 * without first all the MMIO ATA cards/mobos. 307 * Or maybe I'm just being paranoid. 308 */ 309 } 310 311 /** 312 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. 313 * @ap: Port associated with this ATA transaction. 314 * 315 * Clear interrupt and error flags in DMA status register. 316 * 317 * May be used as the irq_clear() entry in ata_port_operations. 318 * 319 * LOCKING: 320 * spin_lock_irqsave(host lock) 321 */ 322 void ata_bmdma_irq_clear(struct ata_port *ap) 323 { 324 void __iomem *mmio = ap->ioaddr.bmdma_addr; 325 326 if (!mmio) 327 return; 328 329 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); 330 } 331 332 /** 333 * ata_bmdma_status - Read PCI IDE BMDMA status 334 * @ap: Port associated with this ATA transaction. 335 * 336 * Read and return BMDMA status register. 337 * 338 * May be used as the bmdma_status() entry in ata_port_operations. 339 * 340 * LOCKING: 341 * spin_lock_irqsave(host lock) 342 */ 343 u8 ata_bmdma_status(struct ata_port *ap) 344 { 345 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); 346 } 347 348 /** 349 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer 350 * @qc: Command we are ending DMA for 351 * 352 * Clears the ATA_DMA_START flag in the dma control register 353 * 354 * May be used as the bmdma_stop() entry in ata_port_operations. 355 * 356 * LOCKING: 357 * spin_lock_irqsave(host lock) 358 */ 359 void ata_bmdma_stop(struct ata_queued_cmd *qc) 360 { 361 struct ata_port *ap = qc->ap; 362 void __iomem *mmio = ap->ioaddr.bmdma_addr; 363 364 /* clear start/stop bit */ 365 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, 366 mmio + ATA_DMA_CMD); 367 368 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ 369 ata_altstatus(ap); /* dummy read */ 370 } 371 372 /** 373 * ata_bmdma_freeze - Freeze BMDMA controller port 374 * @ap: port to freeze 375 * 376 * Freeze BMDMA controller port. 377 * 378 * LOCKING: 379 * Inherited from caller. 380 */ 381 void ata_bmdma_freeze(struct ata_port *ap) 382 { 383 struct ata_ioports *ioaddr = &ap->ioaddr; 384 385 ap->ctl |= ATA_NIEN; 386 ap->last_ctl = ap->ctl; 387 388 iowrite8(ap->ctl, ioaddr->ctl_addr); 389 390 /* Under certain circumstances, some controllers raise IRQ on 391 * ATA_NIEN manipulation. Also, many controllers fail to mask 392 * previously pending IRQ on ATA_NIEN assertion. Clear it. 393 */ 394 ata_chk_status(ap); 395 396 ap->ops->irq_clear(ap); 397 } 398 399 /** 400 * ata_bmdma_thaw - Thaw BMDMA controller port 401 * @ap: port to thaw 402 * 403 * Thaw BMDMA controller port. 404 * 405 * LOCKING: 406 * Inherited from caller. 407 */ 408 void ata_bmdma_thaw(struct ata_port *ap) 409 { 410 /* clear & re-enable interrupts */ 411 ata_chk_status(ap); 412 ap->ops->irq_clear(ap); 413 ap->ops->irq_on(ap); 414 } 415 416 /** 417 * ata_bmdma_drive_eh - Perform EH with given methods for BMDMA controller 418 * @ap: port to handle error for 419 * @prereset: prereset method (can be NULL) 420 * @softreset: softreset method (can be NULL) 421 * @hardreset: hardreset method (can be NULL) 422 * @postreset: postreset method (can be NULL) 423 * 424 * Handle error for ATA BMDMA controller. It can handle both 425 * PATA and SATA controllers. Many controllers should be able to 426 * use this EH as-is or with some added handling before and 427 * after. 428 * 429 * This function is intended to be used for constructing 430 * ->error_handler callback by low level drivers. 431 * 432 * LOCKING: 433 * Kernel thread context (may sleep) 434 */ 435 void ata_bmdma_drive_eh(struct ata_port *ap, ata_prereset_fn_t prereset, 436 ata_reset_fn_t softreset, ata_reset_fn_t hardreset, 437 ata_postreset_fn_t postreset) 438 { 439 struct ata_queued_cmd *qc; 440 unsigned long flags; 441 int thaw = 0; 442 443 qc = __ata_qc_from_tag(ap, ap->active_tag); 444 if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) 445 qc = NULL; 446 447 /* reset PIO HSM and stop DMA engine */ 448 spin_lock_irqsave(ap->lock, flags); 449 450 ap->hsm_task_state = HSM_ST_IDLE; 451 452 if (qc && (qc->tf.protocol == ATA_PROT_DMA || 453 qc->tf.protocol == ATA_PROT_ATAPI_DMA)) { 454 u8 host_stat; 455 456 host_stat = ap->ops->bmdma_status(ap); 457 458 /* BMDMA controllers indicate host bus error by 459 * setting DMA_ERR bit and timing out. As it wasn't 460 * really a timeout event, adjust error mask and 461 * cancel frozen state. 462 */ 463 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { 464 qc->err_mask = AC_ERR_HOST_BUS; 465 thaw = 1; 466 } 467 468 ap->ops->bmdma_stop(qc); 469 } 470 471 ata_altstatus(ap); 472 ata_chk_status(ap); 473 ap->ops->irq_clear(ap); 474 475 spin_unlock_irqrestore(ap->lock, flags); 476 477 if (thaw) 478 ata_eh_thaw_port(ap); 479 480 /* PIO and DMA engines have been stopped, perform recovery */ 481 ata_do_eh(ap, prereset, softreset, hardreset, postreset); 482 } 483 484 /** 485 * ata_bmdma_error_handler - Stock error handler for BMDMA controller 486 * @ap: port to handle error for 487 * 488 * Stock error handler for BMDMA controller. 489 * 490 * LOCKING: 491 * Kernel thread context (may sleep) 492 */ 493 void ata_bmdma_error_handler(struct ata_port *ap) 494 { 495 ata_reset_fn_t hardreset; 496 497 hardreset = NULL; 498 if (sata_scr_valid(ap)) 499 hardreset = sata_std_hardreset; 500 501 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, 502 ata_std_postreset); 503 } 504 505 /** 506 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for 507 * BMDMA controller 508 * @qc: internal command to clean up 509 * 510 * LOCKING: 511 * Kernel thread context (may sleep) 512 */ 513 void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) 514 { 515 if (qc->ap->ioaddr.bmdma_addr) 516 ata_bmdma_stop(qc); 517 } 518 519 #ifdef CONFIG_PCI 520 521 static int ata_resources_present(struct pci_dev *pdev, int port) 522 { 523 int i; 524 525 /* Check the PCI resources for this channel are enabled */ 526 port = port * 2; 527 for (i = 0; i < 2; i ++) { 528 if (pci_resource_start(pdev, port + i) == 0 || 529 pci_resource_len(pdev, port + i) == 0) 530 return 0; 531 } 532 return 1; 533 } 534 535 /** 536 * ata_pci_init_native_mode - Initialize native-mode driver 537 * @pdev: pci device to be initialized 538 * @port: array[2] of pointers to port info structures. 539 * @ports: bitmap of ports present 540 * 541 * Utility function which allocates and initializes an 542 * ata_probe_ent structure for a standard dual-port 543 * PIO-based IDE controller. The returned ata_probe_ent 544 * structure can be passed to ata_device_add(). The returned 545 * ata_probe_ent structure should then be freed with kfree(). 546 * 547 * The caller need only pass the address of the primary port, the 548 * secondary will be deduced automatically. If the device has non 549 * standard secondary port mappings this function can be called twice, 550 * once for each interface. 551 */ 552 553 struct ata_probe_ent * 554 ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports) 555 { 556 struct ata_probe_ent *probe_ent; 557 int i, p = 0; 558 void __iomem * const *iomap; 559 560 /* iomap BARs */ 561 for (i = 0; i < 4; i++) { 562 if (pcim_iomap(pdev, i, 0) == NULL) { 563 dev_printk(KERN_ERR, &pdev->dev, 564 "failed to iomap PCI BAR %d\n", i); 565 return NULL; 566 } 567 } 568 569 pcim_iomap(pdev, 4, 0); /* may fail */ 570 iomap = pcim_iomap_table(pdev); 571 572 /* alloc and init probe_ent */ 573 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); 574 if (!probe_ent) 575 return NULL; 576 577 probe_ent->irq = pdev->irq; 578 probe_ent->irq_flags = IRQF_SHARED; 579 580 /* Discard disabled ports. Some controllers show their 581 unused channels this way */ 582 if (ata_resources_present(pdev, 0) == 0) 583 ports &= ~ATA_PORT_PRIMARY; 584 if (ata_resources_present(pdev, 1) == 0) 585 ports &= ~ATA_PORT_SECONDARY; 586 587 if (ports & ATA_PORT_PRIMARY) { 588 probe_ent->port[p].cmd_addr = iomap[0]; 589 probe_ent->port[p].altstatus_addr = 590 probe_ent->port[p].ctl_addr = (void __iomem *) 591 ((unsigned long)iomap[1] | ATA_PCI_CTL_OFS); 592 if (iomap[4]) { 593 if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && 594 (ioread8(iomap[4] + 2) & 0x80)) 595 probe_ent->_host_flags |= ATA_HOST_SIMPLEX; 596 probe_ent->port[p].bmdma_addr = iomap[4]; 597 } 598 ata_std_ports(&probe_ent->port[p]); 599 p++; 600 } 601 602 if (ports & ATA_PORT_SECONDARY) { 603 probe_ent->port[p].cmd_addr = iomap[2]; 604 probe_ent->port[p].altstatus_addr = 605 probe_ent->port[p].ctl_addr = (void __iomem *) 606 ((unsigned long)iomap[3] | ATA_PCI_CTL_OFS); 607 if (iomap[4]) { 608 if ((!(port[p]->flags & ATA_FLAG_IGN_SIMPLEX)) && 609 (ioread8(iomap[4] + 10) & 0x80)) 610 probe_ent->_host_flags |= ATA_HOST_SIMPLEX; 611 probe_ent->port[p].bmdma_addr = iomap[4] + 8; 612 } 613 ata_std_ports(&probe_ent->port[p]); 614 probe_ent->pinfo2 = port[1]; 615 p++; 616 } 617 618 probe_ent->n_ports = p; 619 return probe_ent; 620 } 621 622 static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, 623 struct ata_port_info **port, int port_mask) 624 { 625 struct ata_probe_ent *probe_ent; 626 void __iomem *iomap[5] = { }, *bmdma; 627 628 if (port_mask & ATA_PORT_PRIMARY) { 629 iomap[0] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CMD, 8); 630 iomap[1] = devm_ioport_map(&pdev->dev, ATA_PRIMARY_CTL, 1); 631 if (!iomap[0] || !iomap[1]) 632 return NULL; 633 } 634 635 if (port_mask & ATA_PORT_SECONDARY) { 636 iomap[2] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CMD, 8); 637 iomap[3] = devm_ioport_map(&pdev->dev, ATA_SECONDARY_CTL, 1); 638 if (!iomap[2] || !iomap[3]) 639 return NULL; 640 } 641 642 bmdma = pcim_iomap(pdev, 4, 16); /* may fail */ 643 644 /* alloc and init probe_ent */ 645 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]); 646 if (!probe_ent) 647 return NULL; 648 649 probe_ent->n_ports = 2; 650 probe_ent->irq_flags = IRQF_SHARED; 651 652 if (port_mask & ATA_PORT_PRIMARY) { 653 probe_ent->irq = ATA_PRIMARY_IRQ(pdev); 654 probe_ent->port[0].cmd_addr = iomap[0]; 655 probe_ent->port[0].altstatus_addr = 656 probe_ent->port[0].ctl_addr = iomap[1]; 657 if (bmdma) { 658 probe_ent->port[0].bmdma_addr = bmdma; 659 if ((!(port[0]->flags & ATA_FLAG_IGN_SIMPLEX)) && 660 (ioread8(bmdma + 2) & 0x80)) 661 probe_ent->_host_flags |= ATA_HOST_SIMPLEX; 662 } 663 ata_std_ports(&probe_ent->port[0]); 664 } else 665 probe_ent->dummy_port_mask |= ATA_PORT_PRIMARY; 666 667 if (port_mask & ATA_PORT_SECONDARY) { 668 if (probe_ent->irq) 669 probe_ent->irq2 = ATA_SECONDARY_IRQ(pdev); 670 else 671 probe_ent->irq = ATA_SECONDARY_IRQ(pdev); 672 probe_ent->port[1].cmd_addr = iomap[2]; 673 probe_ent->port[1].altstatus_addr = 674 probe_ent->port[1].ctl_addr = iomap[3]; 675 if (bmdma) { 676 probe_ent->port[1].bmdma_addr = bmdma + 8; 677 if ((!(port[1]->flags & ATA_FLAG_IGN_SIMPLEX)) && 678 (ioread8(bmdma + 10) & 0x80)) 679 probe_ent->_host_flags |= ATA_HOST_SIMPLEX; 680 } 681 ata_std_ports(&probe_ent->port[1]); 682 683 /* FIXME: could be pointing to stack area; must copy */ 684 probe_ent->pinfo2 = port[1]; 685 } else 686 probe_ent->dummy_port_mask |= ATA_PORT_SECONDARY; 687 688 return probe_ent; 689 } 690 691 692 /** 693 * ata_pci_init_one - Initialize/register PCI IDE host controller 694 * @pdev: Controller to be initialized 695 * @port_info: Information from low-level host driver 696 * @n_ports: Number of ports attached to host controller 697 * 698 * This is a helper function which can be called from a driver's 699 * xxx_init_one() probe function if the hardware uses traditional 700 * IDE taskfile registers. 701 * 702 * This function calls pci_enable_device(), reserves its register 703 * regions, sets the dma mask, enables bus master mode, and calls 704 * ata_device_add() 705 * 706 * ASSUMPTION: 707 * Nobody makes a single channel controller that appears solely as 708 * the secondary legacy port on PCI. 709 * 710 * LOCKING: 711 * Inherited from PCI layer (may sleep). 712 * 713 * RETURNS: 714 * Zero on success, negative on errno-based value on error. 715 */ 716 717 int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info, 718 unsigned int n_ports) 719 { 720 struct device *dev = &pdev->dev; 721 struct ata_probe_ent *probe_ent = NULL; 722 struct ata_port_info *port[2]; 723 u8 mask; 724 unsigned int legacy_mode = 0; 725 int rc; 726 727 DPRINTK("ENTER\n"); 728 729 if (!devres_open_group(dev, NULL, GFP_KERNEL)) 730 return -ENOMEM; 731 732 BUG_ON(n_ports < 1 || n_ports > 2); 733 734 port[0] = port_info[0]; 735 if (n_ports > 1) 736 port[1] = port_info[1]; 737 else 738 port[1] = port[0]; 739 740 /* FIXME: Really for ATA it isn't safe because the device may be 741 multi-purpose and we want to leave it alone if it was already 742 enabled. Secondly for shared use as Arjan says we want refcounting 743 744 Checking dev->is_enabled is insufficient as this is not set at 745 boot for the primary video which is BIOS enabled 746 */ 747 748 rc = pcim_enable_device(pdev); 749 if (rc) 750 goto err_out; 751 752 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { 753 u8 tmp8; 754 755 /* TODO: What if one channel is in native mode ... */ 756 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); 757 mask = (1 << 2) | (1 << 0); 758 if ((tmp8 & mask) != mask) 759 legacy_mode = (1 << 3); 760 #if defined(CONFIG_NO_ATA_LEGACY) 761 /* Some platforms with PCI limits cannot address compat 762 port space. In that case we punt if their firmware has 763 left a device in compatibility mode */ 764 if (legacy_mode) { 765 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); 766 rc = -EOPNOTSUPP; 767 goto err_out; 768 } 769 #endif 770 } 771 772 if (!legacy_mode) { 773 rc = pci_request_regions(pdev, DRV_NAME); 774 if (rc) { 775 pcim_pin_device(pdev); 776 goto err_out; 777 } 778 } else { 779 /* Deal with combined mode hack. This side of the logic all 780 goes away once the combined mode hack is killed in 2.6.21 */ 781 if (!devm_request_region(dev, ATA_PRIMARY_CMD, 8, "libata")) { 782 struct resource *conflict, res; 783 res.start = ATA_PRIMARY_CMD; 784 res.end = ATA_PRIMARY_CMD + 8 - 1; 785 conflict = ____request_resource(&ioport_resource, &res); 786 while (conflict->child) 787 conflict = ____request_resource(conflict, &res); 788 if (!strcmp(conflict->name, "libata")) 789 legacy_mode |= ATA_PORT_PRIMARY; 790 else { 791 pcim_pin_device(pdev); 792 printk(KERN_WARNING "ata: 0x%0X IDE port busy\n" \ 793 "ata: conflict with %s\n", 794 ATA_PRIMARY_CMD, 795 conflict->name); 796 } 797 } else 798 legacy_mode |= ATA_PORT_PRIMARY; 799 800 if (!devm_request_region(dev, ATA_SECONDARY_CMD, 8, "libata")) { 801 struct resource *conflict, res; 802 res.start = ATA_SECONDARY_CMD; 803 res.end = ATA_SECONDARY_CMD + 8 - 1; 804 conflict = ____request_resource(&ioport_resource, &res); 805 while (conflict->child) 806 conflict = ____request_resource(conflict, &res); 807 if (!strcmp(conflict->name, "libata")) 808 legacy_mode |= ATA_PORT_SECONDARY; 809 else { 810 pcim_pin_device(pdev); 811 printk(KERN_WARNING "ata: 0x%X IDE port busy\n" \ 812 "ata: conflict with %s\n", 813 ATA_SECONDARY_CMD, 814 conflict->name); 815 } 816 } else 817 legacy_mode |= ATA_PORT_SECONDARY; 818 819 if (legacy_mode & ATA_PORT_PRIMARY) 820 pci_request_region(pdev, 1, DRV_NAME); 821 if (legacy_mode & ATA_PORT_SECONDARY) 822 pci_request_region(pdev, 3, DRV_NAME); 823 /* If there is a DMA resource, allocate it */ 824 pci_request_region(pdev, 4, DRV_NAME); 825 } 826 827 /* we have legacy mode, but all ports are unavailable */ 828 if (legacy_mode == (1 << 3)) { 829 rc = -EBUSY; 830 goto err_out; 831 } 832 833 /* TODO: If we get no DMA mask we should fall back to PIO */ 834 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 835 if (rc) 836 goto err_out; 837 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 838 if (rc) 839 goto err_out; 840 841 if (legacy_mode) { 842 probe_ent = ata_pci_init_legacy_port(pdev, port, legacy_mode); 843 } else { 844 if (n_ports == 2) 845 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); 846 else 847 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY); 848 } 849 if (!probe_ent) { 850 rc = -ENOMEM; 851 goto err_out; 852 } 853 854 pci_set_master(pdev); 855 856 if (!ata_device_add(probe_ent)) { 857 rc = -ENODEV; 858 goto err_out; 859 } 860 861 devm_kfree(dev, probe_ent); 862 devres_remove_group(dev, NULL); 863 return 0; 864 865 err_out: 866 devres_release_group(dev, NULL); 867 return rc; 868 } 869 870 /** 871 * ata_pci_clear_simplex - attempt to kick device out of simplex 872 * @pdev: PCI device 873 * 874 * Some PCI ATA devices report simplex mode but in fact can be told to 875 * enter non simplex mode. This implements the neccessary logic to 876 * perform the task on such devices. Calling it on other devices will 877 * have -undefined- behaviour. 878 */ 879 880 int ata_pci_clear_simplex(struct pci_dev *pdev) 881 { 882 unsigned long bmdma = pci_resource_start(pdev, 4); 883 u8 simplex; 884 885 if (bmdma == 0) 886 return -ENOENT; 887 888 simplex = inb(bmdma + 0x02); 889 outb(simplex & 0x60, bmdma + 0x02); 890 simplex = inb(bmdma + 0x02); 891 if (simplex & 0x80) 892 return -EOPNOTSUPP; 893 return 0; 894 } 895 896 unsigned long ata_pci_default_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long xfer_mask) 897 { 898 /* Filter out DMA modes if the device has been configured by 899 the BIOS as PIO only */ 900 901 if (ap->ioaddr.bmdma_addr == 0) 902 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); 903 return xfer_mask; 904 } 905 906 #endif /* CONFIG_PCI */ 907 908