1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * libahci.c - Common AHCI SATA low-level routines 4 * 5 * Maintained by: Tejun Heo <tj@kernel.org> 6 * Please ALWAYS copy linux-ide@vger.kernel.org 7 * on emails. 8 * 9 * Copyright 2004-2005 Red Hat, Inc. 10 * 11 * libata documentation is available via 'make {ps|pdf}docs', 12 * as Documentation/driver-api/libata.rst 13 * 14 * AHCI hardware documentation: 15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/gfp.h> 21 #include <linux/module.h> 22 #include <linux/nospec.h> 23 #include <linux/blkdev.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/device.h> 28 #include <scsi/scsi_host.h> 29 #include <scsi/scsi_cmnd.h> 30 #include <linux/libata.h> 31 #include <linux/pci.h> 32 #include "ahci.h" 33 #include "libata.h" 34 35 static int ahci_skip_host_reset; 36 int ahci_ignore_sss; 37 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 38 39 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 40 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 41 42 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 43 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 44 45 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 46 unsigned hints); 47 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 48 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 49 size_t size); 50 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 51 ssize_t size); 52 53 54 55 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 56 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 57 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 58 static int ahci_port_start(struct ata_port *ap); 59 static void ahci_port_stop(struct ata_port *ap); 60 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc); 61 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 62 static void ahci_freeze(struct ata_port *ap); 63 static void ahci_thaw(struct ata_port *ap); 64 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep); 65 static void ahci_enable_fbs(struct ata_port *ap); 66 static void ahci_disable_fbs(struct ata_port *ap); 67 static void ahci_pmp_attach(struct ata_port *ap); 68 static void ahci_pmp_detach(struct ata_port *ap); 69 static int ahci_softreset(struct ata_link *link, unsigned int *class, 70 unsigned long deadline); 71 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 72 unsigned long deadline); 73 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 74 unsigned long deadline); 75 static void ahci_postreset(struct ata_link *link, unsigned int *class); 76 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 77 static void ahci_dev_config(struct ata_device *dev); 78 #ifdef CONFIG_PM 79 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 80 #endif 81 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 82 static ssize_t ahci_activity_store(struct ata_device *dev, 83 enum sw_activity val); 84 static void ahci_init_sw_activity(struct ata_link *link); 85 86 static ssize_t ahci_show_host_caps(struct device *dev, 87 struct device_attribute *attr, char *buf); 88 static ssize_t ahci_show_host_cap2(struct device *dev, 89 struct device_attribute *attr, char *buf); 90 static ssize_t ahci_show_host_version(struct device *dev, 91 struct device_attribute *attr, char *buf); 92 static ssize_t ahci_show_port_cmd(struct device *dev, 93 struct device_attribute *attr, char *buf); 94 static ssize_t ahci_read_em_buffer(struct device *dev, 95 struct device_attribute *attr, char *buf); 96 static ssize_t ahci_store_em_buffer(struct device *dev, 97 struct device_attribute *attr, 98 const char *buf, size_t size); 99 static ssize_t ahci_show_em_supported(struct device *dev, 100 struct device_attribute *attr, char *buf); 101 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance); 102 103 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 104 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 105 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 106 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 107 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 108 ahci_read_em_buffer, ahci_store_em_buffer); 109 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 110 111 struct device_attribute *ahci_shost_attrs[] = { 112 &dev_attr_link_power_management_policy, 113 &dev_attr_em_message_type, 114 &dev_attr_em_message, 115 &dev_attr_ahci_host_caps, 116 &dev_attr_ahci_host_cap2, 117 &dev_attr_ahci_host_version, 118 &dev_attr_ahci_port_cmd, 119 &dev_attr_em_buffer, 120 &dev_attr_em_message_supported, 121 NULL 122 }; 123 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 124 125 struct device_attribute *ahci_sdev_attrs[] = { 126 &dev_attr_sw_activity, 127 &dev_attr_unload_heads, 128 &dev_attr_ncq_prio_supported, 129 &dev_attr_ncq_prio_enable, 130 NULL 131 }; 132 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 133 134 struct ata_port_operations ahci_ops = { 135 .inherits = &sata_pmp_port_ops, 136 137 .qc_defer = ahci_pmp_qc_defer, 138 .qc_prep = ahci_qc_prep, 139 .qc_issue = ahci_qc_issue, 140 .qc_fill_rtf = ahci_qc_fill_rtf, 141 142 .freeze = ahci_freeze, 143 .thaw = ahci_thaw, 144 .softreset = ahci_softreset, 145 .hardreset = ahci_hardreset, 146 .postreset = ahci_postreset, 147 .pmp_softreset = ahci_softreset, 148 .error_handler = ahci_error_handler, 149 .post_internal_cmd = ahci_post_internal_cmd, 150 .dev_config = ahci_dev_config, 151 152 .scr_read = ahci_scr_read, 153 .scr_write = ahci_scr_write, 154 .pmp_attach = ahci_pmp_attach, 155 .pmp_detach = ahci_pmp_detach, 156 157 .set_lpm = ahci_set_lpm, 158 .em_show = ahci_led_show, 159 .em_store = ahci_led_store, 160 .sw_activity_show = ahci_activity_show, 161 .sw_activity_store = ahci_activity_store, 162 .transmit_led_message = ahci_transmit_led_message, 163 #ifdef CONFIG_PM 164 .port_suspend = ahci_port_suspend, 165 .port_resume = ahci_port_resume, 166 #endif 167 .port_start = ahci_port_start, 168 .port_stop = ahci_port_stop, 169 }; 170 EXPORT_SYMBOL_GPL(ahci_ops); 171 172 struct ata_port_operations ahci_pmp_retry_srst_ops = { 173 .inherits = &ahci_ops, 174 .softreset = ahci_pmp_retry_softreset, 175 }; 176 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops); 177 178 static bool ahci_em_messages __read_mostly = true; 179 module_param(ahci_em_messages, bool, 0444); 180 /* add other LED protocol types when they become supported */ 181 MODULE_PARM_DESC(ahci_em_messages, 182 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 183 184 /* device sleep idle timeout in ms */ 185 static int devslp_idle_timeout __read_mostly = 1000; 186 module_param(devslp_idle_timeout, int, 0644); 187 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout"); 188 189 static void ahci_enable_ahci(void __iomem *mmio) 190 { 191 int i; 192 u32 tmp; 193 194 /* turn on AHCI_EN */ 195 tmp = readl(mmio + HOST_CTL); 196 if (tmp & HOST_AHCI_EN) 197 return; 198 199 /* Some controllers need AHCI_EN to be written multiple times. 200 * Try a few times before giving up. 201 */ 202 for (i = 0; i < 5; i++) { 203 tmp |= HOST_AHCI_EN; 204 writel(tmp, mmio + HOST_CTL); 205 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 206 if (tmp & HOST_AHCI_EN) 207 return; 208 msleep(10); 209 } 210 211 WARN_ON(1); 212 } 213 214 /** 215 * ahci_rpm_get_port - Make sure the port is powered on 216 * @ap: Port to power on 217 * 218 * Whenever there is need to access the AHCI host registers outside of 219 * normal execution paths, call this function to make sure the host is 220 * actually powered on. 221 */ 222 static int ahci_rpm_get_port(struct ata_port *ap) 223 { 224 return pm_runtime_get_sync(ap->dev); 225 } 226 227 /** 228 * ahci_rpm_put_port - Undoes ahci_rpm_get_port() 229 * @ap: Port to power down 230 * 231 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host 232 * if it has no more active users. 233 */ 234 static void ahci_rpm_put_port(struct ata_port *ap) 235 { 236 pm_runtime_put(ap->dev); 237 } 238 239 static ssize_t ahci_show_host_caps(struct device *dev, 240 struct device_attribute *attr, char *buf) 241 { 242 struct Scsi_Host *shost = class_to_shost(dev); 243 struct ata_port *ap = ata_shost_to_port(shost); 244 struct ahci_host_priv *hpriv = ap->host->private_data; 245 246 return sprintf(buf, "%x\n", hpriv->cap); 247 } 248 249 static ssize_t ahci_show_host_cap2(struct device *dev, 250 struct device_attribute *attr, char *buf) 251 { 252 struct Scsi_Host *shost = class_to_shost(dev); 253 struct ata_port *ap = ata_shost_to_port(shost); 254 struct ahci_host_priv *hpriv = ap->host->private_data; 255 256 return sprintf(buf, "%x\n", hpriv->cap2); 257 } 258 259 static ssize_t ahci_show_host_version(struct device *dev, 260 struct device_attribute *attr, char *buf) 261 { 262 struct Scsi_Host *shost = class_to_shost(dev); 263 struct ata_port *ap = ata_shost_to_port(shost); 264 struct ahci_host_priv *hpriv = ap->host->private_data; 265 266 return sprintf(buf, "%x\n", hpriv->version); 267 } 268 269 static ssize_t ahci_show_port_cmd(struct device *dev, 270 struct device_attribute *attr, char *buf) 271 { 272 struct Scsi_Host *shost = class_to_shost(dev); 273 struct ata_port *ap = ata_shost_to_port(shost); 274 void __iomem *port_mmio = ahci_port_base(ap); 275 ssize_t ret; 276 277 ahci_rpm_get_port(ap); 278 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 279 ahci_rpm_put_port(ap); 280 281 return ret; 282 } 283 284 static ssize_t ahci_read_em_buffer(struct device *dev, 285 struct device_attribute *attr, char *buf) 286 { 287 struct Scsi_Host *shost = class_to_shost(dev); 288 struct ata_port *ap = ata_shost_to_port(shost); 289 struct ahci_host_priv *hpriv = ap->host->private_data; 290 void __iomem *mmio = hpriv->mmio; 291 void __iomem *em_mmio = mmio + hpriv->em_loc; 292 u32 em_ctl, msg; 293 unsigned long flags; 294 size_t count; 295 int i; 296 297 ahci_rpm_get_port(ap); 298 spin_lock_irqsave(ap->lock, flags); 299 300 em_ctl = readl(mmio + HOST_EM_CTL); 301 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 302 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 303 spin_unlock_irqrestore(ap->lock, flags); 304 ahci_rpm_put_port(ap); 305 return -EINVAL; 306 } 307 308 if (!(em_ctl & EM_CTL_MR)) { 309 spin_unlock_irqrestore(ap->lock, flags); 310 ahci_rpm_put_port(ap); 311 return -EAGAIN; 312 } 313 314 if (!(em_ctl & EM_CTL_SMB)) 315 em_mmio += hpriv->em_buf_sz; 316 317 count = hpriv->em_buf_sz; 318 319 /* the count should not be larger than PAGE_SIZE */ 320 if (count > PAGE_SIZE) { 321 if (printk_ratelimit()) 322 ata_port_warn(ap, 323 "EM read buffer size too large: " 324 "buffer size %u, page size %lu\n", 325 hpriv->em_buf_sz, PAGE_SIZE); 326 count = PAGE_SIZE; 327 } 328 329 for (i = 0; i < count; i += 4) { 330 msg = readl(em_mmio + i); 331 buf[i] = msg & 0xff; 332 buf[i + 1] = (msg >> 8) & 0xff; 333 buf[i + 2] = (msg >> 16) & 0xff; 334 buf[i + 3] = (msg >> 24) & 0xff; 335 } 336 337 spin_unlock_irqrestore(ap->lock, flags); 338 ahci_rpm_put_port(ap); 339 340 return i; 341 } 342 343 static ssize_t ahci_store_em_buffer(struct device *dev, 344 struct device_attribute *attr, 345 const char *buf, size_t size) 346 { 347 struct Scsi_Host *shost = class_to_shost(dev); 348 struct ata_port *ap = ata_shost_to_port(shost); 349 struct ahci_host_priv *hpriv = ap->host->private_data; 350 void __iomem *mmio = hpriv->mmio; 351 void __iomem *em_mmio = mmio + hpriv->em_loc; 352 const unsigned char *msg_buf = buf; 353 u32 em_ctl, msg; 354 unsigned long flags; 355 int i; 356 357 /* check size validity */ 358 if (!(ap->flags & ATA_FLAG_EM) || 359 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 360 size % 4 || size > hpriv->em_buf_sz) 361 return -EINVAL; 362 363 ahci_rpm_get_port(ap); 364 spin_lock_irqsave(ap->lock, flags); 365 366 em_ctl = readl(mmio + HOST_EM_CTL); 367 if (em_ctl & EM_CTL_TM) { 368 spin_unlock_irqrestore(ap->lock, flags); 369 ahci_rpm_put_port(ap); 370 return -EBUSY; 371 } 372 373 for (i = 0; i < size; i += 4) { 374 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 375 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 376 writel(msg, em_mmio + i); 377 } 378 379 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 380 381 spin_unlock_irqrestore(ap->lock, flags); 382 ahci_rpm_put_port(ap); 383 384 return size; 385 } 386 387 static ssize_t ahci_show_em_supported(struct device *dev, 388 struct device_attribute *attr, char *buf) 389 { 390 struct Scsi_Host *shost = class_to_shost(dev); 391 struct ata_port *ap = ata_shost_to_port(shost); 392 struct ahci_host_priv *hpriv = ap->host->private_data; 393 void __iomem *mmio = hpriv->mmio; 394 u32 em_ctl; 395 396 ahci_rpm_get_port(ap); 397 em_ctl = readl(mmio + HOST_EM_CTL); 398 ahci_rpm_put_port(ap); 399 400 return sprintf(buf, "%s%s%s%s\n", 401 em_ctl & EM_CTL_LED ? "led " : "", 402 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 403 em_ctl & EM_CTL_SES ? "ses-2 " : "", 404 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 405 } 406 407 /** 408 * ahci_save_initial_config - Save and fixup initial config values 409 * @dev: target AHCI device 410 * @hpriv: host private area to store config values 411 * 412 * Some registers containing configuration info might be setup by 413 * BIOS and might be cleared on reset. This function saves the 414 * initial values of those registers into @hpriv such that they 415 * can be restored after controller reset. 416 * 417 * If inconsistent, config values are fixed up by this function. 418 * 419 * If it is not set already this function sets hpriv->start_engine to 420 * ahci_start_engine. 421 * 422 * LOCKING: 423 * None. 424 */ 425 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv) 426 { 427 void __iomem *mmio = hpriv->mmio; 428 u32 cap, cap2, vers, port_map; 429 int i; 430 431 /* make sure AHCI mode is enabled before accessing CAP */ 432 ahci_enable_ahci(mmio); 433 434 /* Values prefixed with saved_ are written back to host after 435 * reset. Values without are used for driver operation. 436 */ 437 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 438 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 439 440 /* CAP2 register is only defined for AHCI 1.2 and later */ 441 vers = readl(mmio + HOST_VERSION); 442 if ((vers >> 16) > 1 || 443 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 444 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 445 else 446 hpriv->saved_cap2 = cap2 = 0; 447 448 /* some chips have errata preventing 64bit use */ 449 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 450 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n"); 451 cap &= ~HOST_CAP_64; 452 } 453 454 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 455 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n"); 456 cap &= ~HOST_CAP_NCQ; 457 } 458 459 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 460 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n"); 461 cap |= HOST_CAP_NCQ; 462 } 463 464 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 465 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n"); 466 cap &= ~HOST_CAP_PMP; 467 } 468 469 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 470 dev_info(dev, 471 "controller can't do SNTF, turning off CAP_SNTF\n"); 472 cap &= ~HOST_CAP_SNTF; 473 } 474 475 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) { 476 dev_info(dev, 477 "controller can't do DEVSLP, turning off\n"); 478 cap2 &= ~HOST_CAP2_SDS; 479 cap2 &= ~HOST_CAP2_SADM; 480 } 481 482 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 483 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n"); 484 cap |= HOST_CAP_FBS; 485 } 486 487 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) { 488 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n"); 489 cap &= ~HOST_CAP_FBS; 490 } 491 492 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) { 493 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n"); 494 cap |= HOST_CAP_ALPM; 495 } 496 497 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) { 498 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n"); 499 cap &= ~HOST_CAP_SXS; 500 } 501 502 if (hpriv->force_port_map && port_map != hpriv->force_port_map) { 503 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n", 504 port_map, hpriv->force_port_map); 505 port_map = hpriv->force_port_map; 506 hpriv->saved_port_map = port_map; 507 } 508 509 if (hpriv->mask_port_map) { 510 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n", 511 port_map, 512 port_map & hpriv->mask_port_map); 513 port_map &= hpriv->mask_port_map; 514 } 515 516 /* cross check port_map and cap.n_ports */ 517 if (port_map) { 518 int map_ports = 0; 519 520 for (i = 0; i < AHCI_MAX_PORTS; i++) 521 if (port_map & (1 << i)) 522 map_ports++; 523 524 /* If PI has more ports than n_ports, whine, clear 525 * port_map and let it be generated from n_ports. 526 */ 527 if (map_ports > ahci_nr_ports(cap)) { 528 dev_warn(dev, 529 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n", 530 port_map, ahci_nr_ports(cap)); 531 port_map = 0; 532 } 533 } 534 535 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */ 536 if (!port_map && vers < 0x10300) { 537 port_map = (1 << ahci_nr_ports(cap)) - 1; 538 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map); 539 540 /* write the fixed up value to the PI register */ 541 hpriv->saved_port_map = port_map; 542 } 543 544 /* record values to use during operation */ 545 hpriv->cap = cap; 546 hpriv->cap2 = cap2; 547 hpriv->version = readl(mmio + HOST_VERSION); 548 hpriv->port_map = port_map; 549 550 if (!hpriv->start_engine) 551 hpriv->start_engine = ahci_start_engine; 552 553 if (!hpriv->stop_engine) 554 hpriv->stop_engine = ahci_stop_engine; 555 556 if (!hpriv->irq_handler) 557 hpriv->irq_handler = ahci_single_level_irq_intr; 558 } 559 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 560 561 /** 562 * ahci_restore_initial_config - Restore initial config 563 * @host: target ATA host 564 * 565 * Restore initial config stored by ahci_save_initial_config(). 566 * 567 * LOCKING: 568 * None. 569 */ 570 static void ahci_restore_initial_config(struct ata_host *host) 571 { 572 struct ahci_host_priv *hpriv = host->private_data; 573 void __iomem *mmio = hpriv->mmio; 574 575 writel(hpriv->saved_cap, mmio + HOST_CAP); 576 if (hpriv->saved_cap2) 577 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 578 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 579 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 580 } 581 582 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 583 { 584 static const int offset[] = { 585 [SCR_STATUS] = PORT_SCR_STAT, 586 [SCR_CONTROL] = PORT_SCR_CTL, 587 [SCR_ERROR] = PORT_SCR_ERR, 588 [SCR_ACTIVE] = PORT_SCR_ACT, 589 [SCR_NOTIFICATION] = PORT_SCR_NTF, 590 }; 591 struct ahci_host_priv *hpriv = ap->host->private_data; 592 593 if (sc_reg < ARRAY_SIZE(offset) && 594 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 595 return offset[sc_reg]; 596 return 0; 597 } 598 599 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 600 { 601 void __iomem *port_mmio = ahci_port_base(link->ap); 602 int offset = ahci_scr_offset(link->ap, sc_reg); 603 604 if (offset) { 605 *val = readl(port_mmio + offset); 606 return 0; 607 } 608 return -EINVAL; 609 } 610 611 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 612 { 613 void __iomem *port_mmio = ahci_port_base(link->ap); 614 int offset = ahci_scr_offset(link->ap, sc_reg); 615 616 if (offset) { 617 writel(val, port_mmio + offset); 618 return 0; 619 } 620 return -EINVAL; 621 } 622 623 void ahci_start_engine(struct ata_port *ap) 624 { 625 void __iomem *port_mmio = ahci_port_base(ap); 626 u32 tmp; 627 628 /* start DMA */ 629 tmp = readl(port_mmio + PORT_CMD); 630 tmp |= PORT_CMD_START; 631 writel(tmp, port_mmio + PORT_CMD); 632 readl(port_mmio + PORT_CMD); /* flush */ 633 } 634 EXPORT_SYMBOL_GPL(ahci_start_engine); 635 636 int ahci_stop_engine(struct ata_port *ap) 637 { 638 void __iomem *port_mmio = ahci_port_base(ap); 639 struct ahci_host_priv *hpriv = ap->host->private_data; 640 u32 tmp; 641 642 /* 643 * On some controllers, stopping a port's DMA engine while the port 644 * is in ALPM state (partial or slumber) results in failures on 645 * subsequent DMA engine starts. For those controllers, put the 646 * port back in active state before stopping its DMA engine. 647 */ 648 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) && 649 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) && 650 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) { 651 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n"); 652 return -EIO; 653 } 654 655 tmp = readl(port_mmio + PORT_CMD); 656 657 /* check if the HBA is idle */ 658 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 659 return 0; 660 661 /* 662 * Don't try to issue commands but return with ENODEV if the 663 * AHCI controller not available anymore (e.g. due to PCIe hot 664 * unplugging). Otherwise a 500ms delay for each port is added. 665 */ 666 if (tmp == 0xffffffff) { 667 dev_err(ap->host->dev, "AHCI controller unavailable!\n"); 668 return -ENODEV; 669 } 670 671 /* setting HBA to idle */ 672 tmp &= ~PORT_CMD_START; 673 writel(tmp, port_mmio + PORT_CMD); 674 675 /* wait for engine to stop. This could be as long as 500 msec */ 676 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 677 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 678 if (tmp & PORT_CMD_LIST_ON) 679 return -EIO; 680 681 return 0; 682 } 683 EXPORT_SYMBOL_GPL(ahci_stop_engine); 684 685 void ahci_start_fis_rx(struct ata_port *ap) 686 { 687 void __iomem *port_mmio = ahci_port_base(ap); 688 struct ahci_host_priv *hpriv = ap->host->private_data; 689 struct ahci_port_priv *pp = ap->private_data; 690 u32 tmp; 691 692 /* set FIS registers */ 693 if (hpriv->cap & HOST_CAP_64) 694 writel((pp->cmd_slot_dma >> 16) >> 16, 695 port_mmio + PORT_LST_ADDR_HI); 696 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 697 698 if (hpriv->cap & HOST_CAP_64) 699 writel((pp->rx_fis_dma >> 16) >> 16, 700 port_mmio + PORT_FIS_ADDR_HI); 701 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 702 703 /* enable FIS reception */ 704 tmp = readl(port_mmio + PORT_CMD); 705 tmp |= PORT_CMD_FIS_RX; 706 writel(tmp, port_mmio + PORT_CMD); 707 708 /* flush */ 709 readl(port_mmio + PORT_CMD); 710 } 711 EXPORT_SYMBOL_GPL(ahci_start_fis_rx); 712 713 static int ahci_stop_fis_rx(struct ata_port *ap) 714 { 715 void __iomem *port_mmio = ahci_port_base(ap); 716 u32 tmp; 717 718 /* disable FIS reception */ 719 tmp = readl(port_mmio + PORT_CMD); 720 tmp &= ~PORT_CMD_FIS_RX; 721 writel(tmp, port_mmio + PORT_CMD); 722 723 /* wait for completion, spec says 500ms, give it 1000 */ 724 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 725 PORT_CMD_FIS_ON, 10, 1000); 726 if (tmp & PORT_CMD_FIS_ON) 727 return -EBUSY; 728 729 return 0; 730 } 731 732 static void ahci_power_up(struct ata_port *ap) 733 { 734 struct ahci_host_priv *hpriv = ap->host->private_data; 735 void __iomem *port_mmio = ahci_port_base(ap); 736 u32 cmd; 737 738 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 739 740 /* spin up device */ 741 if (hpriv->cap & HOST_CAP_SSS) { 742 cmd |= PORT_CMD_SPIN_UP; 743 writel(cmd, port_mmio + PORT_CMD); 744 } 745 746 /* wake up link */ 747 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 748 } 749 750 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 751 unsigned int hints) 752 { 753 struct ata_port *ap = link->ap; 754 struct ahci_host_priv *hpriv = ap->host->private_data; 755 struct ahci_port_priv *pp = ap->private_data; 756 void __iomem *port_mmio = ahci_port_base(ap); 757 758 if (policy != ATA_LPM_MAX_POWER) { 759 /* wakeup flag only applies to the max power policy */ 760 hints &= ~ATA_LPM_WAKE_ONLY; 761 762 /* 763 * Disable interrupts on Phy Ready. This keeps us from 764 * getting woken up due to spurious phy ready 765 * interrupts. 766 */ 767 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 768 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 769 770 sata_link_scr_lpm(link, policy, false); 771 } 772 773 if (hpriv->cap & HOST_CAP_ALPM) { 774 u32 cmd = readl(port_mmio + PORT_CMD); 775 776 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 777 if (!(hints & ATA_LPM_WAKE_ONLY)) 778 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 779 cmd |= PORT_CMD_ICC_ACTIVE; 780 781 writel(cmd, port_mmio + PORT_CMD); 782 readl(port_mmio + PORT_CMD); 783 784 /* wait 10ms to be sure we've come out of LPM state */ 785 ata_msleep(ap, 10); 786 787 if (hints & ATA_LPM_WAKE_ONLY) 788 return 0; 789 } else { 790 cmd |= PORT_CMD_ALPE; 791 if (policy == ATA_LPM_MIN_POWER) 792 cmd |= PORT_CMD_ASP; 793 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 794 cmd &= ~PORT_CMD_ASP; 795 796 /* write out new cmd value */ 797 writel(cmd, port_mmio + PORT_CMD); 798 } 799 } 800 801 /* set aggressive device sleep */ 802 if ((hpriv->cap2 & HOST_CAP2_SDS) && 803 (hpriv->cap2 & HOST_CAP2_SADM) && 804 (link->device->flags & ATA_DFLAG_DEVSLP)) { 805 if (policy == ATA_LPM_MIN_POWER || 806 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL) 807 ahci_set_aggressive_devslp(ap, true); 808 else 809 ahci_set_aggressive_devslp(ap, false); 810 } 811 812 if (policy == ATA_LPM_MAX_POWER) { 813 sata_link_scr_lpm(link, policy, false); 814 815 /* turn PHYRDY IRQ back on */ 816 pp->intr_mask |= PORT_IRQ_PHYRDY; 817 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 818 } 819 820 return 0; 821 } 822 823 #ifdef CONFIG_PM 824 static void ahci_power_down(struct ata_port *ap) 825 { 826 struct ahci_host_priv *hpriv = ap->host->private_data; 827 void __iomem *port_mmio = ahci_port_base(ap); 828 u32 cmd, scontrol; 829 830 if (!(hpriv->cap & HOST_CAP_SSS)) 831 return; 832 833 /* put device into listen mode, first set PxSCTL.DET to 0 */ 834 scontrol = readl(port_mmio + PORT_SCR_CTL); 835 scontrol &= ~0xf; 836 writel(scontrol, port_mmio + PORT_SCR_CTL); 837 838 /* then set PxCMD.SUD to 0 */ 839 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 840 cmd &= ~PORT_CMD_SPIN_UP; 841 writel(cmd, port_mmio + PORT_CMD); 842 } 843 #endif 844 845 static void ahci_start_port(struct ata_port *ap) 846 { 847 struct ahci_host_priv *hpriv = ap->host->private_data; 848 struct ahci_port_priv *pp = ap->private_data; 849 struct ata_link *link; 850 struct ahci_em_priv *emp; 851 ssize_t rc; 852 int i; 853 854 /* enable FIS reception */ 855 ahci_start_fis_rx(ap); 856 857 /* enable DMA */ 858 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE)) 859 hpriv->start_engine(ap); 860 861 /* turn on LEDs */ 862 if (ap->flags & ATA_FLAG_EM) { 863 ata_for_each_link(link, ap, EDGE) { 864 emp = &pp->em_priv[link->pmp]; 865 866 /* EM Transmit bit maybe busy during init */ 867 for (i = 0; i < EM_MAX_RETRY; i++) { 868 rc = ap->ops->transmit_led_message(ap, 869 emp->led_state, 870 4); 871 /* 872 * If busy, give a breather but do not 873 * release EH ownership by using msleep() 874 * instead of ata_msleep(). EM Transmit 875 * bit is busy for the whole host and 876 * releasing ownership will cause other 877 * ports to fail the same way. 878 */ 879 if (rc == -EBUSY) 880 msleep(1); 881 else 882 break; 883 } 884 } 885 } 886 887 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 888 ata_for_each_link(link, ap, EDGE) 889 ahci_init_sw_activity(link); 890 891 } 892 893 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 894 { 895 int rc; 896 struct ahci_host_priv *hpriv = ap->host->private_data; 897 898 /* disable DMA */ 899 rc = hpriv->stop_engine(ap); 900 if (rc) { 901 *emsg = "failed to stop engine"; 902 return rc; 903 } 904 905 /* disable FIS reception */ 906 rc = ahci_stop_fis_rx(ap); 907 if (rc) { 908 *emsg = "failed stop FIS RX"; 909 return rc; 910 } 911 912 return 0; 913 } 914 915 int ahci_reset_controller(struct ata_host *host) 916 { 917 struct ahci_host_priv *hpriv = host->private_data; 918 void __iomem *mmio = hpriv->mmio; 919 u32 tmp; 920 921 /* we must be in AHCI mode, before using anything 922 * AHCI-specific, such as HOST_RESET. 923 */ 924 ahci_enable_ahci(mmio); 925 926 /* global controller reset */ 927 if (!ahci_skip_host_reset) { 928 tmp = readl(mmio + HOST_CTL); 929 if ((tmp & HOST_RESET) == 0) { 930 writel(tmp | HOST_RESET, mmio + HOST_CTL); 931 readl(mmio + HOST_CTL); /* flush */ 932 } 933 934 /* 935 * to perform host reset, OS should set HOST_RESET 936 * and poll until this bit is read to be "0". 937 * reset must complete within 1 second, or 938 * the hardware should be considered fried. 939 */ 940 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 941 HOST_RESET, 10, 1000); 942 943 if (tmp & HOST_RESET) { 944 dev_err(host->dev, "controller reset failed (0x%x)\n", 945 tmp); 946 return -EIO; 947 } 948 949 /* turn on AHCI mode */ 950 ahci_enable_ahci(mmio); 951 952 /* Some registers might be cleared on reset. Restore 953 * initial values. 954 */ 955 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO)) 956 ahci_restore_initial_config(host); 957 } else 958 dev_info(host->dev, "skipping global host reset\n"); 959 960 return 0; 961 } 962 EXPORT_SYMBOL_GPL(ahci_reset_controller); 963 964 static void ahci_sw_activity(struct ata_link *link) 965 { 966 struct ata_port *ap = link->ap; 967 struct ahci_port_priv *pp = ap->private_data; 968 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 969 970 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 971 return; 972 973 emp->activity++; 974 if (!timer_pending(&emp->timer)) 975 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 976 } 977 978 static void ahci_sw_activity_blink(struct timer_list *t) 979 { 980 struct ahci_em_priv *emp = from_timer(emp, t, timer); 981 struct ata_link *link = emp->link; 982 struct ata_port *ap = link->ap; 983 984 unsigned long led_message = emp->led_state; 985 u32 activity_led_state; 986 unsigned long flags; 987 988 led_message &= EM_MSG_LED_VALUE; 989 led_message |= ap->port_no | (link->pmp << 8); 990 991 /* check to see if we've had activity. If so, 992 * toggle state of LED and reset timer. If not, 993 * turn LED to desired idle state. 994 */ 995 spin_lock_irqsave(ap->lock, flags); 996 if (emp->saved_activity != emp->activity) { 997 emp->saved_activity = emp->activity; 998 /* get the current LED state */ 999 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 1000 1001 if (activity_led_state) 1002 activity_led_state = 0; 1003 else 1004 activity_led_state = 1; 1005 1006 /* clear old state */ 1007 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1008 1009 /* toggle state */ 1010 led_message |= (activity_led_state << 16); 1011 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 1012 } else { 1013 /* switch to idle */ 1014 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 1015 if (emp->blink_policy == BLINK_OFF) 1016 led_message |= (1 << 16); 1017 } 1018 spin_unlock_irqrestore(ap->lock, flags); 1019 ap->ops->transmit_led_message(ap, led_message, 4); 1020 } 1021 1022 static void ahci_init_sw_activity(struct ata_link *link) 1023 { 1024 struct ata_port *ap = link->ap; 1025 struct ahci_port_priv *pp = ap->private_data; 1026 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1027 1028 /* init activity stats, setup timer */ 1029 emp->saved_activity = emp->activity = 0; 1030 emp->link = link; 1031 timer_setup(&emp->timer, ahci_sw_activity_blink, 0); 1032 1033 /* check our blink policy and set flag for link if it's enabled */ 1034 if (emp->blink_policy) 1035 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1036 } 1037 1038 int ahci_reset_em(struct ata_host *host) 1039 { 1040 struct ahci_host_priv *hpriv = host->private_data; 1041 void __iomem *mmio = hpriv->mmio; 1042 u32 em_ctl; 1043 1044 em_ctl = readl(mmio + HOST_EM_CTL); 1045 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 1046 return -EINVAL; 1047 1048 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 1049 return 0; 1050 } 1051 EXPORT_SYMBOL_GPL(ahci_reset_em); 1052 1053 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 1054 ssize_t size) 1055 { 1056 struct ahci_host_priv *hpriv = ap->host->private_data; 1057 struct ahci_port_priv *pp = ap->private_data; 1058 void __iomem *mmio = hpriv->mmio; 1059 u32 em_ctl; 1060 u32 message[] = {0, 0}; 1061 unsigned long flags; 1062 int pmp; 1063 struct ahci_em_priv *emp; 1064 1065 /* get the slot number from the message */ 1066 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1067 if (pmp < EM_MAX_SLOTS) 1068 emp = &pp->em_priv[pmp]; 1069 else 1070 return -EINVAL; 1071 1072 ahci_rpm_get_port(ap); 1073 spin_lock_irqsave(ap->lock, flags); 1074 1075 /* 1076 * if we are still busy transmitting a previous message, 1077 * do not allow 1078 */ 1079 em_ctl = readl(mmio + HOST_EM_CTL); 1080 if (em_ctl & EM_CTL_TM) { 1081 spin_unlock_irqrestore(ap->lock, flags); 1082 ahci_rpm_put_port(ap); 1083 return -EBUSY; 1084 } 1085 1086 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1087 /* 1088 * create message header - this is all zero except for 1089 * the message size, which is 4 bytes. 1090 */ 1091 message[0] |= (4 << 8); 1092 1093 /* ignore 0:4 of byte zero, fill in port info yourself */ 1094 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1095 1096 /* write message to EM_LOC */ 1097 writel(message[0], mmio + hpriv->em_loc); 1098 writel(message[1], mmio + hpriv->em_loc+4); 1099 1100 /* 1101 * tell hardware to transmit the message 1102 */ 1103 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1104 } 1105 1106 /* save off new led state for port/slot */ 1107 emp->led_state = state; 1108 1109 spin_unlock_irqrestore(ap->lock, flags); 1110 ahci_rpm_put_port(ap); 1111 1112 return size; 1113 } 1114 1115 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1116 { 1117 struct ahci_port_priv *pp = ap->private_data; 1118 struct ata_link *link; 1119 struct ahci_em_priv *emp; 1120 int rc = 0; 1121 1122 ata_for_each_link(link, ap, EDGE) { 1123 emp = &pp->em_priv[link->pmp]; 1124 rc += sprintf(buf, "%lx\n", emp->led_state); 1125 } 1126 return rc; 1127 } 1128 1129 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1130 size_t size) 1131 { 1132 unsigned int state; 1133 int pmp; 1134 struct ahci_port_priv *pp = ap->private_data; 1135 struct ahci_em_priv *emp; 1136 1137 if (kstrtouint(buf, 0, &state) < 0) 1138 return -EINVAL; 1139 1140 /* get the slot number from the message */ 1141 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1142 if (pmp < EM_MAX_SLOTS) { 1143 pmp = array_index_nospec(pmp, EM_MAX_SLOTS); 1144 emp = &pp->em_priv[pmp]; 1145 } else { 1146 return -EINVAL; 1147 } 1148 1149 /* mask off the activity bits if we are in sw_activity 1150 * mode, user should turn off sw_activity before setting 1151 * activity led through em_message 1152 */ 1153 if (emp->blink_policy) 1154 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1155 1156 return ap->ops->transmit_led_message(ap, state, size); 1157 } 1158 1159 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1160 { 1161 struct ata_link *link = dev->link; 1162 struct ata_port *ap = link->ap; 1163 struct ahci_port_priv *pp = ap->private_data; 1164 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1165 u32 port_led_state = emp->led_state; 1166 1167 /* save the desired Activity LED behavior */ 1168 if (val == OFF) { 1169 /* clear LFLAG */ 1170 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1171 1172 /* set the LED to OFF */ 1173 port_led_state &= EM_MSG_LED_VALUE_OFF; 1174 port_led_state |= (ap->port_no | (link->pmp << 8)); 1175 ap->ops->transmit_led_message(ap, port_led_state, 4); 1176 } else { 1177 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1178 if (val == BLINK_OFF) { 1179 /* set LED to ON for idle */ 1180 port_led_state &= EM_MSG_LED_VALUE_OFF; 1181 port_led_state |= (ap->port_no | (link->pmp << 8)); 1182 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1183 ap->ops->transmit_led_message(ap, port_led_state, 4); 1184 } 1185 } 1186 emp->blink_policy = val; 1187 return 0; 1188 } 1189 1190 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1191 { 1192 struct ata_link *link = dev->link; 1193 struct ata_port *ap = link->ap; 1194 struct ahci_port_priv *pp = ap->private_data; 1195 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1196 1197 /* display the saved value of activity behavior for this 1198 * disk. 1199 */ 1200 return sprintf(buf, "%d\n", emp->blink_policy); 1201 } 1202 1203 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1204 int port_no, void __iomem *mmio, 1205 void __iomem *port_mmio) 1206 { 1207 struct ahci_host_priv *hpriv = ap->host->private_data; 1208 const char *emsg = NULL; 1209 int rc; 1210 u32 tmp; 1211 1212 /* make sure port is not active */ 1213 rc = ahci_deinit_port(ap, &emsg); 1214 if (rc) 1215 dev_warn(dev, "%s (%d)\n", emsg, rc); 1216 1217 /* clear SError */ 1218 tmp = readl(port_mmio + PORT_SCR_ERR); 1219 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1220 writel(tmp, port_mmio + PORT_SCR_ERR); 1221 1222 /* clear port IRQ */ 1223 tmp = readl(port_mmio + PORT_IRQ_STAT); 1224 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1225 if (tmp) 1226 writel(tmp, port_mmio + PORT_IRQ_STAT); 1227 1228 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1229 1230 /* mark esata ports */ 1231 tmp = readl(port_mmio + PORT_CMD); 1232 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS)) 1233 ap->pflags |= ATA_PFLAG_EXTERNAL; 1234 } 1235 1236 void ahci_init_controller(struct ata_host *host) 1237 { 1238 struct ahci_host_priv *hpriv = host->private_data; 1239 void __iomem *mmio = hpriv->mmio; 1240 int i; 1241 void __iomem *port_mmio; 1242 u32 tmp; 1243 1244 for (i = 0; i < host->n_ports; i++) { 1245 struct ata_port *ap = host->ports[i]; 1246 1247 port_mmio = ahci_port_base(ap); 1248 if (ata_port_is_dummy(ap)) 1249 continue; 1250 1251 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1252 } 1253 1254 tmp = readl(mmio + HOST_CTL); 1255 VPRINTK("HOST_CTL 0x%x\n", tmp); 1256 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1257 tmp = readl(mmio + HOST_CTL); 1258 VPRINTK("HOST_CTL 0x%x\n", tmp); 1259 } 1260 EXPORT_SYMBOL_GPL(ahci_init_controller); 1261 1262 static void ahci_dev_config(struct ata_device *dev) 1263 { 1264 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1265 1266 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1267 dev->max_sectors = 255; 1268 ata_dev_info(dev, 1269 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1270 } 1271 } 1272 1273 unsigned int ahci_dev_classify(struct ata_port *ap) 1274 { 1275 void __iomem *port_mmio = ahci_port_base(ap); 1276 struct ata_taskfile tf; 1277 u32 tmp; 1278 1279 tmp = readl(port_mmio + PORT_SIG); 1280 tf.lbah = (tmp >> 24) & 0xff; 1281 tf.lbam = (tmp >> 16) & 0xff; 1282 tf.lbal = (tmp >> 8) & 0xff; 1283 tf.nsect = (tmp) & 0xff; 1284 1285 return ata_dev_classify(&tf); 1286 } 1287 EXPORT_SYMBOL_GPL(ahci_dev_classify); 1288 1289 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1290 u32 opts) 1291 { 1292 dma_addr_t cmd_tbl_dma; 1293 1294 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1295 1296 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1297 pp->cmd_slot[tag].status = 0; 1298 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1299 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1300 } 1301 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1302 1303 int ahci_kick_engine(struct ata_port *ap) 1304 { 1305 void __iomem *port_mmio = ahci_port_base(ap); 1306 struct ahci_host_priv *hpriv = ap->host->private_data; 1307 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1308 u32 tmp; 1309 int busy, rc; 1310 1311 /* stop engine */ 1312 rc = hpriv->stop_engine(ap); 1313 if (rc) 1314 goto out_restart; 1315 1316 /* need to do CLO? 1317 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1318 */ 1319 busy = status & (ATA_BUSY | ATA_DRQ); 1320 if (!busy && !sata_pmp_attached(ap)) { 1321 rc = 0; 1322 goto out_restart; 1323 } 1324 1325 if (!(hpriv->cap & HOST_CAP_CLO)) { 1326 rc = -EOPNOTSUPP; 1327 goto out_restart; 1328 } 1329 1330 /* perform CLO */ 1331 tmp = readl(port_mmio + PORT_CMD); 1332 tmp |= PORT_CMD_CLO; 1333 writel(tmp, port_mmio + PORT_CMD); 1334 1335 rc = 0; 1336 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1337 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1338 if (tmp & PORT_CMD_CLO) 1339 rc = -EIO; 1340 1341 /* restart engine */ 1342 out_restart: 1343 hpriv->start_engine(ap); 1344 return rc; 1345 } 1346 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1347 1348 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1349 struct ata_taskfile *tf, int is_cmd, u16 flags, 1350 unsigned long timeout_msec) 1351 { 1352 const u32 cmd_fis_len = 5; /* five dwords */ 1353 struct ahci_port_priv *pp = ap->private_data; 1354 void __iomem *port_mmio = ahci_port_base(ap); 1355 u8 *fis = pp->cmd_tbl; 1356 u32 tmp; 1357 1358 /* prep the command */ 1359 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1360 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1361 1362 /* set port value for softreset of Port Multiplier */ 1363 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) { 1364 tmp = readl(port_mmio + PORT_FBS); 1365 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1366 tmp |= pmp << PORT_FBS_DEV_OFFSET; 1367 writel(tmp, port_mmio + PORT_FBS); 1368 pp->fbs_last_dev = pmp; 1369 } 1370 1371 /* issue & wait */ 1372 writel(1, port_mmio + PORT_CMD_ISSUE); 1373 1374 if (timeout_msec) { 1375 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1376 0x1, 0x1, 1, timeout_msec); 1377 if (tmp & 0x1) { 1378 ahci_kick_engine(ap); 1379 return -EBUSY; 1380 } 1381 } else 1382 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1383 1384 return 0; 1385 } 1386 1387 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1388 int pmp, unsigned long deadline, 1389 int (*check_ready)(struct ata_link *link)) 1390 { 1391 struct ata_port *ap = link->ap; 1392 struct ahci_host_priv *hpriv = ap->host->private_data; 1393 struct ahci_port_priv *pp = ap->private_data; 1394 const char *reason = NULL; 1395 unsigned long now, msecs; 1396 struct ata_taskfile tf; 1397 bool fbs_disabled = false; 1398 int rc; 1399 1400 DPRINTK("ENTER\n"); 1401 1402 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1403 rc = ahci_kick_engine(ap); 1404 if (rc && rc != -EOPNOTSUPP) 1405 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc); 1406 1407 /* 1408 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall 1409 * clear PxFBS.EN to '0' prior to issuing software reset to devices 1410 * that is attached to port multiplier. 1411 */ 1412 if (!ata_is_host_link(link) && pp->fbs_enabled) { 1413 ahci_disable_fbs(ap); 1414 fbs_disabled = true; 1415 } 1416 1417 ata_tf_init(link->device, &tf); 1418 1419 /* issue the first H2D Register FIS */ 1420 msecs = 0; 1421 now = jiffies; 1422 if (time_after(deadline, now)) 1423 msecs = jiffies_to_msecs(deadline - now); 1424 1425 tf.ctl |= ATA_SRST; 1426 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1427 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1428 rc = -EIO; 1429 reason = "1st FIS failed"; 1430 goto fail; 1431 } 1432 1433 /* spec says at least 5us, but be generous and sleep for 1ms */ 1434 ata_msleep(ap, 1); 1435 1436 /* issue the second H2D Register FIS */ 1437 tf.ctl &= ~ATA_SRST; 1438 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1439 1440 /* wait for link to become ready */ 1441 rc = ata_wait_after_reset(link, deadline, check_ready); 1442 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1443 /* 1444 * Workaround for cases where link online status can't 1445 * be trusted. Treat device readiness timeout as link 1446 * offline. 1447 */ 1448 ata_link_info(link, "device not ready, treating as offline\n"); 1449 *class = ATA_DEV_NONE; 1450 } else if (rc) { 1451 /* link occupied, -ENODEV too is an error */ 1452 reason = "device not ready"; 1453 goto fail; 1454 } else 1455 *class = ahci_dev_classify(ap); 1456 1457 /* re-enable FBS if disabled before */ 1458 if (fbs_disabled) 1459 ahci_enable_fbs(ap); 1460 1461 DPRINTK("EXIT, class=%u\n", *class); 1462 return 0; 1463 1464 fail: 1465 ata_link_err(link, "softreset failed (%s)\n", reason); 1466 return rc; 1467 } 1468 1469 int ahci_check_ready(struct ata_link *link) 1470 { 1471 void __iomem *port_mmio = ahci_port_base(link->ap); 1472 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1473 1474 return ata_check_ready(status); 1475 } 1476 EXPORT_SYMBOL_GPL(ahci_check_ready); 1477 1478 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1479 unsigned long deadline) 1480 { 1481 int pmp = sata_srst_pmp(link); 1482 1483 DPRINTK("ENTER\n"); 1484 1485 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1486 } 1487 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1488 1489 static int ahci_bad_pmp_check_ready(struct ata_link *link) 1490 { 1491 void __iomem *port_mmio = ahci_port_base(link->ap); 1492 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1493 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT); 1494 1495 /* 1496 * There is no need to check TFDATA if BAD PMP is found due to HW bug, 1497 * which can save timeout delay. 1498 */ 1499 if (irq_status & PORT_IRQ_BAD_PMP) 1500 return -EIO; 1501 1502 return ata_check_ready(status); 1503 } 1504 1505 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class, 1506 unsigned long deadline) 1507 { 1508 struct ata_port *ap = link->ap; 1509 void __iomem *port_mmio = ahci_port_base(ap); 1510 int pmp = sata_srst_pmp(link); 1511 int rc; 1512 u32 irq_sts; 1513 1514 DPRINTK("ENTER\n"); 1515 1516 rc = ahci_do_softreset(link, class, pmp, deadline, 1517 ahci_bad_pmp_check_ready); 1518 1519 /* 1520 * Soft reset fails with IPMS set when PMP is enabled but 1521 * SATA HDD/ODD is connected to SATA port, do soft reset 1522 * again to port 0. 1523 */ 1524 if (rc == -EIO) { 1525 irq_sts = readl(port_mmio + PORT_IRQ_STAT); 1526 if (irq_sts & PORT_IRQ_BAD_PMP) { 1527 ata_link_warn(link, 1528 "applying PMP SRST workaround " 1529 "and retrying\n"); 1530 rc = ahci_do_softreset(link, class, 0, deadline, 1531 ahci_check_ready); 1532 } 1533 } 1534 1535 return rc; 1536 } 1537 1538 int ahci_do_hardreset(struct ata_link *link, unsigned int *class, 1539 unsigned long deadline, bool *online) 1540 { 1541 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1542 struct ata_port *ap = link->ap; 1543 struct ahci_port_priv *pp = ap->private_data; 1544 struct ahci_host_priv *hpriv = ap->host->private_data; 1545 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1546 struct ata_taskfile tf; 1547 int rc; 1548 1549 DPRINTK("ENTER\n"); 1550 1551 hpriv->stop_engine(ap); 1552 1553 /* clear D2H reception area to properly wait for D2H FIS */ 1554 ata_tf_init(link->device, &tf); 1555 tf.command = ATA_BUSY; 1556 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1557 1558 rc = sata_link_hardreset(link, timing, deadline, online, 1559 ahci_check_ready); 1560 1561 hpriv->start_engine(ap); 1562 1563 if (*online) 1564 *class = ahci_dev_classify(ap); 1565 1566 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1567 return rc; 1568 } 1569 EXPORT_SYMBOL_GPL(ahci_do_hardreset); 1570 1571 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1572 unsigned long deadline) 1573 { 1574 bool online; 1575 1576 return ahci_do_hardreset(link, class, deadline, &online); 1577 } 1578 1579 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1580 { 1581 struct ata_port *ap = link->ap; 1582 void __iomem *port_mmio = ahci_port_base(ap); 1583 u32 new_tmp, tmp; 1584 1585 ata_std_postreset(link, class); 1586 1587 /* Make sure port's ATAPI bit is set appropriately */ 1588 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1589 if (*class == ATA_DEV_ATAPI) 1590 new_tmp |= PORT_CMD_ATAPI; 1591 else 1592 new_tmp &= ~PORT_CMD_ATAPI; 1593 if (new_tmp != tmp) { 1594 writel(new_tmp, port_mmio + PORT_CMD); 1595 readl(port_mmio + PORT_CMD); /* flush */ 1596 } 1597 } 1598 1599 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1600 { 1601 struct scatterlist *sg; 1602 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1603 unsigned int si; 1604 1605 VPRINTK("ENTER\n"); 1606 1607 /* 1608 * Next, the S/G list. 1609 */ 1610 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1611 dma_addr_t addr = sg_dma_address(sg); 1612 u32 sg_len = sg_dma_len(sg); 1613 1614 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1615 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1616 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1617 } 1618 1619 return si; 1620 } 1621 1622 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1623 { 1624 struct ata_port *ap = qc->ap; 1625 struct ahci_port_priv *pp = ap->private_data; 1626 1627 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1628 return ata_std_qc_defer(qc); 1629 else 1630 return sata_pmp_qc_defer_cmd_switch(qc); 1631 } 1632 1633 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc) 1634 { 1635 struct ata_port *ap = qc->ap; 1636 struct ahci_port_priv *pp = ap->private_data; 1637 int is_atapi = ata_is_atapi(qc->tf.protocol); 1638 void *cmd_tbl; 1639 u32 opts; 1640 const u32 cmd_fis_len = 5; /* five dwords */ 1641 unsigned int n_elem; 1642 1643 /* 1644 * Fill in command table information. First, the header, 1645 * a SATA Register - Host to Device command FIS. 1646 */ 1647 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; 1648 1649 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1650 if (is_atapi) { 1651 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1652 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1653 } 1654 1655 n_elem = 0; 1656 if (qc->flags & ATA_QCFLAG_DMAMAP) 1657 n_elem = ahci_fill_sg(qc, cmd_tbl); 1658 1659 /* 1660 * Fill in command slot information. 1661 */ 1662 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1663 if (qc->tf.flags & ATA_TFLAG_WRITE) 1664 opts |= AHCI_CMD_WRITE; 1665 if (is_atapi) 1666 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1667 1668 ahci_fill_cmd_slot(pp, qc->hw_tag, opts); 1669 1670 return AC_ERR_OK; 1671 } 1672 1673 static void ahci_fbs_dec_intr(struct ata_port *ap) 1674 { 1675 struct ahci_port_priv *pp = ap->private_data; 1676 void __iomem *port_mmio = ahci_port_base(ap); 1677 u32 fbs = readl(port_mmio + PORT_FBS); 1678 int retries = 3; 1679 1680 DPRINTK("ENTER\n"); 1681 BUG_ON(!pp->fbs_enabled); 1682 1683 /* time to wait for DEC is not specified by AHCI spec, 1684 * add a retry loop for safety. 1685 */ 1686 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1687 fbs = readl(port_mmio + PORT_FBS); 1688 while ((fbs & PORT_FBS_DEC) && retries--) { 1689 udelay(1); 1690 fbs = readl(port_mmio + PORT_FBS); 1691 } 1692 1693 if (fbs & PORT_FBS_DEC) 1694 dev_err(ap->host->dev, "failed to clear device error\n"); 1695 } 1696 1697 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1698 { 1699 struct ahci_host_priv *hpriv = ap->host->private_data; 1700 struct ahci_port_priv *pp = ap->private_data; 1701 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1702 struct ata_link *link = NULL; 1703 struct ata_queued_cmd *active_qc; 1704 struct ata_eh_info *active_ehi; 1705 bool fbs_need_dec = false; 1706 u32 serror; 1707 1708 /* determine active link with error */ 1709 if (pp->fbs_enabled) { 1710 void __iomem *port_mmio = ahci_port_base(ap); 1711 u32 fbs = readl(port_mmio + PORT_FBS); 1712 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1713 1714 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) { 1715 link = &ap->pmp_link[pmp]; 1716 fbs_need_dec = true; 1717 } 1718 1719 } else 1720 ata_for_each_link(link, ap, EDGE) 1721 if (ata_link_active(link)) 1722 break; 1723 1724 if (!link) 1725 link = &ap->link; 1726 1727 active_qc = ata_qc_from_tag(ap, link->active_tag); 1728 active_ehi = &link->eh_info; 1729 1730 /* record irq stat */ 1731 ata_ehi_clear_desc(host_ehi); 1732 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1733 1734 /* AHCI needs SError cleared; otherwise, it might lock up */ 1735 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1736 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1737 host_ehi->serror |= serror; 1738 1739 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1740 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1741 irq_stat &= ~PORT_IRQ_IF_ERR; 1742 1743 if (irq_stat & PORT_IRQ_TF_ERR) { 1744 /* If qc is active, charge it; otherwise, the active 1745 * link. There's no active qc on NCQ errors. It will 1746 * be determined by EH by reading log page 10h. 1747 */ 1748 if (active_qc) 1749 active_qc->err_mask |= AC_ERR_DEV; 1750 else 1751 active_ehi->err_mask |= AC_ERR_DEV; 1752 1753 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1754 host_ehi->serror &= ~SERR_INTERNAL; 1755 } 1756 1757 if (irq_stat & PORT_IRQ_UNK_FIS) { 1758 u32 *unk = pp->rx_fis + RX_FIS_UNK; 1759 1760 active_ehi->err_mask |= AC_ERR_HSM; 1761 active_ehi->action |= ATA_EH_RESET; 1762 ata_ehi_push_desc(active_ehi, 1763 "unknown FIS %08x %08x %08x %08x" , 1764 unk[0], unk[1], unk[2], unk[3]); 1765 } 1766 1767 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1768 active_ehi->err_mask |= AC_ERR_HSM; 1769 active_ehi->action |= ATA_EH_RESET; 1770 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1771 } 1772 1773 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1774 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1775 host_ehi->action |= ATA_EH_RESET; 1776 ata_ehi_push_desc(host_ehi, "host bus error"); 1777 } 1778 1779 if (irq_stat & PORT_IRQ_IF_ERR) { 1780 if (fbs_need_dec) 1781 active_ehi->err_mask |= AC_ERR_DEV; 1782 else { 1783 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1784 host_ehi->action |= ATA_EH_RESET; 1785 } 1786 1787 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1788 } 1789 1790 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1791 ata_ehi_hotplugged(host_ehi); 1792 ata_ehi_push_desc(host_ehi, "%s", 1793 irq_stat & PORT_IRQ_CONNECT ? 1794 "connection status changed" : "PHY RDY changed"); 1795 } 1796 1797 /* okay, let's hand over to EH */ 1798 1799 if (irq_stat & PORT_IRQ_FREEZE) 1800 ata_port_freeze(ap); 1801 else if (fbs_need_dec) { 1802 ata_link_abort(link); 1803 ahci_fbs_dec_intr(ap); 1804 } else 1805 ata_port_abort(ap); 1806 } 1807 1808 static void ahci_handle_port_interrupt(struct ata_port *ap, 1809 void __iomem *port_mmio, u32 status) 1810 { 1811 struct ata_eh_info *ehi = &ap->link.eh_info; 1812 struct ahci_port_priv *pp = ap->private_data; 1813 struct ahci_host_priv *hpriv = ap->host->private_data; 1814 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1815 u32 qc_active = 0; 1816 int rc; 1817 1818 /* ignore BAD_PMP while resetting */ 1819 if (unlikely(resetting)) 1820 status &= ~PORT_IRQ_BAD_PMP; 1821 1822 if (sata_lpm_ignore_phy_events(&ap->link)) { 1823 status &= ~PORT_IRQ_PHYRDY; 1824 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1825 } 1826 1827 if (unlikely(status & PORT_IRQ_ERROR)) { 1828 ahci_error_intr(ap, status); 1829 return; 1830 } 1831 1832 if (status & PORT_IRQ_SDB_FIS) { 1833 /* If SNotification is available, leave notification 1834 * handling to sata_async_notification(). If not, 1835 * emulate it by snooping SDB FIS RX area. 1836 * 1837 * Snooping FIS RX area is probably cheaper than 1838 * poking SNotification but some constrollers which 1839 * implement SNotification, ICH9 for example, don't 1840 * store AN SDB FIS into receive area. 1841 */ 1842 if (hpriv->cap & HOST_CAP_SNTF) 1843 sata_async_notification(ap); 1844 else { 1845 /* If the 'N' bit in word 0 of the FIS is set, 1846 * we just received asynchronous notification. 1847 * Tell libata about it. 1848 * 1849 * Lack of SNotification should not appear in 1850 * ahci 1.2, so the workaround is unnecessary 1851 * when FBS is enabled. 1852 */ 1853 if (pp->fbs_enabled) 1854 WARN_ON_ONCE(1); 1855 else { 1856 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1857 u32 f0 = le32_to_cpu(f[0]); 1858 if (f0 & (1 << 15)) 1859 sata_async_notification(ap); 1860 } 1861 } 1862 } 1863 1864 /* pp->active_link is not reliable once FBS is enabled, both 1865 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1866 * NCQ and non-NCQ commands may be in flight at the same time. 1867 */ 1868 if (pp->fbs_enabled) { 1869 if (ap->qc_active) { 1870 qc_active = readl(port_mmio + PORT_SCR_ACT); 1871 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1872 } 1873 } else { 1874 /* pp->active_link is valid iff any command is in flight */ 1875 if (ap->qc_active && pp->active_link->sactive) 1876 qc_active = readl(port_mmio + PORT_SCR_ACT); 1877 else 1878 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1879 } 1880 1881 1882 rc = ata_qc_complete_multiple(ap, qc_active); 1883 1884 /* while resetting, invalid completions are expected */ 1885 if (unlikely(rc < 0 && !resetting)) { 1886 ehi->err_mask |= AC_ERR_HSM; 1887 ehi->action |= ATA_EH_RESET; 1888 ata_port_freeze(ap); 1889 } 1890 } 1891 1892 static void ahci_port_intr(struct ata_port *ap) 1893 { 1894 void __iomem *port_mmio = ahci_port_base(ap); 1895 u32 status; 1896 1897 status = readl(port_mmio + PORT_IRQ_STAT); 1898 writel(status, port_mmio + PORT_IRQ_STAT); 1899 1900 ahci_handle_port_interrupt(ap, port_mmio, status); 1901 } 1902 1903 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) 1904 { 1905 struct ata_port *ap = dev_instance; 1906 void __iomem *port_mmio = ahci_port_base(ap); 1907 u32 status; 1908 1909 VPRINTK("ENTER\n"); 1910 1911 status = readl(port_mmio + PORT_IRQ_STAT); 1912 writel(status, port_mmio + PORT_IRQ_STAT); 1913 1914 spin_lock(ap->lock); 1915 ahci_handle_port_interrupt(ap, port_mmio, status); 1916 spin_unlock(ap->lock); 1917 1918 VPRINTK("EXIT\n"); 1919 1920 return IRQ_HANDLED; 1921 } 1922 1923 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) 1924 { 1925 unsigned int i, handled = 0; 1926 1927 for (i = 0; i < host->n_ports; i++) { 1928 struct ata_port *ap; 1929 1930 if (!(irq_masked & (1 << i))) 1931 continue; 1932 1933 ap = host->ports[i]; 1934 if (ap) { 1935 ahci_port_intr(ap); 1936 VPRINTK("port %u\n", i); 1937 } else { 1938 VPRINTK("port %u (no irq)\n", i); 1939 if (ata_ratelimit()) 1940 dev_warn(host->dev, 1941 "interrupt on disabled port %u\n", i); 1942 } 1943 1944 handled = 1; 1945 } 1946 1947 return handled; 1948 } 1949 EXPORT_SYMBOL_GPL(ahci_handle_port_intr); 1950 1951 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) 1952 { 1953 struct ata_host *host = dev_instance; 1954 struct ahci_host_priv *hpriv; 1955 unsigned int rc = 0; 1956 void __iomem *mmio; 1957 u32 irq_stat, irq_masked; 1958 1959 VPRINTK("ENTER\n"); 1960 1961 hpriv = host->private_data; 1962 mmio = hpriv->mmio; 1963 1964 /* sigh. 0xffffffff is a valid return from h/w */ 1965 irq_stat = readl(mmio + HOST_IRQ_STAT); 1966 if (!irq_stat) 1967 return IRQ_NONE; 1968 1969 irq_masked = irq_stat & hpriv->port_map; 1970 1971 spin_lock(&host->lock); 1972 1973 rc = ahci_handle_port_intr(host, irq_masked); 1974 1975 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1976 * it should be cleared after all the port events are cleared; 1977 * otherwise, it will raise a spurious interrupt after each 1978 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1979 * information. 1980 * 1981 * Also, use the unmasked value to clear interrupt as spurious 1982 * pending event on a dummy port might cause screaming IRQ. 1983 */ 1984 writel(irq_stat, mmio + HOST_IRQ_STAT); 1985 1986 spin_unlock(&host->lock); 1987 1988 VPRINTK("EXIT\n"); 1989 1990 return IRQ_RETVAL(rc); 1991 } 1992 1993 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1994 { 1995 struct ata_port *ap = qc->ap; 1996 void __iomem *port_mmio = ahci_port_base(ap); 1997 struct ahci_port_priv *pp = ap->private_data; 1998 1999 /* Keep track of the currently active link. It will be used 2000 * in completion path to determine whether NCQ phase is in 2001 * progress. 2002 */ 2003 pp->active_link = qc->dev->link; 2004 2005 if (ata_is_ncq(qc->tf.protocol)) 2006 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT); 2007 2008 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 2009 u32 fbs = readl(port_mmio + PORT_FBS); 2010 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 2011 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 2012 writel(fbs, port_mmio + PORT_FBS); 2013 pp->fbs_last_dev = qc->dev->link->pmp; 2014 } 2015 2016 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE); 2017 2018 ahci_sw_activity(qc->dev->link); 2019 2020 return 0; 2021 } 2022 EXPORT_SYMBOL_GPL(ahci_qc_issue); 2023 2024 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 2025 { 2026 struct ahci_port_priv *pp = qc->ap->private_data; 2027 u8 *rx_fis = pp->rx_fis; 2028 2029 if (pp->fbs_enabled) 2030 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 2031 2032 /* 2033 * After a successful execution of an ATA PIO data-in command, 2034 * the device doesn't send D2H Reg FIS to update the TF and 2035 * the host should take TF and E_Status from the preceding PIO 2036 * Setup FIS. 2037 */ 2038 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 2039 !(qc->flags & ATA_QCFLAG_FAILED)) { 2040 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 2041 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 2042 } else 2043 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 2044 2045 return true; 2046 } 2047 2048 static void ahci_freeze(struct ata_port *ap) 2049 { 2050 void __iomem *port_mmio = ahci_port_base(ap); 2051 2052 /* turn IRQ off */ 2053 writel(0, port_mmio + PORT_IRQ_MASK); 2054 } 2055 2056 static void ahci_thaw(struct ata_port *ap) 2057 { 2058 struct ahci_host_priv *hpriv = ap->host->private_data; 2059 void __iomem *mmio = hpriv->mmio; 2060 void __iomem *port_mmio = ahci_port_base(ap); 2061 u32 tmp; 2062 struct ahci_port_priv *pp = ap->private_data; 2063 2064 /* clear IRQ */ 2065 tmp = readl(port_mmio + PORT_IRQ_STAT); 2066 writel(tmp, port_mmio + PORT_IRQ_STAT); 2067 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 2068 2069 /* turn IRQ back on */ 2070 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2071 } 2072 2073 void ahci_error_handler(struct ata_port *ap) 2074 { 2075 struct ahci_host_priv *hpriv = ap->host->private_data; 2076 2077 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 2078 /* restart engine */ 2079 hpriv->stop_engine(ap); 2080 hpriv->start_engine(ap); 2081 } 2082 2083 sata_pmp_error_handler(ap); 2084 2085 if (!ata_dev_enabled(ap->link.device)) 2086 hpriv->stop_engine(ap); 2087 } 2088 EXPORT_SYMBOL_GPL(ahci_error_handler); 2089 2090 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 2091 { 2092 struct ata_port *ap = qc->ap; 2093 2094 /* make DMA engine forget about the failed command */ 2095 if (qc->flags & ATA_QCFLAG_FAILED) 2096 ahci_kick_engine(ap); 2097 } 2098 2099 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep) 2100 { 2101 struct ahci_host_priv *hpriv = ap->host->private_data; 2102 void __iomem *port_mmio = ahci_port_base(ap); 2103 struct ata_device *dev = ap->link.device; 2104 u32 devslp, dm, dito, mdat, deto, dito_conf; 2105 int rc; 2106 unsigned int err_mask; 2107 2108 devslp = readl(port_mmio + PORT_DEVSLP); 2109 if (!(devslp & PORT_DEVSLP_DSP)) { 2110 dev_info(ap->host->dev, "port does not support device sleep\n"); 2111 return; 2112 } 2113 2114 /* disable device sleep */ 2115 if (!sleep) { 2116 if (devslp & PORT_DEVSLP_ADSE) { 2117 writel(devslp & ~PORT_DEVSLP_ADSE, 2118 port_mmio + PORT_DEVSLP); 2119 err_mask = ata_dev_set_feature(dev, 2120 SETFEATURES_SATA_DISABLE, 2121 SATA_DEVSLP); 2122 if (err_mask && err_mask != AC_ERR_DEV) 2123 ata_dev_warn(dev, "failed to disable DEVSLP\n"); 2124 } 2125 return; 2126 } 2127 2128 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET; 2129 dito = devslp_idle_timeout / (dm + 1); 2130 if (dito > 0x3ff) 2131 dito = 0x3ff; 2132 2133 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF; 2134 2135 /* device sleep was already enabled and same dito */ 2136 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito)) 2137 return; 2138 2139 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */ 2140 rc = hpriv->stop_engine(ap); 2141 if (rc) 2142 return; 2143 2144 /* Use the nominal value 10 ms if the read MDAT is zero, 2145 * the nominal value of DETO is 20 ms. 2146 */ 2147 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] & 2148 ATA_LOG_DEVSLP_VALID_MASK) { 2149 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] & 2150 ATA_LOG_DEVSLP_MDAT_MASK; 2151 if (!mdat) 2152 mdat = 10; 2153 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO]; 2154 if (!deto) 2155 deto = 20; 2156 } else { 2157 mdat = 10; 2158 deto = 20; 2159 } 2160 2161 /* Make dito, mdat, deto bits to 0s */ 2162 devslp &= ~GENMASK_ULL(24, 2); 2163 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) | 2164 (mdat << PORT_DEVSLP_MDAT_OFFSET) | 2165 (deto << PORT_DEVSLP_DETO_OFFSET) | 2166 PORT_DEVSLP_ADSE); 2167 writel(devslp, port_mmio + PORT_DEVSLP); 2168 2169 hpriv->start_engine(ap); 2170 2171 /* enable device sleep feature for the drive */ 2172 err_mask = ata_dev_set_feature(dev, 2173 SETFEATURES_SATA_ENABLE, 2174 SATA_DEVSLP); 2175 if (err_mask && err_mask != AC_ERR_DEV) 2176 ata_dev_warn(dev, "failed to enable DEVSLP\n"); 2177 } 2178 2179 static void ahci_enable_fbs(struct ata_port *ap) 2180 { 2181 struct ahci_host_priv *hpriv = ap->host->private_data; 2182 struct ahci_port_priv *pp = ap->private_data; 2183 void __iomem *port_mmio = ahci_port_base(ap); 2184 u32 fbs; 2185 int rc; 2186 2187 if (!pp->fbs_supported) 2188 return; 2189 2190 fbs = readl(port_mmio + PORT_FBS); 2191 if (fbs & PORT_FBS_EN) { 2192 pp->fbs_enabled = true; 2193 pp->fbs_last_dev = -1; /* initialization */ 2194 return; 2195 } 2196 2197 rc = hpriv->stop_engine(ap); 2198 if (rc) 2199 return; 2200 2201 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 2202 fbs = readl(port_mmio + PORT_FBS); 2203 if (fbs & PORT_FBS_EN) { 2204 dev_info(ap->host->dev, "FBS is enabled\n"); 2205 pp->fbs_enabled = true; 2206 pp->fbs_last_dev = -1; /* initialization */ 2207 } else 2208 dev_err(ap->host->dev, "Failed to enable FBS\n"); 2209 2210 hpriv->start_engine(ap); 2211 } 2212 2213 static void ahci_disable_fbs(struct ata_port *ap) 2214 { 2215 struct ahci_host_priv *hpriv = ap->host->private_data; 2216 struct ahci_port_priv *pp = ap->private_data; 2217 void __iomem *port_mmio = ahci_port_base(ap); 2218 u32 fbs; 2219 int rc; 2220 2221 if (!pp->fbs_supported) 2222 return; 2223 2224 fbs = readl(port_mmio + PORT_FBS); 2225 if ((fbs & PORT_FBS_EN) == 0) { 2226 pp->fbs_enabled = false; 2227 return; 2228 } 2229 2230 rc = hpriv->stop_engine(ap); 2231 if (rc) 2232 return; 2233 2234 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 2235 fbs = readl(port_mmio + PORT_FBS); 2236 if (fbs & PORT_FBS_EN) 2237 dev_err(ap->host->dev, "Failed to disable FBS\n"); 2238 else { 2239 dev_info(ap->host->dev, "FBS is disabled\n"); 2240 pp->fbs_enabled = false; 2241 } 2242 2243 hpriv->start_engine(ap); 2244 } 2245 2246 static void ahci_pmp_attach(struct ata_port *ap) 2247 { 2248 void __iomem *port_mmio = ahci_port_base(ap); 2249 struct ahci_port_priv *pp = ap->private_data; 2250 u32 cmd; 2251 2252 cmd = readl(port_mmio + PORT_CMD); 2253 cmd |= PORT_CMD_PMP; 2254 writel(cmd, port_mmio + PORT_CMD); 2255 2256 ahci_enable_fbs(ap); 2257 2258 pp->intr_mask |= PORT_IRQ_BAD_PMP; 2259 2260 /* 2261 * We must not change the port interrupt mask register if the 2262 * port is marked frozen, the value in pp->intr_mask will be 2263 * restored later when the port is thawed. 2264 * 2265 * Note that during initialization, the port is marked as 2266 * frozen since the irq handler is not yet registered. 2267 */ 2268 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2269 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2270 } 2271 2272 static void ahci_pmp_detach(struct ata_port *ap) 2273 { 2274 void __iomem *port_mmio = ahci_port_base(ap); 2275 struct ahci_port_priv *pp = ap->private_data; 2276 u32 cmd; 2277 2278 ahci_disable_fbs(ap); 2279 2280 cmd = readl(port_mmio + PORT_CMD); 2281 cmd &= ~PORT_CMD_PMP; 2282 writel(cmd, port_mmio + PORT_CMD); 2283 2284 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 2285 2286 /* see comment above in ahci_pmp_attach() */ 2287 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 2288 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 2289 } 2290 2291 int ahci_port_resume(struct ata_port *ap) 2292 { 2293 ahci_rpm_get_port(ap); 2294 2295 ahci_power_up(ap); 2296 ahci_start_port(ap); 2297 2298 if (sata_pmp_attached(ap)) 2299 ahci_pmp_attach(ap); 2300 else 2301 ahci_pmp_detach(ap); 2302 2303 return 0; 2304 } 2305 EXPORT_SYMBOL_GPL(ahci_port_resume); 2306 2307 #ifdef CONFIG_PM 2308 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2309 { 2310 const char *emsg = NULL; 2311 int rc; 2312 2313 rc = ahci_deinit_port(ap, &emsg); 2314 if (rc == 0) 2315 ahci_power_down(ap); 2316 else { 2317 ata_port_err(ap, "%s (%d)\n", emsg, rc); 2318 ata_port_freeze(ap); 2319 } 2320 2321 ahci_rpm_put_port(ap); 2322 return rc; 2323 } 2324 #endif 2325 2326 static int ahci_port_start(struct ata_port *ap) 2327 { 2328 struct ahci_host_priv *hpriv = ap->host->private_data; 2329 struct device *dev = ap->host->dev; 2330 struct ahci_port_priv *pp; 2331 void *mem; 2332 dma_addr_t mem_dma; 2333 size_t dma_sz, rx_fis_sz; 2334 2335 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2336 if (!pp) 2337 return -ENOMEM; 2338 2339 if (ap->host->n_ports > 1) { 2340 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL); 2341 if (!pp->irq_desc) { 2342 devm_kfree(dev, pp); 2343 return -ENOMEM; 2344 } 2345 snprintf(pp->irq_desc, 8, 2346 "%s%d", dev_driver_string(dev), ap->port_no); 2347 } 2348 2349 /* check FBS capability */ 2350 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2351 void __iomem *port_mmio = ahci_port_base(ap); 2352 u32 cmd = readl(port_mmio + PORT_CMD); 2353 if (cmd & PORT_CMD_FBSCP) 2354 pp->fbs_supported = true; 2355 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2356 dev_info(dev, "port %d can do FBS, forcing FBSCP\n", 2357 ap->port_no); 2358 pp->fbs_supported = true; 2359 } else 2360 dev_warn(dev, "port %d is not capable of FBS\n", 2361 ap->port_no); 2362 } 2363 2364 if (pp->fbs_supported) { 2365 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2366 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2367 } else { 2368 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2369 rx_fis_sz = AHCI_RX_FIS_SZ; 2370 } 2371 2372 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2373 if (!mem) 2374 return -ENOMEM; 2375 2376 /* 2377 * First item in chunk of DMA memory: 32-slot command table, 2378 * 32 bytes each in size 2379 */ 2380 pp->cmd_slot = mem; 2381 pp->cmd_slot_dma = mem_dma; 2382 2383 mem += AHCI_CMD_SLOT_SZ; 2384 mem_dma += AHCI_CMD_SLOT_SZ; 2385 2386 /* 2387 * Second item: Received-FIS area 2388 */ 2389 pp->rx_fis = mem; 2390 pp->rx_fis_dma = mem_dma; 2391 2392 mem += rx_fis_sz; 2393 mem_dma += rx_fis_sz; 2394 2395 /* 2396 * Third item: data area for storing a single command 2397 * and its scatter-gather table 2398 */ 2399 pp->cmd_tbl = mem; 2400 pp->cmd_tbl_dma = mem_dma; 2401 2402 /* 2403 * Save off initial list of interrupts to be enabled. 2404 * This could be changed later 2405 */ 2406 pp->intr_mask = DEF_PORT_IRQ; 2407 2408 /* 2409 * Switch to per-port locking in case each port has its own MSI vector. 2410 */ 2411 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2412 spin_lock_init(&pp->lock); 2413 ap->lock = &pp->lock; 2414 } 2415 2416 ap->private_data = pp; 2417 2418 /* engage engines, captain */ 2419 return ahci_port_resume(ap); 2420 } 2421 2422 static void ahci_port_stop(struct ata_port *ap) 2423 { 2424 const char *emsg = NULL; 2425 struct ahci_host_priv *hpriv = ap->host->private_data; 2426 void __iomem *host_mmio = hpriv->mmio; 2427 int rc; 2428 2429 /* de-initialize port */ 2430 rc = ahci_deinit_port(ap, &emsg); 2431 if (rc) 2432 ata_port_warn(ap, "%s (%d)\n", emsg, rc); 2433 2434 /* 2435 * Clear GHC.IS to prevent stuck INTx after disabling MSI and 2436 * re-enabling INTx. 2437 */ 2438 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT); 2439 2440 ahci_rpm_put_port(ap); 2441 } 2442 2443 void ahci_print_info(struct ata_host *host, const char *scc_s) 2444 { 2445 struct ahci_host_priv *hpriv = host->private_data; 2446 u32 vers, cap, cap2, impl, speed; 2447 const char *speed_s; 2448 2449 vers = hpriv->version; 2450 cap = hpriv->cap; 2451 cap2 = hpriv->cap2; 2452 impl = hpriv->port_map; 2453 2454 speed = (cap >> 20) & 0xf; 2455 if (speed == 1) 2456 speed_s = "1.5"; 2457 else if (speed == 2) 2458 speed_s = "3"; 2459 else if (speed == 3) 2460 speed_s = "6"; 2461 else 2462 speed_s = "?"; 2463 2464 dev_info(host->dev, 2465 "AHCI %02x%02x.%02x%02x " 2466 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2467 , 2468 2469 (vers >> 24) & 0xff, 2470 (vers >> 16) & 0xff, 2471 (vers >> 8) & 0xff, 2472 vers & 0xff, 2473 2474 ((cap >> 8) & 0x1f) + 1, 2475 (cap & 0x1f) + 1, 2476 speed_s, 2477 impl, 2478 scc_s); 2479 2480 dev_info(host->dev, 2481 "flags: " 2482 "%s%s%s%s%s%s%s" 2483 "%s%s%s%s%s%s%s" 2484 "%s%s%s%s%s%s%s" 2485 "%s%s\n" 2486 , 2487 2488 cap & HOST_CAP_64 ? "64bit " : "", 2489 cap & HOST_CAP_NCQ ? "ncq " : "", 2490 cap & HOST_CAP_SNTF ? "sntf " : "", 2491 cap & HOST_CAP_MPS ? "ilck " : "", 2492 cap & HOST_CAP_SSS ? "stag " : "", 2493 cap & HOST_CAP_ALPM ? "pm " : "", 2494 cap & HOST_CAP_LED ? "led " : "", 2495 cap & HOST_CAP_CLO ? "clo " : "", 2496 cap & HOST_CAP_ONLY ? "only " : "", 2497 cap & HOST_CAP_PMP ? "pmp " : "", 2498 cap & HOST_CAP_FBS ? "fbs " : "", 2499 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2500 cap & HOST_CAP_SSC ? "slum " : "", 2501 cap & HOST_CAP_PART ? "part " : "", 2502 cap & HOST_CAP_CCC ? "ccc " : "", 2503 cap & HOST_CAP_EMS ? "ems " : "", 2504 cap & HOST_CAP_SXS ? "sxs " : "", 2505 cap2 & HOST_CAP2_DESO ? "deso " : "", 2506 cap2 & HOST_CAP2_SADM ? "sadm " : "", 2507 cap2 & HOST_CAP2_SDS ? "sds " : "", 2508 cap2 & HOST_CAP2_APST ? "apst " : "", 2509 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2510 cap2 & HOST_CAP2_BOH ? "boh " : "" 2511 ); 2512 } 2513 EXPORT_SYMBOL_GPL(ahci_print_info); 2514 2515 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2516 struct ata_port_info *pi) 2517 { 2518 u8 messages; 2519 void __iomem *mmio = hpriv->mmio; 2520 u32 em_loc = readl(mmio + HOST_EM_LOC); 2521 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2522 2523 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2524 return; 2525 2526 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2527 2528 if (messages) { 2529 /* store em_loc */ 2530 hpriv->em_loc = ((em_loc >> 16) * 4); 2531 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2532 hpriv->em_msg_type = messages; 2533 pi->flags |= ATA_FLAG_EM; 2534 if (!(em_ctl & EM_CTL_ALHD)) 2535 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2536 } 2537 } 2538 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2539 2540 static int ahci_host_activate_multi_irqs(struct ata_host *host, 2541 struct scsi_host_template *sht) 2542 { 2543 struct ahci_host_priv *hpriv = host->private_data; 2544 int i, rc; 2545 2546 rc = ata_host_start(host); 2547 if (rc) 2548 return rc; 2549 /* 2550 * Requests IRQs according to AHCI-1.1 when multiple MSIs were 2551 * allocated. That is one MSI per port, starting from @irq. 2552 */ 2553 for (i = 0; i < host->n_ports; i++) { 2554 struct ahci_port_priv *pp = host->ports[i]->private_data; 2555 int irq = hpriv->get_irq_vector(host, i); 2556 2557 /* Do not receive interrupts sent by dummy ports */ 2558 if (!pp) { 2559 disable_irq(irq); 2560 continue; 2561 } 2562 2563 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard, 2564 0, pp->irq_desc, host->ports[i]); 2565 2566 if (rc) 2567 return rc; 2568 ata_port_desc(host->ports[i], "irq %d", irq); 2569 } 2570 2571 return ata_host_register(host, sht); 2572 } 2573 2574 /** 2575 * ahci_host_activate - start AHCI host, request IRQs and register it 2576 * @host: target ATA host 2577 * @sht: scsi_host_template to use when registering the host 2578 * 2579 * LOCKING: 2580 * Inherited from calling layer (may sleep). 2581 * 2582 * RETURNS: 2583 * 0 on success, -errno otherwise. 2584 */ 2585 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht) 2586 { 2587 struct ahci_host_priv *hpriv = host->private_data; 2588 int irq = hpriv->irq; 2589 int rc; 2590 2591 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) { 2592 if (hpriv->irq_handler && 2593 hpriv->irq_handler != ahci_single_level_irq_intr) 2594 dev_warn(host->dev, 2595 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n"); 2596 if (!hpriv->get_irq_vector) { 2597 dev_err(host->dev, 2598 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n"); 2599 return -EIO; 2600 } 2601 2602 rc = ahci_host_activate_multi_irqs(host, sht); 2603 } else { 2604 rc = ata_host_activate(host, irq, hpriv->irq_handler, 2605 IRQF_SHARED, sht); 2606 } 2607 2608 2609 return rc; 2610 } 2611 EXPORT_SYMBOL_GPL(ahci_host_activate); 2612 2613 MODULE_AUTHOR("Jeff Garzik"); 2614 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2615 MODULE_LICENSE("GPL"); 2616