1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <scsi/scsi_host.h> 45 #include <scsi/scsi_cmnd.h> 46 #include <linux/libata.h> 47 #include "ahci.h" 48 49 static int ahci_skip_host_reset; 50 int ahci_ignore_sss; 51 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 52 53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 55 56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 58 59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 60 unsigned hints); 61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 63 size_t size); 64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 65 ssize_t size); 66 67 68 69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 71 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73 static int ahci_port_start(struct ata_port *ap); 74 static void ahci_port_stop(struct ata_port *ap); 75 static void ahci_qc_prep(struct ata_queued_cmd *qc); 76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77 static void ahci_freeze(struct ata_port *ap); 78 static void ahci_thaw(struct ata_port *ap); 79 static void ahci_enable_fbs(struct ata_port *ap); 80 static void ahci_disable_fbs(struct ata_port *ap); 81 static void ahci_pmp_attach(struct ata_port *ap); 82 static void ahci_pmp_detach(struct ata_port *ap); 83 static int ahci_softreset(struct ata_link *link, unsigned int *class, 84 unsigned long deadline); 85 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 86 unsigned long deadline); 87 static void ahci_postreset(struct ata_link *link, unsigned int *class); 88 static void ahci_error_handler(struct ata_port *ap); 89 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 90 static void ahci_dev_config(struct ata_device *dev); 91 #ifdef CONFIG_PM 92 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 93 #endif 94 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 95 static ssize_t ahci_activity_store(struct ata_device *dev, 96 enum sw_activity val); 97 static void ahci_init_sw_activity(struct ata_link *link); 98 99 static ssize_t ahci_show_host_caps(struct device *dev, 100 struct device_attribute *attr, char *buf); 101 static ssize_t ahci_show_host_cap2(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static ssize_t ahci_show_host_version(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_port_cmd(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_read_em_buffer(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_store_em_buffer(struct device *dev, 110 struct device_attribute *attr, 111 const char *buf, size_t size); 112 static ssize_t ahci_show_em_supported(struct device *dev, 113 struct device_attribute *attr, char *buf); 114 115 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 116 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 117 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 118 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 119 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 120 ahci_read_em_buffer, ahci_store_em_buffer); 121 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 122 123 struct device_attribute *ahci_shost_attrs[] = { 124 &dev_attr_link_power_management_policy, 125 &dev_attr_em_message_type, 126 &dev_attr_em_message, 127 &dev_attr_ahci_host_caps, 128 &dev_attr_ahci_host_cap2, 129 &dev_attr_ahci_host_version, 130 &dev_attr_ahci_port_cmd, 131 &dev_attr_em_buffer, 132 &dev_attr_em_message_supported, 133 NULL 134 }; 135 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 136 137 struct device_attribute *ahci_sdev_attrs[] = { 138 &dev_attr_sw_activity, 139 &dev_attr_unload_heads, 140 NULL 141 }; 142 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 143 144 struct ata_port_operations ahci_ops = { 145 .inherits = &sata_pmp_port_ops, 146 147 .qc_defer = ahci_pmp_qc_defer, 148 .qc_prep = ahci_qc_prep, 149 .qc_issue = ahci_qc_issue, 150 .qc_fill_rtf = ahci_qc_fill_rtf, 151 152 .freeze = ahci_freeze, 153 .thaw = ahci_thaw, 154 .softreset = ahci_softreset, 155 .hardreset = ahci_hardreset, 156 .postreset = ahci_postreset, 157 .pmp_softreset = ahci_softreset, 158 .error_handler = ahci_error_handler, 159 .post_internal_cmd = ahci_post_internal_cmd, 160 .dev_config = ahci_dev_config, 161 162 .scr_read = ahci_scr_read, 163 .scr_write = ahci_scr_write, 164 .pmp_attach = ahci_pmp_attach, 165 .pmp_detach = ahci_pmp_detach, 166 167 .set_lpm = ahci_set_lpm, 168 .em_show = ahci_led_show, 169 .em_store = ahci_led_store, 170 .sw_activity_show = ahci_activity_show, 171 .sw_activity_store = ahci_activity_store, 172 #ifdef CONFIG_PM 173 .port_suspend = ahci_port_suspend, 174 .port_resume = ahci_port_resume, 175 #endif 176 .port_start = ahci_port_start, 177 .port_stop = ahci_port_stop, 178 }; 179 EXPORT_SYMBOL_GPL(ahci_ops); 180 181 int ahci_em_messages = 1; 182 EXPORT_SYMBOL_GPL(ahci_em_messages); 183 module_param(ahci_em_messages, int, 0444); 184 /* add other LED protocol types when they become supported */ 185 MODULE_PARM_DESC(ahci_em_messages, 186 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 187 188 static void ahci_enable_ahci(void __iomem *mmio) 189 { 190 int i; 191 u32 tmp; 192 193 /* turn on AHCI_EN */ 194 tmp = readl(mmio + HOST_CTL); 195 if (tmp & HOST_AHCI_EN) 196 return; 197 198 /* Some controllers need AHCI_EN to be written multiple times. 199 * Try a few times before giving up. 200 */ 201 for (i = 0; i < 5; i++) { 202 tmp |= HOST_AHCI_EN; 203 writel(tmp, mmio + HOST_CTL); 204 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 205 if (tmp & HOST_AHCI_EN) 206 return; 207 msleep(10); 208 } 209 210 WARN_ON(1); 211 } 212 213 static ssize_t ahci_show_host_caps(struct device *dev, 214 struct device_attribute *attr, char *buf) 215 { 216 struct Scsi_Host *shost = class_to_shost(dev); 217 struct ata_port *ap = ata_shost_to_port(shost); 218 struct ahci_host_priv *hpriv = ap->host->private_data; 219 220 return sprintf(buf, "%x\n", hpriv->cap); 221 } 222 223 static ssize_t ahci_show_host_cap2(struct device *dev, 224 struct device_attribute *attr, char *buf) 225 { 226 struct Scsi_Host *shost = class_to_shost(dev); 227 struct ata_port *ap = ata_shost_to_port(shost); 228 struct ahci_host_priv *hpriv = ap->host->private_data; 229 230 return sprintf(buf, "%x\n", hpriv->cap2); 231 } 232 233 static ssize_t ahci_show_host_version(struct device *dev, 234 struct device_attribute *attr, char *buf) 235 { 236 struct Scsi_Host *shost = class_to_shost(dev); 237 struct ata_port *ap = ata_shost_to_port(shost); 238 struct ahci_host_priv *hpriv = ap->host->private_data; 239 void __iomem *mmio = hpriv->mmio; 240 241 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); 242 } 243 244 static ssize_t ahci_show_port_cmd(struct device *dev, 245 struct device_attribute *attr, char *buf) 246 { 247 struct Scsi_Host *shost = class_to_shost(dev); 248 struct ata_port *ap = ata_shost_to_port(shost); 249 void __iomem *port_mmio = ahci_port_base(ap); 250 251 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 252 } 253 254 static ssize_t ahci_read_em_buffer(struct device *dev, 255 struct device_attribute *attr, char *buf) 256 { 257 struct Scsi_Host *shost = class_to_shost(dev); 258 struct ata_port *ap = ata_shost_to_port(shost); 259 struct ahci_host_priv *hpriv = ap->host->private_data; 260 void __iomem *mmio = hpriv->mmio; 261 void __iomem *em_mmio = mmio + hpriv->em_loc; 262 u32 em_ctl, msg; 263 unsigned long flags; 264 size_t count; 265 int i; 266 267 spin_lock_irqsave(ap->lock, flags); 268 269 em_ctl = readl(mmio + HOST_EM_CTL); 270 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 271 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 272 spin_unlock_irqrestore(ap->lock, flags); 273 return -EINVAL; 274 } 275 276 if (!(em_ctl & EM_CTL_MR)) { 277 spin_unlock_irqrestore(ap->lock, flags); 278 return -EAGAIN; 279 } 280 281 if (!(em_ctl & EM_CTL_SMB)) 282 em_mmio += hpriv->em_buf_sz; 283 284 count = hpriv->em_buf_sz; 285 286 /* the count should not be larger than PAGE_SIZE */ 287 if (count > PAGE_SIZE) { 288 if (printk_ratelimit()) 289 ata_port_printk(ap, KERN_WARNING, 290 "EM read buffer size too large: " 291 "buffer size %u, page size %lu\n", 292 hpriv->em_buf_sz, PAGE_SIZE); 293 count = PAGE_SIZE; 294 } 295 296 for (i = 0; i < count; i += 4) { 297 msg = readl(em_mmio + i); 298 buf[i] = msg & 0xff; 299 buf[i + 1] = (msg >> 8) & 0xff; 300 buf[i + 2] = (msg >> 16) & 0xff; 301 buf[i + 3] = (msg >> 24) & 0xff; 302 } 303 304 spin_unlock_irqrestore(ap->lock, flags); 305 306 return i; 307 } 308 309 static ssize_t ahci_store_em_buffer(struct device *dev, 310 struct device_attribute *attr, 311 const char *buf, size_t size) 312 { 313 struct Scsi_Host *shost = class_to_shost(dev); 314 struct ata_port *ap = ata_shost_to_port(shost); 315 struct ahci_host_priv *hpriv = ap->host->private_data; 316 void __iomem *mmio = hpriv->mmio; 317 void __iomem *em_mmio = mmio + hpriv->em_loc; 318 const unsigned char *msg_buf = buf; 319 u32 em_ctl, msg; 320 unsigned long flags; 321 int i; 322 323 /* check size validity */ 324 if (!(ap->flags & ATA_FLAG_EM) || 325 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 326 size % 4 || size > hpriv->em_buf_sz) 327 return -EINVAL; 328 329 spin_lock_irqsave(ap->lock, flags); 330 331 em_ctl = readl(mmio + HOST_EM_CTL); 332 if (em_ctl & EM_CTL_TM) { 333 spin_unlock_irqrestore(ap->lock, flags); 334 return -EBUSY; 335 } 336 337 for (i = 0; i < size; i += 4) { 338 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 339 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 340 writel(msg, em_mmio + i); 341 } 342 343 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 344 345 spin_unlock_irqrestore(ap->lock, flags); 346 347 return size; 348 } 349 350 static ssize_t ahci_show_em_supported(struct device *dev, 351 struct device_attribute *attr, char *buf) 352 { 353 struct Scsi_Host *shost = class_to_shost(dev); 354 struct ata_port *ap = ata_shost_to_port(shost); 355 struct ahci_host_priv *hpriv = ap->host->private_data; 356 void __iomem *mmio = hpriv->mmio; 357 u32 em_ctl; 358 359 em_ctl = readl(mmio + HOST_EM_CTL); 360 361 return sprintf(buf, "%s%s%s%s\n", 362 em_ctl & EM_CTL_LED ? "led " : "", 363 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 364 em_ctl & EM_CTL_SES ? "ses-2 " : "", 365 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 366 } 367 368 /** 369 * ahci_save_initial_config - Save and fixup initial config values 370 * @dev: target AHCI device 371 * @hpriv: host private area to store config values 372 * @force_port_map: force port map to a specified value 373 * @mask_port_map: mask out particular bits from port map 374 * 375 * Some registers containing configuration info might be setup by 376 * BIOS and might be cleared on reset. This function saves the 377 * initial values of those registers into @hpriv such that they 378 * can be restored after controller reset. 379 * 380 * If inconsistent, config values are fixed up by this function. 381 * 382 * LOCKING: 383 * None. 384 */ 385 void ahci_save_initial_config(struct device *dev, 386 struct ahci_host_priv *hpriv, 387 unsigned int force_port_map, 388 unsigned int mask_port_map) 389 { 390 void __iomem *mmio = hpriv->mmio; 391 u32 cap, cap2, vers, port_map; 392 int i; 393 394 /* make sure AHCI mode is enabled before accessing CAP */ 395 ahci_enable_ahci(mmio); 396 397 /* Values prefixed with saved_ are written back to host after 398 * reset. Values without are used for driver operation. 399 */ 400 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 401 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 402 403 /* CAP2 register is only defined for AHCI 1.2 and later */ 404 vers = readl(mmio + HOST_VERSION); 405 if ((vers >> 16) > 1 || 406 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 407 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 408 else 409 hpriv->saved_cap2 = cap2 = 0; 410 411 /* some chips have errata preventing 64bit use */ 412 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 413 dev_printk(KERN_INFO, dev, 414 "controller can't do 64bit DMA, forcing 32bit\n"); 415 cap &= ~HOST_CAP_64; 416 } 417 418 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 419 dev_printk(KERN_INFO, dev, 420 "controller can't do NCQ, turning off CAP_NCQ\n"); 421 cap &= ~HOST_CAP_NCQ; 422 } 423 424 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 425 dev_printk(KERN_INFO, dev, 426 "controller can do NCQ, turning on CAP_NCQ\n"); 427 cap |= HOST_CAP_NCQ; 428 } 429 430 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 431 dev_printk(KERN_INFO, dev, 432 "controller can't do PMP, turning off CAP_PMP\n"); 433 cap &= ~HOST_CAP_PMP; 434 } 435 436 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 437 dev_printk(KERN_INFO, dev, 438 "controller can't do SNTF, turning off CAP_SNTF\n"); 439 cap &= ~HOST_CAP_SNTF; 440 } 441 442 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 443 dev_printk(KERN_INFO, dev, 444 "controller can do FBS, turning on CAP_FBS\n"); 445 cap |= HOST_CAP_FBS; 446 } 447 448 if (force_port_map && port_map != force_port_map) { 449 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n", 450 port_map, force_port_map); 451 port_map = force_port_map; 452 } 453 454 if (mask_port_map) { 455 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n", 456 port_map, 457 port_map & mask_port_map); 458 port_map &= mask_port_map; 459 } 460 461 /* cross check port_map and cap.n_ports */ 462 if (port_map) { 463 int map_ports = 0; 464 465 for (i = 0; i < AHCI_MAX_PORTS; i++) 466 if (port_map & (1 << i)) 467 map_ports++; 468 469 /* If PI has more ports than n_ports, whine, clear 470 * port_map and let it be generated from n_ports. 471 */ 472 if (map_ports > ahci_nr_ports(cap)) { 473 dev_printk(KERN_WARNING, dev, 474 "implemented port map (0x%x) contains more " 475 "ports than nr_ports (%u), using nr_ports\n", 476 port_map, ahci_nr_ports(cap)); 477 port_map = 0; 478 } 479 } 480 481 /* fabricate port_map from cap.nr_ports */ 482 if (!port_map) { 483 port_map = (1 << ahci_nr_ports(cap)) - 1; 484 dev_printk(KERN_WARNING, dev, 485 "forcing PORTS_IMPL to 0x%x\n", port_map); 486 487 /* write the fixed up value to the PI register */ 488 hpriv->saved_port_map = port_map; 489 } 490 491 /* record values to use during operation */ 492 hpriv->cap = cap; 493 hpriv->cap2 = cap2; 494 hpriv->port_map = port_map; 495 } 496 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 497 498 /** 499 * ahci_restore_initial_config - Restore initial config 500 * @host: target ATA host 501 * 502 * Restore initial config stored by ahci_save_initial_config(). 503 * 504 * LOCKING: 505 * None. 506 */ 507 static void ahci_restore_initial_config(struct ata_host *host) 508 { 509 struct ahci_host_priv *hpriv = host->private_data; 510 void __iomem *mmio = hpriv->mmio; 511 512 writel(hpriv->saved_cap, mmio + HOST_CAP); 513 if (hpriv->saved_cap2) 514 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 515 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 516 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 517 } 518 519 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 520 { 521 static const int offset[] = { 522 [SCR_STATUS] = PORT_SCR_STAT, 523 [SCR_CONTROL] = PORT_SCR_CTL, 524 [SCR_ERROR] = PORT_SCR_ERR, 525 [SCR_ACTIVE] = PORT_SCR_ACT, 526 [SCR_NOTIFICATION] = PORT_SCR_NTF, 527 }; 528 struct ahci_host_priv *hpriv = ap->host->private_data; 529 530 if (sc_reg < ARRAY_SIZE(offset) && 531 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 532 return offset[sc_reg]; 533 return 0; 534 } 535 536 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 537 { 538 void __iomem *port_mmio = ahci_port_base(link->ap); 539 int offset = ahci_scr_offset(link->ap, sc_reg); 540 541 if (offset) { 542 *val = readl(port_mmio + offset); 543 return 0; 544 } 545 return -EINVAL; 546 } 547 548 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 549 { 550 void __iomem *port_mmio = ahci_port_base(link->ap); 551 int offset = ahci_scr_offset(link->ap, sc_reg); 552 553 if (offset) { 554 writel(val, port_mmio + offset); 555 return 0; 556 } 557 return -EINVAL; 558 } 559 560 void ahci_start_engine(struct ata_port *ap) 561 { 562 void __iomem *port_mmio = ahci_port_base(ap); 563 u32 tmp; 564 u8 status; 565 566 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 567 568 /* 569 * At end of section 10.1 of AHCI spec (rev 1.3), it states 570 * Software shall not set PxCMD.ST to 1 until it is determined 571 * that a functoinal device is present on the port as determined by 572 * PxTFD.STS.BSY=0, PxTFD.STS.DRQ=0 and PxSSTS.DET=3h 573 * 574 * Even though most AHCI host controllers work without this check, 575 * specific controller will fail under this condition 576 */ 577 if (status & (ATA_BUSY | ATA_DRQ)) 578 return; 579 else { 580 ahci_scr_read(&ap->link, SCR_STATUS, &tmp); 581 582 if ((tmp & 0xf) != 0x3) 583 return; 584 } 585 586 /* start DMA */ 587 tmp = readl(port_mmio + PORT_CMD); 588 tmp |= PORT_CMD_START; 589 writel(tmp, port_mmio + PORT_CMD); 590 readl(port_mmio + PORT_CMD); /* flush */ 591 } 592 EXPORT_SYMBOL_GPL(ahci_start_engine); 593 594 int ahci_stop_engine(struct ata_port *ap) 595 { 596 void __iomem *port_mmio = ahci_port_base(ap); 597 u32 tmp; 598 599 tmp = readl(port_mmio + PORT_CMD); 600 601 /* check if the HBA is idle */ 602 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 603 return 0; 604 605 /* setting HBA to idle */ 606 tmp &= ~PORT_CMD_START; 607 writel(tmp, port_mmio + PORT_CMD); 608 609 /* wait for engine to stop. This could be as long as 500 msec */ 610 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 611 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 612 if (tmp & PORT_CMD_LIST_ON) 613 return -EIO; 614 615 return 0; 616 } 617 EXPORT_SYMBOL_GPL(ahci_stop_engine); 618 619 static void ahci_start_fis_rx(struct ata_port *ap) 620 { 621 void __iomem *port_mmio = ahci_port_base(ap); 622 struct ahci_host_priv *hpriv = ap->host->private_data; 623 struct ahci_port_priv *pp = ap->private_data; 624 u32 tmp; 625 626 /* set FIS registers */ 627 if (hpriv->cap & HOST_CAP_64) 628 writel((pp->cmd_slot_dma >> 16) >> 16, 629 port_mmio + PORT_LST_ADDR_HI); 630 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 631 632 if (hpriv->cap & HOST_CAP_64) 633 writel((pp->rx_fis_dma >> 16) >> 16, 634 port_mmio + PORT_FIS_ADDR_HI); 635 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 636 637 /* enable FIS reception */ 638 tmp = readl(port_mmio + PORT_CMD); 639 tmp |= PORT_CMD_FIS_RX; 640 writel(tmp, port_mmio + PORT_CMD); 641 642 /* flush */ 643 readl(port_mmio + PORT_CMD); 644 } 645 646 static int ahci_stop_fis_rx(struct ata_port *ap) 647 { 648 void __iomem *port_mmio = ahci_port_base(ap); 649 u32 tmp; 650 651 /* disable FIS reception */ 652 tmp = readl(port_mmio + PORT_CMD); 653 tmp &= ~PORT_CMD_FIS_RX; 654 writel(tmp, port_mmio + PORT_CMD); 655 656 /* wait for completion, spec says 500ms, give it 1000 */ 657 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 658 PORT_CMD_FIS_ON, 10, 1000); 659 if (tmp & PORT_CMD_FIS_ON) 660 return -EBUSY; 661 662 return 0; 663 } 664 665 static void ahci_power_up(struct ata_port *ap) 666 { 667 struct ahci_host_priv *hpriv = ap->host->private_data; 668 void __iomem *port_mmio = ahci_port_base(ap); 669 u32 cmd; 670 671 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 672 673 /* spin up device */ 674 if (hpriv->cap & HOST_CAP_SSS) { 675 cmd |= PORT_CMD_SPIN_UP; 676 writel(cmd, port_mmio + PORT_CMD); 677 } 678 679 /* wake up link */ 680 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 681 } 682 683 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 684 unsigned int hints) 685 { 686 struct ata_port *ap = link->ap; 687 struct ahci_host_priv *hpriv = ap->host->private_data; 688 struct ahci_port_priv *pp = ap->private_data; 689 void __iomem *port_mmio = ahci_port_base(ap); 690 691 if (policy != ATA_LPM_MAX_POWER) { 692 /* 693 * Disable interrupts on Phy Ready. This keeps us from 694 * getting woken up due to spurious phy ready 695 * interrupts. 696 */ 697 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 698 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 699 700 sata_link_scr_lpm(link, policy, false); 701 } 702 703 if (hpriv->cap & HOST_CAP_ALPM) { 704 u32 cmd = readl(port_mmio + PORT_CMD); 705 706 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 707 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 708 cmd |= PORT_CMD_ICC_ACTIVE; 709 710 writel(cmd, port_mmio + PORT_CMD); 711 readl(port_mmio + PORT_CMD); 712 713 /* wait 10ms to be sure we've come out of LPM state */ 714 ata_msleep(ap, 10); 715 } else { 716 cmd |= PORT_CMD_ALPE; 717 if (policy == ATA_LPM_MIN_POWER) 718 cmd |= PORT_CMD_ASP; 719 720 /* write out new cmd value */ 721 writel(cmd, port_mmio + PORT_CMD); 722 } 723 } 724 725 if (policy == ATA_LPM_MAX_POWER) { 726 sata_link_scr_lpm(link, policy, false); 727 728 /* turn PHYRDY IRQ back on */ 729 pp->intr_mask |= PORT_IRQ_PHYRDY; 730 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 731 } 732 733 return 0; 734 } 735 736 #ifdef CONFIG_PM 737 static void ahci_power_down(struct ata_port *ap) 738 { 739 struct ahci_host_priv *hpriv = ap->host->private_data; 740 void __iomem *port_mmio = ahci_port_base(ap); 741 u32 cmd, scontrol; 742 743 if (!(hpriv->cap & HOST_CAP_SSS)) 744 return; 745 746 /* put device into listen mode, first set PxSCTL.DET to 0 */ 747 scontrol = readl(port_mmio + PORT_SCR_CTL); 748 scontrol &= ~0xf; 749 writel(scontrol, port_mmio + PORT_SCR_CTL); 750 751 /* then set PxCMD.SUD to 0 */ 752 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 753 cmd &= ~PORT_CMD_SPIN_UP; 754 writel(cmd, port_mmio + PORT_CMD); 755 } 756 #endif 757 758 static void ahci_start_port(struct ata_port *ap) 759 { 760 struct ahci_port_priv *pp = ap->private_data; 761 struct ata_link *link; 762 struct ahci_em_priv *emp; 763 ssize_t rc; 764 int i; 765 766 /* enable FIS reception */ 767 ahci_start_fis_rx(ap); 768 769 /* enable DMA */ 770 ahci_start_engine(ap); 771 772 /* turn on LEDs */ 773 if (ap->flags & ATA_FLAG_EM) { 774 ata_for_each_link(link, ap, EDGE) { 775 emp = &pp->em_priv[link->pmp]; 776 777 /* EM Transmit bit maybe busy during init */ 778 for (i = 0; i < EM_MAX_RETRY; i++) { 779 rc = ahci_transmit_led_message(ap, 780 emp->led_state, 781 4); 782 if (rc == -EBUSY) 783 ata_msleep(ap, 1); 784 else 785 break; 786 } 787 } 788 } 789 790 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 791 ata_for_each_link(link, ap, EDGE) 792 ahci_init_sw_activity(link); 793 794 } 795 796 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 797 { 798 int rc; 799 800 /* disable DMA */ 801 rc = ahci_stop_engine(ap); 802 if (rc) { 803 *emsg = "failed to stop engine"; 804 return rc; 805 } 806 807 /* disable FIS reception */ 808 rc = ahci_stop_fis_rx(ap); 809 if (rc) { 810 *emsg = "failed stop FIS RX"; 811 return rc; 812 } 813 814 return 0; 815 } 816 817 int ahci_reset_controller(struct ata_host *host) 818 { 819 struct ahci_host_priv *hpriv = host->private_data; 820 void __iomem *mmio = hpriv->mmio; 821 u32 tmp; 822 823 /* we must be in AHCI mode, before using anything 824 * AHCI-specific, such as HOST_RESET. 825 */ 826 ahci_enable_ahci(mmio); 827 828 /* global controller reset */ 829 if (!ahci_skip_host_reset) { 830 tmp = readl(mmio + HOST_CTL); 831 if ((tmp & HOST_RESET) == 0) { 832 writel(tmp | HOST_RESET, mmio + HOST_CTL); 833 readl(mmio + HOST_CTL); /* flush */ 834 } 835 836 /* 837 * to perform host reset, OS should set HOST_RESET 838 * and poll until this bit is read to be "0". 839 * reset must complete within 1 second, or 840 * the hardware should be considered fried. 841 */ 842 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 843 HOST_RESET, 10, 1000); 844 845 if (tmp & HOST_RESET) { 846 dev_printk(KERN_ERR, host->dev, 847 "controller reset failed (0x%x)\n", tmp); 848 return -EIO; 849 } 850 851 /* turn on AHCI mode */ 852 ahci_enable_ahci(mmio); 853 854 /* Some registers might be cleared on reset. Restore 855 * initial values. 856 */ 857 ahci_restore_initial_config(host); 858 } else 859 dev_printk(KERN_INFO, host->dev, 860 "skipping global host reset\n"); 861 862 return 0; 863 } 864 EXPORT_SYMBOL_GPL(ahci_reset_controller); 865 866 static void ahci_sw_activity(struct ata_link *link) 867 { 868 struct ata_port *ap = link->ap; 869 struct ahci_port_priv *pp = ap->private_data; 870 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 871 872 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 873 return; 874 875 emp->activity++; 876 if (!timer_pending(&emp->timer)) 877 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 878 } 879 880 static void ahci_sw_activity_blink(unsigned long arg) 881 { 882 struct ata_link *link = (struct ata_link *)arg; 883 struct ata_port *ap = link->ap; 884 struct ahci_port_priv *pp = ap->private_data; 885 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 886 unsigned long led_message = emp->led_state; 887 u32 activity_led_state; 888 unsigned long flags; 889 890 led_message &= EM_MSG_LED_VALUE; 891 led_message |= ap->port_no | (link->pmp << 8); 892 893 /* check to see if we've had activity. If so, 894 * toggle state of LED and reset timer. If not, 895 * turn LED to desired idle state. 896 */ 897 spin_lock_irqsave(ap->lock, flags); 898 if (emp->saved_activity != emp->activity) { 899 emp->saved_activity = emp->activity; 900 /* get the current LED state */ 901 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 902 903 if (activity_led_state) 904 activity_led_state = 0; 905 else 906 activity_led_state = 1; 907 908 /* clear old state */ 909 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 910 911 /* toggle state */ 912 led_message |= (activity_led_state << 16); 913 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 914 } else { 915 /* switch to idle */ 916 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 917 if (emp->blink_policy == BLINK_OFF) 918 led_message |= (1 << 16); 919 } 920 spin_unlock_irqrestore(ap->lock, flags); 921 ahci_transmit_led_message(ap, led_message, 4); 922 } 923 924 static void ahci_init_sw_activity(struct ata_link *link) 925 { 926 struct ata_port *ap = link->ap; 927 struct ahci_port_priv *pp = ap->private_data; 928 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 929 930 /* init activity stats, setup timer */ 931 emp->saved_activity = emp->activity = 0; 932 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 933 934 /* check our blink policy and set flag for link if it's enabled */ 935 if (emp->blink_policy) 936 link->flags |= ATA_LFLAG_SW_ACTIVITY; 937 } 938 939 int ahci_reset_em(struct ata_host *host) 940 { 941 struct ahci_host_priv *hpriv = host->private_data; 942 void __iomem *mmio = hpriv->mmio; 943 u32 em_ctl; 944 945 em_ctl = readl(mmio + HOST_EM_CTL); 946 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 947 return -EINVAL; 948 949 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 950 return 0; 951 } 952 EXPORT_SYMBOL_GPL(ahci_reset_em); 953 954 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 955 ssize_t size) 956 { 957 struct ahci_host_priv *hpriv = ap->host->private_data; 958 struct ahci_port_priv *pp = ap->private_data; 959 void __iomem *mmio = hpriv->mmio; 960 u32 em_ctl; 961 u32 message[] = {0, 0}; 962 unsigned long flags; 963 int pmp; 964 struct ahci_em_priv *emp; 965 966 /* get the slot number from the message */ 967 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 968 if (pmp < EM_MAX_SLOTS) 969 emp = &pp->em_priv[pmp]; 970 else 971 return -EINVAL; 972 973 spin_lock_irqsave(ap->lock, flags); 974 975 /* 976 * if we are still busy transmitting a previous message, 977 * do not allow 978 */ 979 em_ctl = readl(mmio + HOST_EM_CTL); 980 if (em_ctl & EM_CTL_TM) { 981 spin_unlock_irqrestore(ap->lock, flags); 982 return -EBUSY; 983 } 984 985 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 986 /* 987 * create message header - this is all zero except for 988 * the message size, which is 4 bytes. 989 */ 990 message[0] |= (4 << 8); 991 992 /* ignore 0:4 of byte zero, fill in port info yourself */ 993 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 994 995 /* write message to EM_LOC */ 996 writel(message[0], mmio + hpriv->em_loc); 997 writel(message[1], mmio + hpriv->em_loc+4); 998 999 /* 1000 * tell hardware to transmit the message 1001 */ 1002 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1003 } 1004 1005 /* save off new led state for port/slot */ 1006 emp->led_state = state; 1007 1008 spin_unlock_irqrestore(ap->lock, flags); 1009 return size; 1010 } 1011 1012 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1013 { 1014 struct ahci_port_priv *pp = ap->private_data; 1015 struct ata_link *link; 1016 struct ahci_em_priv *emp; 1017 int rc = 0; 1018 1019 ata_for_each_link(link, ap, EDGE) { 1020 emp = &pp->em_priv[link->pmp]; 1021 rc += sprintf(buf, "%lx\n", emp->led_state); 1022 } 1023 return rc; 1024 } 1025 1026 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1027 size_t size) 1028 { 1029 int state; 1030 int pmp; 1031 struct ahci_port_priv *pp = ap->private_data; 1032 struct ahci_em_priv *emp; 1033 1034 state = simple_strtoul(buf, NULL, 0); 1035 1036 /* get the slot number from the message */ 1037 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1038 if (pmp < EM_MAX_SLOTS) 1039 emp = &pp->em_priv[pmp]; 1040 else 1041 return -EINVAL; 1042 1043 /* mask off the activity bits if we are in sw_activity 1044 * mode, user should turn off sw_activity before setting 1045 * activity led through em_message 1046 */ 1047 if (emp->blink_policy) 1048 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1049 1050 return ahci_transmit_led_message(ap, state, size); 1051 } 1052 1053 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1054 { 1055 struct ata_link *link = dev->link; 1056 struct ata_port *ap = link->ap; 1057 struct ahci_port_priv *pp = ap->private_data; 1058 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1059 u32 port_led_state = emp->led_state; 1060 1061 /* save the desired Activity LED behavior */ 1062 if (val == OFF) { 1063 /* clear LFLAG */ 1064 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1065 1066 /* set the LED to OFF */ 1067 port_led_state &= EM_MSG_LED_VALUE_OFF; 1068 port_led_state |= (ap->port_no | (link->pmp << 8)); 1069 ahci_transmit_led_message(ap, port_led_state, 4); 1070 } else { 1071 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1072 if (val == BLINK_OFF) { 1073 /* set LED to ON for idle */ 1074 port_led_state &= EM_MSG_LED_VALUE_OFF; 1075 port_led_state |= (ap->port_no | (link->pmp << 8)); 1076 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1077 ahci_transmit_led_message(ap, port_led_state, 4); 1078 } 1079 } 1080 emp->blink_policy = val; 1081 return 0; 1082 } 1083 1084 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1085 { 1086 struct ata_link *link = dev->link; 1087 struct ata_port *ap = link->ap; 1088 struct ahci_port_priv *pp = ap->private_data; 1089 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1090 1091 /* display the saved value of activity behavior for this 1092 * disk. 1093 */ 1094 return sprintf(buf, "%d\n", emp->blink_policy); 1095 } 1096 1097 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1098 int port_no, void __iomem *mmio, 1099 void __iomem *port_mmio) 1100 { 1101 const char *emsg = NULL; 1102 int rc; 1103 u32 tmp; 1104 1105 /* make sure port is not active */ 1106 rc = ahci_deinit_port(ap, &emsg); 1107 if (rc) 1108 dev_warn(dev, "%s (%d)\n", emsg, rc); 1109 1110 /* clear SError */ 1111 tmp = readl(port_mmio + PORT_SCR_ERR); 1112 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1113 writel(tmp, port_mmio + PORT_SCR_ERR); 1114 1115 /* clear port IRQ */ 1116 tmp = readl(port_mmio + PORT_IRQ_STAT); 1117 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1118 if (tmp) 1119 writel(tmp, port_mmio + PORT_IRQ_STAT); 1120 1121 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1122 } 1123 1124 void ahci_init_controller(struct ata_host *host) 1125 { 1126 struct ahci_host_priv *hpriv = host->private_data; 1127 void __iomem *mmio = hpriv->mmio; 1128 int i; 1129 void __iomem *port_mmio; 1130 u32 tmp; 1131 1132 for (i = 0; i < host->n_ports; i++) { 1133 struct ata_port *ap = host->ports[i]; 1134 1135 port_mmio = ahci_port_base(ap); 1136 if (ata_port_is_dummy(ap)) 1137 continue; 1138 1139 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1140 } 1141 1142 tmp = readl(mmio + HOST_CTL); 1143 VPRINTK("HOST_CTL 0x%x\n", tmp); 1144 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1145 tmp = readl(mmio + HOST_CTL); 1146 VPRINTK("HOST_CTL 0x%x\n", tmp); 1147 } 1148 EXPORT_SYMBOL_GPL(ahci_init_controller); 1149 1150 static void ahci_dev_config(struct ata_device *dev) 1151 { 1152 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1153 1154 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1155 dev->max_sectors = 255; 1156 ata_dev_printk(dev, KERN_INFO, 1157 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1158 } 1159 } 1160 1161 static unsigned int ahci_dev_classify(struct ata_port *ap) 1162 { 1163 void __iomem *port_mmio = ahci_port_base(ap); 1164 struct ata_taskfile tf; 1165 u32 tmp; 1166 1167 tmp = readl(port_mmio + PORT_SIG); 1168 tf.lbah = (tmp >> 24) & 0xff; 1169 tf.lbam = (tmp >> 16) & 0xff; 1170 tf.lbal = (tmp >> 8) & 0xff; 1171 tf.nsect = (tmp) & 0xff; 1172 1173 return ata_dev_classify(&tf); 1174 } 1175 1176 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1177 u32 opts) 1178 { 1179 dma_addr_t cmd_tbl_dma; 1180 1181 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1182 1183 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1184 pp->cmd_slot[tag].status = 0; 1185 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1186 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1187 } 1188 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1189 1190 int ahci_kick_engine(struct ata_port *ap) 1191 { 1192 void __iomem *port_mmio = ahci_port_base(ap); 1193 struct ahci_host_priv *hpriv = ap->host->private_data; 1194 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1195 u32 tmp; 1196 int busy, rc; 1197 1198 /* stop engine */ 1199 rc = ahci_stop_engine(ap); 1200 if (rc) 1201 goto out_restart; 1202 1203 /* need to do CLO? 1204 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1205 */ 1206 busy = status & (ATA_BUSY | ATA_DRQ); 1207 if (!busy && !sata_pmp_attached(ap)) { 1208 rc = 0; 1209 goto out_restart; 1210 } 1211 1212 if (!(hpriv->cap & HOST_CAP_CLO)) { 1213 rc = -EOPNOTSUPP; 1214 goto out_restart; 1215 } 1216 1217 /* perform CLO */ 1218 tmp = readl(port_mmio + PORT_CMD); 1219 tmp |= PORT_CMD_CLO; 1220 writel(tmp, port_mmio + PORT_CMD); 1221 1222 rc = 0; 1223 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1224 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1225 if (tmp & PORT_CMD_CLO) 1226 rc = -EIO; 1227 1228 /* restart engine */ 1229 out_restart: 1230 ahci_start_engine(ap); 1231 return rc; 1232 } 1233 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1234 1235 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1236 struct ata_taskfile *tf, int is_cmd, u16 flags, 1237 unsigned long timeout_msec) 1238 { 1239 const u32 cmd_fis_len = 5; /* five dwords */ 1240 struct ahci_port_priv *pp = ap->private_data; 1241 void __iomem *port_mmio = ahci_port_base(ap); 1242 u8 *fis = pp->cmd_tbl; 1243 u32 tmp; 1244 1245 /* prep the command */ 1246 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1247 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1248 1249 /* issue & wait */ 1250 writel(1, port_mmio + PORT_CMD_ISSUE); 1251 1252 if (timeout_msec) { 1253 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1254 0x1, 0x1, 1, timeout_msec); 1255 if (tmp & 0x1) { 1256 ahci_kick_engine(ap); 1257 return -EBUSY; 1258 } 1259 } else 1260 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1261 1262 return 0; 1263 } 1264 1265 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1266 int pmp, unsigned long deadline, 1267 int (*check_ready)(struct ata_link *link)) 1268 { 1269 struct ata_port *ap = link->ap; 1270 struct ahci_host_priv *hpriv = ap->host->private_data; 1271 const char *reason = NULL; 1272 unsigned long now, msecs; 1273 struct ata_taskfile tf; 1274 int rc; 1275 1276 DPRINTK("ENTER\n"); 1277 1278 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1279 rc = ahci_kick_engine(ap); 1280 if (rc && rc != -EOPNOTSUPP) 1281 ata_link_printk(link, KERN_WARNING, 1282 "failed to reset engine (errno=%d)\n", rc); 1283 1284 ata_tf_init(link->device, &tf); 1285 1286 /* issue the first D2H Register FIS */ 1287 msecs = 0; 1288 now = jiffies; 1289 if (time_after(deadline, now)) 1290 msecs = jiffies_to_msecs(deadline - now); 1291 1292 tf.ctl |= ATA_SRST; 1293 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1294 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1295 rc = -EIO; 1296 reason = "1st FIS failed"; 1297 goto fail; 1298 } 1299 1300 /* spec says at least 5us, but be generous and sleep for 1ms */ 1301 ata_msleep(ap, 1); 1302 1303 /* issue the second D2H Register FIS */ 1304 tf.ctl &= ~ATA_SRST; 1305 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1306 1307 /* wait for link to become ready */ 1308 rc = ata_wait_after_reset(link, deadline, check_ready); 1309 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1310 /* 1311 * Workaround for cases where link online status can't 1312 * be trusted. Treat device readiness timeout as link 1313 * offline. 1314 */ 1315 ata_link_printk(link, KERN_INFO, 1316 "device not ready, treating as offline\n"); 1317 *class = ATA_DEV_NONE; 1318 } else if (rc) { 1319 /* link occupied, -ENODEV too is an error */ 1320 reason = "device not ready"; 1321 goto fail; 1322 } else 1323 *class = ahci_dev_classify(ap); 1324 1325 DPRINTK("EXIT, class=%u\n", *class); 1326 return 0; 1327 1328 fail: 1329 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 1330 return rc; 1331 } 1332 1333 int ahci_check_ready(struct ata_link *link) 1334 { 1335 void __iomem *port_mmio = ahci_port_base(link->ap); 1336 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1337 1338 return ata_check_ready(status); 1339 } 1340 EXPORT_SYMBOL_GPL(ahci_check_ready); 1341 1342 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1343 unsigned long deadline) 1344 { 1345 int pmp = sata_srst_pmp(link); 1346 1347 DPRINTK("ENTER\n"); 1348 1349 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1350 } 1351 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1352 1353 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1354 unsigned long deadline) 1355 { 1356 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1357 struct ata_port *ap = link->ap; 1358 struct ahci_port_priv *pp = ap->private_data; 1359 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1360 struct ata_taskfile tf; 1361 bool online; 1362 int rc; 1363 1364 DPRINTK("ENTER\n"); 1365 1366 ahci_stop_engine(ap); 1367 1368 /* clear D2H reception area to properly wait for D2H FIS */ 1369 ata_tf_init(link->device, &tf); 1370 tf.command = 0x80; 1371 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1372 1373 rc = sata_link_hardreset(link, timing, deadline, &online, 1374 ahci_check_ready); 1375 1376 ahci_start_engine(ap); 1377 1378 if (online) 1379 *class = ahci_dev_classify(ap); 1380 1381 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1382 return rc; 1383 } 1384 1385 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1386 { 1387 struct ata_port *ap = link->ap; 1388 void __iomem *port_mmio = ahci_port_base(ap); 1389 u32 new_tmp, tmp; 1390 1391 ata_std_postreset(link, class); 1392 1393 /* Make sure port's ATAPI bit is set appropriately */ 1394 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1395 if (*class == ATA_DEV_ATAPI) 1396 new_tmp |= PORT_CMD_ATAPI; 1397 else 1398 new_tmp &= ~PORT_CMD_ATAPI; 1399 if (new_tmp != tmp) { 1400 writel(new_tmp, port_mmio + PORT_CMD); 1401 readl(port_mmio + PORT_CMD); /* flush */ 1402 } 1403 } 1404 1405 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1406 { 1407 struct scatterlist *sg; 1408 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1409 unsigned int si; 1410 1411 VPRINTK("ENTER\n"); 1412 1413 /* 1414 * Next, the S/G list. 1415 */ 1416 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1417 dma_addr_t addr = sg_dma_address(sg); 1418 u32 sg_len = sg_dma_len(sg); 1419 1420 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1421 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1422 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1423 } 1424 1425 return si; 1426 } 1427 1428 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1429 { 1430 struct ata_port *ap = qc->ap; 1431 struct ahci_port_priv *pp = ap->private_data; 1432 1433 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1434 return ata_std_qc_defer(qc); 1435 else 1436 return sata_pmp_qc_defer_cmd_switch(qc); 1437 } 1438 1439 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1440 { 1441 struct ata_port *ap = qc->ap; 1442 struct ahci_port_priv *pp = ap->private_data; 1443 int is_atapi = ata_is_atapi(qc->tf.protocol); 1444 void *cmd_tbl; 1445 u32 opts; 1446 const u32 cmd_fis_len = 5; /* five dwords */ 1447 unsigned int n_elem; 1448 1449 /* 1450 * Fill in command table information. First, the header, 1451 * a SATA Register - Host to Device command FIS. 1452 */ 1453 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1454 1455 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1456 if (is_atapi) { 1457 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1458 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1459 } 1460 1461 n_elem = 0; 1462 if (qc->flags & ATA_QCFLAG_DMAMAP) 1463 n_elem = ahci_fill_sg(qc, cmd_tbl); 1464 1465 /* 1466 * Fill in command slot information. 1467 */ 1468 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1469 if (qc->tf.flags & ATA_TFLAG_WRITE) 1470 opts |= AHCI_CMD_WRITE; 1471 if (is_atapi) 1472 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1473 1474 ahci_fill_cmd_slot(pp, qc->tag, opts); 1475 } 1476 1477 static void ahci_fbs_dec_intr(struct ata_port *ap) 1478 { 1479 struct ahci_port_priv *pp = ap->private_data; 1480 void __iomem *port_mmio = ahci_port_base(ap); 1481 u32 fbs = readl(port_mmio + PORT_FBS); 1482 int retries = 3; 1483 1484 DPRINTK("ENTER\n"); 1485 BUG_ON(!pp->fbs_enabled); 1486 1487 /* time to wait for DEC is not specified by AHCI spec, 1488 * add a retry loop for safety. 1489 */ 1490 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1491 fbs = readl(port_mmio + PORT_FBS); 1492 while ((fbs & PORT_FBS_DEC) && retries--) { 1493 udelay(1); 1494 fbs = readl(port_mmio + PORT_FBS); 1495 } 1496 1497 if (fbs & PORT_FBS_DEC) 1498 dev_printk(KERN_ERR, ap->host->dev, 1499 "failed to clear device error\n"); 1500 } 1501 1502 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1503 { 1504 struct ahci_host_priv *hpriv = ap->host->private_data; 1505 struct ahci_port_priv *pp = ap->private_data; 1506 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1507 struct ata_link *link = NULL; 1508 struct ata_queued_cmd *active_qc; 1509 struct ata_eh_info *active_ehi; 1510 bool fbs_need_dec = false; 1511 u32 serror; 1512 1513 /* determine active link with error */ 1514 if (pp->fbs_enabled) { 1515 void __iomem *port_mmio = ahci_port_base(ap); 1516 u32 fbs = readl(port_mmio + PORT_FBS); 1517 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1518 1519 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) && 1520 ata_link_online(&ap->pmp_link[pmp])) { 1521 link = &ap->pmp_link[pmp]; 1522 fbs_need_dec = true; 1523 } 1524 1525 } else 1526 ata_for_each_link(link, ap, EDGE) 1527 if (ata_link_active(link)) 1528 break; 1529 1530 if (!link) 1531 link = &ap->link; 1532 1533 active_qc = ata_qc_from_tag(ap, link->active_tag); 1534 active_ehi = &link->eh_info; 1535 1536 /* record irq stat */ 1537 ata_ehi_clear_desc(host_ehi); 1538 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1539 1540 /* AHCI needs SError cleared; otherwise, it might lock up */ 1541 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1542 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1543 host_ehi->serror |= serror; 1544 1545 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1546 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1547 irq_stat &= ~PORT_IRQ_IF_ERR; 1548 1549 if (irq_stat & PORT_IRQ_TF_ERR) { 1550 /* If qc is active, charge it; otherwise, the active 1551 * link. There's no active qc on NCQ errors. It will 1552 * be determined by EH by reading log page 10h. 1553 */ 1554 if (active_qc) 1555 active_qc->err_mask |= AC_ERR_DEV; 1556 else 1557 active_ehi->err_mask |= AC_ERR_DEV; 1558 1559 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1560 host_ehi->serror &= ~SERR_INTERNAL; 1561 } 1562 1563 if (irq_stat & PORT_IRQ_UNK_FIS) { 1564 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 1565 1566 active_ehi->err_mask |= AC_ERR_HSM; 1567 active_ehi->action |= ATA_EH_RESET; 1568 ata_ehi_push_desc(active_ehi, 1569 "unknown FIS %08x %08x %08x %08x" , 1570 unk[0], unk[1], unk[2], unk[3]); 1571 } 1572 1573 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1574 active_ehi->err_mask |= AC_ERR_HSM; 1575 active_ehi->action |= ATA_EH_RESET; 1576 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1577 } 1578 1579 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1580 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1581 host_ehi->action |= ATA_EH_RESET; 1582 ata_ehi_push_desc(host_ehi, "host bus error"); 1583 } 1584 1585 if (irq_stat & PORT_IRQ_IF_ERR) { 1586 if (fbs_need_dec) 1587 active_ehi->err_mask |= AC_ERR_DEV; 1588 else { 1589 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1590 host_ehi->action |= ATA_EH_RESET; 1591 } 1592 1593 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1594 } 1595 1596 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1597 ata_ehi_hotplugged(host_ehi); 1598 ata_ehi_push_desc(host_ehi, "%s", 1599 irq_stat & PORT_IRQ_CONNECT ? 1600 "connection status changed" : "PHY RDY changed"); 1601 } 1602 1603 /* okay, let's hand over to EH */ 1604 1605 if (irq_stat & PORT_IRQ_FREEZE) 1606 ata_port_freeze(ap); 1607 else if (fbs_need_dec) { 1608 ata_link_abort(link); 1609 ahci_fbs_dec_intr(ap); 1610 } else 1611 ata_port_abort(ap); 1612 } 1613 1614 static void ahci_port_intr(struct ata_port *ap) 1615 { 1616 void __iomem *port_mmio = ahci_port_base(ap); 1617 struct ata_eh_info *ehi = &ap->link.eh_info; 1618 struct ahci_port_priv *pp = ap->private_data; 1619 struct ahci_host_priv *hpriv = ap->host->private_data; 1620 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1621 u32 status, qc_active = 0; 1622 int rc; 1623 1624 status = readl(port_mmio + PORT_IRQ_STAT); 1625 writel(status, port_mmio + PORT_IRQ_STAT); 1626 1627 /* ignore BAD_PMP while resetting */ 1628 if (unlikely(resetting)) 1629 status &= ~PORT_IRQ_BAD_PMP; 1630 1631 /* if LPM is enabled, PHYRDY doesn't mean anything */ 1632 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) { 1633 status &= ~PORT_IRQ_PHYRDY; 1634 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1635 } 1636 1637 if (unlikely(status & PORT_IRQ_ERROR)) { 1638 ahci_error_intr(ap, status); 1639 return; 1640 } 1641 1642 if (status & PORT_IRQ_SDB_FIS) { 1643 /* If SNotification is available, leave notification 1644 * handling to sata_async_notification(). If not, 1645 * emulate it by snooping SDB FIS RX area. 1646 * 1647 * Snooping FIS RX area is probably cheaper than 1648 * poking SNotification but some constrollers which 1649 * implement SNotification, ICH9 for example, don't 1650 * store AN SDB FIS into receive area. 1651 */ 1652 if (hpriv->cap & HOST_CAP_SNTF) 1653 sata_async_notification(ap); 1654 else { 1655 /* If the 'N' bit in word 0 of the FIS is set, 1656 * we just received asynchronous notification. 1657 * Tell libata about it. 1658 * 1659 * Lack of SNotification should not appear in 1660 * ahci 1.2, so the workaround is unnecessary 1661 * when FBS is enabled. 1662 */ 1663 if (pp->fbs_enabled) 1664 WARN_ON_ONCE(1); 1665 else { 1666 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1667 u32 f0 = le32_to_cpu(f[0]); 1668 if (f0 & (1 << 15)) 1669 sata_async_notification(ap); 1670 } 1671 } 1672 } 1673 1674 /* pp->active_link is not reliable once FBS is enabled, both 1675 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1676 * NCQ and non-NCQ commands may be in flight at the same time. 1677 */ 1678 if (pp->fbs_enabled) { 1679 if (ap->qc_active) { 1680 qc_active = readl(port_mmio + PORT_SCR_ACT); 1681 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1682 } 1683 } else { 1684 /* pp->active_link is valid iff any command is in flight */ 1685 if (ap->qc_active && pp->active_link->sactive) 1686 qc_active = readl(port_mmio + PORT_SCR_ACT); 1687 else 1688 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1689 } 1690 1691 1692 rc = ata_qc_complete_multiple(ap, qc_active); 1693 1694 /* while resetting, invalid completions are expected */ 1695 if (unlikely(rc < 0 && !resetting)) { 1696 ehi->err_mask |= AC_ERR_HSM; 1697 ehi->action |= ATA_EH_RESET; 1698 ata_port_freeze(ap); 1699 } 1700 } 1701 1702 irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1703 { 1704 struct ata_host *host = dev_instance; 1705 struct ahci_host_priv *hpriv; 1706 unsigned int i, handled = 0; 1707 void __iomem *mmio; 1708 u32 irq_stat, irq_masked; 1709 1710 VPRINTK("ENTER\n"); 1711 1712 hpriv = host->private_data; 1713 mmio = hpriv->mmio; 1714 1715 /* sigh. 0xffffffff is a valid return from h/w */ 1716 irq_stat = readl(mmio + HOST_IRQ_STAT); 1717 if (!irq_stat) 1718 return IRQ_NONE; 1719 1720 irq_masked = irq_stat & hpriv->port_map; 1721 1722 spin_lock(&host->lock); 1723 1724 for (i = 0; i < host->n_ports; i++) { 1725 struct ata_port *ap; 1726 1727 if (!(irq_masked & (1 << i))) 1728 continue; 1729 1730 ap = host->ports[i]; 1731 if (ap) { 1732 ahci_port_intr(ap); 1733 VPRINTK("port %u\n", i); 1734 } else { 1735 VPRINTK("port %u (no irq)\n", i); 1736 if (ata_ratelimit()) 1737 dev_printk(KERN_WARNING, host->dev, 1738 "interrupt on disabled port %u\n", i); 1739 } 1740 1741 handled = 1; 1742 } 1743 1744 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1745 * it should be cleared after all the port events are cleared; 1746 * otherwise, it will raise a spurious interrupt after each 1747 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1748 * information. 1749 * 1750 * Also, use the unmasked value to clear interrupt as spurious 1751 * pending event on a dummy port might cause screaming IRQ. 1752 */ 1753 writel(irq_stat, mmio + HOST_IRQ_STAT); 1754 1755 spin_unlock(&host->lock); 1756 1757 VPRINTK("EXIT\n"); 1758 1759 return IRQ_RETVAL(handled); 1760 } 1761 EXPORT_SYMBOL_GPL(ahci_interrupt); 1762 1763 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1764 { 1765 struct ata_port *ap = qc->ap; 1766 void __iomem *port_mmio = ahci_port_base(ap); 1767 struct ahci_port_priv *pp = ap->private_data; 1768 1769 /* Keep track of the currently active link. It will be used 1770 * in completion path to determine whether NCQ phase is in 1771 * progress. 1772 */ 1773 pp->active_link = qc->dev->link; 1774 1775 if (qc->tf.protocol == ATA_PROT_NCQ) 1776 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1777 1778 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1779 u32 fbs = readl(port_mmio + PORT_FBS); 1780 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1781 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1782 writel(fbs, port_mmio + PORT_FBS); 1783 pp->fbs_last_dev = qc->dev->link->pmp; 1784 } 1785 1786 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1787 1788 ahci_sw_activity(qc->dev->link); 1789 1790 return 0; 1791 } 1792 1793 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1794 { 1795 struct ahci_port_priv *pp = qc->ap->private_data; 1796 u8 *rx_fis = pp->rx_fis; 1797 1798 if (pp->fbs_enabled) 1799 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 1800 1801 /* 1802 * After a successful execution of an ATA PIO data-in command, 1803 * the device doesn't send D2H Reg FIS to update the TF and 1804 * the host should take TF and E_Status from the preceding PIO 1805 * Setup FIS. 1806 */ 1807 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 1808 !(qc->flags & ATA_QCFLAG_FAILED)) { 1809 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 1810 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 1811 } else 1812 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 1813 1814 return true; 1815 } 1816 1817 static void ahci_freeze(struct ata_port *ap) 1818 { 1819 void __iomem *port_mmio = ahci_port_base(ap); 1820 1821 /* turn IRQ off */ 1822 writel(0, port_mmio + PORT_IRQ_MASK); 1823 } 1824 1825 static void ahci_thaw(struct ata_port *ap) 1826 { 1827 struct ahci_host_priv *hpriv = ap->host->private_data; 1828 void __iomem *mmio = hpriv->mmio; 1829 void __iomem *port_mmio = ahci_port_base(ap); 1830 u32 tmp; 1831 struct ahci_port_priv *pp = ap->private_data; 1832 1833 /* clear IRQ */ 1834 tmp = readl(port_mmio + PORT_IRQ_STAT); 1835 writel(tmp, port_mmio + PORT_IRQ_STAT); 1836 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 1837 1838 /* turn IRQ back on */ 1839 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1840 } 1841 1842 static void ahci_error_handler(struct ata_port *ap) 1843 { 1844 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1845 /* restart engine */ 1846 ahci_stop_engine(ap); 1847 ahci_start_engine(ap); 1848 } 1849 1850 sata_pmp_error_handler(ap); 1851 1852 if (!ata_dev_enabled(ap->link.device)) 1853 ahci_stop_engine(ap); 1854 } 1855 1856 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1857 { 1858 struct ata_port *ap = qc->ap; 1859 1860 /* make DMA engine forget about the failed command */ 1861 if (qc->flags & ATA_QCFLAG_FAILED) 1862 ahci_kick_engine(ap); 1863 } 1864 1865 static void ahci_enable_fbs(struct ata_port *ap) 1866 { 1867 struct ahci_port_priv *pp = ap->private_data; 1868 void __iomem *port_mmio = ahci_port_base(ap); 1869 u32 fbs; 1870 int rc; 1871 1872 if (!pp->fbs_supported) 1873 return; 1874 1875 fbs = readl(port_mmio + PORT_FBS); 1876 if (fbs & PORT_FBS_EN) { 1877 pp->fbs_enabled = true; 1878 pp->fbs_last_dev = -1; /* initialization */ 1879 return; 1880 } 1881 1882 rc = ahci_stop_engine(ap); 1883 if (rc) 1884 return; 1885 1886 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 1887 fbs = readl(port_mmio + PORT_FBS); 1888 if (fbs & PORT_FBS_EN) { 1889 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n"); 1890 pp->fbs_enabled = true; 1891 pp->fbs_last_dev = -1; /* initialization */ 1892 } else 1893 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n"); 1894 1895 ahci_start_engine(ap); 1896 } 1897 1898 static void ahci_disable_fbs(struct ata_port *ap) 1899 { 1900 struct ahci_port_priv *pp = ap->private_data; 1901 void __iomem *port_mmio = ahci_port_base(ap); 1902 u32 fbs; 1903 int rc; 1904 1905 if (!pp->fbs_supported) 1906 return; 1907 1908 fbs = readl(port_mmio + PORT_FBS); 1909 if ((fbs & PORT_FBS_EN) == 0) { 1910 pp->fbs_enabled = false; 1911 return; 1912 } 1913 1914 rc = ahci_stop_engine(ap); 1915 if (rc) 1916 return; 1917 1918 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 1919 fbs = readl(port_mmio + PORT_FBS); 1920 if (fbs & PORT_FBS_EN) 1921 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n"); 1922 else { 1923 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n"); 1924 pp->fbs_enabled = false; 1925 } 1926 1927 ahci_start_engine(ap); 1928 } 1929 1930 static void ahci_pmp_attach(struct ata_port *ap) 1931 { 1932 void __iomem *port_mmio = ahci_port_base(ap); 1933 struct ahci_port_priv *pp = ap->private_data; 1934 u32 cmd; 1935 1936 cmd = readl(port_mmio + PORT_CMD); 1937 cmd |= PORT_CMD_PMP; 1938 writel(cmd, port_mmio + PORT_CMD); 1939 1940 ahci_enable_fbs(ap); 1941 1942 pp->intr_mask |= PORT_IRQ_BAD_PMP; 1943 1944 /* 1945 * We must not change the port interrupt mask register if the 1946 * port is marked frozen, the value in pp->intr_mask will be 1947 * restored later when the port is thawed. 1948 * 1949 * Note that during initialization, the port is marked as 1950 * frozen since the irq handler is not yet registered. 1951 */ 1952 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 1953 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1954 } 1955 1956 static void ahci_pmp_detach(struct ata_port *ap) 1957 { 1958 void __iomem *port_mmio = ahci_port_base(ap); 1959 struct ahci_port_priv *pp = ap->private_data; 1960 u32 cmd; 1961 1962 ahci_disable_fbs(ap); 1963 1964 cmd = readl(port_mmio + PORT_CMD); 1965 cmd &= ~PORT_CMD_PMP; 1966 writel(cmd, port_mmio + PORT_CMD); 1967 1968 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 1969 1970 /* see comment above in ahci_pmp_attach() */ 1971 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 1972 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1973 } 1974 1975 int ahci_port_resume(struct ata_port *ap) 1976 { 1977 ahci_power_up(ap); 1978 ahci_start_port(ap); 1979 1980 if (sata_pmp_attached(ap)) 1981 ahci_pmp_attach(ap); 1982 else 1983 ahci_pmp_detach(ap); 1984 1985 return 0; 1986 } 1987 EXPORT_SYMBOL_GPL(ahci_port_resume); 1988 1989 #ifdef CONFIG_PM 1990 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 1991 { 1992 const char *emsg = NULL; 1993 int rc; 1994 1995 rc = ahci_deinit_port(ap, &emsg); 1996 if (rc == 0) 1997 ahci_power_down(ap); 1998 else { 1999 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 2000 ahci_start_port(ap); 2001 } 2002 2003 return rc; 2004 } 2005 #endif 2006 2007 static int ahci_port_start(struct ata_port *ap) 2008 { 2009 struct ahci_host_priv *hpriv = ap->host->private_data; 2010 struct device *dev = ap->host->dev; 2011 struct ahci_port_priv *pp; 2012 void *mem; 2013 dma_addr_t mem_dma; 2014 size_t dma_sz, rx_fis_sz; 2015 2016 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2017 if (!pp) 2018 return -ENOMEM; 2019 2020 /* check FBS capability */ 2021 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2022 void __iomem *port_mmio = ahci_port_base(ap); 2023 u32 cmd = readl(port_mmio + PORT_CMD); 2024 if (cmd & PORT_CMD_FBSCP) 2025 pp->fbs_supported = true; 2026 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2027 dev_printk(KERN_INFO, dev, 2028 "port %d can do FBS, forcing FBSCP\n", 2029 ap->port_no); 2030 pp->fbs_supported = true; 2031 } else 2032 dev_printk(KERN_WARNING, dev, 2033 "port %d is not capable of FBS\n", 2034 ap->port_no); 2035 } 2036 2037 if (pp->fbs_supported) { 2038 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2039 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2040 } else { 2041 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2042 rx_fis_sz = AHCI_RX_FIS_SZ; 2043 } 2044 2045 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2046 if (!mem) 2047 return -ENOMEM; 2048 memset(mem, 0, dma_sz); 2049 2050 /* 2051 * First item in chunk of DMA memory: 32-slot command table, 2052 * 32 bytes each in size 2053 */ 2054 pp->cmd_slot = mem; 2055 pp->cmd_slot_dma = mem_dma; 2056 2057 mem += AHCI_CMD_SLOT_SZ; 2058 mem_dma += AHCI_CMD_SLOT_SZ; 2059 2060 /* 2061 * Second item: Received-FIS area 2062 */ 2063 pp->rx_fis = mem; 2064 pp->rx_fis_dma = mem_dma; 2065 2066 mem += rx_fis_sz; 2067 mem_dma += rx_fis_sz; 2068 2069 /* 2070 * Third item: data area for storing a single command 2071 * and its scatter-gather table 2072 */ 2073 pp->cmd_tbl = mem; 2074 pp->cmd_tbl_dma = mem_dma; 2075 2076 /* 2077 * Save off initial list of interrupts to be enabled. 2078 * This could be changed later 2079 */ 2080 pp->intr_mask = DEF_PORT_IRQ; 2081 2082 ap->private_data = pp; 2083 2084 /* engage engines, captain */ 2085 return ahci_port_resume(ap); 2086 } 2087 2088 static void ahci_port_stop(struct ata_port *ap) 2089 { 2090 const char *emsg = NULL; 2091 int rc; 2092 2093 /* de-initialize port */ 2094 rc = ahci_deinit_port(ap, &emsg); 2095 if (rc) 2096 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 2097 } 2098 2099 void ahci_print_info(struct ata_host *host, const char *scc_s) 2100 { 2101 struct ahci_host_priv *hpriv = host->private_data; 2102 void __iomem *mmio = hpriv->mmio; 2103 u32 vers, cap, cap2, impl, speed; 2104 const char *speed_s; 2105 2106 vers = readl(mmio + HOST_VERSION); 2107 cap = hpriv->cap; 2108 cap2 = hpriv->cap2; 2109 impl = hpriv->port_map; 2110 2111 speed = (cap >> 20) & 0xf; 2112 if (speed == 1) 2113 speed_s = "1.5"; 2114 else if (speed == 2) 2115 speed_s = "3"; 2116 else if (speed == 3) 2117 speed_s = "6"; 2118 else 2119 speed_s = "?"; 2120 2121 dev_info(host->dev, 2122 "AHCI %02x%02x.%02x%02x " 2123 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2124 , 2125 2126 (vers >> 24) & 0xff, 2127 (vers >> 16) & 0xff, 2128 (vers >> 8) & 0xff, 2129 vers & 0xff, 2130 2131 ((cap >> 8) & 0x1f) + 1, 2132 (cap & 0x1f) + 1, 2133 speed_s, 2134 impl, 2135 scc_s); 2136 2137 dev_info(host->dev, 2138 "flags: " 2139 "%s%s%s%s%s%s%s" 2140 "%s%s%s%s%s%s%s" 2141 "%s%s%s%s%s%s\n" 2142 , 2143 2144 cap & HOST_CAP_64 ? "64bit " : "", 2145 cap & HOST_CAP_NCQ ? "ncq " : "", 2146 cap & HOST_CAP_SNTF ? "sntf " : "", 2147 cap & HOST_CAP_MPS ? "ilck " : "", 2148 cap & HOST_CAP_SSS ? "stag " : "", 2149 cap & HOST_CAP_ALPM ? "pm " : "", 2150 cap & HOST_CAP_LED ? "led " : "", 2151 cap & HOST_CAP_CLO ? "clo " : "", 2152 cap & HOST_CAP_ONLY ? "only " : "", 2153 cap & HOST_CAP_PMP ? "pmp " : "", 2154 cap & HOST_CAP_FBS ? "fbs " : "", 2155 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2156 cap & HOST_CAP_SSC ? "slum " : "", 2157 cap & HOST_CAP_PART ? "part " : "", 2158 cap & HOST_CAP_CCC ? "ccc " : "", 2159 cap & HOST_CAP_EMS ? "ems " : "", 2160 cap & HOST_CAP_SXS ? "sxs " : "", 2161 cap2 & HOST_CAP2_APST ? "apst " : "", 2162 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2163 cap2 & HOST_CAP2_BOH ? "boh " : "" 2164 ); 2165 } 2166 EXPORT_SYMBOL_GPL(ahci_print_info); 2167 2168 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2169 struct ata_port_info *pi) 2170 { 2171 u8 messages; 2172 void __iomem *mmio = hpriv->mmio; 2173 u32 em_loc = readl(mmio + HOST_EM_LOC); 2174 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2175 2176 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2177 return; 2178 2179 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2180 2181 if (messages) { 2182 /* store em_loc */ 2183 hpriv->em_loc = ((em_loc >> 16) * 4); 2184 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2185 hpriv->em_msg_type = messages; 2186 pi->flags |= ATA_FLAG_EM; 2187 if (!(em_ctl & EM_CTL_ALHD)) 2188 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2189 } 2190 } 2191 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2192 2193 MODULE_AUTHOR("Jeff Garzik"); 2194 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2195 MODULE_LICENSE("GPL"); 2196