1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <scsi/scsi_host.h> 45 #include <scsi/scsi_cmnd.h> 46 #include <linux/libata.h> 47 #include "ahci.h" 48 49 static int ahci_skip_host_reset; 50 int ahci_ignore_sss; 51 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 52 53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 55 56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 58 59 static int ahci_enable_alpm(struct ata_port *ap, 60 enum link_pm policy); 61 static void ahci_disable_alpm(struct ata_port *ap); 62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 64 size_t size); 65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 66 ssize_t size); 67 68 69 70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 72 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 74 static int ahci_port_start(struct ata_port *ap); 75 static void ahci_port_stop(struct ata_port *ap); 76 static void ahci_qc_prep(struct ata_queued_cmd *qc); 77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 78 static void ahci_freeze(struct ata_port *ap); 79 static void ahci_thaw(struct ata_port *ap); 80 static void ahci_enable_fbs(struct ata_port *ap); 81 static void ahci_disable_fbs(struct ata_port *ap); 82 static void ahci_pmp_attach(struct ata_port *ap); 83 static void ahci_pmp_detach(struct ata_port *ap); 84 static int ahci_softreset(struct ata_link *link, unsigned int *class, 85 unsigned long deadline); 86 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 87 unsigned long deadline); 88 static void ahci_postreset(struct ata_link *link, unsigned int *class); 89 static void ahci_error_handler(struct ata_port *ap); 90 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 91 static int ahci_port_resume(struct ata_port *ap); 92 static void ahci_dev_config(struct ata_device *dev); 93 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 94 u32 opts); 95 #ifdef CONFIG_PM 96 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 97 #endif 98 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 99 static ssize_t ahci_activity_store(struct ata_device *dev, 100 enum sw_activity val); 101 static void ahci_init_sw_activity(struct ata_link *link); 102 103 static ssize_t ahci_show_host_caps(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_host_cap2(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_show_host_version(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_show_port_cmd(struct device *dev, 110 struct device_attribute *attr, char *buf); 111 static ssize_t ahci_read_em_buffer(struct device *dev, 112 struct device_attribute *attr, char *buf); 113 static ssize_t ahci_store_em_buffer(struct device *dev, 114 struct device_attribute *attr, 115 const char *buf, size_t size); 116 117 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 118 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 119 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 120 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 121 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 122 ahci_read_em_buffer, ahci_store_em_buffer); 123 124 static struct device_attribute *ahci_shost_attrs[] = { 125 &dev_attr_link_power_management_policy, 126 &dev_attr_em_message_type, 127 &dev_attr_em_message, 128 &dev_attr_ahci_host_caps, 129 &dev_attr_ahci_host_cap2, 130 &dev_attr_ahci_host_version, 131 &dev_attr_ahci_port_cmd, 132 &dev_attr_em_buffer, 133 NULL 134 }; 135 136 static struct device_attribute *ahci_sdev_attrs[] = { 137 &dev_attr_sw_activity, 138 &dev_attr_unload_heads, 139 NULL 140 }; 141 142 struct scsi_host_template ahci_sht = { 143 ATA_NCQ_SHT("ahci"), 144 .can_queue = AHCI_MAX_CMDS - 1, 145 .sg_tablesize = AHCI_MAX_SG, 146 .dma_boundary = AHCI_DMA_BOUNDARY, 147 .shost_attrs = ahci_shost_attrs, 148 .sdev_attrs = ahci_sdev_attrs, 149 }; 150 EXPORT_SYMBOL_GPL(ahci_sht); 151 152 struct ata_port_operations ahci_ops = { 153 .inherits = &sata_pmp_port_ops, 154 155 .qc_defer = ahci_pmp_qc_defer, 156 .qc_prep = ahci_qc_prep, 157 .qc_issue = ahci_qc_issue, 158 .qc_fill_rtf = ahci_qc_fill_rtf, 159 160 .freeze = ahci_freeze, 161 .thaw = ahci_thaw, 162 .softreset = ahci_softreset, 163 .hardreset = ahci_hardreset, 164 .postreset = ahci_postreset, 165 .pmp_softreset = ahci_softreset, 166 .error_handler = ahci_error_handler, 167 .post_internal_cmd = ahci_post_internal_cmd, 168 .dev_config = ahci_dev_config, 169 170 .scr_read = ahci_scr_read, 171 .scr_write = ahci_scr_write, 172 .pmp_attach = ahci_pmp_attach, 173 .pmp_detach = ahci_pmp_detach, 174 175 .enable_pm = ahci_enable_alpm, 176 .disable_pm = ahci_disable_alpm, 177 .em_show = ahci_led_show, 178 .em_store = ahci_led_store, 179 .sw_activity_show = ahci_activity_show, 180 .sw_activity_store = ahci_activity_store, 181 #ifdef CONFIG_PM 182 .port_suspend = ahci_port_suspend, 183 .port_resume = ahci_port_resume, 184 #endif 185 .port_start = ahci_port_start, 186 .port_stop = ahci_port_stop, 187 }; 188 EXPORT_SYMBOL_GPL(ahci_ops); 189 190 int ahci_em_messages = 1; 191 EXPORT_SYMBOL_GPL(ahci_em_messages); 192 module_param(ahci_em_messages, int, 0444); 193 /* add other LED protocol types when they become supported */ 194 MODULE_PARM_DESC(ahci_em_messages, 195 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 196 197 static void ahci_enable_ahci(void __iomem *mmio) 198 { 199 int i; 200 u32 tmp; 201 202 /* turn on AHCI_EN */ 203 tmp = readl(mmio + HOST_CTL); 204 if (tmp & HOST_AHCI_EN) 205 return; 206 207 /* Some controllers need AHCI_EN to be written multiple times. 208 * Try a few times before giving up. 209 */ 210 for (i = 0; i < 5; i++) { 211 tmp |= HOST_AHCI_EN; 212 writel(tmp, mmio + HOST_CTL); 213 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 214 if (tmp & HOST_AHCI_EN) 215 return; 216 msleep(10); 217 } 218 219 WARN_ON(1); 220 } 221 222 static ssize_t ahci_show_host_caps(struct device *dev, 223 struct device_attribute *attr, char *buf) 224 { 225 struct Scsi_Host *shost = class_to_shost(dev); 226 struct ata_port *ap = ata_shost_to_port(shost); 227 struct ahci_host_priv *hpriv = ap->host->private_data; 228 229 return sprintf(buf, "%x\n", hpriv->cap); 230 } 231 232 static ssize_t ahci_show_host_cap2(struct device *dev, 233 struct device_attribute *attr, char *buf) 234 { 235 struct Scsi_Host *shost = class_to_shost(dev); 236 struct ata_port *ap = ata_shost_to_port(shost); 237 struct ahci_host_priv *hpriv = ap->host->private_data; 238 239 return sprintf(buf, "%x\n", hpriv->cap2); 240 } 241 242 static ssize_t ahci_show_host_version(struct device *dev, 243 struct device_attribute *attr, char *buf) 244 { 245 struct Scsi_Host *shost = class_to_shost(dev); 246 struct ata_port *ap = ata_shost_to_port(shost); 247 struct ahci_host_priv *hpriv = ap->host->private_data; 248 void __iomem *mmio = hpriv->mmio; 249 250 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); 251 } 252 253 static ssize_t ahci_show_port_cmd(struct device *dev, 254 struct device_attribute *attr, char *buf) 255 { 256 struct Scsi_Host *shost = class_to_shost(dev); 257 struct ata_port *ap = ata_shost_to_port(shost); 258 void __iomem *port_mmio = ahci_port_base(ap); 259 260 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 261 } 262 263 static ssize_t ahci_read_em_buffer(struct device *dev, 264 struct device_attribute *attr, char *buf) 265 { 266 struct Scsi_Host *shost = class_to_shost(dev); 267 struct ata_port *ap = ata_shost_to_port(shost); 268 struct ahci_host_priv *hpriv = ap->host->private_data; 269 void __iomem *mmio = hpriv->mmio; 270 void __iomem *em_mmio = mmio + hpriv->em_loc; 271 u32 em_ctl, msg; 272 unsigned long flags; 273 size_t count; 274 int i; 275 276 spin_lock_irqsave(ap->lock, flags); 277 278 em_ctl = readl(mmio + HOST_EM_CTL); 279 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 280 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 281 spin_unlock_irqrestore(ap->lock, flags); 282 return -EINVAL; 283 } 284 285 if (!(em_ctl & EM_CTL_MR)) { 286 spin_unlock_irqrestore(ap->lock, flags); 287 return -EAGAIN; 288 } 289 290 if (!(em_ctl & EM_CTL_SMB)) 291 em_mmio += hpriv->em_buf_sz; 292 293 count = hpriv->em_buf_sz; 294 295 /* the count should not be larger than PAGE_SIZE */ 296 if (count > PAGE_SIZE) { 297 if (printk_ratelimit()) 298 ata_port_printk(ap, KERN_WARNING, 299 "EM read buffer size too large: " 300 "buffer size %u, page size %lu\n", 301 hpriv->em_buf_sz, PAGE_SIZE); 302 count = PAGE_SIZE; 303 } 304 305 for (i = 0; i < count; i += 4) { 306 msg = readl(em_mmio + i); 307 buf[i] = msg & 0xff; 308 buf[i + 1] = (msg >> 8) & 0xff; 309 buf[i + 2] = (msg >> 16) & 0xff; 310 buf[i + 3] = (msg >> 24) & 0xff; 311 } 312 313 spin_unlock_irqrestore(ap->lock, flags); 314 315 return i; 316 } 317 318 static ssize_t ahci_store_em_buffer(struct device *dev, 319 struct device_attribute *attr, 320 const char *buf, size_t size) 321 { 322 struct Scsi_Host *shost = class_to_shost(dev); 323 struct ata_port *ap = ata_shost_to_port(shost); 324 struct ahci_host_priv *hpriv = ap->host->private_data; 325 void __iomem *mmio = hpriv->mmio; 326 void __iomem *em_mmio = mmio + hpriv->em_loc; 327 const unsigned char *msg_buf = buf; 328 u32 em_ctl, msg; 329 unsigned long flags; 330 int i; 331 332 /* check size validity */ 333 if (!(ap->flags & ATA_FLAG_EM) || 334 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 335 size % 4 || size > hpriv->em_buf_sz) 336 return -EINVAL; 337 338 spin_lock_irqsave(ap->lock, flags); 339 340 em_ctl = readl(mmio + HOST_EM_CTL); 341 if (em_ctl & EM_CTL_TM) { 342 spin_unlock_irqrestore(ap->lock, flags); 343 return -EBUSY; 344 } 345 346 for (i = 0; i < size; i += 4) { 347 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 348 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 349 writel(msg, em_mmio + i); 350 } 351 352 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 353 354 spin_unlock_irqrestore(ap->lock, flags); 355 356 return size; 357 } 358 359 /** 360 * ahci_save_initial_config - Save and fixup initial config values 361 * @dev: target AHCI device 362 * @hpriv: host private area to store config values 363 * @force_port_map: force port map to a specified value 364 * @mask_port_map: mask out particular bits from port map 365 * 366 * Some registers containing configuration info might be setup by 367 * BIOS and might be cleared on reset. This function saves the 368 * initial values of those registers into @hpriv such that they 369 * can be restored after controller reset. 370 * 371 * If inconsistent, config values are fixed up by this function. 372 * 373 * LOCKING: 374 * None. 375 */ 376 void ahci_save_initial_config(struct device *dev, 377 struct ahci_host_priv *hpriv, 378 unsigned int force_port_map, 379 unsigned int mask_port_map) 380 { 381 void __iomem *mmio = hpriv->mmio; 382 u32 cap, cap2, vers, port_map; 383 int i; 384 385 /* make sure AHCI mode is enabled before accessing CAP */ 386 ahci_enable_ahci(mmio); 387 388 /* Values prefixed with saved_ are written back to host after 389 * reset. Values without are used for driver operation. 390 */ 391 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 392 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 393 394 /* CAP2 register is only defined for AHCI 1.2 and later */ 395 vers = readl(mmio + HOST_VERSION); 396 if ((vers >> 16) > 1 || 397 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 398 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 399 else 400 hpriv->saved_cap2 = cap2 = 0; 401 402 /* some chips have errata preventing 64bit use */ 403 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 404 dev_printk(KERN_INFO, dev, 405 "controller can't do 64bit DMA, forcing 32bit\n"); 406 cap &= ~HOST_CAP_64; 407 } 408 409 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 410 dev_printk(KERN_INFO, dev, 411 "controller can't do NCQ, turning off CAP_NCQ\n"); 412 cap &= ~HOST_CAP_NCQ; 413 } 414 415 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 416 dev_printk(KERN_INFO, dev, 417 "controller can do NCQ, turning on CAP_NCQ\n"); 418 cap |= HOST_CAP_NCQ; 419 } 420 421 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 422 dev_printk(KERN_INFO, dev, 423 "controller can't do PMP, turning off CAP_PMP\n"); 424 cap &= ~HOST_CAP_PMP; 425 } 426 427 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 428 dev_printk(KERN_INFO, dev, 429 "controller can't do SNTF, turning off CAP_SNTF\n"); 430 cap &= ~HOST_CAP_SNTF; 431 } 432 433 if (force_port_map && port_map != force_port_map) { 434 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n", 435 port_map, force_port_map); 436 port_map = force_port_map; 437 } 438 439 if (mask_port_map) { 440 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n", 441 port_map, 442 port_map & mask_port_map); 443 port_map &= mask_port_map; 444 } 445 446 /* cross check port_map and cap.n_ports */ 447 if (port_map) { 448 int map_ports = 0; 449 450 for (i = 0; i < AHCI_MAX_PORTS; i++) 451 if (port_map & (1 << i)) 452 map_ports++; 453 454 /* If PI has more ports than n_ports, whine, clear 455 * port_map and let it be generated from n_ports. 456 */ 457 if (map_ports > ahci_nr_ports(cap)) { 458 dev_printk(KERN_WARNING, dev, 459 "implemented port map (0x%x) contains more " 460 "ports than nr_ports (%u), using nr_ports\n", 461 port_map, ahci_nr_ports(cap)); 462 port_map = 0; 463 } 464 } 465 466 /* fabricate port_map from cap.nr_ports */ 467 if (!port_map) { 468 port_map = (1 << ahci_nr_ports(cap)) - 1; 469 dev_printk(KERN_WARNING, dev, 470 "forcing PORTS_IMPL to 0x%x\n", port_map); 471 472 /* write the fixed up value to the PI register */ 473 hpriv->saved_port_map = port_map; 474 } 475 476 /* record values to use during operation */ 477 hpriv->cap = cap; 478 hpriv->cap2 = cap2; 479 hpriv->port_map = port_map; 480 } 481 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 482 483 /** 484 * ahci_restore_initial_config - Restore initial config 485 * @host: target ATA host 486 * 487 * Restore initial config stored by ahci_save_initial_config(). 488 * 489 * LOCKING: 490 * None. 491 */ 492 static void ahci_restore_initial_config(struct ata_host *host) 493 { 494 struct ahci_host_priv *hpriv = host->private_data; 495 void __iomem *mmio = hpriv->mmio; 496 497 writel(hpriv->saved_cap, mmio + HOST_CAP); 498 if (hpriv->saved_cap2) 499 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 500 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 501 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 502 } 503 504 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 505 { 506 static const int offset[] = { 507 [SCR_STATUS] = PORT_SCR_STAT, 508 [SCR_CONTROL] = PORT_SCR_CTL, 509 [SCR_ERROR] = PORT_SCR_ERR, 510 [SCR_ACTIVE] = PORT_SCR_ACT, 511 [SCR_NOTIFICATION] = PORT_SCR_NTF, 512 }; 513 struct ahci_host_priv *hpriv = ap->host->private_data; 514 515 if (sc_reg < ARRAY_SIZE(offset) && 516 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 517 return offset[sc_reg]; 518 return 0; 519 } 520 521 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 522 { 523 void __iomem *port_mmio = ahci_port_base(link->ap); 524 int offset = ahci_scr_offset(link->ap, sc_reg); 525 526 if (offset) { 527 *val = readl(port_mmio + offset); 528 return 0; 529 } 530 return -EINVAL; 531 } 532 533 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 534 { 535 void __iomem *port_mmio = ahci_port_base(link->ap); 536 int offset = ahci_scr_offset(link->ap, sc_reg); 537 538 if (offset) { 539 writel(val, port_mmio + offset); 540 return 0; 541 } 542 return -EINVAL; 543 } 544 545 void ahci_start_engine(struct ata_port *ap) 546 { 547 void __iomem *port_mmio = ahci_port_base(ap); 548 u32 tmp; 549 550 /* start DMA */ 551 tmp = readl(port_mmio + PORT_CMD); 552 tmp |= PORT_CMD_START; 553 writel(tmp, port_mmio + PORT_CMD); 554 readl(port_mmio + PORT_CMD); /* flush */ 555 } 556 EXPORT_SYMBOL_GPL(ahci_start_engine); 557 558 int ahci_stop_engine(struct ata_port *ap) 559 { 560 void __iomem *port_mmio = ahci_port_base(ap); 561 u32 tmp; 562 563 tmp = readl(port_mmio + PORT_CMD); 564 565 /* check if the HBA is idle */ 566 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 567 return 0; 568 569 /* setting HBA to idle */ 570 tmp &= ~PORT_CMD_START; 571 writel(tmp, port_mmio + PORT_CMD); 572 573 /* wait for engine to stop. This could be as long as 500 msec */ 574 tmp = ata_wait_register(port_mmio + PORT_CMD, 575 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 576 if (tmp & PORT_CMD_LIST_ON) 577 return -EIO; 578 579 return 0; 580 } 581 EXPORT_SYMBOL_GPL(ahci_stop_engine); 582 583 static void ahci_start_fis_rx(struct ata_port *ap) 584 { 585 void __iomem *port_mmio = ahci_port_base(ap); 586 struct ahci_host_priv *hpriv = ap->host->private_data; 587 struct ahci_port_priv *pp = ap->private_data; 588 u32 tmp; 589 590 /* set FIS registers */ 591 if (hpriv->cap & HOST_CAP_64) 592 writel((pp->cmd_slot_dma >> 16) >> 16, 593 port_mmio + PORT_LST_ADDR_HI); 594 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 595 596 if (hpriv->cap & HOST_CAP_64) 597 writel((pp->rx_fis_dma >> 16) >> 16, 598 port_mmio + PORT_FIS_ADDR_HI); 599 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 600 601 /* enable FIS reception */ 602 tmp = readl(port_mmio + PORT_CMD); 603 tmp |= PORT_CMD_FIS_RX; 604 writel(tmp, port_mmio + PORT_CMD); 605 606 /* flush */ 607 readl(port_mmio + PORT_CMD); 608 } 609 610 static int ahci_stop_fis_rx(struct ata_port *ap) 611 { 612 void __iomem *port_mmio = ahci_port_base(ap); 613 u32 tmp; 614 615 /* disable FIS reception */ 616 tmp = readl(port_mmio + PORT_CMD); 617 tmp &= ~PORT_CMD_FIS_RX; 618 writel(tmp, port_mmio + PORT_CMD); 619 620 /* wait for completion, spec says 500ms, give it 1000 */ 621 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 622 PORT_CMD_FIS_ON, 10, 1000); 623 if (tmp & PORT_CMD_FIS_ON) 624 return -EBUSY; 625 626 return 0; 627 } 628 629 static void ahci_power_up(struct ata_port *ap) 630 { 631 struct ahci_host_priv *hpriv = ap->host->private_data; 632 void __iomem *port_mmio = ahci_port_base(ap); 633 u32 cmd; 634 635 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 636 637 /* spin up device */ 638 if (hpriv->cap & HOST_CAP_SSS) { 639 cmd |= PORT_CMD_SPIN_UP; 640 writel(cmd, port_mmio + PORT_CMD); 641 } 642 643 /* wake up link */ 644 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 645 } 646 647 static void ahci_disable_alpm(struct ata_port *ap) 648 { 649 struct ahci_host_priv *hpriv = ap->host->private_data; 650 void __iomem *port_mmio = ahci_port_base(ap); 651 u32 cmd; 652 struct ahci_port_priv *pp = ap->private_data; 653 654 /* IPM bits should be disabled by libata-core */ 655 /* get the existing command bits */ 656 cmd = readl(port_mmio + PORT_CMD); 657 658 /* disable ALPM and ASP */ 659 cmd &= ~PORT_CMD_ASP; 660 cmd &= ~PORT_CMD_ALPE; 661 662 /* force the interface back to active */ 663 cmd |= PORT_CMD_ICC_ACTIVE; 664 665 /* write out new cmd value */ 666 writel(cmd, port_mmio + PORT_CMD); 667 cmd = readl(port_mmio + PORT_CMD); 668 669 /* wait 10ms to be sure we've come out of any low power state */ 670 msleep(10); 671 672 /* clear out any PhyRdy stuff from interrupt status */ 673 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT); 674 675 /* go ahead and clean out PhyRdy Change from Serror too */ 676 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); 677 678 /* 679 * Clear flag to indicate that we should ignore all PhyRdy 680 * state changes 681 */ 682 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG; 683 684 /* 685 * Enable interrupts on Phy Ready. 686 */ 687 pp->intr_mask |= PORT_IRQ_PHYRDY; 688 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 689 690 /* 691 * don't change the link pm policy - we can be called 692 * just to turn of link pm temporarily 693 */ 694 } 695 696 static int ahci_enable_alpm(struct ata_port *ap, 697 enum link_pm policy) 698 { 699 struct ahci_host_priv *hpriv = ap->host->private_data; 700 void __iomem *port_mmio = ahci_port_base(ap); 701 u32 cmd; 702 struct ahci_port_priv *pp = ap->private_data; 703 u32 asp; 704 705 /* Make sure the host is capable of link power management */ 706 if (!(hpriv->cap & HOST_CAP_ALPM)) 707 return -EINVAL; 708 709 switch (policy) { 710 case MAX_PERFORMANCE: 711 case NOT_AVAILABLE: 712 /* 713 * if we came here with NOT_AVAILABLE, 714 * it just means this is the first time we 715 * have tried to enable - default to max performance, 716 * and let the user go to lower power modes on request. 717 */ 718 ahci_disable_alpm(ap); 719 return 0; 720 case MIN_POWER: 721 /* configure HBA to enter SLUMBER */ 722 asp = PORT_CMD_ASP; 723 break; 724 case MEDIUM_POWER: 725 /* configure HBA to enter PARTIAL */ 726 asp = 0; 727 break; 728 default: 729 return -EINVAL; 730 } 731 732 /* 733 * Disable interrupts on Phy Ready. This keeps us from 734 * getting woken up due to spurious phy ready interrupts 735 * TBD - Hot plug should be done via polling now, is 736 * that even supported? 737 */ 738 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 739 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 740 741 /* 742 * Set a flag to indicate that we should ignore all PhyRdy 743 * state changes since these can happen now whenever we 744 * change link state 745 */ 746 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG; 747 748 /* get the existing command bits */ 749 cmd = readl(port_mmio + PORT_CMD); 750 751 /* 752 * Set ASP based on Policy 753 */ 754 cmd |= asp; 755 756 /* 757 * Setting this bit will instruct the HBA to aggressively 758 * enter a lower power link state when it's appropriate and 759 * based on the value set above for ASP 760 */ 761 cmd |= PORT_CMD_ALPE; 762 763 /* write out new cmd value */ 764 writel(cmd, port_mmio + PORT_CMD); 765 cmd = readl(port_mmio + PORT_CMD); 766 767 /* IPM bits should be set by libata-core */ 768 return 0; 769 } 770 771 #ifdef CONFIG_PM 772 static void ahci_power_down(struct ata_port *ap) 773 { 774 struct ahci_host_priv *hpriv = ap->host->private_data; 775 void __iomem *port_mmio = ahci_port_base(ap); 776 u32 cmd, scontrol; 777 778 if (!(hpriv->cap & HOST_CAP_SSS)) 779 return; 780 781 /* put device into listen mode, first set PxSCTL.DET to 0 */ 782 scontrol = readl(port_mmio + PORT_SCR_CTL); 783 scontrol &= ~0xf; 784 writel(scontrol, port_mmio + PORT_SCR_CTL); 785 786 /* then set PxCMD.SUD to 0 */ 787 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 788 cmd &= ~PORT_CMD_SPIN_UP; 789 writel(cmd, port_mmio + PORT_CMD); 790 } 791 #endif 792 793 static void ahci_start_port(struct ata_port *ap) 794 { 795 struct ahci_port_priv *pp = ap->private_data; 796 struct ata_link *link; 797 struct ahci_em_priv *emp; 798 ssize_t rc; 799 int i; 800 801 /* enable FIS reception */ 802 ahci_start_fis_rx(ap); 803 804 /* enable DMA */ 805 ahci_start_engine(ap); 806 807 /* turn on LEDs */ 808 if (ap->flags & ATA_FLAG_EM) { 809 ata_for_each_link(link, ap, EDGE) { 810 emp = &pp->em_priv[link->pmp]; 811 812 /* EM Transmit bit maybe busy during init */ 813 for (i = 0; i < EM_MAX_RETRY; i++) { 814 rc = ahci_transmit_led_message(ap, 815 emp->led_state, 816 4); 817 if (rc == -EBUSY) 818 msleep(1); 819 else 820 break; 821 } 822 } 823 } 824 825 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 826 ata_for_each_link(link, ap, EDGE) 827 ahci_init_sw_activity(link); 828 829 } 830 831 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 832 { 833 int rc; 834 835 /* disable DMA */ 836 rc = ahci_stop_engine(ap); 837 if (rc) { 838 *emsg = "failed to stop engine"; 839 return rc; 840 } 841 842 /* disable FIS reception */ 843 rc = ahci_stop_fis_rx(ap); 844 if (rc) { 845 *emsg = "failed stop FIS RX"; 846 return rc; 847 } 848 849 return 0; 850 } 851 852 int ahci_reset_controller(struct ata_host *host) 853 { 854 struct ahci_host_priv *hpriv = host->private_data; 855 void __iomem *mmio = hpriv->mmio; 856 u32 tmp; 857 858 /* we must be in AHCI mode, before using anything 859 * AHCI-specific, such as HOST_RESET. 860 */ 861 ahci_enable_ahci(mmio); 862 863 /* global controller reset */ 864 if (!ahci_skip_host_reset) { 865 tmp = readl(mmio + HOST_CTL); 866 if ((tmp & HOST_RESET) == 0) { 867 writel(tmp | HOST_RESET, mmio + HOST_CTL); 868 readl(mmio + HOST_CTL); /* flush */ 869 } 870 871 /* 872 * to perform host reset, OS should set HOST_RESET 873 * and poll until this bit is read to be "0". 874 * reset must complete within 1 second, or 875 * the hardware should be considered fried. 876 */ 877 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET, 878 HOST_RESET, 10, 1000); 879 880 if (tmp & HOST_RESET) { 881 dev_printk(KERN_ERR, host->dev, 882 "controller reset failed (0x%x)\n", tmp); 883 return -EIO; 884 } 885 886 /* turn on AHCI mode */ 887 ahci_enable_ahci(mmio); 888 889 /* Some registers might be cleared on reset. Restore 890 * initial values. 891 */ 892 ahci_restore_initial_config(host); 893 } else 894 dev_printk(KERN_INFO, host->dev, 895 "skipping global host reset\n"); 896 897 return 0; 898 } 899 EXPORT_SYMBOL_GPL(ahci_reset_controller); 900 901 static void ahci_sw_activity(struct ata_link *link) 902 { 903 struct ata_port *ap = link->ap; 904 struct ahci_port_priv *pp = ap->private_data; 905 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 906 907 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 908 return; 909 910 emp->activity++; 911 if (!timer_pending(&emp->timer)) 912 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 913 } 914 915 static void ahci_sw_activity_blink(unsigned long arg) 916 { 917 struct ata_link *link = (struct ata_link *)arg; 918 struct ata_port *ap = link->ap; 919 struct ahci_port_priv *pp = ap->private_data; 920 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 921 unsigned long led_message = emp->led_state; 922 u32 activity_led_state; 923 unsigned long flags; 924 925 led_message &= EM_MSG_LED_VALUE; 926 led_message |= ap->port_no | (link->pmp << 8); 927 928 /* check to see if we've had activity. If so, 929 * toggle state of LED and reset timer. If not, 930 * turn LED to desired idle state. 931 */ 932 spin_lock_irqsave(ap->lock, flags); 933 if (emp->saved_activity != emp->activity) { 934 emp->saved_activity = emp->activity; 935 /* get the current LED state */ 936 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 937 938 if (activity_led_state) 939 activity_led_state = 0; 940 else 941 activity_led_state = 1; 942 943 /* clear old state */ 944 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 945 946 /* toggle state */ 947 led_message |= (activity_led_state << 16); 948 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 949 } else { 950 /* switch to idle */ 951 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 952 if (emp->blink_policy == BLINK_OFF) 953 led_message |= (1 << 16); 954 } 955 spin_unlock_irqrestore(ap->lock, flags); 956 ahci_transmit_led_message(ap, led_message, 4); 957 } 958 959 static void ahci_init_sw_activity(struct ata_link *link) 960 { 961 struct ata_port *ap = link->ap; 962 struct ahci_port_priv *pp = ap->private_data; 963 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 964 965 /* init activity stats, setup timer */ 966 emp->saved_activity = emp->activity = 0; 967 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 968 969 /* check our blink policy and set flag for link if it's enabled */ 970 if (emp->blink_policy) 971 link->flags |= ATA_LFLAG_SW_ACTIVITY; 972 } 973 974 int ahci_reset_em(struct ata_host *host) 975 { 976 struct ahci_host_priv *hpriv = host->private_data; 977 void __iomem *mmio = hpriv->mmio; 978 u32 em_ctl; 979 980 em_ctl = readl(mmio + HOST_EM_CTL); 981 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 982 return -EINVAL; 983 984 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 985 return 0; 986 } 987 EXPORT_SYMBOL_GPL(ahci_reset_em); 988 989 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 990 ssize_t size) 991 { 992 struct ahci_host_priv *hpriv = ap->host->private_data; 993 struct ahci_port_priv *pp = ap->private_data; 994 void __iomem *mmio = hpriv->mmio; 995 u32 em_ctl; 996 u32 message[] = {0, 0}; 997 unsigned long flags; 998 int pmp; 999 struct ahci_em_priv *emp; 1000 1001 /* get the slot number from the message */ 1002 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1003 if (pmp < EM_MAX_SLOTS) 1004 emp = &pp->em_priv[pmp]; 1005 else 1006 return -EINVAL; 1007 1008 spin_lock_irqsave(ap->lock, flags); 1009 1010 /* 1011 * if we are still busy transmitting a previous message, 1012 * do not allow 1013 */ 1014 em_ctl = readl(mmio + HOST_EM_CTL); 1015 if (em_ctl & EM_CTL_TM) { 1016 spin_unlock_irqrestore(ap->lock, flags); 1017 return -EBUSY; 1018 } 1019 1020 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 1021 /* 1022 * create message header - this is all zero except for 1023 * the message size, which is 4 bytes. 1024 */ 1025 message[0] |= (4 << 8); 1026 1027 /* ignore 0:4 of byte zero, fill in port info yourself */ 1028 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 1029 1030 /* write message to EM_LOC */ 1031 writel(message[0], mmio + hpriv->em_loc); 1032 writel(message[1], mmio + hpriv->em_loc+4); 1033 1034 /* 1035 * tell hardware to transmit the message 1036 */ 1037 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 1038 } 1039 1040 /* save off new led state for port/slot */ 1041 emp->led_state = state; 1042 1043 spin_unlock_irqrestore(ap->lock, flags); 1044 return size; 1045 } 1046 1047 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 1048 { 1049 struct ahci_port_priv *pp = ap->private_data; 1050 struct ata_link *link; 1051 struct ahci_em_priv *emp; 1052 int rc = 0; 1053 1054 ata_for_each_link(link, ap, EDGE) { 1055 emp = &pp->em_priv[link->pmp]; 1056 rc += sprintf(buf, "%lx\n", emp->led_state); 1057 } 1058 return rc; 1059 } 1060 1061 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1062 size_t size) 1063 { 1064 int state; 1065 int pmp; 1066 struct ahci_port_priv *pp = ap->private_data; 1067 struct ahci_em_priv *emp; 1068 1069 state = simple_strtoul(buf, NULL, 0); 1070 1071 /* get the slot number from the message */ 1072 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1073 if (pmp < EM_MAX_SLOTS) 1074 emp = &pp->em_priv[pmp]; 1075 else 1076 return -EINVAL; 1077 1078 /* mask off the activity bits if we are in sw_activity 1079 * mode, user should turn off sw_activity before setting 1080 * activity led through em_message 1081 */ 1082 if (emp->blink_policy) 1083 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1084 1085 return ahci_transmit_led_message(ap, state, size); 1086 } 1087 1088 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1089 { 1090 struct ata_link *link = dev->link; 1091 struct ata_port *ap = link->ap; 1092 struct ahci_port_priv *pp = ap->private_data; 1093 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1094 u32 port_led_state = emp->led_state; 1095 1096 /* save the desired Activity LED behavior */ 1097 if (val == OFF) { 1098 /* clear LFLAG */ 1099 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1100 1101 /* set the LED to OFF */ 1102 port_led_state &= EM_MSG_LED_VALUE_OFF; 1103 port_led_state |= (ap->port_no | (link->pmp << 8)); 1104 ahci_transmit_led_message(ap, port_led_state, 4); 1105 } else { 1106 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1107 if (val == BLINK_OFF) { 1108 /* set LED to ON for idle */ 1109 port_led_state &= EM_MSG_LED_VALUE_OFF; 1110 port_led_state |= (ap->port_no | (link->pmp << 8)); 1111 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1112 ahci_transmit_led_message(ap, port_led_state, 4); 1113 } 1114 } 1115 emp->blink_policy = val; 1116 return 0; 1117 } 1118 1119 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1120 { 1121 struct ata_link *link = dev->link; 1122 struct ata_port *ap = link->ap; 1123 struct ahci_port_priv *pp = ap->private_data; 1124 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1125 1126 /* display the saved value of activity behavior for this 1127 * disk. 1128 */ 1129 return sprintf(buf, "%d\n", emp->blink_policy); 1130 } 1131 1132 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1133 int port_no, void __iomem *mmio, 1134 void __iomem *port_mmio) 1135 { 1136 const char *emsg = NULL; 1137 int rc; 1138 u32 tmp; 1139 1140 /* make sure port is not active */ 1141 rc = ahci_deinit_port(ap, &emsg); 1142 if (rc) 1143 dev_warn(dev, "%s (%d)\n", emsg, rc); 1144 1145 /* clear SError */ 1146 tmp = readl(port_mmio + PORT_SCR_ERR); 1147 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1148 writel(tmp, port_mmio + PORT_SCR_ERR); 1149 1150 /* clear port IRQ */ 1151 tmp = readl(port_mmio + PORT_IRQ_STAT); 1152 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1153 if (tmp) 1154 writel(tmp, port_mmio + PORT_IRQ_STAT); 1155 1156 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1157 } 1158 1159 void ahci_init_controller(struct ata_host *host) 1160 { 1161 struct ahci_host_priv *hpriv = host->private_data; 1162 void __iomem *mmio = hpriv->mmio; 1163 int i; 1164 void __iomem *port_mmio; 1165 u32 tmp; 1166 1167 for (i = 0; i < host->n_ports; i++) { 1168 struct ata_port *ap = host->ports[i]; 1169 1170 port_mmio = ahci_port_base(ap); 1171 if (ata_port_is_dummy(ap)) 1172 continue; 1173 1174 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1175 } 1176 1177 tmp = readl(mmio + HOST_CTL); 1178 VPRINTK("HOST_CTL 0x%x\n", tmp); 1179 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1180 tmp = readl(mmio + HOST_CTL); 1181 VPRINTK("HOST_CTL 0x%x\n", tmp); 1182 } 1183 EXPORT_SYMBOL_GPL(ahci_init_controller); 1184 1185 static void ahci_dev_config(struct ata_device *dev) 1186 { 1187 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1188 1189 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1190 dev->max_sectors = 255; 1191 ata_dev_printk(dev, KERN_INFO, 1192 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1193 } 1194 } 1195 1196 static unsigned int ahci_dev_classify(struct ata_port *ap) 1197 { 1198 void __iomem *port_mmio = ahci_port_base(ap); 1199 struct ata_taskfile tf; 1200 u32 tmp; 1201 1202 tmp = readl(port_mmio + PORT_SIG); 1203 tf.lbah = (tmp >> 24) & 0xff; 1204 tf.lbam = (tmp >> 16) & 0xff; 1205 tf.lbal = (tmp >> 8) & 0xff; 1206 tf.nsect = (tmp) & 0xff; 1207 1208 return ata_dev_classify(&tf); 1209 } 1210 1211 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1212 u32 opts) 1213 { 1214 dma_addr_t cmd_tbl_dma; 1215 1216 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1217 1218 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1219 pp->cmd_slot[tag].status = 0; 1220 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1221 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1222 } 1223 1224 int ahci_kick_engine(struct ata_port *ap) 1225 { 1226 void __iomem *port_mmio = ahci_port_base(ap); 1227 struct ahci_host_priv *hpriv = ap->host->private_data; 1228 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1229 u32 tmp; 1230 int busy, rc; 1231 1232 /* stop engine */ 1233 rc = ahci_stop_engine(ap); 1234 if (rc) 1235 goto out_restart; 1236 1237 /* need to do CLO? 1238 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1239 */ 1240 busy = status & (ATA_BUSY | ATA_DRQ); 1241 if (!busy && !sata_pmp_attached(ap)) { 1242 rc = 0; 1243 goto out_restart; 1244 } 1245 1246 if (!(hpriv->cap & HOST_CAP_CLO)) { 1247 rc = -EOPNOTSUPP; 1248 goto out_restart; 1249 } 1250 1251 /* perform CLO */ 1252 tmp = readl(port_mmio + PORT_CMD); 1253 tmp |= PORT_CMD_CLO; 1254 writel(tmp, port_mmio + PORT_CMD); 1255 1256 rc = 0; 1257 tmp = ata_wait_register(port_mmio + PORT_CMD, 1258 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1259 if (tmp & PORT_CMD_CLO) 1260 rc = -EIO; 1261 1262 /* restart engine */ 1263 out_restart: 1264 ahci_start_engine(ap); 1265 return rc; 1266 } 1267 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1268 1269 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1270 struct ata_taskfile *tf, int is_cmd, u16 flags, 1271 unsigned long timeout_msec) 1272 { 1273 const u32 cmd_fis_len = 5; /* five dwords */ 1274 struct ahci_port_priv *pp = ap->private_data; 1275 void __iomem *port_mmio = ahci_port_base(ap); 1276 u8 *fis = pp->cmd_tbl; 1277 u32 tmp; 1278 1279 /* prep the command */ 1280 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1281 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1282 1283 /* issue & wait */ 1284 writel(1, port_mmio + PORT_CMD_ISSUE); 1285 1286 if (timeout_msec) { 1287 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1288 1, timeout_msec); 1289 if (tmp & 0x1) { 1290 ahci_kick_engine(ap); 1291 return -EBUSY; 1292 } 1293 } else 1294 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1295 1296 return 0; 1297 } 1298 1299 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1300 int pmp, unsigned long deadline, 1301 int (*check_ready)(struct ata_link *link)) 1302 { 1303 struct ata_port *ap = link->ap; 1304 struct ahci_host_priv *hpriv = ap->host->private_data; 1305 const char *reason = NULL; 1306 unsigned long now, msecs; 1307 struct ata_taskfile tf; 1308 int rc; 1309 1310 DPRINTK("ENTER\n"); 1311 1312 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1313 rc = ahci_kick_engine(ap); 1314 if (rc && rc != -EOPNOTSUPP) 1315 ata_link_printk(link, KERN_WARNING, 1316 "failed to reset engine (errno=%d)\n", rc); 1317 1318 ata_tf_init(link->device, &tf); 1319 1320 /* issue the first D2H Register FIS */ 1321 msecs = 0; 1322 now = jiffies; 1323 if (time_after(now, deadline)) 1324 msecs = jiffies_to_msecs(deadline - now); 1325 1326 tf.ctl |= ATA_SRST; 1327 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1328 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1329 rc = -EIO; 1330 reason = "1st FIS failed"; 1331 goto fail; 1332 } 1333 1334 /* spec says at least 5us, but be generous and sleep for 1ms */ 1335 msleep(1); 1336 1337 /* issue the second D2H Register FIS */ 1338 tf.ctl &= ~ATA_SRST; 1339 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1340 1341 /* wait for link to become ready */ 1342 rc = ata_wait_after_reset(link, deadline, check_ready); 1343 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1344 /* 1345 * Workaround for cases where link online status can't 1346 * be trusted. Treat device readiness timeout as link 1347 * offline. 1348 */ 1349 ata_link_printk(link, KERN_INFO, 1350 "device not ready, treating as offline\n"); 1351 *class = ATA_DEV_NONE; 1352 } else if (rc) { 1353 /* link occupied, -ENODEV too is an error */ 1354 reason = "device not ready"; 1355 goto fail; 1356 } else 1357 *class = ahci_dev_classify(ap); 1358 1359 DPRINTK("EXIT, class=%u\n", *class); 1360 return 0; 1361 1362 fail: 1363 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 1364 return rc; 1365 } 1366 1367 int ahci_check_ready(struct ata_link *link) 1368 { 1369 void __iomem *port_mmio = ahci_port_base(link->ap); 1370 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1371 1372 return ata_check_ready(status); 1373 } 1374 EXPORT_SYMBOL_GPL(ahci_check_ready); 1375 1376 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1377 unsigned long deadline) 1378 { 1379 int pmp = sata_srst_pmp(link); 1380 1381 DPRINTK("ENTER\n"); 1382 1383 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1384 } 1385 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1386 1387 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1388 unsigned long deadline) 1389 { 1390 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1391 struct ata_port *ap = link->ap; 1392 struct ahci_port_priv *pp = ap->private_data; 1393 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1394 struct ata_taskfile tf; 1395 bool online; 1396 int rc; 1397 1398 DPRINTK("ENTER\n"); 1399 1400 ahci_stop_engine(ap); 1401 1402 /* clear D2H reception area to properly wait for D2H FIS */ 1403 ata_tf_init(link->device, &tf); 1404 tf.command = 0x80; 1405 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1406 1407 rc = sata_link_hardreset(link, timing, deadline, &online, 1408 ahci_check_ready); 1409 1410 ahci_start_engine(ap); 1411 1412 if (online) 1413 *class = ahci_dev_classify(ap); 1414 1415 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1416 return rc; 1417 } 1418 1419 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1420 { 1421 struct ata_port *ap = link->ap; 1422 void __iomem *port_mmio = ahci_port_base(ap); 1423 u32 new_tmp, tmp; 1424 1425 ata_std_postreset(link, class); 1426 1427 /* Make sure port's ATAPI bit is set appropriately */ 1428 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1429 if (*class == ATA_DEV_ATAPI) 1430 new_tmp |= PORT_CMD_ATAPI; 1431 else 1432 new_tmp &= ~PORT_CMD_ATAPI; 1433 if (new_tmp != tmp) { 1434 writel(new_tmp, port_mmio + PORT_CMD); 1435 readl(port_mmio + PORT_CMD); /* flush */ 1436 } 1437 } 1438 1439 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1440 { 1441 struct scatterlist *sg; 1442 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1443 unsigned int si; 1444 1445 VPRINTK("ENTER\n"); 1446 1447 /* 1448 * Next, the S/G list. 1449 */ 1450 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1451 dma_addr_t addr = sg_dma_address(sg); 1452 u32 sg_len = sg_dma_len(sg); 1453 1454 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1455 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1456 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1457 } 1458 1459 return si; 1460 } 1461 1462 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1463 { 1464 struct ata_port *ap = qc->ap; 1465 struct ahci_port_priv *pp = ap->private_data; 1466 1467 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1468 return ata_std_qc_defer(qc); 1469 else 1470 return sata_pmp_qc_defer_cmd_switch(qc); 1471 } 1472 1473 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1474 { 1475 struct ata_port *ap = qc->ap; 1476 struct ahci_port_priv *pp = ap->private_data; 1477 int is_atapi = ata_is_atapi(qc->tf.protocol); 1478 void *cmd_tbl; 1479 u32 opts; 1480 const u32 cmd_fis_len = 5; /* five dwords */ 1481 unsigned int n_elem; 1482 1483 /* 1484 * Fill in command table information. First, the header, 1485 * a SATA Register - Host to Device command FIS. 1486 */ 1487 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1488 1489 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1490 if (is_atapi) { 1491 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1492 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1493 } 1494 1495 n_elem = 0; 1496 if (qc->flags & ATA_QCFLAG_DMAMAP) 1497 n_elem = ahci_fill_sg(qc, cmd_tbl); 1498 1499 /* 1500 * Fill in command slot information. 1501 */ 1502 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1503 if (qc->tf.flags & ATA_TFLAG_WRITE) 1504 opts |= AHCI_CMD_WRITE; 1505 if (is_atapi) 1506 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1507 1508 ahci_fill_cmd_slot(pp, qc->tag, opts); 1509 } 1510 1511 static void ahci_fbs_dec_intr(struct ata_port *ap) 1512 { 1513 struct ahci_port_priv *pp = ap->private_data; 1514 void __iomem *port_mmio = ahci_port_base(ap); 1515 u32 fbs = readl(port_mmio + PORT_FBS); 1516 int retries = 3; 1517 1518 DPRINTK("ENTER\n"); 1519 BUG_ON(!pp->fbs_enabled); 1520 1521 /* time to wait for DEC is not specified by AHCI spec, 1522 * add a retry loop for safety. 1523 */ 1524 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1525 fbs = readl(port_mmio + PORT_FBS); 1526 while ((fbs & PORT_FBS_DEC) && retries--) { 1527 udelay(1); 1528 fbs = readl(port_mmio + PORT_FBS); 1529 } 1530 1531 if (fbs & PORT_FBS_DEC) 1532 dev_printk(KERN_ERR, ap->host->dev, 1533 "failed to clear device error\n"); 1534 } 1535 1536 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1537 { 1538 struct ahci_host_priv *hpriv = ap->host->private_data; 1539 struct ahci_port_priv *pp = ap->private_data; 1540 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1541 struct ata_link *link = NULL; 1542 struct ata_queued_cmd *active_qc; 1543 struct ata_eh_info *active_ehi; 1544 bool fbs_need_dec = false; 1545 u32 serror; 1546 1547 /* determine active link with error */ 1548 if (pp->fbs_enabled) { 1549 void __iomem *port_mmio = ahci_port_base(ap); 1550 u32 fbs = readl(port_mmio + PORT_FBS); 1551 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1552 1553 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) && 1554 ata_link_online(&ap->pmp_link[pmp])) { 1555 link = &ap->pmp_link[pmp]; 1556 fbs_need_dec = true; 1557 } 1558 1559 } else 1560 ata_for_each_link(link, ap, EDGE) 1561 if (ata_link_active(link)) 1562 break; 1563 1564 if (!link) 1565 link = &ap->link; 1566 1567 active_qc = ata_qc_from_tag(ap, link->active_tag); 1568 active_ehi = &link->eh_info; 1569 1570 /* record irq stat */ 1571 ata_ehi_clear_desc(host_ehi); 1572 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1573 1574 /* AHCI needs SError cleared; otherwise, it might lock up */ 1575 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1576 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1577 host_ehi->serror |= serror; 1578 1579 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1580 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1581 irq_stat &= ~PORT_IRQ_IF_ERR; 1582 1583 if (irq_stat & PORT_IRQ_TF_ERR) { 1584 /* If qc is active, charge it; otherwise, the active 1585 * link. There's no active qc on NCQ errors. It will 1586 * be determined by EH by reading log page 10h. 1587 */ 1588 if (active_qc) 1589 active_qc->err_mask |= AC_ERR_DEV; 1590 else 1591 active_ehi->err_mask |= AC_ERR_DEV; 1592 1593 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1594 host_ehi->serror &= ~SERR_INTERNAL; 1595 } 1596 1597 if (irq_stat & PORT_IRQ_UNK_FIS) { 1598 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 1599 1600 active_ehi->err_mask |= AC_ERR_HSM; 1601 active_ehi->action |= ATA_EH_RESET; 1602 ata_ehi_push_desc(active_ehi, 1603 "unknown FIS %08x %08x %08x %08x" , 1604 unk[0], unk[1], unk[2], unk[3]); 1605 } 1606 1607 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1608 active_ehi->err_mask |= AC_ERR_HSM; 1609 active_ehi->action |= ATA_EH_RESET; 1610 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1611 } 1612 1613 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1614 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1615 host_ehi->action |= ATA_EH_RESET; 1616 ata_ehi_push_desc(host_ehi, "host bus error"); 1617 } 1618 1619 if (irq_stat & PORT_IRQ_IF_ERR) { 1620 if (fbs_need_dec) 1621 active_ehi->err_mask |= AC_ERR_DEV; 1622 else { 1623 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1624 host_ehi->action |= ATA_EH_RESET; 1625 } 1626 1627 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1628 } 1629 1630 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1631 ata_ehi_hotplugged(host_ehi); 1632 ata_ehi_push_desc(host_ehi, "%s", 1633 irq_stat & PORT_IRQ_CONNECT ? 1634 "connection status changed" : "PHY RDY changed"); 1635 } 1636 1637 /* okay, let's hand over to EH */ 1638 1639 if (irq_stat & PORT_IRQ_FREEZE) 1640 ata_port_freeze(ap); 1641 else if (fbs_need_dec) { 1642 ata_link_abort(link); 1643 ahci_fbs_dec_intr(ap); 1644 } else 1645 ata_port_abort(ap); 1646 } 1647 1648 static void ahci_port_intr(struct ata_port *ap) 1649 { 1650 void __iomem *port_mmio = ahci_port_base(ap); 1651 struct ata_eh_info *ehi = &ap->link.eh_info; 1652 struct ahci_port_priv *pp = ap->private_data; 1653 struct ahci_host_priv *hpriv = ap->host->private_data; 1654 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1655 u32 status, qc_active = 0; 1656 int rc; 1657 1658 status = readl(port_mmio + PORT_IRQ_STAT); 1659 writel(status, port_mmio + PORT_IRQ_STAT); 1660 1661 /* ignore BAD_PMP while resetting */ 1662 if (unlikely(resetting)) 1663 status &= ~PORT_IRQ_BAD_PMP; 1664 1665 /* If we are getting PhyRdy, this is 1666 * just a power state change, we should 1667 * clear out this, plus the PhyRdy/Comm 1668 * Wake bits from Serror 1669 */ 1670 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) && 1671 (status & PORT_IRQ_PHYRDY)) { 1672 status &= ~PORT_IRQ_PHYRDY; 1673 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18))); 1674 } 1675 1676 if (unlikely(status & PORT_IRQ_ERROR)) { 1677 ahci_error_intr(ap, status); 1678 return; 1679 } 1680 1681 if (status & PORT_IRQ_SDB_FIS) { 1682 /* If SNotification is available, leave notification 1683 * handling to sata_async_notification(). If not, 1684 * emulate it by snooping SDB FIS RX area. 1685 * 1686 * Snooping FIS RX area is probably cheaper than 1687 * poking SNotification but some constrollers which 1688 * implement SNotification, ICH9 for example, don't 1689 * store AN SDB FIS into receive area. 1690 */ 1691 if (hpriv->cap & HOST_CAP_SNTF) 1692 sata_async_notification(ap); 1693 else { 1694 /* If the 'N' bit in word 0 of the FIS is set, 1695 * we just received asynchronous notification. 1696 * Tell libata about it. 1697 * 1698 * Lack of SNotification should not appear in 1699 * ahci 1.2, so the workaround is unnecessary 1700 * when FBS is enabled. 1701 */ 1702 if (pp->fbs_enabled) 1703 WARN_ON_ONCE(1); 1704 else { 1705 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1706 u32 f0 = le32_to_cpu(f[0]); 1707 if (f0 & (1 << 15)) 1708 sata_async_notification(ap); 1709 } 1710 } 1711 } 1712 1713 /* pp->active_link is not reliable once FBS is enabled, both 1714 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1715 * NCQ and non-NCQ commands may be in flight at the same time. 1716 */ 1717 if (pp->fbs_enabled) { 1718 if (ap->qc_active) { 1719 qc_active = readl(port_mmio + PORT_SCR_ACT); 1720 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1721 } 1722 } else { 1723 /* pp->active_link is valid iff any command is in flight */ 1724 if (ap->qc_active && pp->active_link->sactive) 1725 qc_active = readl(port_mmio + PORT_SCR_ACT); 1726 else 1727 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1728 } 1729 1730 1731 rc = ata_qc_complete_multiple(ap, qc_active); 1732 1733 /* while resetting, invalid completions are expected */ 1734 if (unlikely(rc < 0 && !resetting)) { 1735 ehi->err_mask |= AC_ERR_HSM; 1736 ehi->action |= ATA_EH_RESET; 1737 ata_port_freeze(ap); 1738 } 1739 } 1740 1741 irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1742 { 1743 struct ata_host *host = dev_instance; 1744 struct ahci_host_priv *hpriv; 1745 unsigned int i, handled = 0; 1746 void __iomem *mmio; 1747 u32 irq_stat, irq_masked; 1748 1749 VPRINTK("ENTER\n"); 1750 1751 hpriv = host->private_data; 1752 mmio = hpriv->mmio; 1753 1754 /* sigh. 0xffffffff is a valid return from h/w */ 1755 irq_stat = readl(mmio + HOST_IRQ_STAT); 1756 if (!irq_stat) 1757 return IRQ_NONE; 1758 1759 irq_masked = irq_stat & hpriv->port_map; 1760 1761 spin_lock(&host->lock); 1762 1763 for (i = 0; i < host->n_ports; i++) { 1764 struct ata_port *ap; 1765 1766 if (!(irq_masked & (1 << i))) 1767 continue; 1768 1769 ap = host->ports[i]; 1770 if (ap) { 1771 ahci_port_intr(ap); 1772 VPRINTK("port %u\n", i); 1773 } else { 1774 VPRINTK("port %u (no irq)\n", i); 1775 if (ata_ratelimit()) 1776 dev_printk(KERN_WARNING, host->dev, 1777 "interrupt on disabled port %u\n", i); 1778 } 1779 1780 handled = 1; 1781 } 1782 1783 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1784 * it should be cleared after all the port events are cleared; 1785 * otherwise, it will raise a spurious interrupt after each 1786 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1787 * information. 1788 * 1789 * Also, use the unmasked value to clear interrupt as spurious 1790 * pending event on a dummy port might cause screaming IRQ. 1791 */ 1792 writel(irq_stat, mmio + HOST_IRQ_STAT); 1793 1794 spin_unlock(&host->lock); 1795 1796 VPRINTK("EXIT\n"); 1797 1798 return IRQ_RETVAL(handled); 1799 } 1800 EXPORT_SYMBOL_GPL(ahci_interrupt); 1801 1802 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1803 { 1804 struct ata_port *ap = qc->ap; 1805 void __iomem *port_mmio = ahci_port_base(ap); 1806 struct ahci_port_priv *pp = ap->private_data; 1807 1808 /* Keep track of the currently active link. It will be used 1809 * in completion path to determine whether NCQ phase is in 1810 * progress. 1811 */ 1812 pp->active_link = qc->dev->link; 1813 1814 if (qc->tf.protocol == ATA_PROT_NCQ) 1815 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1816 1817 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1818 u32 fbs = readl(port_mmio + PORT_FBS); 1819 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1820 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1821 writel(fbs, port_mmio + PORT_FBS); 1822 pp->fbs_last_dev = qc->dev->link->pmp; 1823 } 1824 1825 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1826 1827 ahci_sw_activity(qc->dev->link); 1828 1829 return 0; 1830 } 1831 1832 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1833 { 1834 struct ahci_port_priv *pp = qc->ap->private_data; 1835 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1836 1837 if (pp->fbs_enabled) 1838 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 1839 1840 ata_tf_from_fis(d2h_fis, &qc->result_tf); 1841 return true; 1842 } 1843 1844 static void ahci_freeze(struct ata_port *ap) 1845 { 1846 void __iomem *port_mmio = ahci_port_base(ap); 1847 1848 /* turn IRQ off */ 1849 writel(0, port_mmio + PORT_IRQ_MASK); 1850 } 1851 1852 static void ahci_thaw(struct ata_port *ap) 1853 { 1854 struct ahci_host_priv *hpriv = ap->host->private_data; 1855 void __iomem *mmio = hpriv->mmio; 1856 void __iomem *port_mmio = ahci_port_base(ap); 1857 u32 tmp; 1858 struct ahci_port_priv *pp = ap->private_data; 1859 1860 /* clear IRQ */ 1861 tmp = readl(port_mmio + PORT_IRQ_STAT); 1862 writel(tmp, port_mmio + PORT_IRQ_STAT); 1863 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 1864 1865 /* turn IRQ back on */ 1866 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1867 } 1868 1869 static void ahci_error_handler(struct ata_port *ap) 1870 { 1871 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1872 /* restart engine */ 1873 ahci_stop_engine(ap); 1874 ahci_start_engine(ap); 1875 } 1876 1877 sata_pmp_error_handler(ap); 1878 1879 if (!ata_dev_enabled(ap->link.device)) 1880 ahci_stop_engine(ap); 1881 } 1882 1883 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1884 { 1885 struct ata_port *ap = qc->ap; 1886 1887 /* make DMA engine forget about the failed command */ 1888 if (qc->flags & ATA_QCFLAG_FAILED) 1889 ahci_kick_engine(ap); 1890 } 1891 1892 static void ahci_enable_fbs(struct ata_port *ap) 1893 { 1894 struct ahci_port_priv *pp = ap->private_data; 1895 void __iomem *port_mmio = ahci_port_base(ap); 1896 u32 fbs; 1897 int rc; 1898 1899 if (!pp->fbs_supported) 1900 return; 1901 1902 fbs = readl(port_mmio + PORT_FBS); 1903 if (fbs & PORT_FBS_EN) { 1904 pp->fbs_enabled = true; 1905 pp->fbs_last_dev = -1; /* initialization */ 1906 return; 1907 } 1908 1909 rc = ahci_stop_engine(ap); 1910 if (rc) 1911 return; 1912 1913 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 1914 fbs = readl(port_mmio + PORT_FBS); 1915 if (fbs & PORT_FBS_EN) { 1916 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n"); 1917 pp->fbs_enabled = true; 1918 pp->fbs_last_dev = -1; /* initialization */ 1919 } else 1920 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n"); 1921 1922 ahci_start_engine(ap); 1923 } 1924 1925 static void ahci_disable_fbs(struct ata_port *ap) 1926 { 1927 struct ahci_port_priv *pp = ap->private_data; 1928 void __iomem *port_mmio = ahci_port_base(ap); 1929 u32 fbs; 1930 int rc; 1931 1932 if (!pp->fbs_supported) 1933 return; 1934 1935 fbs = readl(port_mmio + PORT_FBS); 1936 if ((fbs & PORT_FBS_EN) == 0) { 1937 pp->fbs_enabled = false; 1938 return; 1939 } 1940 1941 rc = ahci_stop_engine(ap); 1942 if (rc) 1943 return; 1944 1945 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 1946 fbs = readl(port_mmio + PORT_FBS); 1947 if (fbs & PORT_FBS_EN) 1948 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n"); 1949 else { 1950 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n"); 1951 pp->fbs_enabled = false; 1952 } 1953 1954 ahci_start_engine(ap); 1955 } 1956 1957 static void ahci_pmp_attach(struct ata_port *ap) 1958 { 1959 void __iomem *port_mmio = ahci_port_base(ap); 1960 struct ahci_port_priv *pp = ap->private_data; 1961 u32 cmd; 1962 1963 cmd = readl(port_mmio + PORT_CMD); 1964 cmd |= PORT_CMD_PMP; 1965 writel(cmd, port_mmio + PORT_CMD); 1966 1967 ahci_enable_fbs(ap); 1968 1969 pp->intr_mask |= PORT_IRQ_BAD_PMP; 1970 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1971 } 1972 1973 static void ahci_pmp_detach(struct ata_port *ap) 1974 { 1975 void __iomem *port_mmio = ahci_port_base(ap); 1976 struct ahci_port_priv *pp = ap->private_data; 1977 u32 cmd; 1978 1979 ahci_disable_fbs(ap); 1980 1981 cmd = readl(port_mmio + PORT_CMD); 1982 cmd &= ~PORT_CMD_PMP; 1983 writel(cmd, port_mmio + PORT_CMD); 1984 1985 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 1986 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1987 } 1988 1989 static int ahci_port_resume(struct ata_port *ap) 1990 { 1991 ahci_power_up(ap); 1992 ahci_start_port(ap); 1993 1994 if (sata_pmp_attached(ap)) 1995 ahci_pmp_attach(ap); 1996 else 1997 ahci_pmp_detach(ap); 1998 1999 return 0; 2000 } 2001 2002 #ifdef CONFIG_PM 2003 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 2004 { 2005 const char *emsg = NULL; 2006 int rc; 2007 2008 rc = ahci_deinit_port(ap, &emsg); 2009 if (rc == 0) 2010 ahci_power_down(ap); 2011 else { 2012 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 2013 ahci_start_port(ap); 2014 } 2015 2016 return rc; 2017 } 2018 #endif 2019 2020 static int ahci_port_start(struct ata_port *ap) 2021 { 2022 struct ahci_host_priv *hpriv = ap->host->private_data; 2023 struct device *dev = ap->host->dev; 2024 struct ahci_port_priv *pp; 2025 void *mem; 2026 dma_addr_t mem_dma; 2027 size_t dma_sz, rx_fis_sz; 2028 2029 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 2030 if (!pp) 2031 return -ENOMEM; 2032 2033 /* check FBS capability */ 2034 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2035 void __iomem *port_mmio = ahci_port_base(ap); 2036 u32 cmd = readl(port_mmio + PORT_CMD); 2037 if (cmd & PORT_CMD_FBSCP) 2038 pp->fbs_supported = true; 2039 else 2040 dev_printk(KERN_WARNING, dev, 2041 "The port is not capable of FBS\n"); 2042 } 2043 2044 if (pp->fbs_supported) { 2045 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2046 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2047 } else { 2048 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2049 rx_fis_sz = AHCI_RX_FIS_SZ; 2050 } 2051 2052 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2053 if (!mem) 2054 return -ENOMEM; 2055 memset(mem, 0, dma_sz); 2056 2057 /* 2058 * First item in chunk of DMA memory: 32-slot command table, 2059 * 32 bytes each in size 2060 */ 2061 pp->cmd_slot = mem; 2062 pp->cmd_slot_dma = mem_dma; 2063 2064 mem += AHCI_CMD_SLOT_SZ; 2065 mem_dma += AHCI_CMD_SLOT_SZ; 2066 2067 /* 2068 * Second item: Received-FIS area 2069 */ 2070 pp->rx_fis = mem; 2071 pp->rx_fis_dma = mem_dma; 2072 2073 mem += rx_fis_sz; 2074 mem_dma += rx_fis_sz; 2075 2076 /* 2077 * Third item: data area for storing a single command 2078 * and its scatter-gather table 2079 */ 2080 pp->cmd_tbl = mem; 2081 pp->cmd_tbl_dma = mem_dma; 2082 2083 /* 2084 * Save off initial list of interrupts to be enabled. 2085 * This could be changed later 2086 */ 2087 pp->intr_mask = DEF_PORT_IRQ; 2088 2089 ap->private_data = pp; 2090 2091 /* engage engines, captain */ 2092 return ahci_port_resume(ap); 2093 } 2094 2095 static void ahci_port_stop(struct ata_port *ap) 2096 { 2097 const char *emsg = NULL; 2098 int rc; 2099 2100 /* de-initialize port */ 2101 rc = ahci_deinit_port(ap, &emsg); 2102 if (rc) 2103 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 2104 } 2105 2106 void ahci_print_info(struct ata_host *host, const char *scc_s) 2107 { 2108 struct ahci_host_priv *hpriv = host->private_data; 2109 void __iomem *mmio = hpriv->mmio; 2110 u32 vers, cap, cap2, impl, speed; 2111 const char *speed_s; 2112 2113 vers = readl(mmio + HOST_VERSION); 2114 cap = hpriv->cap; 2115 cap2 = hpriv->cap2; 2116 impl = hpriv->port_map; 2117 2118 speed = (cap >> 20) & 0xf; 2119 if (speed == 1) 2120 speed_s = "1.5"; 2121 else if (speed == 2) 2122 speed_s = "3"; 2123 else if (speed == 3) 2124 speed_s = "6"; 2125 else 2126 speed_s = "?"; 2127 2128 dev_info(host->dev, 2129 "AHCI %02x%02x.%02x%02x " 2130 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2131 , 2132 2133 (vers >> 24) & 0xff, 2134 (vers >> 16) & 0xff, 2135 (vers >> 8) & 0xff, 2136 vers & 0xff, 2137 2138 ((cap >> 8) & 0x1f) + 1, 2139 (cap & 0x1f) + 1, 2140 speed_s, 2141 impl, 2142 scc_s); 2143 2144 dev_info(host->dev, 2145 "flags: " 2146 "%s%s%s%s%s%s%s" 2147 "%s%s%s%s%s%s%s" 2148 "%s%s%s%s%s%s\n" 2149 , 2150 2151 cap & HOST_CAP_64 ? "64bit " : "", 2152 cap & HOST_CAP_NCQ ? "ncq " : "", 2153 cap & HOST_CAP_SNTF ? "sntf " : "", 2154 cap & HOST_CAP_MPS ? "ilck " : "", 2155 cap & HOST_CAP_SSS ? "stag " : "", 2156 cap & HOST_CAP_ALPM ? "pm " : "", 2157 cap & HOST_CAP_LED ? "led " : "", 2158 cap & HOST_CAP_CLO ? "clo " : "", 2159 cap & HOST_CAP_ONLY ? "only " : "", 2160 cap & HOST_CAP_PMP ? "pmp " : "", 2161 cap & HOST_CAP_FBS ? "fbs " : "", 2162 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2163 cap & HOST_CAP_SSC ? "slum " : "", 2164 cap & HOST_CAP_PART ? "part " : "", 2165 cap & HOST_CAP_CCC ? "ccc " : "", 2166 cap & HOST_CAP_EMS ? "ems " : "", 2167 cap & HOST_CAP_SXS ? "sxs " : "", 2168 cap2 & HOST_CAP2_APST ? "apst " : "", 2169 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2170 cap2 & HOST_CAP2_BOH ? "boh " : "" 2171 ); 2172 } 2173 EXPORT_SYMBOL_GPL(ahci_print_info); 2174 2175 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2176 struct ata_port_info *pi) 2177 { 2178 u8 messages; 2179 void __iomem *mmio = hpriv->mmio; 2180 u32 em_loc = readl(mmio + HOST_EM_LOC); 2181 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2182 2183 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2184 return; 2185 2186 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2187 2188 if (messages) { 2189 /* store em_loc */ 2190 hpriv->em_loc = ((em_loc >> 16) * 4); 2191 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2192 hpriv->em_msg_type = messages; 2193 pi->flags |= ATA_FLAG_EM; 2194 if (!(em_ctl & EM_CTL_ALHD)) 2195 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2196 } 2197 } 2198 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2199 2200 MODULE_AUTHOR("Jeff Garzik"); 2201 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2202 MODULE_LICENSE("GPL"); 2203