1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <scsi/scsi_host.h> 45 #include <scsi/scsi_cmnd.h> 46 #include <linux/libata.h> 47 #include "ahci.h" 48 49 static int ahci_skip_host_reset; 50 int ahci_ignore_sss; 51 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 52 53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 55 56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 58 59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 60 unsigned hints); 61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 63 size_t size); 64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 65 ssize_t size); 66 67 68 69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 71 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73 static int ahci_port_start(struct ata_port *ap); 74 static void ahci_port_stop(struct ata_port *ap); 75 static void ahci_qc_prep(struct ata_queued_cmd *qc); 76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77 static void ahci_freeze(struct ata_port *ap); 78 static void ahci_thaw(struct ata_port *ap); 79 static void ahci_enable_fbs(struct ata_port *ap); 80 static void ahci_disable_fbs(struct ata_port *ap); 81 static void ahci_pmp_attach(struct ata_port *ap); 82 static void ahci_pmp_detach(struct ata_port *ap); 83 static int ahci_softreset(struct ata_link *link, unsigned int *class, 84 unsigned long deadline); 85 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 86 unsigned long deadline); 87 static void ahci_postreset(struct ata_link *link, unsigned int *class); 88 static void ahci_error_handler(struct ata_port *ap); 89 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 90 static int ahci_port_resume(struct ata_port *ap); 91 static void ahci_dev_config(struct ata_device *dev); 92 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 93 u32 opts); 94 #ifdef CONFIG_PM 95 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 96 #endif 97 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 98 static ssize_t ahci_activity_store(struct ata_device *dev, 99 enum sw_activity val); 100 static void ahci_init_sw_activity(struct ata_link *link); 101 102 static ssize_t ahci_show_host_caps(struct device *dev, 103 struct device_attribute *attr, char *buf); 104 static ssize_t ahci_show_host_cap2(struct device *dev, 105 struct device_attribute *attr, char *buf); 106 static ssize_t ahci_show_host_version(struct device *dev, 107 struct device_attribute *attr, char *buf); 108 static ssize_t ahci_show_port_cmd(struct device *dev, 109 struct device_attribute *attr, char *buf); 110 static ssize_t ahci_read_em_buffer(struct device *dev, 111 struct device_attribute *attr, char *buf); 112 static ssize_t ahci_store_em_buffer(struct device *dev, 113 struct device_attribute *attr, 114 const char *buf, size_t size); 115 116 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 117 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 118 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 119 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 120 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 121 ahci_read_em_buffer, ahci_store_em_buffer); 122 123 struct device_attribute *ahci_shost_attrs[] = { 124 &dev_attr_link_power_management_policy, 125 &dev_attr_em_message_type, 126 &dev_attr_em_message, 127 &dev_attr_ahci_host_caps, 128 &dev_attr_ahci_host_cap2, 129 &dev_attr_ahci_host_version, 130 &dev_attr_ahci_port_cmd, 131 &dev_attr_em_buffer, 132 NULL 133 }; 134 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 135 136 struct device_attribute *ahci_sdev_attrs[] = { 137 &dev_attr_sw_activity, 138 &dev_attr_unload_heads, 139 NULL 140 }; 141 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 142 143 struct ata_port_operations ahci_ops = { 144 .inherits = &sata_pmp_port_ops, 145 146 .qc_defer = ahci_pmp_qc_defer, 147 .qc_prep = ahci_qc_prep, 148 .qc_issue = ahci_qc_issue, 149 .qc_fill_rtf = ahci_qc_fill_rtf, 150 151 .freeze = ahci_freeze, 152 .thaw = ahci_thaw, 153 .softreset = ahci_softreset, 154 .hardreset = ahci_hardreset, 155 .postreset = ahci_postreset, 156 .pmp_softreset = ahci_softreset, 157 .error_handler = ahci_error_handler, 158 .post_internal_cmd = ahci_post_internal_cmd, 159 .dev_config = ahci_dev_config, 160 161 .scr_read = ahci_scr_read, 162 .scr_write = ahci_scr_write, 163 .pmp_attach = ahci_pmp_attach, 164 .pmp_detach = ahci_pmp_detach, 165 166 .set_lpm = ahci_set_lpm, 167 .em_show = ahci_led_show, 168 .em_store = ahci_led_store, 169 .sw_activity_show = ahci_activity_show, 170 .sw_activity_store = ahci_activity_store, 171 #ifdef CONFIG_PM 172 .port_suspend = ahci_port_suspend, 173 .port_resume = ahci_port_resume, 174 #endif 175 .port_start = ahci_port_start, 176 .port_stop = ahci_port_stop, 177 }; 178 EXPORT_SYMBOL_GPL(ahci_ops); 179 180 int ahci_em_messages = 1; 181 EXPORT_SYMBOL_GPL(ahci_em_messages); 182 module_param(ahci_em_messages, int, 0444); 183 /* add other LED protocol types when they become supported */ 184 MODULE_PARM_DESC(ahci_em_messages, 185 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 186 187 static void ahci_enable_ahci(void __iomem *mmio) 188 { 189 int i; 190 u32 tmp; 191 192 /* turn on AHCI_EN */ 193 tmp = readl(mmio + HOST_CTL); 194 if (tmp & HOST_AHCI_EN) 195 return; 196 197 /* Some controllers need AHCI_EN to be written multiple times. 198 * Try a few times before giving up. 199 */ 200 for (i = 0; i < 5; i++) { 201 tmp |= HOST_AHCI_EN; 202 writel(tmp, mmio + HOST_CTL); 203 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 204 if (tmp & HOST_AHCI_EN) 205 return; 206 msleep(10); 207 } 208 209 WARN_ON(1); 210 } 211 212 static ssize_t ahci_show_host_caps(struct device *dev, 213 struct device_attribute *attr, char *buf) 214 { 215 struct Scsi_Host *shost = class_to_shost(dev); 216 struct ata_port *ap = ata_shost_to_port(shost); 217 struct ahci_host_priv *hpriv = ap->host->private_data; 218 219 return sprintf(buf, "%x\n", hpriv->cap); 220 } 221 222 static ssize_t ahci_show_host_cap2(struct device *dev, 223 struct device_attribute *attr, char *buf) 224 { 225 struct Scsi_Host *shost = class_to_shost(dev); 226 struct ata_port *ap = ata_shost_to_port(shost); 227 struct ahci_host_priv *hpriv = ap->host->private_data; 228 229 return sprintf(buf, "%x\n", hpriv->cap2); 230 } 231 232 static ssize_t ahci_show_host_version(struct device *dev, 233 struct device_attribute *attr, char *buf) 234 { 235 struct Scsi_Host *shost = class_to_shost(dev); 236 struct ata_port *ap = ata_shost_to_port(shost); 237 struct ahci_host_priv *hpriv = ap->host->private_data; 238 void __iomem *mmio = hpriv->mmio; 239 240 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); 241 } 242 243 static ssize_t ahci_show_port_cmd(struct device *dev, 244 struct device_attribute *attr, char *buf) 245 { 246 struct Scsi_Host *shost = class_to_shost(dev); 247 struct ata_port *ap = ata_shost_to_port(shost); 248 void __iomem *port_mmio = ahci_port_base(ap); 249 250 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 251 } 252 253 static ssize_t ahci_read_em_buffer(struct device *dev, 254 struct device_attribute *attr, char *buf) 255 { 256 struct Scsi_Host *shost = class_to_shost(dev); 257 struct ata_port *ap = ata_shost_to_port(shost); 258 struct ahci_host_priv *hpriv = ap->host->private_data; 259 void __iomem *mmio = hpriv->mmio; 260 void __iomem *em_mmio = mmio + hpriv->em_loc; 261 u32 em_ctl, msg; 262 unsigned long flags; 263 size_t count; 264 int i; 265 266 spin_lock_irqsave(ap->lock, flags); 267 268 em_ctl = readl(mmio + HOST_EM_CTL); 269 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 270 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 271 spin_unlock_irqrestore(ap->lock, flags); 272 return -EINVAL; 273 } 274 275 if (!(em_ctl & EM_CTL_MR)) { 276 spin_unlock_irqrestore(ap->lock, flags); 277 return -EAGAIN; 278 } 279 280 if (!(em_ctl & EM_CTL_SMB)) 281 em_mmio += hpriv->em_buf_sz; 282 283 count = hpriv->em_buf_sz; 284 285 /* the count should not be larger than PAGE_SIZE */ 286 if (count > PAGE_SIZE) { 287 if (printk_ratelimit()) 288 ata_port_printk(ap, KERN_WARNING, 289 "EM read buffer size too large: " 290 "buffer size %u, page size %lu\n", 291 hpriv->em_buf_sz, PAGE_SIZE); 292 count = PAGE_SIZE; 293 } 294 295 for (i = 0; i < count; i += 4) { 296 msg = readl(em_mmio + i); 297 buf[i] = msg & 0xff; 298 buf[i + 1] = (msg >> 8) & 0xff; 299 buf[i + 2] = (msg >> 16) & 0xff; 300 buf[i + 3] = (msg >> 24) & 0xff; 301 } 302 303 spin_unlock_irqrestore(ap->lock, flags); 304 305 return i; 306 } 307 308 static ssize_t ahci_store_em_buffer(struct device *dev, 309 struct device_attribute *attr, 310 const char *buf, size_t size) 311 { 312 struct Scsi_Host *shost = class_to_shost(dev); 313 struct ata_port *ap = ata_shost_to_port(shost); 314 struct ahci_host_priv *hpriv = ap->host->private_data; 315 void __iomem *mmio = hpriv->mmio; 316 void __iomem *em_mmio = mmio + hpriv->em_loc; 317 const unsigned char *msg_buf = buf; 318 u32 em_ctl, msg; 319 unsigned long flags; 320 int i; 321 322 /* check size validity */ 323 if (!(ap->flags & ATA_FLAG_EM) || 324 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 325 size % 4 || size > hpriv->em_buf_sz) 326 return -EINVAL; 327 328 spin_lock_irqsave(ap->lock, flags); 329 330 em_ctl = readl(mmio + HOST_EM_CTL); 331 if (em_ctl & EM_CTL_TM) { 332 spin_unlock_irqrestore(ap->lock, flags); 333 return -EBUSY; 334 } 335 336 for (i = 0; i < size; i += 4) { 337 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 338 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 339 writel(msg, em_mmio + i); 340 } 341 342 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 343 344 spin_unlock_irqrestore(ap->lock, flags); 345 346 return size; 347 } 348 349 /** 350 * ahci_save_initial_config - Save and fixup initial config values 351 * @dev: target AHCI device 352 * @hpriv: host private area to store config values 353 * @force_port_map: force port map to a specified value 354 * @mask_port_map: mask out particular bits from port map 355 * 356 * Some registers containing configuration info might be setup by 357 * BIOS and might be cleared on reset. This function saves the 358 * initial values of those registers into @hpriv such that they 359 * can be restored after controller reset. 360 * 361 * If inconsistent, config values are fixed up by this function. 362 * 363 * LOCKING: 364 * None. 365 */ 366 void ahci_save_initial_config(struct device *dev, 367 struct ahci_host_priv *hpriv, 368 unsigned int force_port_map, 369 unsigned int mask_port_map) 370 { 371 void __iomem *mmio = hpriv->mmio; 372 u32 cap, cap2, vers, port_map; 373 int i; 374 375 /* make sure AHCI mode is enabled before accessing CAP */ 376 ahci_enable_ahci(mmio); 377 378 /* Values prefixed with saved_ are written back to host after 379 * reset. Values without are used for driver operation. 380 */ 381 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 382 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 383 384 /* CAP2 register is only defined for AHCI 1.2 and later */ 385 vers = readl(mmio + HOST_VERSION); 386 if ((vers >> 16) > 1 || 387 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 388 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 389 else 390 hpriv->saved_cap2 = cap2 = 0; 391 392 /* some chips have errata preventing 64bit use */ 393 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 394 dev_printk(KERN_INFO, dev, 395 "controller can't do 64bit DMA, forcing 32bit\n"); 396 cap &= ~HOST_CAP_64; 397 } 398 399 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 400 dev_printk(KERN_INFO, dev, 401 "controller can't do NCQ, turning off CAP_NCQ\n"); 402 cap &= ~HOST_CAP_NCQ; 403 } 404 405 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 406 dev_printk(KERN_INFO, dev, 407 "controller can do NCQ, turning on CAP_NCQ\n"); 408 cap |= HOST_CAP_NCQ; 409 } 410 411 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 412 dev_printk(KERN_INFO, dev, 413 "controller can't do PMP, turning off CAP_PMP\n"); 414 cap &= ~HOST_CAP_PMP; 415 } 416 417 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 418 dev_printk(KERN_INFO, dev, 419 "controller can't do SNTF, turning off CAP_SNTF\n"); 420 cap &= ~HOST_CAP_SNTF; 421 } 422 423 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 424 dev_printk(KERN_INFO, dev, 425 "controller can do FBS, turning on CAP_FBS\n"); 426 cap |= HOST_CAP_FBS; 427 } 428 429 if (force_port_map && port_map != force_port_map) { 430 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n", 431 port_map, force_port_map); 432 port_map = force_port_map; 433 } 434 435 if (mask_port_map) { 436 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n", 437 port_map, 438 port_map & mask_port_map); 439 port_map &= mask_port_map; 440 } 441 442 /* cross check port_map and cap.n_ports */ 443 if (port_map) { 444 int map_ports = 0; 445 446 for (i = 0; i < AHCI_MAX_PORTS; i++) 447 if (port_map & (1 << i)) 448 map_ports++; 449 450 /* If PI has more ports than n_ports, whine, clear 451 * port_map and let it be generated from n_ports. 452 */ 453 if (map_ports > ahci_nr_ports(cap)) { 454 dev_printk(KERN_WARNING, dev, 455 "implemented port map (0x%x) contains more " 456 "ports than nr_ports (%u), using nr_ports\n", 457 port_map, ahci_nr_ports(cap)); 458 port_map = 0; 459 } 460 } 461 462 /* fabricate port_map from cap.nr_ports */ 463 if (!port_map) { 464 port_map = (1 << ahci_nr_ports(cap)) - 1; 465 dev_printk(KERN_WARNING, dev, 466 "forcing PORTS_IMPL to 0x%x\n", port_map); 467 468 /* write the fixed up value to the PI register */ 469 hpriv->saved_port_map = port_map; 470 } 471 472 /* record values to use during operation */ 473 hpriv->cap = cap; 474 hpriv->cap2 = cap2; 475 hpriv->port_map = port_map; 476 } 477 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 478 479 /** 480 * ahci_restore_initial_config - Restore initial config 481 * @host: target ATA host 482 * 483 * Restore initial config stored by ahci_save_initial_config(). 484 * 485 * LOCKING: 486 * None. 487 */ 488 static void ahci_restore_initial_config(struct ata_host *host) 489 { 490 struct ahci_host_priv *hpriv = host->private_data; 491 void __iomem *mmio = hpriv->mmio; 492 493 writel(hpriv->saved_cap, mmio + HOST_CAP); 494 if (hpriv->saved_cap2) 495 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 496 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 497 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 498 } 499 500 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 501 { 502 static const int offset[] = { 503 [SCR_STATUS] = PORT_SCR_STAT, 504 [SCR_CONTROL] = PORT_SCR_CTL, 505 [SCR_ERROR] = PORT_SCR_ERR, 506 [SCR_ACTIVE] = PORT_SCR_ACT, 507 [SCR_NOTIFICATION] = PORT_SCR_NTF, 508 }; 509 struct ahci_host_priv *hpriv = ap->host->private_data; 510 511 if (sc_reg < ARRAY_SIZE(offset) && 512 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 513 return offset[sc_reg]; 514 return 0; 515 } 516 517 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 518 { 519 void __iomem *port_mmio = ahci_port_base(link->ap); 520 int offset = ahci_scr_offset(link->ap, sc_reg); 521 522 if (offset) { 523 *val = readl(port_mmio + offset); 524 return 0; 525 } 526 return -EINVAL; 527 } 528 529 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 530 { 531 void __iomem *port_mmio = ahci_port_base(link->ap); 532 int offset = ahci_scr_offset(link->ap, sc_reg); 533 534 if (offset) { 535 writel(val, port_mmio + offset); 536 return 0; 537 } 538 return -EINVAL; 539 } 540 541 void ahci_start_engine(struct ata_port *ap) 542 { 543 void __iomem *port_mmio = ahci_port_base(ap); 544 u32 tmp; 545 546 /* start DMA */ 547 tmp = readl(port_mmio + PORT_CMD); 548 tmp |= PORT_CMD_START; 549 writel(tmp, port_mmio + PORT_CMD); 550 readl(port_mmio + PORT_CMD); /* flush */ 551 } 552 EXPORT_SYMBOL_GPL(ahci_start_engine); 553 554 int ahci_stop_engine(struct ata_port *ap) 555 { 556 void __iomem *port_mmio = ahci_port_base(ap); 557 u32 tmp; 558 559 tmp = readl(port_mmio + PORT_CMD); 560 561 /* check if the HBA is idle */ 562 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 563 return 0; 564 565 /* setting HBA to idle */ 566 tmp &= ~PORT_CMD_START; 567 writel(tmp, port_mmio + PORT_CMD); 568 569 /* wait for engine to stop. This could be as long as 500 msec */ 570 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 571 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 572 if (tmp & PORT_CMD_LIST_ON) 573 return -EIO; 574 575 return 0; 576 } 577 EXPORT_SYMBOL_GPL(ahci_stop_engine); 578 579 static void ahci_start_fis_rx(struct ata_port *ap) 580 { 581 void __iomem *port_mmio = ahci_port_base(ap); 582 struct ahci_host_priv *hpriv = ap->host->private_data; 583 struct ahci_port_priv *pp = ap->private_data; 584 u32 tmp; 585 586 /* set FIS registers */ 587 if (hpriv->cap & HOST_CAP_64) 588 writel((pp->cmd_slot_dma >> 16) >> 16, 589 port_mmio + PORT_LST_ADDR_HI); 590 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 591 592 if (hpriv->cap & HOST_CAP_64) 593 writel((pp->rx_fis_dma >> 16) >> 16, 594 port_mmio + PORT_FIS_ADDR_HI); 595 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 596 597 /* enable FIS reception */ 598 tmp = readl(port_mmio + PORT_CMD); 599 tmp |= PORT_CMD_FIS_RX; 600 writel(tmp, port_mmio + PORT_CMD); 601 602 /* flush */ 603 readl(port_mmio + PORT_CMD); 604 } 605 606 static int ahci_stop_fis_rx(struct ata_port *ap) 607 { 608 void __iomem *port_mmio = ahci_port_base(ap); 609 u32 tmp; 610 611 /* disable FIS reception */ 612 tmp = readl(port_mmio + PORT_CMD); 613 tmp &= ~PORT_CMD_FIS_RX; 614 writel(tmp, port_mmio + PORT_CMD); 615 616 /* wait for completion, spec says 500ms, give it 1000 */ 617 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 618 PORT_CMD_FIS_ON, 10, 1000); 619 if (tmp & PORT_CMD_FIS_ON) 620 return -EBUSY; 621 622 return 0; 623 } 624 625 static void ahci_power_up(struct ata_port *ap) 626 { 627 struct ahci_host_priv *hpriv = ap->host->private_data; 628 void __iomem *port_mmio = ahci_port_base(ap); 629 u32 cmd; 630 631 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 632 633 /* spin up device */ 634 if (hpriv->cap & HOST_CAP_SSS) { 635 cmd |= PORT_CMD_SPIN_UP; 636 writel(cmd, port_mmio + PORT_CMD); 637 } 638 639 /* wake up link */ 640 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 641 } 642 643 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 644 unsigned int hints) 645 { 646 struct ata_port *ap = link->ap; 647 struct ahci_host_priv *hpriv = ap->host->private_data; 648 struct ahci_port_priv *pp = ap->private_data; 649 void __iomem *port_mmio = ahci_port_base(ap); 650 651 if (policy != ATA_LPM_MAX_POWER) { 652 /* 653 * Disable interrupts on Phy Ready. This keeps us from 654 * getting woken up due to spurious phy ready 655 * interrupts. 656 */ 657 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 658 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 659 660 sata_link_scr_lpm(link, policy, false); 661 } 662 663 if (hpriv->cap & HOST_CAP_ALPM) { 664 u32 cmd = readl(port_mmio + PORT_CMD); 665 666 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 667 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 668 cmd |= PORT_CMD_ICC_ACTIVE; 669 670 writel(cmd, port_mmio + PORT_CMD); 671 readl(port_mmio + PORT_CMD); 672 673 /* wait 10ms to be sure we've come out of LPM state */ 674 ata_msleep(ap, 10); 675 } else { 676 cmd |= PORT_CMD_ALPE; 677 if (policy == ATA_LPM_MIN_POWER) 678 cmd |= PORT_CMD_ASP; 679 680 /* write out new cmd value */ 681 writel(cmd, port_mmio + PORT_CMD); 682 } 683 } 684 685 if (policy == ATA_LPM_MAX_POWER) { 686 sata_link_scr_lpm(link, policy, false); 687 688 /* turn PHYRDY IRQ back on */ 689 pp->intr_mask |= PORT_IRQ_PHYRDY; 690 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 691 } 692 693 return 0; 694 } 695 696 #ifdef CONFIG_PM 697 static void ahci_power_down(struct ata_port *ap) 698 { 699 struct ahci_host_priv *hpriv = ap->host->private_data; 700 void __iomem *port_mmio = ahci_port_base(ap); 701 u32 cmd, scontrol; 702 703 if (!(hpriv->cap & HOST_CAP_SSS)) 704 return; 705 706 /* put device into listen mode, first set PxSCTL.DET to 0 */ 707 scontrol = readl(port_mmio + PORT_SCR_CTL); 708 scontrol &= ~0xf; 709 writel(scontrol, port_mmio + PORT_SCR_CTL); 710 711 /* then set PxCMD.SUD to 0 */ 712 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 713 cmd &= ~PORT_CMD_SPIN_UP; 714 writel(cmd, port_mmio + PORT_CMD); 715 } 716 #endif 717 718 static void ahci_start_port(struct ata_port *ap) 719 { 720 struct ahci_port_priv *pp = ap->private_data; 721 struct ata_link *link; 722 struct ahci_em_priv *emp; 723 ssize_t rc; 724 int i; 725 726 /* enable FIS reception */ 727 ahci_start_fis_rx(ap); 728 729 /* enable DMA */ 730 ahci_start_engine(ap); 731 732 /* turn on LEDs */ 733 if (ap->flags & ATA_FLAG_EM) { 734 ata_for_each_link(link, ap, EDGE) { 735 emp = &pp->em_priv[link->pmp]; 736 737 /* EM Transmit bit maybe busy during init */ 738 for (i = 0; i < EM_MAX_RETRY; i++) { 739 rc = ahci_transmit_led_message(ap, 740 emp->led_state, 741 4); 742 if (rc == -EBUSY) 743 ata_msleep(ap, 1); 744 else 745 break; 746 } 747 } 748 } 749 750 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 751 ata_for_each_link(link, ap, EDGE) 752 ahci_init_sw_activity(link); 753 754 } 755 756 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 757 { 758 int rc; 759 760 /* disable DMA */ 761 rc = ahci_stop_engine(ap); 762 if (rc) { 763 *emsg = "failed to stop engine"; 764 return rc; 765 } 766 767 /* disable FIS reception */ 768 rc = ahci_stop_fis_rx(ap); 769 if (rc) { 770 *emsg = "failed stop FIS RX"; 771 return rc; 772 } 773 774 return 0; 775 } 776 777 int ahci_reset_controller(struct ata_host *host) 778 { 779 struct ahci_host_priv *hpriv = host->private_data; 780 void __iomem *mmio = hpriv->mmio; 781 u32 tmp; 782 783 /* we must be in AHCI mode, before using anything 784 * AHCI-specific, such as HOST_RESET. 785 */ 786 ahci_enable_ahci(mmio); 787 788 /* global controller reset */ 789 if (!ahci_skip_host_reset) { 790 tmp = readl(mmio + HOST_CTL); 791 if ((tmp & HOST_RESET) == 0) { 792 writel(tmp | HOST_RESET, mmio + HOST_CTL); 793 readl(mmio + HOST_CTL); /* flush */ 794 } 795 796 /* 797 * to perform host reset, OS should set HOST_RESET 798 * and poll until this bit is read to be "0". 799 * reset must complete within 1 second, or 800 * the hardware should be considered fried. 801 */ 802 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 803 HOST_RESET, 10, 1000); 804 805 if (tmp & HOST_RESET) { 806 dev_printk(KERN_ERR, host->dev, 807 "controller reset failed (0x%x)\n", tmp); 808 return -EIO; 809 } 810 811 /* turn on AHCI mode */ 812 ahci_enable_ahci(mmio); 813 814 /* Some registers might be cleared on reset. Restore 815 * initial values. 816 */ 817 ahci_restore_initial_config(host); 818 } else 819 dev_printk(KERN_INFO, host->dev, 820 "skipping global host reset\n"); 821 822 return 0; 823 } 824 EXPORT_SYMBOL_GPL(ahci_reset_controller); 825 826 static void ahci_sw_activity(struct ata_link *link) 827 { 828 struct ata_port *ap = link->ap; 829 struct ahci_port_priv *pp = ap->private_data; 830 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 831 832 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 833 return; 834 835 emp->activity++; 836 if (!timer_pending(&emp->timer)) 837 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 838 } 839 840 static void ahci_sw_activity_blink(unsigned long arg) 841 { 842 struct ata_link *link = (struct ata_link *)arg; 843 struct ata_port *ap = link->ap; 844 struct ahci_port_priv *pp = ap->private_data; 845 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 846 unsigned long led_message = emp->led_state; 847 u32 activity_led_state; 848 unsigned long flags; 849 850 led_message &= EM_MSG_LED_VALUE; 851 led_message |= ap->port_no | (link->pmp << 8); 852 853 /* check to see if we've had activity. If so, 854 * toggle state of LED and reset timer. If not, 855 * turn LED to desired idle state. 856 */ 857 spin_lock_irqsave(ap->lock, flags); 858 if (emp->saved_activity != emp->activity) { 859 emp->saved_activity = emp->activity; 860 /* get the current LED state */ 861 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 862 863 if (activity_led_state) 864 activity_led_state = 0; 865 else 866 activity_led_state = 1; 867 868 /* clear old state */ 869 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 870 871 /* toggle state */ 872 led_message |= (activity_led_state << 16); 873 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 874 } else { 875 /* switch to idle */ 876 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 877 if (emp->blink_policy == BLINK_OFF) 878 led_message |= (1 << 16); 879 } 880 spin_unlock_irqrestore(ap->lock, flags); 881 ahci_transmit_led_message(ap, led_message, 4); 882 } 883 884 static void ahci_init_sw_activity(struct ata_link *link) 885 { 886 struct ata_port *ap = link->ap; 887 struct ahci_port_priv *pp = ap->private_data; 888 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 889 890 /* init activity stats, setup timer */ 891 emp->saved_activity = emp->activity = 0; 892 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 893 894 /* check our blink policy and set flag for link if it's enabled */ 895 if (emp->blink_policy) 896 link->flags |= ATA_LFLAG_SW_ACTIVITY; 897 } 898 899 int ahci_reset_em(struct ata_host *host) 900 { 901 struct ahci_host_priv *hpriv = host->private_data; 902 void __iomem *mmio = hpriv->mmio; 903 u32 em_ctl; 904 905 em_ctl = readl(mmio + HOST_EM_CTL); 906 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 907 return -EINVAL; 908 909 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 910 return 0; 911 } 912 EXPORT_SYMBOL_GPL(ahci_reset_em); 913 914 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 915 ssize_t size) 916 { 917 struct ahci_host_priv *hpriv = ap->host->private_data; 918 struct ahci_port_priv *pp = ap->private_data; 919 void __iomem *mmio = hpriv->mmio; 920 u32 em_ctl; 921 u32 message[] = {0, 0}; 922 unsigned long flags; 923 int pmp; 924 struct ahci_em_priv *emp; 925 926 /* get the slot number from the message */ 927 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 928 if (pmp < EM_MAX_SLOTS) 929 emp = &pp->em_priv[pmp]; 930 else 931 return -EINVAL; 932 933 spin_lock_irqsave(ap->lock, flags); 934 935 /* 936 * if we are still busy transmitting a previous message, 937 * do not allow 938 */ 939 em_ctl = readl(mmio + HOST_EM_CTL); 940 if (em_ctl & EM_CTL_TM) { 941 spin_unlock_irqrestore(ap->lock, flags); 942 return -EBUSY; 943 } 944 945 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 946 /* 947 * create message header - this is all zero except for 948 * the message size, which is 4 bytes. 949 */ 950 message[0] |= (4 << 8); 951 952 /* ignore 0:4 of byte zero, fill in port info yourself */ 953 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 954 955 /* write message to EM_LOC */ 956 writel(message[0], mmio + hpriv->em_loc); 957 writel(message[1], mmio + hpriv->em_loc+4); 958 959 /* 960 * tell hardware to transmit the message 961 */ 962 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 963 } 964 965 /* save off new led state for port/slot */ 966 emp->led_state = state; 967 968 spin_unlock_irqrestore(ap->lock, flags); 969 return size; 970 } 971 972 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 973 { 974 struct ahci_port_priv *pp = ap->private_data; 975 struct ata_link *link; 976 struct ahci_em_priv *emp; 977 int rc = 0; 978 979 ata_for_each_link(link, ap, EDGE) { 980 emp = &pp->em_priv[link->pmp]; 981 rc += sprintf(buf, "%lx\n", emp->led_state); 982 } 983 return rc; 984 } 985 986 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 987 size_t size) 988 { 989 int state; 990 int pmp; 991 struct ahci_port_priv *pp = ap->private_data; 992 struct ahci_em_priv *emp; 993 994 state = simple_strtoul(buf, NULL, 0); 995 996 /* get the slot number from the message */ 997 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 998 if (pmp < EM_MAX_SLOTS) 999 emp = &pp->em_priv[pmp]; 1000 else 1001 return -EINVAL; 1002 1003 /* mask off the activity bits if we are in sw_activity 1004 * mode, user should turn off sw_activity before setting 1005 * activity led through em_message 1006 */ 1007 if (emp->blink_policy) 1008 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1009 1010 return ahci_transmit_led_message(ap, state, size); 1011 } 1012 1013 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1014 { 1015 struct ata_link *link = dev->link; 1016 struct ata_port *ap = link->ap; 1017 struct ahci_port_priv *pp = ap->private_data; 1018 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1019 u32 port_led_state = emp->led_state; 1020 1021 /* save the desired Activity LED behavior */ 1022 if (val == OFF) { 1023 /* clear LFLAG */ 1024 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1025 1026 /* set the LED to OFF */ 1027 port_led_state &= EM_MSG_LED_VALUE_OFF; 1028 port_led_state |= (ap->port_no | (link->pmp << 8)); 1029 ahci_transmit_led_message(ap, port_led_state, 4); 1030 } else { 1031 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1032 if (val == BLINK_OFF) { 1033 /* set LED to ON for idle */ 1034 port_led_state &= EM_MSG_LED_VALUE_OFF; 1035 port_led_state |= (ap->port_no | (link->pmp << 8)); 1036 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1037 ahci_transmit_led_message(ap, port_led_state, 4); 1038 } 1039 } 1040 emp->blink_policy = val; 1041 return 0; 1042 } 1043 1044 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1045 { 1046 struct ata_link *link = dev->link; 1047 struct ata_port *ap = link->ap; 1048 struct ahci_port_priv *pp = ap->private_data; 1049 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1050 1051 /* display the saved value of activity behavior for this 1052 * disk. 1053 */ 1054 return sprintf(buf, "%d\n", emp->blink_policy); 1055 } 1056 1057 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1058 int port_no, void __iomem *mmio, 1059 void __iomem *port_mmio) 1060 { 1061 const char *emsg = NULL; 1062 int rc; 1063 u32 tmp; 1064 1065 /* make sure port is not active */ 1066 rc = ahci_deinit_port(ap, &emsg); 1067 if (rc) 1068 dev_warn(dev, "%s (%d)\n", emsg, rc); 1069 1070 /* clear SError */ 1071 tmp = readl(port_mmio + PORT_SCR_ERR); 1072 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1073 writel(tmp, port_mmio + PORT_SCR_ERR); 1074 1075 /* clear port IRQ */ 1076 tmp = readl(port_mmio + PORT_IRQ_STAT); 1077 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1078 if (tmp) 1079 writel(tmp, port_mmio + PORT_IRQ_STAT); 1080 1081 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1082 } 1083 1084 void ahci_init_controller(struct ata_host *host) 1085 { 1086 struct ahci_host_priv *hpriv = host->private_data; 1087 void __iomem *mmio = hpriv->mmio; 1088 int i; 1089 void __iomem *port_mmio; 1090 u32 tmp; 1091 1092 for (i = 0; i < host->n_ports; i++) { 1093 struct ata_port *ap = host->ports[i]; 1094 1095 port_mmio = ahci_port_base(ap); 1096 if (ata_port_is_dummy(ap)) 1097 continue; 1098 1099 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1100 } 1101 1102 tmp = readl(mmio + HOST_CTL); 1103 VPRINTK("HOST_CTL 0x%x\n", tmp); 1104 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1105 tmp = readl(mmio + HOST_CTL); 1106 VPRINTK("HOST_CTL 0x%x\n", tmp); 1107 } 1108 EXPORT_SYMBOL_GPL(ahci_init_controller); 1109 1110 static void ahci_dev_config(struct ata_device *dev) 1111 { 1112 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1113 1114 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1115 dev->max_sectors = 255; 1116 ata_dev_printk(dev, KERN_INFO, 1117 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1118 } 1119 } 1120 1121 static unsigned int ahci_dev_classify(struct ata_port *ap) 1122 { 1123 void __iomem *port_mmio = ahci_port_base(ap); 1124 struct ata_taskfile tf; 1125 u32 tmp; 1126 1127 tmp = readl(port_mmio + PORT_SIG); 1128 tf.lbah = (tmp >> 24) & 0xff; 1129 tf.lbam = (tmp >> 16) & 0xff; 1130 tf.lbal = (tmp >> 8) & 0xff; 1131 tf.nsect = (tmp) & 0xff; 1132 1133 return ata_dev_classify(&tf); 1134 } 1135 1136 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1137 u32 opts) 1138 { 1139 dma_addr_t cmd_tbl_dma; 1140 1141 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1142 1143 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1144 pp->cmd_slot[tag].status = 0; 1145 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1146 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1147 } 1148 1149 int ahci_kick_engine(struct ata_port *ap) 1150 { 1151 void __iomem *port_mmio = ahci_port_base(ap); 1152 struct ahci_host_priv *hpriv = ap->host->private_data; 1153 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1154 u32 tmp; 1155 int busy, rc; 1156 1157 /* stop engine */ 1158 rc = ahci_stop_engine(ap); 1159 if (rc) 1160 goto out_restart; 1161 1162 /* need to do CLO? 1163 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1164 */ 1165 busy = status & (ATA_BUSY | ATA_DRQ); 1166 if (!busy && !sata_pmp_attached(ap)) { 1167 rc = 0; 1168 goto out_restart; 1169 } 1170 1171 if (!(hpriv->cap & HOST_CAP_CLO)) { 1172 rc = -EOPNOTSUPP; 1173 goto out_restart; 1174 } 1175 1176 /* perform CLO */ 1177 tmp = readl(port_mmio + PORT_CMD); 1178 tmp |= PORT_CMD_CLO; 1179 writel(tmp, port_mmio + PORT_CMD); 1180 1181 rc = 0; 1182 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1183 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1184 if (tmp & PORT_CMD_CLO) 1185 rc = -EIO; 1186 1187 /* restart engine */ 1188 out_restart: 1189 ahci_start_engine(ap); 1190 return rc; 1191 } 1192 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1193 1194 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1195 struct ata_taskfile *tf, int is_cmd, u16 flags, 1196 unsigned long timeout_msec) 1197 { 1198 const u32 cmd_fis_len = 5; /* five dwords */ 1199 struct ahci_port_priv *pp = ap->private_data; 1200 void __iomem *port_mmio = ahci_port_base(ap); 1201 u8 *fis = pp->cmd_tbl; 1202 u32 tmp; 1203 1204 /* prep the command */ 1205 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1206 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1207 1208 /* issue & wait */ 1209 writel(1, port_mmio + PORT_CMD_ISSUE); 1210 1211 if (timeout_msec) { 1212 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1213 0x1, 0x1, 1, timeout_msec); 1214 if (tmp & 0x1) { 1215 ahci_kick_engine(ap); 1216 return -EBUSY; 1217 } 1218 } else 1219 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1220 1221 return 0; 1222 } 1223 1224 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1225 int pmp, unsigned long deadline, 1226 int (*check_ready)(struct ata_link *link)) 1227 { 1228 struct ata_port *ap = link->ap; 1229 struct ahci_host_priv *hpriv = ap->host->private_data; 1230 const char *reason = NULL; 1231 unsigned long now, msecs; 1232 struct ata_taskfile tf; 1233 int rc; 1234 1235 DPRINTK("ENTER\n"); 1236 1237 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1238 rc = ahci_kick_engine(ap); 1239 if (rc && rc != -EOPNOTSUPP) 1240 ata_link_printk(link, KERN_WARNING, 1241 "failed to reset engine (errno=%d)\n", rc); 1242 1243 ata_tf_init(link->device, &tf); 1244 1245 /* issue the first D2H Register FIS */ 1246 msecs = 0; 1247 now = jiffies; 1248 if (time_after(deadline, now)) 1249 msecs = jiffies_to_msecs(deadline - now); 1250 1251 tf.ctl |= ATA_SRST; 1252 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1253 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1254 rc = -EIO; 1255 reason = "1st FIS failed"; 1256 goto fail; 1257 } 1258 1259 /* spec says at least 5us, but be generous and sleep for 1ms */ 1260 ata_msleep(ap, 1); 1261 1262 /* issue the second D2H Register FIS */ 1263 tf.ctl &= ~ATA_SRST; 1264 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1265 1266 /* wait for link to become ready */ 1267 rc = ata_wait_after_reset(link, deadline, check_ready); 1268 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1269 /* 1270 * Workaround for cases where link online status can't 1271 * be trusted. Treat device readiness timeout as link 1272 * offline. 1273 */ 1274 ata_link_printk(link, KERN_INFO, 1275 "device not ready, treating as offline\n"); 1276 *class = ATA_DEV_NONE; 1277 } else if (rc) { 1278 /* link occupied, -ENODEV too is an error */ 1279 reason = "device not ready"; 1280 goto fail; 1281 } else 1282 *class = ahci_dev_classify(ap); 1283 1284 DPRINTK("EXIT, class=%u\n", *class); 1285 return 0; 1286 1287 fail: 1288 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 1289 return rc; 1290 } 1291 1292 int ahci_check_ready(struct ata_link *link) 1293 { 1294 void __iomem *port_mmio = ahci_port_base(link->ap); 1295 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1296 1297 return ata_check_ready(status); 1298 } 1299 EXPORT_SYMBOL_GPL(ahci_check_ready); 1300 1301 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1302 unsigned long deadline) 1303 { 1304 int pmp = sata_srst_pmp(link); 1305 1306 DPRINTK("ENTER\n"); 1307 1308 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1309 } 1310 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1311 1312 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1313 unsigned long deadline) 1314 { 1315 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1316 struct ata_port *ap = link->ap; 1317 struct ahci_port_priv *pp = ap->private_data; 1318 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1319 struct ata_taskfile tf; 1320 bool online; 1321 int rc; 1322 1323 DPRINTK("ENTER\n"); 1324 1325 ahci_stop_engine(ap); 1326 1327 /* clear D2H reception area to properly wait for D2H FIS */ 1328 ata_tf_init(link->device, &tf); 1329 tf.command = 0x80; 1330 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1331 1332 rc = sata_link_hardreset(link, timing, deadline, &online, 1333 ahci_check_ready); 1334 1335 ahci_start_engine(ap); 1336 1337 if (online) 1338 *class = ahci_dev_classify(ap); 1339 1340 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1341 return rc; 1342 } 1343 1344 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1345 { 1346 struct ata_port *ap = link->ap; 1347 void __iomem *port_mmio = ahci_port_base(ap); 1348 u32 new_tmp, tmp; 1349 1350 ata_std_postreset(link, class); 1351 1352 /* Make sure port's ATAPI bit is set appropriately */ 1353 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1354 if (*class == ATA_DEV_ATAPI) 1355 new_tmp |= PORT_CMD_ATAPI; 1356 else 1357 new_tmp &= ~PORT_CMD_ATAPI; 1358 if (new_tmp != tmp) { 1359 writel(new_tmp, port_mmio + PORT_CMD); 1360 readl(port_mmio + PORT_CMD); /* flush */ 1361 } 1362 } 1363 1364 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1365 { 1366 struct scatterlist *sg; 1367 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1368 unsigned int si; 1369 1370 VPRINTK("ENTER\n"); 1371 1372 /* 1373 * Next, the S/G list. 1374 */ 1375 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1376 dma_addr_t addr = sg_dma_address(sg); 1377 u32 sg_len = sg_dma_len(sg); 1378 1379 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1380 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1381 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1382 } 1383 1384 return si; 1385 } 1386 1387 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1388 { 1389 struct ata_port *ap = qc->ap; 1390 struct ahci_port_priv *pp = ap->private_data; 1391 1392 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1393 return ata_std_qc_defer(qc); 1394 else 1395 return sata_pmp_qc_defer_cmd_switch(qc); 1396 } 1397 1398 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1399 { 1400 struct ata_port *ap = qc->ap; 1401 struct ahci_port_priv *pp = ap->private_data; 1402 int is_atapi = ata_is_atapi(qc->tf.protocol); 1403 void *cmd_tbl; 1404 u32 opts; 1405 const u32 cmd_fis_len = 5; /* five dwords */ 1406 unsigned int n_elem; 1407 1408 /* 1409 * Fill in command table information. First, the header, 1410 * a SATA Register - Host to Device command FIS. 1411 */ 1412 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1413 1414 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1415 if (is_atapi) { 1416 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1417 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1418 } 1419 1420 n_elem = 0; 1421 if (qc->flags & ATA_QCFLAG_DMAMAP) 1422 n_elem = ahci_fill_sg(qc, cmd_tbl); 1423 1424 /* 1425 * Fill in command slot information. 1426 */ 1427 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1428 if (qc->tf.flags & ATA_TFLAG_WRITE) 1429 opts |= AHCI_CMD_WRITE; 1430 if (is_atapi) 1431 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1432 1433 ahci_fill_cmd_slot(pp, qc->tag, opts); 1434 } 1435 1436 static void ahci_fbs_dec_intr(struct ata_port *ap) 1437 { 1438 struct ahci_port_priv *pp = ap->private_data; 1439 void __iomem *port_mmio = ahci_port_base(ap); 1440 u32 fbs = readl(port_mmio + PORT_FBS); 1441 int retries = 3; 1442 1443 DPRINTK("ENTER\n"); 1444 BUG_ON(!pp->fbs_enabled); 1445 1446 /* time to wait for DEC is not specified by AHCI spec, 1447 * add a retry loop for safety. 1448 */ 1449 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1450 fbs = readl(port_mmio + PORT_FBS); 1451 while ((fbs & PORT_FBS_DEC) && retries--) { 1452 udelay(1); 1453 fbs = readl(port_mmio + PORT_FBS); 1454 } 1455 1456 if (fbs & PORT_FBS_DEC) 1457 dev_printk(KERN_ERR, ap->host->dev, 1458 "failed to clear device error\n"); 1459 } 1460 1461 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1462 { 1463 struct ahci_host_priv *hpriv = ap->host->private_data; 1464 struct ahci_port_priv *pp = ap->private_data; 1465 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1466 struct ata_link *link = NULL; 1467 struct ata_queued_cmd *active_qc; 1468 struct ata_eh_info *active_ehi; 1469 bool fbs_need_dec = false; 1470 u32 serror; 1471 1472 /* determine active link with error */ 1473 if (pp->fbs_enabled) { 1474 void __iomem *port_mmio = ahci_port_base(ap); 1475 u32 fbs = readl(port_mmio + PORT_FBS); 1476 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1477 1478 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) && 1479 ata_link_online(&ap->pmp_link[pmp])) { 1480 link = &ap->pmp_link[pmp]; 1481 fbs_need_dec = true; 1482 } 1483 1484 } else 1485 ata_for_each_link(link, ap, EDGE) 1486 if (ata_link_active(link)) 1487 break; 1488 1489 if (!link) 1490 link = &ap->link; 1491 1492 active_qc = ata_qc_from_tag(ap, link->active_tag); 1493 active_ehi = &link->eh_info; 1494 1495 /* record irq stat */ 1496 ata_ehi_clear_desc(host_ehi); 1497 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1498 1499 /* AHCI needs SError cleared; otherwise, it might lock up */ 1500 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1501 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1502 host_ehi->serror |= serror; 1503 1504 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1505 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1506 irq_stat &= ~PORT_IRQ_IF_ERR; 1507 1508 if (irq_stat & PORT_IRQ_TF_ERR) { 1509 /* If qc is active, charge it; otherwise, the active 1510 * link. There's no active qc on NCQ errors. It will 1511 * be determined by EH by reading log page 10h. 1512 */ 1513 if (active_qc) 1514 active_qc->err_mask |= AC_ERR_DEV; 1515 else 1516 active_ehi->err_mask |= AC_ERR_DEV; 1517 1518 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1519 host_ehi->serror &= ~SERR_INTERNAL; 1520 } 1521 1522 if (irq_stat & PORT_IRQ_UNK_FIS) { 1523 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 1524 1525 active_ehi->err_mask |= AC_ERR_HSM; 1526 active_ehi->action |= ATA_EH_RESET; 1527 ata_ehi_push_desc(active_ehi, 1528 "unknown FIS %08x %08x %08x %08x" , 1529 unk[0], unk[1], unk[2], unk[3]); 1530 } 1531 1532 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1533 active_ehi->err_mask |= AC_ERR_HSM; 1534 active_ehi->action |= ATA_EH_RESET; 1535 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1536 } 1537 1538 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1539 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1540 host_ehi->action |= ATA_EH_RESET; 1541 ata_ehi_push_desc(host_ehi, "host bus error"); 1542 } 1543 1544 if (irq_stat & PORT_IRQ_IF_ERR) { 1545 if (fbs_need_dec) 1546 active_ehi->err_mask |= AC_ERR_DEV; 1547 else { 1548 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1549 host_ehi->action |= ATA_EH_RESET; 1550 } 1551 1552 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1553 } 1554 1555 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1556 ata_ehi_hotplugged(host_ehi); 1557 ata_ehi_push_desc(host_ehi, "%s", 1558 irq_stat & PORT_IRQ_CONNECT ? 1559 "connection status changed" : "PHY RDY changed"); 1560 } 1561 1562 /* okay, let's hand over to EH */ 1563 1564 if (irq_stat & PORT_IRQ_FREEZE) 1565 ata_port_freeze(ap); 1566 else if (fbs_need_dec) { 1567 ata_link_abort(link); 1568 ahci_fbs_dec_intr(ap); 1569 } else 1570 ata_port_abort(ap); 1571 } 1572 1573 static void ahci_port_intr(struct ata_port *ap) 1574 { 1575 void __iomem *port_mmio = ahci_port_base(ap); 1576 struct ata_eh_info *ehi = &ap->link.eh_info; 1577 struct ahci_port_priv *pp = ap->private_data; 1578 struct ahci_host_priv *hpriv = ap->host->private_data; 1579 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1580 u32 status, qc_active = 0; 1581 int rc; 1582 1583 status = readl(port_mmio + PORT_IRQ_STAT); 1584 writel(status, port_mmio + PORT_IRQ_STAT); 1585 1586 /* ignore BAD_PMP while resetting */ 1587 if (unlikely(resetting)) 1588 status &= ~PORT_IRQ_BAD_PMP; 1589 1590 /* if LPM is enabled, PHYRDY doesn't mean anything */ 1591 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) { 1592 status &= ~PORT_IRQ_PHYRDY; 1593 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1594 } 1595 1596 if (unlikely(status & PORT_IRQ_ERROR)) { 1597 ahci_error_intr(ap, status); 1598 return; 1599 } 1600 1601 if (status & PORT_IRQ_SDB_FIS) { 1602 /* If SNotification is available, leave notification 1603 * handling to sata_async_notification(). If not, 1604 * emulate it by snooping SDB FIS RX area. 1605 * 1606 * Snooping FIS RX area is probably cheaper than 1607 * poking SNotification but some constrollers which 1608 * implement SNotification, ICH9 for example, don't 1609 * store AN SDB FIS into receive area. 1610 */ 1611 if (hpriv->cap & HOST_CAP_SNTF) 1612 sata_async_notification(ap); 1613 else { 1614 /* If the 'N' bit in word 0 of the FIS is set, 1615 * we just received asynchronous notification. 1616 * Tell libata about it. 1617 * 1618 * Lack of SNotification should not appear in 1619 * ahci 1.2, so the workaround is unnecessary 1620 * when FBS is enabled. 1621 */ 1622 if (pp->fbs_enabled) 1623 WARN_ON_ONCE(1); 1624 else { 1625 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1626 u32 f0 = le32_to_cpu(f[0]); 1627 if (f0 & (1 << 15)) 1628 sata_async_notification(ap); 1629 } 1630 } 1631 } 1632 1633 /* pp->active_link is not reliable once FBS is enabled, both 1634 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1635 * NCQ and non-NCQ commands may be in flight at the same time. 1636 */ 1637 if (pp->fbs_enabled) { 1638 if (ap->qc_active) { 1639 qc_active = readl(port_mmio + PORT_SCR_ACT); 1640 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1641 } 1642 } else { 1643 /* pp->active_link is valid iff any command is in flight */ 1644 if (ap->qc_active && pp->active_link->sactive) 1645 qc_active = readl(port_mmio + PORT_SCR_ACT); 1646 else 1647 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1648 } 1649 1650 1651 rc = ata_qc_complete_multiple(ap, qc_active); 1652 1653 /* while resetting, invalid completions are expected */ 1654 if (unlikely(rc < 0 && !resetting)) { 1655 ehi->err_mask |= AC_ERR_HSM; 1656 ehi->action |= ATA_EH_RESET; 1657 ata_port_freeze(ap); 1658 } 1659 } 1660 1661 irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1662 { 1663 struct ata_host *host = dev_instance; 1664 struct ahci_host_priv *hpriv; 1665 unsigned int i, handled = 0; 1666 void __iomem *mmio; 1667 u32 irq_stat, irq_masked; 1668 1669 VPRINTK("ENTER\n"); 1670 1671 hpriv = host->private_data; 1672 mmio = hpriv->mmio; 1673 1674 /* sigh. 0xffffffff is a valid return from h/w */ 1675 irq_stat = readl(mmio + HOST_IRQ_STAT); 1676 if (!irq_stat) 1677 return IRQ_NONE; 1678 1679 irq_masked = irq_stat & hpriv->port_map; 1680 1681 spin_lock(&host->lock); 1682 1683 for (i = 0; i < host->n_ports; i++) { 1684 struct ata_port *ap; 1685 1686 if (!(irq_masked & (1 << i))) 1687 continue; 1688 1689 ap = host->ports[i]; 1690 if (ap) { 1691 ahci_port_intr(ap); 1692 VPRINTK("port %u\n", i); 1693 } else { 1694 VPRINTK("port %u (no irq)\n", i); 1695 if (ata_ratelimit()) 1696 dev_printk(KERN_WARNING, host->dev, 1697 "interrupt on disabled port %u\n", i); 1698 } 1699 1700 handled = 1; 1701 } 1702 1703 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1704 * it should be cleared after all the port events are cleared; 1705 * otherwise, it will raise a spurious interrupt after each 1706 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1707 * information. 1708 * 1709 * Also, use the unmasked value to clear interrupt as spurious 1710 * pending event on a dummy port might cause screaming IRQ. 1711 */ 1712 writel(irq_stat, mmio + HOST_IRQ_STAT); 1713 1714 spin_unlock(&host->lock); 1715 1716 VPRINTK("EXIT\n"); 1717 1718 return IRQ_RETVAL(handled); 1719 } 1720 EXPORT_SYMBOL_GPL(ahci_interrupt); 1721 1722 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1723 { 1724 struct ata_port *ap = qc->ap; 1725 void __iomem *port_mmio = ahci_port_base(ap); 1726 struct ahci_port_priv *pp = ap->private_data; 1727 1728 /* Keep track of the currently active link. It will be used 1729 * in completion path to determine whether NCQ phase is in 1730 * progress. 1731 */ 1732 pp->active_link = qc->dev->link; 1733 1734 if (qc->tf.protocol == ATA_PROT_NCQ) 1735 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1736 1737 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1738 u32 fbs = readl(port_mmio + PORT_FBS); 1739 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1740 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1741 writel(fbs, port_mmio + PORT_FBS); 1742 pp->fbs_last_dev = qc->dev->link->pmp; 1743 } 1744 1745 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1746 1747 ahci_sw_activity(qc->dev->link); 1748 1749 return 0; 1750 } 1751 1752 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1753 { 1754 struct ahci_port_priv *pp = qc->ap->private_data; 1755 u8 *rx_fis = pp->rx_fis; 1756 1757 if (pp->fbs_enabled) 1758 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 1759 1760 /* 1761 * After a successful execution of an ATA PIO data-in command, 1762 * the device doesn't send D2H Reg FIS to update the TF and 1763 * the host should take TF and E_Status from the preceding PIO 1764 * Setup FIS. 1765 */ 1766 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 1767 !(qc->flags & ATA_QCFLAG_FAILED)) { 1768 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 1769 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 1770 } else 1771 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 1772 1773 return true; 1774 } 1775 1776 static void ahci_freeze(struct ata_port *ap) 1777 { 1778 void __iomem *port_mmio = ahci_port_base(ap); 1779 1780 /* turn IRQ off */ 1781 writel(0, port_mmio + PORT_IRQ_MASK); 1782 } 1783 1784 static void ahci_thaw(struct ata_port *ap) 1785 { 1786 struct ahci_host_priv *hpriv = ap->host->private_data; 1787 void __iomem *mmio = hpriv->mmio; 1788 void __iomem *port_mmio = ahci_port_base(ap); 1789 u32 tmp; 1790 struct ahci_port_priv *pp = ap->private_data; 1791 1792 /* clear IRQ */ 1793 tmp = readl(port_mmio + PORT_IRQ_STAT); 1794 writel(tmp, port_mmio + PORT_IRQ_STAT); 1795 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 1796 1797 /* turn IRQ back on */ 1798 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1799 } 1800 1801 static void ahci_error_handler(struct ata_port *ap) 1802 { 1803 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1804 /* restart engine */ 1805 ahci_stop_engine(ap); 1806 ahci_start_engine(ap); 1807 } 1808 1809 sata_pmp_error_handler(ap); 1810 1811 if (!ata_dev_enabled(ap->link.device)) 1812 ahci_stop_engine(ap); 1813 } 1814 1815 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1816 { 1817 struct ata_port *ap = qc->ap; 1818 1819 /* make DMA engine forget about the failed command */ 1820 if (qc->flags & ATA_QCFLAG_FAILED) 1821 ahci_kick_engine(ap); 1822 } 1823 1824 static void ahci_enable_fbs(struct ata_port *ap) 1825 { 1826 struct ahci_port_priv *pp = ap->private_data; 1827 void __iomem *port_mmio = ahci_port_base(ap); 1828 u32 fbs; 1829 int rc; 1830 1831 if (!pp->fbs_supported) 1832 return; 1833 1834 fbs = readl(port_mmio + PORT_FBS); 1835 if (fbs & PORT_FBS_EN) { 1836 pp->fbs_enabled = true; 1837 pp->fbs_last_dev = -1; /* initialization */ 1838 return; 1839 } 1840 1841 rc = ahci_stop_engine(ap); 1842 if (rc) 1843 return; 1844 1845 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 1846 fbs = readl(port_mmio + PORT_FBS); 1847 if (fbs & PORT_FBS_EN) { 1848 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n"); 1849 pp->fbs_enabled = true; 1850 pp->fbs_last_dev = -1; /* initialization */ 1851 } else 1852 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n"); 1853 1854 ahci_start_engine(ap); 1855 } 1856 1857 static void ahci_disable_fbs(struct ata_port *ap) 1858 { 1859 struct ahci_port_priv *pp = ap->private_data; 1860 void __iomem *port_mmio = ahci_port_base(ap); 1861 u32 fbs; 1862 int rc; 1863 1864 if (!pp->fbs_supported) 1865 return; 1866 1867 fbs = readl(port_mmio + PORT_FBS); 1868 if ((fbs & PORT_FBS_EN) == 0) { 1869 pp->fbs_enabled = false; 1870 return; 1871 } 1872 1873 rc = ahci_stop_engine(ap); 1874 if (rc) 1875 return; 1876 1877 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 1878 fbs = readl(port_mmio + PORT_FBS); 1879 if (fbs & PORT_FBS_EN) 1880 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n"); 1881 else { 1882 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n"); 1883 pp->fbs_enabled = false; 1884 } 1885 1886 ahci_start_engine(ap); 1887 } 1888 1889 static void ahci_pmp_attach(struct ata_port *ap) 1890 { 1891 void __iomem *port_mmio = ahci_port_base(ap); 1892 struct ahci_port_priv *pp = ap->private_data; 1893 u32 cmd; 1894 1895 cmd = readl(port_mmio + PORT_CMD); 1896 cmd |= PORT_CMD_PMP; 1897 writel(cmd, port_mmio + PORT_CMD); 1898 1899 ahci_enable_fbs(ap); 1900 1901 pp->intr_mask |= PORT_IRQ_BAD_PMP; 1902 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1903 } 1904 1905 static void ahci_pmp_detach(struct ata_port *ap) 1906 { 1907 void __iomem *port_mmio = ahci_port_base(ap); 1908 struct ahci_port_priv *pp = ap->private_data; 1909 u32 cmd; 1910 1911 ahci_disable_fbs(ap); 1912 1913 cmd = readl(port_mmio + PORT_CMD); 1914 cmd &= ~PORT_CMD_PMP; 1915 writel(cmd, port_mmio + PORT_CMD); 1916 1917 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 1918 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1919 } 1920 1921 static int ahci_port_resume(struct ata_port *ap) 1922 { 1923 ahci_power_up(ap); 1924 ahci_start_port(ap); 1925 1926 if (sata_pmp_attached(ap)) 1927 ahci_pmp_attach(ap); 1928 else 1929 ahci_pmp_detach(ap); 1930 1931 return 0; 1932 } 1933 1934 #ifdef CONFIG_PM 1935 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 1936 { 1937 const char *emsg = NULL; 1938 int rc; 1939 1940 rc = ahci_deinit_port(ap, &emsg); 1941 if (rc == 0) 1942 ahci_power_down(ap); 1943 else { 1944 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 1945 ahci_start_port(ap); 1946 } 1947 1948 return rc; 1949 } 1950 #endif 1951 1952 static int ahci_port_start(struct ata_port *ap) 1953 { 1954 struct ahci_host_priv *hpriv = ap->host->private_data; 1955 struct device *dev = ap->host->dev; 1956 struct ahci_port_priv *pp; 1957 void *mem; 1958 dma_addr_t mem_dma; 1959 size_t dma_sz, rx_fis_sz; 1960 1961 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1962 if (!pp) 1963 return -ENOMEM; 1964 1965 /* check FBS capability */ 1966 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 1967 void __iomem *port_mmio = ahci_port_base(ap); 1968 u32 cmd = readl(port_mmio + PORT_CMD); 1969 if (cmd & PORT_CMD_FBSCP) 1970 pp->fbs_supported = true; 1971 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 1972 dev_printk(KERN_INFO, dev, 1973 "port %d can do FBS, forcing FBSCP\n", 1974 ap->port_no); 1975 pp->fbs_supported = true; 1976 } else 1977 dev_printk(KERN_WARNING, dev, 1978 "port %d is not capable of FBS\n", 1979 ap->port_no); 1980 } 1981 1982 if (pp->fbs_supported) { 1983 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 1984 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 1985 } else { 1986 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 1987 rx_fis_sz = AHCI_RX_FIS_SZ; 1988 } 1989 1990 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 1991 if (!mem) 1992 return -ENOMEM; 1993 memset(mem, 0, dma_sz); 1994 1995 /* 1996 * First item in chunk of DMA memory: 32-slot command table, 1997 * 32 bytes each in size 1998 */ 1999 pp->cmd_slot = mem; 2000 pp->cmd_slot_dma = mem_dma; 2001 2002 mem += AHCI_CMD_SLOT_SZ; 2003 mem_dma += AHCI_CMD_SLOT_SZ; 2004 2005 /* 2006 * Second item: Received-FIS area 2007 */ 2008 pp->rx_fis = mem; 2009 pp->rx_fis_dma = mem_dma; 2010 2011 mem += rx_fis_sz; 2012 mem_dma += rx_fis_sz; 2013 2014 /* 2015 * Third item: data area for storing a single command 2016 * and its scatter-gather table 2017 */ 2018 pp->cmd_tbl = mem; 2019 pp->cmd_tbl_dma = mem_dma; 2020 2021 /* 2022 * Save off initial list of interrupts to be enabled. 2023 * This could be changed later 2024 */ 2025 pp->intr_mask = DEF_PORT_IRQ; 2026 2027 ap->private_data = pp; 2028 2029 /* engage engines, captain */ 2030 return ahci_port_resume(ap); 2031 } 2032 2033 static void ahci_port_stop(struct ata_port *ap) 2034 { 2035 const char *emsg = NULL; 2036 int rc; 2037 2038 /* de-initialize port */ 2039 rc = ahci_deinit_port(ap, &emsg); 2040 if (rc) 2041 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 2042 } 2043 2044 void ahci_print_info(struct ata_host *host, const char *scc_s) 2045 { 2046 struct ahci_host_priv *hpriv = host->private_data; 2047 void __iomem *mmio = hpriv->mmio; 2048 u32 vers, cap, cap2, impl, speed; 2049 const char *speed_s; 2050 2051 vers = readl(mmio + HOST_VERSION); 2052 cap = hpriv->cap; 2053 cap2 = hpriv->cap2; 2054 impl = hpriv->port_map; 2055 2056 speed = (cap >> 20) & 0xf; 2057 if (speed == 1) 2058 speed_s = "1.5"; 2059 else if (speed == 2) 2060 speed_s = "3"; 2061 else if (speed == 3) 2062 speed_s = "6"; 2063 else 2064 speed_s = "?"; 2065 2066 dev_info(host->dev, 2067 "AHCI %02x%02x.%02x%02x " 2068 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2069 , 2070 2071 (vers >> 24) & 0xff, 2072 (vers >> 16) & 0xff, 2073 (vers >> 8) & 0xff, 2074 vers & 0xff, 2075 2076 ((cap >> 8) & 0x1f) + 1, 2077 (cap & 0x1f) + 1, 2078 speed_s, 2079 impl, 2080 scc_s); 2081 2082 dev_info(host->dev, 2083 "flags: " 2084 "%s%s%s%s%s%s%s" 2085 "%s%s%s%s%s%s%s" 2086 "%s%s%s%s%s%s\n" 2087 , 2088 2089 cap & HOST_CAP_64 ? "64bit " : "", 2090 cap & HOST_CAP_NCQ ? "ncq " : "", 2091 cap & HOST_CAP_SNTF ? "sntf " : "", 2092 cap & HOST_CAP_MPS ? "ilck " : "", 2093 cap & HOST_CAP_SSS ? "stag " : "", 2094 cap & HOST_CAP_ALPM ? "pm " : "", 2095 cap & HOST_CAP_LED ? "led " : "", 2096 cap & HOST_CAP_CLO ? "clo " : "", 2097 cap & HOST_CAP_ONLY ? "only " : "", 2098 cap & HOST_CAP_PMP ? "pmp " : "", 2099 cap & HOST_CAP_FBS ? "fbs " : "", 2100 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2101 cap & HOST_CAP_SSC ? "slum " : "", 2102 cap & HOST_CAP_PART ? "part " : "", 2103 cap & HOST_CAP_CCC ? "ccc " : "", 2104 cap & HOST_CAP_EMS ? "ems " : "", 2105 cap & HOST_CAP_SXS ? "sxs " : "", 2106 cap2 & HOST_CAP2_APST ? "apst " : "", 2107 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2108 cap2 & HOST_CAP2_BOH ? "boh " : "" 2109 ); 2110 } 2111 EXPORT_SYMBOL_GPL(ahci_print_info); 2112 2113 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2114 struct ata_port_info *pi) 2115 { 2116 u8 messages; 2117 void __iomem *mmio = hpriv->mmio; 2118 u32 em_loc = readl(mmio + HOST_EM_LOC); 2119 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2120 2121 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2122 return; 2123 2124 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2125 2126 if (messages) { 2127 /* store em_loc */ 2128 hpriv->em_loc = ((em_loc >> 16) * 4); 2129 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2130 hpriv->em_msg_type = messages; 2131 pi->flags |= ATA_FLAG_EM; 2132 if (!(em_ctl & EM_CTL_ALHD)) 2133 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2134 } 2135 } 2136 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2137 2138 MODULE_AUTHOR("Jeff Garzik"); 2139 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2140 MODULE_LICENSE("GPL"); 2141