1 /* 2 * libahci.c - Common AHCI SATA low-level routines 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2004-2005 Red Hat, Inc. 9 * 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; see the file COPYING. If not, write to 23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * 26 * libata documentation is available via 'make {ps|pdf}docs', 27 * as Documentation/DocBook/libata.* 28 * 29 * AHCI hardware documentation: 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf 32 * 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/gfp.h> 37 #include <linux/module.h> 38 #include <linux/init.h> 39 #include <linux/blkdev.h> 40 #include <linux/delay.h> 41 #include <linux/interrupt.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/device.h> 44 #include <scsi/scsi_host.h> 45 #include <scsi/scsi_cmnd.h> 46 #include <linux/libata.h> 47 #include "ahci.h" 48 49 static int ahci_skip_host_reset; 50 int ahci_ignore_sss; 51 EXPORT_SYMBOL_GPL(ahci_ignore_sss); 52 53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444); 54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)"); 55 56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444); 57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)"); 58 59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 60 unsigned hints); 61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf); 62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 63 size_t size); 64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 65 ssize_t size); 66 67 68 69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); 70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); 71 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 72 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc); 73 static int ahci_port_start(struct ata_port *ap); 74 static void ahci_port_stop(struct ata_port *ap); 75 static void ahci_qc_prep(struct ata_queued_cmd *qc); 76 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc); 77 static void ahci_freeze(struct ata_port *ap); 78 static void ahci_thaw(struct ata_port *ap); 79 static void ahci_enable_fbs(struct ata_port *ap); 80 static void ahci_disable_fbs(struct ata_port *ap); 81 static void ahci_pmp_attach(struct ata_port *ap); 82 static void ahci_pmp_detach(struct ata_port *ap); 83 static int ahci_softreset(struct ata_link *link, unsigned int *class, 84 unsigned long deadline); 85 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 86 unsigned long deadline); 87 static void ahci_postreset(struct ata_link *link, unsigned int *class); 88 static void ahci_error_handler(struct ata_port *ap); 89 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); 90 static void ahci_dev_config(struct ata_device *dev); 91 #ifdef CONFIG_PM 92 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); 93 #endif 94 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf); 95 static ssize_t ahci_activity_store(struct ata_device *dev, 96 enum sw_activity val); 97 static void ahci_init_sw_activity(struct ata_link *link); 98 99 static ssize_t ahci_show_host_caps(struct device *dev, 100 struct device_attribute *attr, char *buf); 101 static ssize_t ahci_show_host_cap2(struct device *dev, 102 struct device_attribute *attr, char *buf); 103 static ssize_t ahci_show_host_version(struct device *dev, 104 struct device_attribute *attr, char *buf); 105 static ssize_t ahci_show_port_cmd(struct device *dev, 106 struct device_attribute *attr, char *buf); 107 static ssize_t ahci_read_em_buffer(struct device *dev, 108 struct device_attribute *attr, char *buf); 109 static ssize_t ahci_store_em_buffer(struct device *dev, 110 struct device_attribute *attr, 111 const char *buf, size_t size); 112 static ssize_t ahci_show_em_supported(struct device *dev, 113 struct device_attribute *attr, char *buf); 114 115 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL); 116 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL); 117 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL); 118 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL); 119 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO, 120 ahci_read_em_buffer, ahci_store_em_buffer); 121 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL); 122 123 struct device_attribute *ahci_shost_attrs[] = { 124 &dev_attr_link_power_management_policy, 125 &dev_attr_em_message_type, 126 &dev_attr_em_message, 127 &dev_attr_ahci_host_caps, 128 &dev_attr_ahci_host_cap2, 129 &dev_attr_ahci_host_version, 130 &dev_attr_ahci_port_cmd, 131 &dev_attr_em_buffer, 132 &dev_attr_em_message_supported, 133 NULL 134 }; 135 EXPORT_SYMBOL_GPL(ahci_shost_attrs); 136 137 struct device_attribute *ahci_sdev_attrs[] = { 138 &dev_attr_sw_activity, 139 &dev_attr_unload_heads, 140 NULL 141 }; 142 EXPORT_SYMBOL_GPL(ahci_sdev_attrs); 143 144 struct ata_port_operations ahci_ops = { 145 .inherits = &sata_pmp_port_ops, 146 147 .qc_defer = ahci_pmp_qc_defer, 148 .qc_prep = ahci_qc_prep, 149 .qc_issue = ahci_qc_issue, 150 .qc_fill_rtf = ahci_qc_fill_rtf, 151 152 .freeze = ahci_freeze, 153 .thaw = ahci_thaw, 154 .softreset = ahci_softreset, 155 .hardreset = ahci_hardreset, 156 .postreset = ahci_postreset, 157 .pmp_softreset = ahci_softreset, 158 .error_handler = ahci_error_handler, 159 .post_internal_cmd = ahci_post_internal_cmd, 160 .dev_config = ahci_dev_config, 161 162 .scr_read = ahci_scr_read, 163 .scr_write = ahci_scr_write, 164 .pmp_attach = ahci_pmp_attach, 165 .pmp_detach = ahci_pmp_detach, 166 167 .set_lpm = ahci_set_lpm, 168 .em_show = ahci_led_show, 169 .em_store = ahci_led_store, 170 .sw_activity_show = ahci_activity_show, 171 .sw_activity_store = ahci_activity_store, 172 #ifdef CONFIG_PM 173 .port_suspend = ahci_port_suspend, 174 .port_resume = ahci_port_resume, 175 #endif 176 .port_start = ahci_port_start, 177 .port_stop = ahci_port_stop, 178 }; 179 EXPORT_SYMBOL_GPL(ahci_ops); 180 181 int ahci_em_messages = 1; 182 EXPORT_SYMBOL_GPL(ahci_em_messages); 183 module_param(ahci_em_messages, int, 0444); 184 /* add other LED protocol types when they become supported */ 185 MODULE_PARM_DESC(ahci_em_messages, 186 "AHCI Enclosure Management Message control (0 = off, 1 = on)"); 187 188 static void ahci_enable_ahci(void __iomem *mmio) 189 { 190 int i; 191 u32 tmp; 192 193 /* turn on AHCI_EN */ 194 tmp = readl(mmio + HOST_CTL); 195 if (tmp & HOST_AHCI_EN) 196 return; 197 198 /* Some controllers need AHCI_EN to be written multiple times. 199 * Try a few times before giving up. 200 */ 201 for (i = 0; i < 5; i++) { 202 tmp |= HOST_AHCI_EN; 203 writel(tmp, mmio + HOST_CTL); 204 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */ 205 if (tmp & HOST_AHCI_EN) 206 return; 207 msleep(10); 208 } 209 210 WARN_ON(1); 211 } 212 213 static ssize_t ahci_show_host_caps(struct device *dev, 214 struct device_attribute *attr, char *buf) 215 { 216 struct Scsi_Host *shost = class_to_shost(dev); 217 struct ata_port *ap = ata_shost_to_port(shost); 218 struct ahci_host_priv *hpriv = ap->host->private_data; 219 220 return sprintf(buf, "%x\n", hpriv->cap); 221 } 222 223 static ssize_t ahci_show_host_cap2(struct device *dev, 224 struct device_attribute *attr, char *buf) 225 { 226 struct Scsi_Host *shost = class_to_shost(dev); 227 struct ata_port *ap = ata_shost_to_port(shost); 228 struct ahci_host_priv *hpriv = ap->host->private_data; 229 230 return sprintf(buf, "%x\n", hpriv->cap2); 231 } 232 233 static ssize_t ahci_show_host_version(struct device *dev, 234 struct device_attribute *attr, char *buf) 235 { 236 struct Scsi_Host *shost = class_to_shost(dev); 237 struct ata_port *ap = ata_shost_to_port(shost); 238 struct ahci_host_priv *hpriv = ap->host->private_data; 239 void __iomem *mmio = hpriv->mmio; 240 241 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION)); 242 } 243 244 static ssize_t ahci_show_port_cmd(struct device *dev, 245 struct device_attribute *attr, char *buf) 246 { 247 struct Scsi_Host *shost = class_to_shost(dev); 248 struct ata_port *ap = ata_shost_to_port(shost); 249 void __iomem *port_mmio = ahci_port_base(ap); 250 251 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); 252 } 253 254 static ssize_t ahci_read_em_buffer(struct device *dev, 255 struct device_attribute *attr, char *buf) 256 { 257 struct Scsi_Host *shost = class_to_shost(dev); 258 struct ata_port *ap = ata_shost_to_port(shost); 259 struct ahci_host_priv *hpriv = ap->host->private_data; 260 void __iomem *mmio = hpriv->mmio; 261 void __iomem *em_mmio = mmio + hpriv->em_loc; 262 u32 em_ctl, msg; 263 unsigned long flags; 264 size_t count; 265 int i; 266 267 spin_lock_irqsave(ap->lock, flags); 268 269 em_ctl = readl(mmio + HOST_EM_CTL); 270 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT || 271 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) { 272 spin_unlock_irqrestore(ap->lock, flags); 273 return -EINVAL; 274 } 275 276 if (!(em_ctl & EM_CTL_MR)) { 277 spin_unlock_irqrestore(ap->lock, flags); 278 return -EAGAIN; 279 } 280 281 if (!(em_ctl & EM_CTL_SMB)) 282 em_mmio += hpriv->em_buf_sz; 283 284 count = hpriv->em_buf_sz; 285 286 /* the count should not be larger than PAGE_SIZE */ 287 if (count > PAGE_SIZE) { 288 if (printk_ratelimit()) 289 ata_port_printk(ap, KERN_WARNING, 290 "EM read buffer size too large: " 291 "buffer size %u, page size %lu\n", 292 hpriv->em_buf_sz, PAGE_SIZE); 293 count = PAGE_SIZE; 294 } 295 296 for (i = 0; i < count; i += 4) { 297 msg = readl(em_mmio + i); 298 buf[i] = msg & 0xff; 299 buf[i + 1] = (msg >> 8) & 0xff; 300 buf[i + 2] = (msg >> 16) & 0xff; 301 buf[i + 3] = (msg >> 24) & 0xff; 302 } 303 304 spin_unlock_irqrestore(ap->lock, flags); 305 306 return i; 307 } 308 309 static ssize_t ahci_store_em_buffer(struct device *dev, 310 struct device_attribute *attr, 311 const char *buf, size_t size) 312 { 313 struct Scsi_Host *shost = class_to_shost(dev); 314 struct ata_port *ap = ata_shost_to_port(shost); 315 struct ahci_host_priv *hpriv = ap->host->private_data; 316 void __iomem *mmio = hpriv->mmio; 317 void __iomem *em_mmio = mmio + hpriv->em_loc; 318 const unsigned char *msg_buf = buf; 319 u32 em_ctl, msg; 320 unsigned long flags; 321 int i; 322 323 /* check size validity */ 324 if (!(ap->flags & ATA_FLAG_EM) || 325 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) || 326 size % 4 || size > hpriv->em_buf_sz) 327 return -EINVAL; 328 329 spin_lock_irqsave(ap->lock, flags); 330 331 em_ctl = readl(mmio + HOST_EM_CTL); 332 if (em_ctl & EM_CTL_TM) { 333 spin_unlock_irqrestore(ap->lock, flags); 334 return -EBUSY; 335 } 336 337 for (i = 0; i < size; i += 4) { 338 msg = msg_buf[i] | msg_buf[i + 1] << 8 | 339 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24; 340 writel(msg, em_mmio + i); 341 } 342 343 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 344 345 spin_unlock_irqrestore(ap->lock, flags); 346 347 return size; 348 } 349 350 static ssize_t ahci_show_em_supported(struct device *dev, 351 struct device_attribute *attr, char *buf) 352 { 353 struct Scsi_Host *shost = class_to_shost(dev); 354 struct ata_port *ap = ata_shost_to_port(shost); 355 struct ahci_host_priv *hpriv = ap->host->private_data; 356 void __iomem *mmio = hpriv->mmio; 357 u32 em_ctl; 358 359 em_ctl = readl(mmio + HOST_EM_CTL); 360 361 return sprintf(buf, "%s%s%s%s\n", 362 em_ctl & EM_CTL_LED ? "led " : "", 363 em_ctl & EM_CTL_SAFTE ? "saf-te " : "", 364 em_ctl & EM_CTL_SES ? "ses-2 " : "", 365 em_ctl & EM_CTL_SGPIO ? "sgpio " : ""); 366 } 367 368 /** 369 * ahci_save_initial_config - Save and fixup initial config values 370 * @dev: target AHCI device 371 * @hpriv: host private area to store config values 372 * @force_port_map: force port map to a specified value 373 * @mask_port_map: mask out particular bits from port map 374 * 375 * Some registers containing configuration info might be setup by 376 * BIOS and might be cleared on reset. This function saves the 377 * initial values of those registers into @hpriv such that they 378 * can be restored after controller reset. 379 * 380 * If inconsistent, config values are fixed up by this function. 381 * 382 * LOCKING: 383 * None. 384 */ 385 void ahci_save_initial_config(struct device *dev, 386 struct ahci_host_priv *hpriv, 387 unsigned int force_port_map, 388 unsigned int mask_port_map) 389 { 390 void __iomem *mmio = hpriv->mmio; 391 u32 cap, cap2, vers, port_map; 392 int i; 393 394 /* make sure AHCI mode is enabled before accessing CAP */ 395 ahci_enable_ahci(mmio); 396 397 /* Values prefixed with saved_ are written back to host after 398 * reset. Values without are used for driver operation. 399 */ 400 hpriv->saved_cap = cap = readl(mmio + HOST_CAP); 401 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL); 402 403 /* CAP2 register is only defined for AHCI 1.2 and later */ 404 vers = readl(mmio + HOST_VERSION); 405 if ((vers >> 16) > 1 || 406 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200)) 407 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2); 408 else 409 hpriv->saved_cap2 = cap2 = 0; 410 411 /* some chips have errata preventing 64bit use */ 412 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) { 413 dev_printk(KERN_INFO, dev, 414 "controller can't do 64bit DMA, forcing 32bit\n"); 415 cap &= ~HOST_CAP_64; 416 } 417 418 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) { 419 dev_printk(KERN_INFO, dev, 420 "controller can't do NCQ, turning off CAP_NCQ\n"); 421 cap &= ~HOST_CAP_NCQ; 422 } 423 424 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) { 425 dev_printk(KERN_INFO, dev, 426 "controller can do NCQ, turning on CAP_NCQ\n"); 427 cap |= HOST_CAP_NCQ; 428 } 429 430 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) { 431 dev_printk(KERN_INFO, dev, 432 "controller can't do PMP, turning off CAP_PMP\n"); 433 cap &= ~HOST_CAP_PMP; 434 } 435 436 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) { 437 dev_printk(KERN_INFO, dev, 438 "controller can't do SNTF, turning off CAP_SNTF\n"); 439 cap &= ~HOST_CAP_SNTF; 440 } 441 442 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) { 443 dev_printk(KERN_INFO, dev, 444 "controller can do FBS, turning on CAP_FBS\n"); 445 cap |= HOST_CAP_FBS; 446 } 447 448 if (force_port_map && port_map != force_port_map) { 449 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n", 450 port_map, force_port_map); 451 port_map = force_port_map; 452 } 453 454 if (mask_port_map) { 455 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n", 456 port_map, 457 port_map & mask_port_map); 458 port_map &= mask_port_map; 459 } 460 461 /* cross check port_map and cap.n_ports */ 462 if (port_map) { 463 int map_ports = 0; 464 465 for (i = 0; i < AHCI_MAX_PORTS; i++) 466 if (port_map & (1 << i)) 467 map_ports++; 468 469 /* If PI has more ports than n_ports, whine, clear 470 * port_map and let it be generated from n_ports. 471 */ 472 if (map_ports > ahci_nr_ports(cap)) { 473 dev_printk(KERN_WARNING, dev, 474 "implemented port map (0x%x) contains more " 475 "ports than nr_ports (%u), using nr_ports\n", 476 port_map, ahci_nr_ports(cap)); 477 port_map = 0; 478 } 479 } 480 481 /* fabricate port_map from cap.nr_ports */ 482 if (!port_map) { 483 port_map = (1 << ahci_nr_ports(cap)) - 1; 484 dev_printk(KERN_WARNING, dev, 485 "forcing PORTS_IMPL to 0x%x\n", port_map); 486 487 /* write the fixed up value to the PI register */ 488 hpriv->saved_port_map = port_map; 489 } 490 491 /* record values to use during operation */ 492 hpriv->cap = cap; 493 hpriv->cap2 = cap2; 494 hpriv->port_map = port_map; 495 } 496 EXPORT_SYMBOL_GPL(ahci_save_initial_config); 497 498 /** 499 * ahci_restore_initial_config - Restore initial config 500 * @host: target ATA host 501 * 502 * Restore initial config stored by ahci_save_initial_config(). 503 * 504 * LOCKING: 505 * None. 506 */ 507 static void ahci_restore_initial_config(struct ata_host *host) 508 { 509 struct ahci_host_priv *hpriv = host->private_data; 510 void __iomem *mmio = hpriv->mmio; 511 512 writel(hpriv->saved_cap, mmio + HOST_CAP); 513 if (hpriv->saved_cap2) 514 writel(hpriv->saved_cap2, mmio + HOST_CAP2); 515 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 516 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 517 } 518 519 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg) 520 { 521 static const int offset[] = { 522 [SCR_STATUS] = PORT_SCR_STAT, 523 [SCR_CONTROL] = PORT_SCR_CTL, 524 [SCR_ERROR] = PORT_SCR_ERR, 525 [SCR_ACTIVE] = PORT_SCR_ACT, 526 [SCR_NOTIFICATION] = PORT_SCR_NTF, 527 }; 528 struct ahci_host_priv *hpriv = ap->host->private_data; 529 530 if (sc_reg < ARRAY_SIZE(offset) && 531 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF))) 532 return offset[sc_reg]; 533 return 0; 534 } 535 536 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) 537 { 538 void __iomem *port_mmio = ahci_port_base(link->ap); 539 int offset = ahci_scr_offset(link->ap, sc_reg); 540 541 if (offset) { 542 *val = readl(port_mmio + offset); 543 return 0; 544 } 545 return -EINVAL; 546 } 547 548 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) 549 { 550 void __iomem *port_mmio = ahci_port_base(link->ap); 551 int offset = ahci_scr_offset(link->ap, sc_reg); 552 553 if (offset) { 554 writel(val, port_mmio + offset); 555 return 0; 556 } 557 return -EINVAL; 558 } 559 560 void ahci_start_engine(struct ata_port *ap) 561 { 562 void __iomem *port_mmio = ahci_port_base(ap); 563 u32 tmp; 564 565 /* start DMA */ 566 tmp = readl(port_mmio + PORT_CMD); 567 tmp |= PORT_CMD_START; 568 writel(tmp, port_mmio + PORT_CMD); 569 readl(port_mmio + PORT_CMD); /* flush */ 570 } 571 EXPORT_SYMBOL_GPL(ahci_start_engine); 572 573 int ahci_stop_engine(struct ata_port *ap) 574 { 575 void __iomem *port_mmio = ahci_port_base(ap); 576 u32 tmp; 577 578 tmp = readl(port_mmio + PORT_CMD); 579 580 /* check if the HBA is idle */ 581 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) 582 return 0; 583 584 /* setting HBA to idle */ 585 tmp &= ~PORT_CMD_START; 586 writel(tmp, port_mmio + PORT_CMD); 587 588 /* wait for engine to stop. This could be as long as 500 msec */ 589 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 590 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); 591 if (tmp & PORT_CMD_LIST_ON) 592 return -EIO; 593 594 return 0; 595 } 596 EXPORT_SYMBOL_GPL(ahci_stop_engine); 597 598 static void ahci_start_fis_rx(struct ata_port *ap) 599 { 600 void __iomem *port_mmio = ahci_port_base(ap); 601 struct ahci_host_priv *hpriv = ap->host->private_data; 602 struct ahci_port_priv *pp = ap->private_data; 603 u32 tmp; 604 605 /* set FIS registers */ 606 if (hpriv->cap & HOST_CAP_64) 607 writel((pp->cmd_slot_dma >> 16) >> 16, 608 port_mmio + PORT_LST_ADDR_HI); 609 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 610 611 if (hpriv->cap & HOST_CAP_64) 612 writel((pp->rx_fis_dma >> 16) >> 16, 613 port_mmio + PORT_FIS_ADDR_HI); 614 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 615 616 /* enable FIS reception */ 617 tmp = readl(port_mmio + PORT_CMD); 618 tmp |= PORT_CMD_FIS_RX; 619 writel(tmp, port_mmio + PORT_CMD); 620 621 /* flush */ 622 readl(port_mmio + PORT_CMD); 623 } 624 625 static int ahci_stop_fis_rx(struct ata_port *ap) 626 { 627 void __iomem *port_mmio = ahci_port_base(ap); 628 u32 tmp; 629 630 /* disable FIS reception */ 631 tmp = readl(port_mmio + PORT_CMD); 632 tmp &= ~PORT_CMD_FIS_RX; 633 writel(tmp, port_mmio + PORT_CMD); 634 635 /* wait for completion, spec says 500ms, give it 1000 */ 636 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON, 637 PORT_CMD_FIS_ON, 10, 1000); 638 if (tmp & PORT_CMD_FIS_ON) 639 return -EBUSY; 640 641 return 0; 642 } 643 644 static void ahci_power_up(struct ata_port *ap) 645 { 646 struct ahci_host_priv *hpriv = ap->host->private_data; 647 void __iomem *port_mmio = ahci_port_base(ap); 648 u32 cmd; 649 650 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 651 652 /* spin up device */ 653 if (hpriv->cap & HOST_CAP_SSS) { 654 cmd |= PORT_CMD_SPIN_UP; 655 writel(cmd, port_mmio + PORT_CMD); 656 } 657 658 /* wake up link */ 659 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); 660 } 661 662 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, 663 unsigned int hints) 664 { 665 struct ata_port *ap = link->ap; 666 struct ahci_host_priv *hpriv = ap->host->private_data; 667 struct ahci_port_priv *pp = ap->private_data; 668 void __iomem *port_mmio = ahci_port_base(ap); 669 670 if (policy != ATA_LPM_MAX_POWER) { 671 /* 672 * Disable interrupts on Phy Ready. This keeps us from 673 * getting woken up due to spurious phy ready 674 * interrupts. 675 */ 676 pp->intr_mask &= ~PORT_IRQ_PHYRDY; 677 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 678 679 sata_link_scr_lpm(link, policy, false); 680 } 681 682 if (hpriv->cap & HOST_CAP_ALPM) { 683 u32 cmd = readl(port_mmio + PORT_CMD); 684 685 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) { 686 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE); 687 cmd |= PORT_CMD_ICC_ACTIVE; 688 689 writel(cmd, port_mmio + PORT_CMD); 690 readl(port_mmio + PORT_CMD); 691 692 /* wait 10ms to be sure we've come out of LPM state */ 693 ata_msleep(ap, 10); 694 } else { 695 cmd |= PORT_CMD_ALPE; 696 if (policy == ATA_LPM_MIN_POWER) 697 cmd |= PORT_CMD_ASP; 698 699 /* write out new cmd value */ 700 writel(cmd, port_mmio + PORT_CMD); 701 } 702 } 703 704 if (policy == ATA_LPM_MAX_POWER) { 705 sata_link_scr_lpm(link, policy, false); 706 707 /* turn PHYRDY IRQ back on */ 708 pp->intr_mask |= PORT_IRQ_PHYRDY; 709 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 710 } 711 712 return 0; 713 } 714 715 #ifdef CONFIG_PM 716 static void ahci_power_down(struct ata_port *ap) 717 { 718 struct ahci_host_priv *hpriv = ap->host->private_data; 719 void __iomem *port_mmio = ahci_port_base(ap); 720 u32 cmd, scontrol; 721 722 if (!(hpriv->cap & HOST_CAP_SSS)) 723 return; 724 725 /* put device into listen mode, first set PxSCTL.DET to 0 */ 726 scontrol = readl(port_mmio + PORT_SCR_CTL); 727 scontrol &= ~0xf; 728 writel(scontrol, port_mmio + PORT_SCR_CTL); 729 730 /* then set PxCMD.SUD to 0 */ 731 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 732 cmd &= ~PORT_CMD_SPIN_UP; 733 writel(cmd, port_mmio + PORT_CMD); 734 } 735 #endif 736 737 static void ahci_start_port(struct ata_port *ap) 738 { 739 struct ahci_port_priv *pp = ap->private_data; 740 struct ata_link *link; 741 struct ahci_em_priv *emp; 742 ssize_t rc; 743 int i; 744 745 /* enable FIS reception */ 746 ahci_start_fis_rx(ap); 747 748 /* enable DMA */ 749 ahci_start_engine(ap); 750 751 /* turn on LEDs */ 752 if (ap->flags & ATA_FLAG_EM) { 753 ata_for_each_link(link, ap, EDGE) { 754 emp = &pp->em_priv[link->pmp]; 755 756 /* EM Transmit bit maybe busy during init */ 757 for (i = 0; i < EM_MAX_RETRY; i++) { 758 rc = ahci_transmit_led_message(ap, 759 emp->led_state, 760 4); 761 if (rc == -EBUSY) 762 ata_msleep(ap, 1); 763 else 764 break; 765 } 766 } 767 } 768 769 if (ap->flags & ATA_FLAG_SW_ACTIVITY) 770 ata_for_each_link(link, ap, EDGE) 771 ahci_init_sw_activity(link); 772 773 } 774 775 static int ahci_deinit_port(struct ata_port *ap, const char **emsg) 776 { 777 int rc; 778 779 /* disable DMA */ 780 rc = ahci_stop_engine(ap); 781 if (rc) { 782 *emsg = "failed to stop engine"; 783 return rc; 784 } 785 786 /* disable FIS reception */ 787 rc = ahci_stop_fis_rx(ap); 788 if (rc) { 789 *emsg = "failed stop FIS RX"; 790 return rc; 791 } 792 793 return 0; 794 } 795 796 int ahci_reset_controller(struct ata_host *host) 797 { 798 struct ahci_host_priv *hpriv = host->private_data; 799 void __iomem *mmio = hpriv->mmio; 800 u32 tmp; 801 802 /* we must be in AHCI mode, before using anything 803 * AHCI-specific, such as HOST_RESET. 804 */ 805 ahci_enable_ahci(mmio); 806 807 /* global controller reset */ 808 if (!ahci_skip_host_reset) { 809 tmp = readl(mmio + HOST_CTL); 810 if ((tmp & HOST_RESET) == 0) { 811 writel(tmp | HOST_RESET, mmio + HOST_CTL); 812 readl(mmio + HOST_CTL); /* flush */ 813 } 814 815 /* 816 * to perform host reset, OS should set HOST_RESET 817 * and poll until this bit is read to be "0". 818 * reset must complete within 1 second, or 819 * the hardware should be considered fried. 820 */ 821 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET, 822 HOST_RESET, 10, 1000); 823 824 if (tmp & HOST_RESET) { 825 dev_printk(KERN_ERR, host->dev, 826 "controller reset failed (0x%x)\n", tmp); 827 return -EIO; 828 } 829 830 /* turn on AHCI mode */ 831 ahci_enable_ahci(mmio); 832 833 /* Some registers might be cleared on reset. Restore 834 * initial values. 835 */ 836 ahci_restore_initial_config(host); 837 } else 838 dev_printk(KERN_INFO, host->dev, 839 "skipping global host reset\n"); 840 841 return 0; 842 } 843 EXPORT_SYMBOL_GPL(ahci_reset_controller); 844 845 static void ahci_sw_activity(struct ata_link *link) 846 { 847 struct ata_port *ap = link->ap; 848 struct ahci_port_priv *pp = ap->private_data; 849 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 850 851 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY)) 852 return; 853 854 emp->activity++; 855 if (!timer_pending(&emp->timer)) 856 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10)); 857 } 858 859 static void ahci_sw_activity_blink(unsigned long arg) 860 { 861 struct ata_link *link = (struct ata_link *)arg; 862 struct ata_port *ap = link->ap; 863 struct ahci_port_priv *pp = ap->private_data; 864 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 865 unsigned long led_message = emp->led_state; 866 u32 activity_led_state; 867 unsigned long flags; 868 869 led_message &= EM_MSG_LED_VALUE; 870 led_message |= ap->port_no | (link->pmp << 8); 871 872 /* check to see if we've had activity. If so, 873 * toggle state of LED and reset timer. If not, 874 * turn LED to desired idle state. 875 */ 876 spin_lock_irqsave(ap->lock, flags); 877 if (emp->saved_activity != emp->activity) { 878 emp->saved_activity = emp->activity; 879 /* get the current LED state */ 880 activity_led_state = led_message & EM_MSG_LED_VALUE_ON; 881 882 if (activity_led_state) 883 activity_led_state = 0; 884 else 885 activity_led_state = 1; 886 887 /* clear old state */ 888 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 889 890 /* toggle state */ 891 led_message |= (activity_led_state << 16); 892 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100)); 893 } else { 894 /* switch to idle */ 895 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY; 896 if (emp->blink_policy == BLINK_OFF) 897 led_message |= (1 << 16); 898 } 899 spin_unlock_irqrestore(ap->lock, flags); 900 ahci_transmit_led_message(ap, led_message, 4); 901 } 902 903 static void ahci_init_sw_activity(struct ata_link *link) 904 { 905 struct ata_port *ap = link->ap; 906 struct ahci_port_priv *pp = ap->private_data; 907 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 908 909 /* init activity stats, setup timer */ 910 emp->saved_activity = emp->activity = 0; 911 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link); 912 913 /* check our blink policy and set flag for link if it's enabled */ 914 if (emp->blink_policy) 915 link->flags |= ATA_LFLAG_SW_ACTIVITY; 916 } 917 918 int ahci_reset_em(struct ata_host *host) 919 { 920 struct ahci_host_priv *hpriv = host->private_data; 921 void __iomem *mmio = hpriv->mmio; 922 u32 em_ctl; 923 924 em_ctl = readl(mmio + HOST_EM_CTL); 925 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST)) 926 return -EINVAL; 927 928 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL); 929 return 0; 930 } 931 EXPORT_SYMBOL_GPL(ahci_reset_em); 932 933 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state, 934 ssize_t size) 935 { 936 struct ahci_host_priv *hpriv = ap->host->private_data; 937 struct ahci_port_priv *pp = ap->private_data; 938 void __iomem *mmio = hpriv->mmio; 939 u32 em_ctl; 940 u32 message[] = {0, 0}; 941 unsigned long flags; 942 int pmp; 943 struct ahci_em_priv *emp; 944 945 /* get the slot number from the message */ 946 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 947 if (pmp < EM_MAX_SLOTS) 948 emp = &pp->em_priv[pmp]; 949 else 950 return -EINVAL; 951 952 spin_lock_irqsave(ap->lock, flags); 953 954 /* 955 * if we are still busy transmitting a previous message, 956 * do not allow 957 */ 958 em_ctl = readl(mmio + HOST_EM_CTL); 959 if (em_ctl & EM_CTL_TM) { 960 spin_unlock_irqrestore(ap->lock, flags); 961 return -EBUSY; 962 } 963 964 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) { 965 /* 966 * create message header - this is all zero except for 967 * the message size, which is 4 bytes. 968 */ 969 message[0] |= (4 << 8); 970 971 /* ignore 0:4 of byte zero, fill in port info yourself */ 972 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no); 973 974 /* write message to EM_LOC */ 975 writel(message[0], mmio + hpriv->em_loc); 976 writel(message[1], mmio + hpriv->em_loc+4); 977 978 /* 979 * tell hardware to transmit the message 980 */ 981 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL); 982 } 983 984 /* save off new led state for port/slot */ 985 emp->led_state = state; 986 987 spin_unlock_irqrestore(ap->lock, flags); 988 return size; 989 } 990 991 static ssize_t ahci_led_show(struct ata_port *ap, char *buf) 992 { 993 struct ahci_port_priv *pp = ap->private_data; 994 struct ata_link *link; 995 struct ahci_em_priv *emp; 996 int rc = 0; 997 998 ata_for_each_link(link, ap, EDGE) { 999 emp = &pp->em_priv[link->pmp]; 1000 rc += sprintf(buf, "%lx\n", emp->led_state); 1001 } 1002 return rc; 1003 } 1004 1005 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf, 1006 size_t size) 1007 { 1008 int state; 1009 int pmp; 1010 struct ahci_port_priv *pp = ap->private_data; 1011 struct ahci_em_priv *emp; 1012 1013 state = simple_strtoul(buf, NULL, 0); 1014 1015 /* get the slot number from the message */ 1016 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; 1017 if (pmp < EM_MAX_SLOTS) 1018 emp = &pp->em_priv[pmp]; 1019 else 1020 return -EINVAL; 1021 1022 /* mask off the activity bits if we are in sw_activity 1023 * mode, user should turn off sw_activity before setting 1024 * activity led through em_message 1025 */ 1026 if (emp->blink_policy) 1027 state &= ~EM_MSG_LED_VALUE_ACTIVITY; 1028 1029 return ahci_transmit_led_message(ap, state, size); 1030 } 1031 1032 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val) 1033 { 1034 struct ata_link *link = dev->link; 1035 struct ata_port *ap = link->ap; 1036 struct ahci_port_priv *pp = ap->private_data; 1037 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1038 u32 port_led_state = emp->led_state; 1039 1040 /* save the desired Activity LED behavior */ 1041 if (val == OFF) { 1042 /* clear LFLAG */ 1043 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY); 1044 1045 /* set the LED to OFF */ 1046 port_led_state &= EM_MSG_LED_VALUE_OFF; 1047 port_led_state |= (ap->port_no | (link->pmp << 8)); 1048 ahci_transmit_led_message(ap, port_led_state, 4); 1049 } else { 1050 link->flags |= ATA_LFLAG_SW_ACTIVITY; 1051 if (val == BLINK_OFF) { 1052 /* set LED to ON for idle */ 1053 port_led_state &= EM_MSG_LED_VALUE_OFF; 1054 port_led_state |= (ap->port_no | (link->pmp << 8)); 1055 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */ 1056 ahci_transmit_led_message(ap, port_led_state, 4); 1057 } 1058 } 1059 emp->blink_policy = val; 1060 return 0; 1061 } 1062 1063 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) 1064 { 1065 struct ata_link *link = dev->link; 1066 struct ata_port *ap = link->ap; 1067 struct ahci_port_priv *pp = ap->private_data; 1068 struct ahci_em_priv *emp = &pp->em_priv[link->pmp]; 1069 1070 /* display the saved value of activity behavior for this 1071 * disk. 1072 */ 1073 return sprintf(buf, "%d\n", emp->blink_policy); 1074 } 1075 1076 static void ahci_port_init(struct device *dev, struct ata_port *ap, 1077 int port_no, void __iomem *mmio, 1078 void __iomem *port_mmio) 1079 { 1080 const char *emsg = NULL; 1081 int rc; 1082 u32 tmp; 1083 1084 /* make sure port is not active */ 1085 rc = ahci_deinit_port(ap, &emsg); 1086 if (rc) 1087 dev_warn(dev, "%s (%d)\n", emsg, rc); 1088 1089 /* clear SError */ 1090 tmp = readl(port_mmio + PORT_SCR_ERR); 1091 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); 1092 writel(tmp, port_mmio + PORT_SCR_ERR); 1093 1094 /* clear port IRQ */ 1095 tmp = readl(port_mmio + PORT_IRQ_STAT); 1096 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); 1097 if (tmp) 1098 writel(tmp, port_mmio + PORT_IRQ_STAT); 1099 1100 writel(1 << port_no, mmio + HOST_IRQ_STAT); 1101 } 1102 1103 void ahci_init_controller(struct ata_host *host) 1104 { 1105 struct ahci_host_priv *hpriv = host->private_data; 1106 void __iomem *mmio = hpriv->mmio; 1107 int i; 1108 void __iomem *port_mmio; 1109 u32 tmp; 1110 1111 for (i = 0; i < host->n_ports; i++) { 1112 struct ata_port *ap = host->ports[i]; 1113 1114 port_mmio = ahci_port_base(ap); 1115 if (ata_port_is_dummy(ap)) 1116 continue; 1117 1118 ahci_port_init(host->dev, ap, i, mmio, port_mmio); 1119 } 1120 1121 tmp = readl(mmio + HOST_CTL); 1122 VPRINTK("HOST_CTL 0x%x\n", tmp); 1123 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 1124 tmp = readl(mmio + HOST_CTL); 1125 VPRINTK("HOST_CTL 0x%x\n", tmp); 1126 } 1127 EXPORT_SYMBOL_GPL(ahci_init_controller); 1128 1129 static void ahci_dev_config(struct ata_device *dev) 1130 { 1131 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data; 1132 1133 if (hpriv->flags & AHCI_HFLAG_SECT255) { 1134 dev->max_sectors = 255; 1135 ata_dev_printk(dev, KERN_INFO, 1136 "SB600 AHCI: limiting to 255 sectors per cmd\n"); 1137 } 1138 } 1139 1140 static unsigned int ahci_dev_classify(struct ata_port *ap) 1141 { 1142 void __iomem *port_mmio = ahci_port_base(ap); 1143 struct ata_taskfile tf; 1144 u32 tmp; 1145 1146 tmp = readl(port_mmio + PORT_SIG); 1147 tf.lbah = (tmp >> 24) & 0xff; 1148 tf.lbam = (tmp >> 16) & 0xff; 1149 tf.lbal = (tmp >> 8) & 0xff; 1150 tf.nsect = (tmp) & 0xff; 1151 1152 return ata_dev_classify(&tf); 1153 } 1154 1155 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, 1156 u32 opts) 1157 { 1158 dma_addr_t cmd_tbl_dma; 1159 1160 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; 1161 1162 pp->cmd_slot[tag].opts = cpu_to_le32(opts); 1163 pp->cmd_slot[tag].status = 0; 1164 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); 1165 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); 1166 } 1167 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot); 1168 1169 int ahci_kick_engine(struct ata_port *ap) 1170 { 1171 void __iomem *port_mmio = ahci_port_base(ap); 1172 struct ahci_host_priv *hpriv = ap->host->private_data; 1173 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1174 u32 tmp; 1175 int busy, rc; 1176 1177 /* stop engine */ 1178 rc = ahci_stop_engine(ap); 1179 if (rc) 1180 goto out_restart; 1181 1182 /* need to do CLO? 1183 * always do CLO if PMP is attached (AHCI-1.3 9.2) 1184 */ 1185 busy = status & (ATA_BUSY | ATA_DRQ); 1186 if (!busy && !sata_pmp_attached(ap)) { 1187 rc = 0; 1188 goto out_restart; 1189 } 1190 1191 if (!(hpriv->cap & HOST_CAP_CLO)) { 1192 rc = -EOPNOTSUPP; 1193 goto out_restart; 1194 } 1195 1196 /* perform CLO */ 1197 tmp = readl(port_mmio + PORT_CMD); 1198 tmp |= PORT_CMD_CLO; 1199 writel(tmp, port_mmio + PORT_CMD); 1200 1201 rc = 0; 1202 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, 1203 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); 1204 if (tmp & PORT_CMD_CLO) 1205 rc = -EIO; 1206 1207 /* restart engine */ 1208 out_restart: 1209 ahci_start_engine(ap); 1210 return rc; 1211 } 1212 EXPORT_SYMBOL_GPL(ahci_kick_engine); 1213 1214 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, 1215 struct ata_taskfile *tf, int is_cmd, u16 flags, 1216 unsigned long timeout_msec) 1217 { 1218 const u32 cmd_fis_len = 5; /* five dwords */ 1219 struct ahci_port_priv *pp = ap->private_data; 1220 void __iomem *port_mmio = ahci_port_base(ap); 1221 u8 *fis = pp->cmd_tbl; 1222 u32 tmp; 1223 1224 /* prep the command */ 1225 ata_tf_to_fis(tf, pmp, is_cmd, fis); 1226 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12)); 1227 1228 /* issue & wait */ 1229 writel(1, port_mmio + PORT_CMD_ISSUE); 1230 1231 if (timeout_msec) { 1232 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE, 1233 0x1, 0x1, 1, timeout_msec); 1234 if (tmp & 0x1) { 1235 ahci_kick_engine(ap); 1236 return -EBUSY; 1237 } 1238 } else 1239 readl(port_mmio + PORT_CMD_ISSUE); /* flush */ 1240 1241 return 0; 1242 } 1243 1244 int ahci_do_softreset(struct ata_link *link, unsigned int *class, 1245 int pmp, unsigned long deadline, 1246 int (*check_ready)(struct ata_link *link)) 1247 { 1248 struct ata_port *ap = link->ap; 1249 struct ahci_host_priv *hpriv = ap->host->private_data; 1250 const char *reason = NULL; 1251 unsigned long now, msecs; 1252 struct ata_taskfile tf; 1253 int rc; 1254 1255 DPRINTK("ENTER\n"); 1256 1257 /* prepare for SRST (AHCI-1.1 10.4.1) */ 1258 rc = ahci_kick_engine(ap); 1259 if (rc && rc != -EOPNOTSUPP) 1260 ata_link_printk(link, KERN_WARNING, 1261 "failed to reset engine (errno=%d)\n", rc); 1262 1263 ata_tf_init(link->device, &tf); 1264 1265 /* issue the first D2H Register FIS */ 1266 msecs = 0; 1267 now = jiffies; 1268 if (time_after(deadline, now)) 1269 msecs = jiffies_to_msecs(deadline - now); 1270 1271 tf.ctl |= ATA_SRST; 1272 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0, 1273 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) { 1274 rc = -EIO; 1275 reason = "1st FIS failed"; 1276 goto fail; 1277 } 1278 1279 /* spec says at least 5us, but be generous and sleep for 1ms */ 1280 ata_msleep(ap, 1); 1281 1282 /* issue the second D2H Register FIS */ 1283 tf.ctl &= ~ATA_SRST; 1284 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0); 1285 1286 /* wait for link to become ready */ 1287 rc = ata_wait_after_reset(link, deadline, check_ready); 1288 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) { 1289 /* 1290 * Workaround for cases where link online status can't 1291 * be trusted. Treat device readiness timeout as link 1292 * offline. 1293 */ 1294 ata_link_printk(link, KERN_INFO, 1295 "device not ready, treating as offline\n"); 1296 *class = ATA_DEV_NONE; 1297 } else if (rc) { 1298 /* link occupied, -ENODEV too is an error */ 1299 reason = "device not ready"; 1300 goto fail; 1301 } else 1302 *class = ahci_dev_classify(ap); 1303 1304 DPRINTK("EXIT, class=%u\n", *class); 1305 return 0; 1306 1307 fail: 1308 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); 1309 return rc; 1310 } 1311 1312 int ahci_check_ready(struct ata_link *link) 1313 { 1314 void __iomem *port_mmio = ahci_port_base(link->ap); 1315 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF; 1316 1317 return ata_check_ready(status); 1318 } 1319 EXPORT_SYMBOL_GPL(ahci_check_ready); 1320 1321 static int ahci_softreset(struct ata_link *link, unsigned int *class, 1322 unsigned long deadline) 1323 { 1324 int pmp = sata_srst_pmp(link); 1325 1326 DPRINTK("ENTER\n"); 1327 1328 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready); 1329 } 1330 EXPORT_SYMBOL_GPL(ahci_do_softreset); 1331 1332 static int ahci_hardreset(struct ata_link *link, unsigned int *class, 1333 unsigned long deadline) 1334 { 1335 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 1336 struct ata_port *ap = link->ap; 1337 struct ahci_port_priv *pp = ap->private_data; 1338 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 1339 struct ata_taskfile tf; 1340 bool online; 1341 int rc; 1342 1343 DPRINTK("ENTER\n"); 1344 1345 ahci_stop_engine(ap); 1346 1347 /* clear D2H reception area to properly wait for D2H FIS */ 1348 ata_tf_init(link->device, &tf); 1349 tf.command = 0x80; 1350 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 1351 1352 rc = sata_link_hardreset(link, timing, deadline, &online, 1353 ahci_check_ready); 1354 1355 ahci_start_engine(ap); 1356 1357 if (online) 1358 *class = ahci_dev_classify(ap); 1359 1360 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1361 return rc; 1362 } 1363 1364 static void ahci_postreset(struct ata_link *link, unsigned int *class) 1365 { 1366 struct ata_port *ap = link->ap; 1367 void __iomem *port_mmio = ahci_port_base(ap); 1368 u32 new_tmp, tmp; 1369 1370 ata_std_postreset(link, class); 1371 1372 /* Make sure port's ATAPI bit is set appropriately */ 1373 new_tmp = tmp = readl(port_mmio + PORT_CMD); 1374 if (*class == ATA_DEV_ATAPI) 1375 new_tmp |= PORT_CMD_ATAPI; 1376 else 1377 new_tmp &= ~PORT_CMD_ATAPI; 1378 if (new_tmp != tmp) { 1379 writel(new_tmp, port_mmio + PORT_CMD); 1380 readl(port_mmio + PORT_CMD); /* flush */ 1381 } 1382 } 1383 1384 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) 1385 { 1386 struct scatterlist *sg; 1387 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; 1388 unsigned int si; 1389 1390 VPRINTK("ENTER\n"); 1391 1392 /* 1393 * Next, the S/G list. 1394 */ 1395 for_each_sg(qc->sg, sg, qc->n_elem, si) { 1396 dma_addr_t addr = sg_dma_address(sg); 1397 u32 sg_len = sg_dma_len(sg); 1398 1399 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff); 1400 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); 1401 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1); 1402 } 1403 1404 return si; 1405 } 1406 1407 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc) 1408 { 1409 struct ata_port *ap = qc->ap; 1410 struct ahci_port_priv *pp = ap->private_data; 1411 1412 if (!sata_pmp_attached(ap) || pp->fbs_enabled) 1413 return ata_std_qc_defer(qc); 1414 else 1415 return sata_pmp_qc_defer_cmd_switch(qc); 1416 } 1417 1418 static void ahci_qc_prep(struct ata_queued_cmd *qc) 1419 { 1420 struct ata_port *ap = qc->ap; 1421 struct ahci_port_priv *pp = ap->private_data; 1422 int is_atapi = ata_is_atapi(qc->tf.protocol); 1423 void *cmd_tbl; 1424 u32 opts; 1425 const u32 cmd_fis_len = 5; /* five dwords */ 1426 unsigned int n_elem; 1427 1428 /* 1429 * Fill in command table information. First, the header, 1430 * a SATA Register - Host to Device command FIS. 1431 */ 1432 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; 1433 1434 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); 1435 if (is_atapi) { 1436 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); 1437 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); 1438 } 1439 1440 n_elem = 0; 1441 if (qc->flags & ATA_QCFLAG_DMAMAP) 1442 n_elem = ahci_fill_sg(qc, cmd_tbl); 1443 1444 /* 1445 * Fill in command slot information. 1446 */ 1447 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12); 1448 if (qc->tf.flags & ATA_TFLAG_WRITE) 1449 opts |= AHCI_CMD_WRITE; 1450 if (is_atapi) 1451 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; 1452 1453 ahci_fill_cmd_slot(pp, qc->tag, opts); 1454 } 1455 1456 static void ahci_fbs_dec_intr(struct ata_port *ap) 1457 { 1458 struct ahci_port_priv *pp = ap->private_data; 1459 void __iomem *port_mmio = ahci_port_base(ap); 1460 u32 fbs = readl(port_mmio + PORT_FBS); 1461 int retries = 3; 1462 1463 DPRINTK("ENTER\n"); 1464 BUG_ON(!pp->fbs_enabled); 1465 1466 /* time to wait for DEC is not specified by AHCI spec, 1467 * add a retry loop for safety. 1468 */ 1469 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS); 1470 fbs = readl(port_mmio + PORT_FBS); 1471 while ((fbs & PORT_FBS_DEC) && retries--) { 1472 udelay(1); 1473 fbs = readl(port_mmio + PORT_FBS); 1474 } 1475 1476 if (fbs & PORT_FBS_DEC) 1477 dev_printk(KERN_ERR, ap->host->dev, 1478 "failed to clear device error\n"); 1479 } 1480 1481 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) 1482 { 1483 struct ahci_host_priv *hpriv = ap->host->private_data; 1484 struct ahci_port_priv *pp = ap->private_data; 1485 struct ata_eh_info *host_ehi = &ap->link.eh_info; 1486 struct ata_link *link = NULL; 1487 struct ata_queued_cmd *active_qc; 1488 struct ata_eh_info *active_ehi; 1489 bool fbs_need_dec = false; 1490 u32 serror; 1491 1492 /* determine active link with error */ 1493 if (pp->fbs_enabled) { 1494 void __iomem *port_mmio = ahci_port_base(ap); 1495 u32 fbs = readl(port_mmio + PORT_FBS); 1496 int pmp = fbs >> PORT_FBS_DWE_OFFSET; 1497 1498 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) && 1499 ata_link_online(&ap->pmp_link[pmp])) { 1500 link = &ap->pmp_link[pmp]; 1501 fbs_need_dec = true; 1502 } 1503 1504 } else 1505 ata_for_each_link(link, ap, EDGE) 1506 if (ata_link_active(link)) 1507 break; 1508 1509 if (!link) 1510 link = &ap->link; 1511 1512 active_qc = ata_qc_from_tag(ap, link->active_tag); 1513 active_ehi = &link->eh_info; 1514 1515 /* record irq stat */ 1516 ata_ehi_clear_desc(host_ehi); 1517 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat); 1518 1519 /* AHCI needs SError cleared; otherwise, it might lock up */ 1520 ahci_scr_read(&ap->link, SCR_ERROR, &serror); 1521 ahci_scr_write(&ap->link, SCR_ERROR, serror); 1522 host_ehi->serror |= serror; 1523 1524 /* some controllers set IRQ_IF_ERR on device errors, ignore it */ 1525 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR) 1526 irq_stat &= ~PORT_IRQ_IF_ERR; 1527 1528 if (irq_stat & PORT_IRQ_TF_ERR) { 1529 /* If qc is active, charge it; otherwise, the active 1530 * link. There's no active qc on NCQ errors. It will 1531 * be determined by EH by reading log page 10h. 1532 */ 1533 if (active_qc) 1534 active_qc->err_mask |= AC_ERR_DEV; 1535 else 1536 active_ehi->err_mask |= AC_ERR_DEV; 1537 1538 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL) 1539 host_ehi->serror &= ~SERR_INTERNAL; 1540 } 1541 1542 if (irq_stat & PORT_IRQ_UNK_FIS) { 1543 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); 1544 1545 active_ehi->err_mask |= AC_ERR_HSM; 1546 active_ehi->action |= ATA_EH_RESET; 1547 ata_ehi_push_desc(active_ehi, 1548 "unknown FIS %08x %08x %08x %08x" , 1549 unk[0], unk[1], unk[2], unk[3]); 1550 } 1551 1552 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) { 1553 active_ehi->err_mask |= AC_ERR_HSM; 1554 active_ehi->action |= ATA_EH_RESET; 1555 ata_ehi_push_desc(active_ehi, "incorrect PMP"); 1556 } 1557 1558 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { 1559 host_ehi->err_mask |= AC_ERR_HOST_BUS; 1560 host_ehi->action |= ATA_EH_RESET; 1561 ata_ehi_push_desc(host_ehi, "host bus error"); 1562 } 1563 1564 if (irq_stat & PORT_IRQ_IF_ERR) { 1565 if (fbs_need_dec) 1566 active_ehi->err_mask |= AC_ERR_DEV; 1567 else { 1568 host_ehi->err_mask |= AC_ERR_ATA_BUS; 1569 host_ehi->action |= ATA_EH_RESET; 1570 } 1571 1572 ata_ehi_push_desc(host_ehi, "interface fatal error"); 1573 } 1574 1575 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { 1576 ata_ehi_hotplugged(host_ehi); 1577 ata_ehi_push_desc(host_ehi, "%s", 1578 irq_stat & PORT_IRQ_CONNECT ? 1579 "connection status changed" : "PHY RDY changed"); 1580 } 1581 1582 /* okay, let's hand over to EH */ 1583 1584 if (irq_stat & PORT_IRQ_FREEZE) 1585 ata_port_freeze(ap); 1586 else if (fbs_need_dec) { 1587 ata_link_abort(link); 1588 ahci_fbs_dec_intr(ap); 1589 } else 1590 ata_port_abort(ap); 1591 } 1592 1593 static void ahci_port_intr(struct ata_port *ap) 1594 { 1595 void __iomem *port_mmio = ahci_port_base(ap); 1596 struct ata_eh_info *ehi = &ap->link.eh_info; 1597 struct ahci_port_priv *pp = ap->private_data; 1598 struct ahci_host_priv *hpriv = ap->host->private_data; 1599 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING); 1600 u32 status, qc_active = 0; 1601 int rc; 1602 1603 status = readl(port_mmio + PORT_IRQ_STAT); 1604 writel(status, port_mmio + PORT_IRQ_STAT); 1605 1606 /* ignore BAD_PMP while resetting */ 1607 if (unlikely(resetting)) 1608 status &= ~PORT_IRQ_BAD_PMP; 1609 1610 /* if LPM is enabled, PHYRDY doesn't mean anything */ 1611 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) { 1612 status &= ~PORT_IRQ_PHYRDY; 1613 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG); 1614 } 1615 1616 if (unlikely(status & PORT_IRQ_ERROR)) { 1617 ahci_error_intr(ap, status); 1618 return; 1619 } 1620 1621 if (status & PORT_IRQ_SDB_FIS) { 1622 /* If SNotification is available, leave notification 1623 * handling to sata_async_notification(). If not, 1624 * emulate it by snooping SDB FIS RX area. 1625 * 1626 * Snooping FIS RX area is probably cheaper than 1627 * poking SNotification but some constrollers which 1628 * implement SNotification, ICH9 for example, don't 1629 * store AN SDB FIS into receive area. 1630 */ 1631 if (hpriv->cap & HOST_CAP_SNTF) 1632 sata_async_notification(ap); 1633 else { 1634 /* If the 'N' bit in word 0 of the FIS is set, 1635 * we just received asynchronous notification. 1636 * Tell libata about it. 1637 * 1638 * Lack of SNotification should not appear in 1639 * ahci 1.2, so the workaround is unnecessary 1640 * when FBS is enabled. 1641 */ 1642 if (pp->fbs_enabled) 1643 WARN_ON_ONCE(1); 1644 else { 1645 const __le32 *f = pp->rx_fis + RX_FIS_SDB; 1646 u32 f0 = le32_to_cpu(f[0]); 1647 if (f0 & (1 << 15)) 1648 sata_async_notification(ap); 1649 } 1650 } 1651 } 1652 1653 /* pp->active_link is not reliable once FBS is enabled, both 1654 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because 1655 * NCQ and non-NCQ commands may be in flight at the same time. 1656 */ 1657 if (pp->fbs_enabled) { 1658 if (ap->qc_active) { 1659 qc_active = readl(port_mmio + PORT_SCR_ACT); 1660 qc_active |= readl(port_mmio + PORT_CMD_ISSUE); 1661 } 1662 } else { 1663 /* pp->active_link is valid iff any command is in flight */ 1664 if (ap->qc_active && pp->active_link->sactive) 1665 qc_active = readl(port_mmio + PORT_SCR_ACT); 1666 else 1667 qc_active = readl(port_mmio + PORT_CMD_ISSUE); 1668 } 1669 1670 1671 rc = ata_qc_complete_multiple(ap, qc_active); 1672 1673 /* while resetting, invalid completions are expected */ 1674 if (unlikely(rc < 0 && !resetting)) { 1675 ehi->err_mask |= AC_ERR_HSM; 1676 ehi->action |= ATA_EH_RESET; 1677 ata_port_freeze(ap); 1678 } 1679 } 1680 1681 irqreturn_t ahci_interrupt(int irq, void *dev_instance) 1682 { 1683 struct ata_host *host = dev_instance; 1684 struct ahci_host_priv *hpriv; 1685 unsigned int i, handled = 0; 1686 void __iomem *mmio; 1687 u32 irq_stat, irq_masked; 1688 1689 VPRINTK("ENTER\n"); 1690 1691 hpriv = host->private_data; 1692 mmio = hpriv->mmio; 1693 1694 /* sigh. 0xffffffff is a valid return from h/w */ 1695 irq_stat = readl(mmio + HOST_IRQ_STAT); 1696 if (!irq_stat) 1697 return IRQ_NONE; 1698 1699 irq_masked = irq_stat & hpriv->port_map; 1700 1701 spin_lock(&host->lock); 1702 1703 for (i = 0; i < host->n_ports; i++) { 1704 struct ata_port *ap; 1705 1706 if (!(irq_masked & (1 << i))) 1707 continue; 1708 1709 ap = host->ports[i]; 1710 if (ap) { 1711 ahci_port_intr(ap); 1712 VPRINTK("port %u\n", i); 1713 } else { 1714 VPRINTK("port %u (no irq)\n", i); 1715 if (ata_ratelimit()) 1716 dev_printk(KERN_WARNING, host->dev, 1717 "interrupt on disabled port %u\n", i); 1718 } 1719 1720 handled = 1; 1721 } 1722 1723 /* HOST_IRQ_STAT behaves as level triggered latch meaning that 1724 * it should be cleared after all the port events are cleared; 1725 * otherwise, it will raise a spurious interrupt after each 1726 * valid one. Please read section 10.6.2 of ahci 1.1 for more 1727 * information. 1728 * 1729 * Also, use the unmasked value to clear interrupt as spurious 1730 * pending event on a dummy port might cause screaming IRQ. 1731 */ 1732 writel(irq_stat, mmio + HOST_IRQ_STAT); 1733 1734 spin_unlock(&host->lock); 1735 1736 VPRINTK("EXIT\n"); 1737 1738 return IRQ_RETVAL(handled); 1739 } 1740 EXPORT_SYMBOL_GPL(ahci_interrupt); 1741 1742 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1743 { 1744 struct ata_port *ap = qc->ap; 1745 void __iomem *port_mmio = ahci_port_base(ap); 1746 struct ahci_port_priv *pp = ap->private_data; 1747 1748 /* Keep track of the currently active link. It will be used 1749 * in completion path to determine whether NCQ phase is in 1750 * progress. 1751 */ 1752 pp->active_link = qc->dev->link; 1753 1754 if (qc->tf.protocol == ATA_PROT_NCQ) 1755 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1756 1757 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) { 1758 u32 fbs = readl(port_mmio + PORT_FBS); 1759 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC); 1760 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET; 1761 writel(fbs, port_mmio + PORT_FBS); 1762 pp->fbs_last_dev = qc->dev->link->pmp; 1763 } 1764 1765 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); 1766 1767 ahci_sw_activity(qc->dev->link); 1768 1769 return 0; 1770 } 1771 1772 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc) 1773 { 1774 struct ahci_port_priv *pp = qc->ap->private_data; 1775 u8 *rx_fis = pp->rx_fis; 1776 1777 if (pp->fbs_enabled) 1778 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ; 1779 1780 /* 1781 * After a successful execution of an ATA PIO data-in command, 1782 * the device doesn't send D2H Reg FIS to update the TF and 1783 * the host should take TF and E_Status from the preceding PIO 1784 * Setup FIS. 1785 */ 1786 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && 1787 !(qc->flags & ATA_QCFLAG_FAILED)) { 1788 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); 1789 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; 1790 } else 1791 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); 1792 1793 return true; 1794 } 1795 1796 static void ahci_freeze(struct ata_port *ap) 1797 { 1798 void __iomem *port_mmio = ahci_port_base(ap); 1799 1800 /* turn IRQ off */ 1801 writel(0, port_mmio + PORT_IRQ_MASK); 1802 } 1803 1804 static void ahci_thaw(struct ata_port *ap) 1805 { 1806 struct ahci_host_priv *hpriv = ap->host->private_data; 1807 void __iomem *mmio = hpriv->mmio; 1808 void __iomem *port_mmio = ahci_port_base(ap); 1809 u32 tmp; 1810 struct ahci_port_priv *pp = ap->private_data; 1811 1812 /* clear IRQ */ 1813 tmp = readl(port_mmio + PORT_IRQ_STAT); 1814 writel(tmp, port_mmio + PORT_IRQ_STAT); 1815 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT); 1816 1817 /* turn IRQ back on */ 1818 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1819 } 1820 1821 static void ahci_error_handler(struct ata_port *ap) 1822 { 1823 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1824 /* restart engine */ 1825 ahci_stop_engine(ap); 1826 ahci_start_engine(ap); 1827 } 1828 1829 sata_pmp_error_handler(ap); 1830 1831 if (!ata_dev_enabled(ap->link.device)) 1832 ahci_stop_engine(ap); 1833 } 1834 1835 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1836 { 1837 struct ata_port *ap = qc->ap; 1838 1839 /* make DMA engine forget about the failed command */ 1840 if (qc->flags & ATA_QCFLAG_FAILED) 1841 ahci_kick_engine(ap); 1842 } 1843 1844 static void ahci_enable_fbs(struct ata_port *ap) 1845 { 1846 struct ahci_port_priv *pp = ap->private_data; 1847 void __iomem *port_mmio = ahci_port_base(ap); 1848 u32 fbs; 1849 int rc; 1850 1851 if (!pp->fbs_supported) 1852 return; 1853 1854 fbs = readl(port_mmio + PORT_FBS); 1855 if (fbs & PORT_FBS_EN) { 1856 pp->fbs_enabled = true; 1857 pp->fbs_last_dev = -1; /* initialization */ 1858 return; 1859 } 1860 1861 rc = ahci_stop_engine(ap); 1862 if (rc) 1863 return; 1864 1865 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); 1866 fbs = readl(port_mmio + PORT_FBS); 1867 if (fbs & PORT_FBS_EN) { 1868 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n"); 1869 pp->fbs_enabled = true; 1870 pp->fbs_last_dev = -1; /* initialization */ 1871 } else 1872 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n"); 1873 1874 ahci_start_engine(ap); 1875 } 1876 1877 static void ahci_disable_fbs(struct ata_port *ap) 1878 { 1879 struct ahci_port_priv *pp = ap->private_data; 1880 void __iomem *port_mmio = ahci_port_base(ap); 1881 u32 fbs; 1882 int rc; 1883 1884 if (!pp->fbs_supported) 1885 return; 1886 1887 fbs = readl(port_mmio + PORT_FBS); 1888 if ((fbs & PORT_FBS_EN) == 0) { 1889 pp->fbs_enabled = false; 1890 return; 1891 } 1892 1893 rc = ahci_stop_engine(ap); 1894 if (rc) 1895 return; 1896 1897 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS); 1898 fbs = readl(port_mmio + PORT_FBS); 1899 if (fbs & PORT_FBS_EN) 1900 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n"); 1901 else { 1902 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n"); 1903 pp->fbs_enabled = false; 1904 } 1905 1906 ahci_start_engine(ap); 1907 } 1908 1909 static void ahci_pmp_attach(struct ata_port *ap) 1910 { 1911 void __iomem *port_mmio = ahci_port_base(ap); 1912 struct ahci_port_priv *pp = ap->private_data; 1913 u32 cmd; 1914 1915 cmd = readl(port_mmio + PORT_CMD); 1916 cmd |= PORT_CMD_PMP; 1917 writel(cmd, port_mmio + PORT_CMD); 1918 1919 ahci_enable_fbs(ap); 1920 1921 pp->intr_mask |= PORT_IRQ_BAD_PMP; 1922 1923 /* 1924 * We must not change the port interrupt mask register if the 1925 * port is marked frozen, the value in pp->intr_mask will be 1926 * restored later when the port is thawed. 1927 * 1928 * Note that during initialization, the port is marked as 1929 * frozen since the irq handler is not yet registered. 1930 */ 1931 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 1932 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1933 } 1934 1935 static void ahci_pmp_detach(struct ata_port *ap) 1936 { 1937 void __iomem *port_mmio = ahci_port_base(ap); 1938 struct ahci_port_priv *pp = ap->private_data; 1939 u32 cmd; 1940 1941 ahci_disable_fbs(ap); 1942 1943 cmd = readl(port_mmio + PORT_CMD); 1944 cmd &= ~PORT_CMD_PMP; 1945 writel(cmd, port_mmio + PORT_CMD); 1946 1947 pp->intr_mask &= ~PORT_IRQ_BAD_PMP; 1948 1949 /* see comment above in ahci_pmp_attach() */ 1950 if (!(ap->pflags & ATA_PFLAG_FROZEN)) 1951 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK); 1952 } 1953 1954 int ahci_port_resume(struct ata_port *ap) 1955 { 1956 ahci_power_up(ap); 1957 ahci_start_port(ap); 1958 1959 if (sata_pmp_attached(ap)) 1960 ahci_pmp_attach(ap); 1961 else 1962 ahci_pmp_detach(ap); 1963 1964 return 0; 1965 } 1966 EXPORT_SYMBOL_GPL(ahci_port_resume); 1967 1968 #ifdef CONFIG_PM 1969 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 1970 { 1971 const char *emsg = NULL; 1972 int rc; 1973 1974 rc = ahci_deinit_port(ap, &emsg); 1975 if (rc == 0) 1976 ahci_power_down(ap); 1977 else { 1978 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 1979 ahci_start_port(ap); 1980 } 1981 1982 return rc; 1983 } 1984 #endif 1985 1986 static int ahci_port_start(struct ata_port *ap) 1987 { 1988 struct ahci_host_priv *hpriv = ap->host->private_data; 1989 struct device *dev = ap->host->dev; 1990 struct ahci_port_priv *pp; 1991 void *mem; 1992 dma_addr_t mem_dma; 1993 size_t dma_sz, rx_fis_sz; 1994 1995 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 1996 if (!pp) 1997 return -ENOMEM; 1998 1999 /* check FBS capability */ 2000 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { 2001 void __iomem *port_mmio = ahci_port_base(ap); 2002 u32 cmd = readl(port_mmio + PORT_CMD); 2003 if (cmd & PORT_CMD_FBSCP) 2004 pp->fbs_supported = true; 2005 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { 2006 dev_printk(KERN_INFO, dev, 2007 "port %d can do FBS, forcing FBSCP\n", 2008 ap->port_no); 2009 pp->fbs_supported = true; 2010 } else 2011 dev_printk(KERN_WARNING, dev, 2012 "port %d is not capable of FBS\n", 2013 ap->port_no); 2014 } 2015 2016 if (pp->fbs_supported) { 2017 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; 2018 rx_fis_sz = AHCI_RX_FIS_SZ * 16; 2019 } else { 2020 dma_sz = AHCI_PORT_PRIV_DMA_SZ; 2021 rx_fis_sz = AHCI_RX_FIS_SZ; 2022 } 2023 2024 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); 2025 if (!mem) 2026 return -ENOMEM; 2027 memset(mem, 0, dma_sz); 2028 2029 /* 2030 * First item in chunk of DMA memory: 32-slot command table, 2031 * 32 bytes each in size 2032 */ 2033 pp->cmd_slot = mem; 2034 pp->cmd_slot_dma = mem_dma; 2035 2036 mem += AHCI_CMD_SLOT_SZ; 2037 mem_dma += AHCI_CMD_SLOT_SZ; 2038 2039 /* 2040 * Second item: Received-FIS area 2041 */ 2042 pp->rx_fis = mem; 2043 pp->rx_fis_dma = mem_dma; 2044 2045 mem += rx_fis_sz; 2046 mem_dma += rx_fis_sz; 2047 2048 /* 2049 * Third item: data area for storing a single command 2050 * and its scatter-gather table 2051 */ 2052 pp->cmd_tbl = mem; 2053 pp->cmd_tbl_dma = mem_dma; 2054 2055 /* 2056 * Save off initial list of interrupts to be enabled. 2057 * This could be changed later 2058 */ 2059 pp->intr_mask = DEF_PORT_IRQ; 2060 2061 ap->private_data = pp; 2062 2063 /* engage engines, captain */ 2064 return ahci_port_resume(ap); 2065 } 2066 2067 static void ahci_port_stop(struct ata_port *ap) 2068 { 2069 const char *emsg = NULL; 2070 int rc; 2071 2072 /* de-initialize port */ 2073 rc = ahci_deinit_port(ap, &emsg); 2074 if (rc) 2075 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 2076 } 2077 2078 void ahci_print_info(struct ata_host *host, const char *scc_s) 2079 { 2080 struct ahci_host_priv *hpriv = host->private_data; 2081 void __iomem *mmio = hpriv->mmio; 2082 u32 vers, cap, cap2, impl, speed; 2083 const char *speed_s; 2084 2085 vers = readl(mmio + HOST_VERSION); 2086 cap = hpriv->cap; 2087 cap2 = hpriv->cap2; 2088 impl = hpriv->port_map; 2089 2090 speed = (cap >> 20) & 0xf; 2091 if (speed == 1) 2092 speed_s = "1.5"; 2093 else if (speed == 2) 2094 speed_s = "3"; 2095 else if (speed == 3) 2096 speed_s = "6"; 2097 else 2098 speed_s = "?"; 2099 2100 dev_info(host->dev, 2101 "AHCI %02x%02x.%02x%02x " 2102 "%u slots %u ports %s Gbps 0x%x impl %s mode\n" 2103 , 2104 2105 (vers >> 24) & 0xff, 2106 (vers >> 16) & 0xff, 2107 (vers >> 8) & 0xff, 2108 vers & 0xff, 2109 2110 ((cap >> 8) & 0x1f) + 1, 2111 (cap & 0x1f) + 1, 2112 speed_s, 2113 impl, 2114 scc_s); 2115 2116 dev_info(host->dev, 2117 "flags: " 2118 "%s%s%s%s%s%s%s" 2119 "%s%s%s%s%s%s%s" 2120 "%s%s%s%s%s%s\n" 2121 , 2122 2123 cap & HOST_CAP_64 ? "64bit " : "", 2124 cap & HOST_CAP_NCQ ? "ncq " : "", 2125 cap & HOST_CAP_SNTF ? "sntf " : "", 2126 cap & HOST_CAP_MPS ? "ilck " : "", 2127 cap & HOST_CAP_SSS ? "stag " : "", 2128 cap & HOST_CAP_ALPM ? "pm " : "", 2129 cap & HOST_CAP_LED ? "led " : "", 2130 cap & HOST_CAP_CLO ? "clo " : "", 2131 cap & HOST_CAP_ONLY ? "only " : "", 2132 cap & HOST_CAP_PMP ? "pmp " : "", 2133 cap & HOST_CAP_FBS ? "fbs " : "", 2134 cap & HOST_CAP_PIO_MULTI ? "pio " : "", 2135 cap & HOST_CAP_SSC ? "slum " : "", 2136 cap & HOST_CAP_PART ? "part " : "", 2137 cap & HOST_CAP_CCC ? "ccc " : "", 2138 cap & HOST_CAP_EMS ? "ems " : "", 2139 cap & HOST_CAP_SXS ? "sxs " : "", 2140 cap2 & HOST_CAP2_APST ? "apst " : "", 2141 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "", 2142 cap2 & HOST_CAP2_BOH ? "boh " : "" 2143 ); 2144 } 2145 EXPORT_SYMBOL_GPL(ahci_print_info); 2146 2147 void ahci_set_em_messages(struct ahci_host_priv *hpriv, 2148 struct ata_port_info *pi) 2149 { 2150 u8 messages; 2151 void __iomem *mmio = hpriv->mmio; 2152 u32 em_loc = readl(mmio + HOST_EM_LOC); 2153 u32 em_ctl = readl(mmio + HOST_EM_CTL); 2154 2155 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS)) 2156 return; 2157 2158 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16; 2159 2160 if (messages) { 2161 /* store em_loc */ 2162 hpriv->em_loc = ((em_loc >> 16) * 4); 2163 hpriv->em_buf_sz = ((em_loc & 0xff) * 4); 2164 hpriv->em_msg_type = messages; 2165 pi->flags |= ATA_FLAG_EM; 2166 if (!(em_ctl & EM_CTL_ALHD)) 2167 pi->flags |= ATA_FLAG_SW_ACTIVITY; 2168 } 2169 } 2170 EXPORT_SYMBOL_GPL(ahci_set_em_messages); 2171 2172 MODULE_AUTHOR("Jeff Garzik"); 2173 MODULE_DESCRIPTION("Common AHCI SATA low-level routines"); 2174 MODULE_LICENSE("GPL"); 2175