1 /* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The orginal Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * 76 * Should have been BIOS fixed: 77 * 450NX: errata #19 - DMA hangs on old 450NX 78 * 450NX: errata #20 - DMA hangs on old 450NX 79 * 450NX: errata #25 - Corruption with DMA on old 450NX 80 * ICH3 errata #15 - IDE deadlock under high load 81 * (BIOS must set dev 31 fn 0 bit 23) 82 * ICH3 errata #18 - Don't use native mode 83 */ 84 85 #include <linux/kernel.h> 86 #include <linux/module.h> 87 #include <linux/pci.h> 88 #include <linux/init.h> 89 #include <linux/blkdev.h> 90 #include <linux/delay.h> 91 #include <linux/device.h> 92 #include <scsi/scsi_host.h> 93 #include <linux/libata.h> 94 95 #define DRV_NAME "ata_piix" 96 #define DRV_VERSION "2.11" 97 98 enum { 99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 100 ICH5_PMR = 0x90, /* port mapping register */ 101 ICH5_PCS = 0x92, /* port control and status */ 102 PIIX_SCC = 0x0A, /* sub-class code register */ 103 104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */ 105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ 106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 107 108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 110 111 /* combined mode. if set, PATA is channel 0. 112 * if clear, PATA is channel 1. 113 */ 114 PIIX_PORT_ENABLED = (1 << 0), 115 PIIX_PORT_PRESENT = (1 << 4), 116 117 PIIX_80C_PRI = (1 << 5) | (1 << 4), 118 PIIX_80C_SEC = (1 << 7) | (1 << 6), 119 120 /* controller IDs */ 121 piix_pata_33 = 0, /* PIIX4 at 33Mhz */ 122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */ 123 ich_pata_66 = 2, /* ICH up to 66 Mhz */ 124 ich_pata_100 = 3, /* ICH up to UDMA 100 */ 125 ich_pata_133 = 4, /* ICH up to UDMA 133 */ 126 ich5_sata = 5, 127 ich6_sata = 6, 128 ich6_sata_ahci = 7, 129 ich6m_sata_ahci = 8, 130 ich8_sata_ahci = 9, 131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ 132 133 /* constants for mapping table */ 134 P0 = 0, /* port 0 */ 135 P1 = 1, /* port 1 */ 136 P2 = 2, /* port 2 */ 137 P3 = 3, /* port 3 */ 138 IDE = -1, /* IDE */ 139 NA = -2, /* not avaliable */ 140 RV = -3, /* reserved */ 141 142 PIIX_AHCI_DEVICE = 6, 143 }; 144 145 struct piix_map_db { 146 const u32 mask; 147 const u16 port_enable; 148 const int map[][4]; 149 }; 150 151 struct piix_host_priv { 152 const int *map; 153 }; 154 155 static int piix_init_one (struct pci_dev *pdev, 156 const struct pci_device_id *ent); 157 static void piix_pata_error_handler(struct ata_port *ap); 158 static void piix_sata_error_handler(struct ata_port *ap); 159 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); 160 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); 161 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev); 162 static int ich_pata_cable_detect(struct ata_port *ap); 163 164 static unsigned int in_module_init = 1; 165 166 static const struct pci_device_id piix_pci_tbl[] = { 167 /* Intel PIIX3 for the 430HX etc */ 168 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 169 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 170 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 171 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 172 /* Intel PIIX4 */ 173 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 174 /* Intel PIIX4 */ 175 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 176 /* Intel PIIX */ 177 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 178 /* Intel ICH (i810, i815, i840) UDMA 66*/ 179 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 180 /* Intel ICH0 : UDMA 33*/ 181 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 182 /* Intel ICH2M */ 183 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 184 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 185 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 186 /* Intel ICH3M */ 187 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 188 /* Intel ICH3 (E7500/1) UDMA 100 */ 189 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 190 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 191 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 192 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 193 /* Intel ICH5 */ 194 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, 195 /* C-ICH (i810E2) */ 196 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 197 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 198 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 199 /* ICH6 (and 6) (i915) UDMA 100 */ 200 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 201 /* ICH7/7-R (i945, i975) UDMA 100*/ 202 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, 203 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 204 205 /* NOTE: The following PCI ids must be kept in sync with the 206 * list in drivers/pci/quirks.c. 207 */ 208 209 /* 82801EB (ICH5) */ 210 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 211 /* 82801EB (ICH5) */ 212 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 213 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 214 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 215 /* 6300ESB pretending RAID */ 216 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 217 /* 82801FB/FW (ICH6/ICH6W) */ 218 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 219 /* 82801FR/FRW (ICH6R/ICH6RW) */ 220 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 221 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ 222 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 223 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 224 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 225 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 226 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 227 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 228 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 229 /* SATA Controller 1 IDE (ICH8) */ 230 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 231 /* SATA Controller 2 IDE (ICH8) */ 232 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 233 /* Mobile SATA Controller IDE (ICH8M) */ 234 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 235 /* SATA Controller IDE (ICH9) */ 236 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 237 /* SATA Controller IDE (ICH9) */ 238 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 239 /* SATA Controller IDE (ICH9) */ 240 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 241 /* SATA Controller IDE (ICH9M) */ 242 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 243 /* SATA Controller IDE (ICH9M) */ 244 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 245 /* SATA Controller IDE (ICH9M) */ 246 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 247 248 { } /* terminate list */ 249 }; 250 251 static struct pci_driver piix_pci_driver = { 252 .name = DRV_NAME, 253 .id_table = piix_pci_tbl, 254 .probe = piix_init_one, 255 .remove = ata_pci_remove_one, 256 #ifdef CONFIG_PM 257 .suspend = ata_pci_device_suspend, 258 .resume = ata_pci_device_resume, 259 #endif 260 }; 261 262 static struct scsi_host_template piix_sht = { 263 .module = THIS_MODULE, 264 .name = DRV_NAME, 265 .ioctl = ata_scsi_ioctl, 266 .queuecommand = ata_scsi_queuecmd, 267 .can_queue = ATA_DEF_QUEUE, 268 .this_id = ATA_SHT_THIS_ID, 269 .sg_tablesize = LIBATA_MAX_PRD, 270 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 271 .emulated = ATA_SHT_EMULATED, 272 .use_clustering = ATA_SHT_USE_CLUSTERING, 273 .proc_name = DRV_NAME, 274 .dma_boundary = ATA_DMA_BOUNDARY, 275 .slave_configure = ata_scsi_slave_config, 276 .slave_destroy = ata_scsi_slave_destroy, 277 .bios_param = ata_std_bios_param, 278 #ifdef CONFIG_PM 279 .resume = ata_scsi_device_resume, 280 .suspend = ata_scsi_device_suspend, 281 #endif 282 }; 283 284 static const struct ata_port_operations piix_pata_ops = { 285 .port_disable = ata_port_disable, 286 .set_piomode = piix_set_piomode, 287 .set_dmamode = piix_set_dmamode, 288 .mode_filter = ata_pci_default_filter, 289 290 .tf_load = ata_tf_load, 291 .tf_read = ata_tf_read, 292 .check_status = ata_check_status, 293 .exec_command = ata_exec_command, 294 .dev_select = ata_std_dev_select, 295 296 .bmdma_setup = ata_bmdma_setup, 297 .bmdma_start = ata_bmdma_start, 298 .bmdma_stop = ata_bmdma_stop, 299 .bmdma_status = ata_bmdma_status, 300 .qc_prep = ata_qc_prep, 301 .qc_issue = ata_qc_issue_prot, 302 .data_xfer = ata_data_xfer, 303 304 .freeze = ata_bmdma_freeze, 305 .thaw = ata_bmdma_thaw, 306 .error_handler = piix_pata_error_handler, 307 .post_internal_cmd = ata_bmdma_post_internal_cmd, 308 .cable_detect = ata_cable_40wire, 309 310 .irq_handler = ata_interrupt, 311 .irq_clear = ata_bmdma_irq_clear, 312 .irq_on = ata_irq_on, 313 .irq_ack = ata_irq_ack, 314 315 .port_start = ata_port_start, 316 }; 317 318 static const struct ata_port_operations ich_pata_ops = { 319 .port_disable = ata_port_disable, 320 .set_piomode = piix_set_piomode, 321 .set_dmamode = ich_set_dmamode, 322 .mode_filter = ata_pci_default_filter, 323 324 .tf_load = ata_tf_load, 325 .tf_read = ata_tf_read, 326 .check_status = ata_check_status, 327 .exec_command = ata_exec_command, 328 .dev_select = ata_std_dev_select, 329 330 .bmdma_setup = ata_bmdma_setup, 331 .bmdma_start = ata_bmdma_start, 332 .bmdma_stop = ata_bmdma_stop, 333 .bmdma_status = ata_bmdma_status, 334 .qc_prep = ata_qc_prep, 335 .qc_issue = ata_qc_issue_prot, 336 .data_xfer = ata_data_xfer, 337 338 .freeze = ata_bmdma_freeze, 339 .thaw = ata_bmdma_thaw, 340 .error_handler = piix_pata_error_handler, 341 .post_internal_cmd = ata_bmdma_post_internal_cmd, 342 .cable_detect = ich_pata_cable_detect, 343 344 .irq_handler = ata_interrupt, 345 .irq_clear = ata_bmdma_irq_clear, 346 .irq_on = ata_irq_on, 347 .irq_ack = ata_irq_ack, 348 349 .port_start = ata_port_start, 350 }; 351 352 static const struct ata_port_operations piix_sata_ops = { 353 .port_disable = ata_port_disable, 354 355 .tf_load = ata_tf_load, 356 .tf_read = ata_tf_read, 357 .check_status = ata_check_status, 358 .exec_command = ata_exec_command, 359 .dev_select = ata_std_dev_select, 360 361 .bmdma_setup = ata_bmdma_setup, 362 .bmdma_start = ata_bmdma_start, 363 .bmdma_stop = ata_bmdma_stop, 364 .bmdma_status = ata_bmdma_status, 365 .qc_prep = ata_qc_prep, 366 .qc_issue = ata_qc_issue_prot, 367 .data_xfer = ata_data_xfer, 368 369 .freeze = ata_bmdma_freeze, 370 .thaw = ata_bmdma_thaw, 371 .error_handler = piix_sata_error_handler, 372 .post_internal_cmd = ata_bmdma_post_internal_cmd, 373 374 .irq_handler = ata_interrupt, 375 .irq_clear = ata_bmdma_irq_clear, 376 .irq_on = ata_irq_on, 377 .irq_ack = ata_irq_ack, 378 379 .port_start = ata_port_start, 380 }; 381 382 static const struct piix_map_db ich5_map_db = { 383 .mask = 0x7, 384 .port_enable = 0x3, 385 .map = { 386 /* PM PS SM SS MAP */ 387 { P0, NA, P1, NA }, /* 000b */ 388 { P1, NA, P0, NA }, /* 001b */ 389 { RV, RV, RV, RV }, 390 { RV, RV, RV, RV }, 391 { P0, P1, IDE, IDE }, /* 100b */ 392 { P1, P0, IDE, IDE }, /* 101b */ 393 { IDE, IDE, P0, P1 }, /* 110b */ 394 { IDE, IDE, P1, P0 }, /* 111b */ 395 }, 396 }; 397 398 static const struct piix_map_db ich6_map_db = { 399 .mask = 0x3, 400 .port_enable = 0xf, 401 .map = { 402 /* PM PS SM SS MAP */ 403 { P0, P2, P1, P3 }, /* 00b */ 404 { IDE, IDE, P1, P3 }, /* 01b */ 405 { P0, P2, IDE, IDE }, /* 10b */ 406 { RV, RV, RV, RV }, 407 }, 408 }; 409 410 static const struct piix_map_db ich6m_map_db = { 411 .mask = 0x3, 412 .port_enable = 0x5, 413 414 /* Map 01b isn't specified in the doc but some notebooks use 415 * it anyway. MAP 01b have been spotted on both ICH6M and 416 * ICH7M. 417 */ 418 .map = { 419 /* PM PS SM SS MAP */ 420 { P0, P2, RV, RV }, /* 00b */ 421 { IDE, IDE, P1, P3 }, /* 01b */ 422 { P0, P2, IDE, IDE }, /* 10b */ 423 { RV, RV, RV, RV }, 424 }, 425 }; 426 427 static const struct piix_map_db ich8_map_db = { 428 .mask = 0x3, 429 .port_enable = 0x3, 430 .map = { 431 /* PM PS SM SS MAP */ 432 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 433 { RV, RV, RV, RV }, 434 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */ 435 { RV, RV, RV, RV }, 436 }, 437 }; 438 439 static const struct piix_map_db *piix_map_db_table[] = { 440 [ich5_sata] = &ich5_map_db, 441 [ich6_sata] = &ich6_map_db, 442 [ich6_sata_ahci] = &ich6_map_db, 443 [ich6m_sata_ahci] = &ich6m_map_db, 444 [ich8_sata_ahci] = &ich8_map_db, 445 }; 446 447 static struct ata_port_info piix_port_info[] = { 448 /* piix_pata_33: 0: PIIX4 at 33MHz */ 449 { 450 .sht = &piix_sht, 451 .flags = PIIX_PATA_FLAGS, 452 .pio_mask = 0x1f, /* pio0-4 */ 453 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 454 .udma_mask = ATA_UDMA_MASK_40C, 455 .port_ops = &piix_pata_ops, 456 }, 457 458 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/ 459 { 460 .sht = &piix_sht, 461 .flags = PIIX_PATA_FLAGS, 462 .pio_mask = 0x1f, /* pio 0-4 */ 463 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 464 .udma_mask = ATA_UDMA2, /* UDMA33 */ 465 .port_ops = &ich_pata_ops, 466 }, 467 /* ich_pata_66: 2 ICH controllers up to 66MHz */ 468 { 469 .sht = &piix_sht, 470 .flags = PIIX_PATA_FLAGS, 471 .pio_mask = 0x1f, /* pio 0-4 */ 472 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ 473 .udma_mask = ATA_UDMA4, 474 .port_ops = &ich_pata_ops, 475 }, 476 477 /* ich_pata_100: 3 */ 478 { 479 .sht = &piix_sht, 480 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 481 .pio_mask = 0x1f, /* pio0-4 */ 482 .mwdma_mask = 0x06, /* mwdma1-2 */ 483 .udma_mask = ATA_UDMA5, /* udma0-5 */ 484 .port_ops = &ich_pata_ops, 485 }, 486 487 /* ich_pata_133: 4 ICH with full UDMA6 */ 488 { 489 .sht = &piix_sht, 490 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 491 .pio_mask = 0x1f, /* pio 0-4 */ 492 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 493 .udma_mask = ATA_UDMA6, /* UDMA133 */ 494 .port_ops = &ich_pata_ops, 495 }, 496 497 /* ich5_sata: 5 */ 498 { 499 .sht = &piix_sht, 500 .flags = PIIX_SATA_FLAGS, 501 .pio_mask = 0x1f, /* pio0-4 */ 502 .mwdma_mask = 0x07, /* mwdma0-2 */ 503 .udma_mask = 0x7f, /* udma0-6 */ 504 .port_ops = &piix_sata_ops, 505 }, 506 507 /* ich6_sata: 6 */ 508 { 509 .sht = &piix_sht, 510 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, 511 .pio_mask = 0x1f, /* pio0-4 */ 512 .mwdma_mask = 0x07, /* mwdma0-2 */ 513 .udma_mask = 0x7f, /* udma0-6 */ 514 .port_ops = &piix_sata_ops, 515 }, 516 517 /* ich6_sata_ahci: 7 */ 518 { 519 .sht = &piix_sht, 520 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 521 PIIX_FLAG_AHCI, 522 .pio_mask = 0x1f, /* pio0-4 */ 523 .mwdma_mask = 0x07, /* mwdma0-2 */ 524 .udma_mask = 0x7f, /* udma0-6 */ 525 .port_ops = &piix_sata_ops, 526 }, 527 528 /* ich6m_sata_ahci: 8 */ 529 { 530 .sht = &piix_sht, 531 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 532 PIIX_FLAG_AHCI, 533 .pio_mask = 0x1f, /* pio0-4 */ 534 .mwdma_mask = 0x07, /* mwdma0-2 */ 535 .udma_mask = 0x7f, /* udma0-6 */ 536 .port_ops = &piix_sata_ops, 537 }, 538 539 /* ich8_sata_ahci: 9 */ 540 { 541 .sht = &piix_sht, 542 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 543 PIIX_FLAG_AHCI, 544 .pio_mask = 0x1f, /* pio0-4 */ 545 .mwdma_mask = 0x07, /* mwdma0-2 */ 546 .udma_mask = 0x7f, /* udma0-6 */ 547 .port_ops = &piix_sata_ops, 548 }, 549 550 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */ 551 { 552 .sht = &piix_sht, 553 .flags = PIIX_PATA_FLAGS, 554 .pio_mask = 0x1f, /* pio0-4 */ 555 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 556 .port_ops = &piix_pata_ops, 557 }, 558 }; 559 560 static struct pci_bits piix_enable_bits[] = { 561 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 562 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 563 }; 564 565 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 566 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 567 MODULE_LICENSE("GPL"); 568 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 569 MODULE_VERSION(DRV_VERSION); 570 571 struct ich_laptop { 572 u16 device; 573 u16 subvendor; 574 u16 subdevice; 575 }; 576 577 /* 578 * List of laptops that use short cables rather than 80 wire 579 */ 580 581 static const struct ich_laptop ich_laptop[] = { 582 /* devid, subvendor, subdev */ 583 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 584 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 585 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 586 /* end marker */ 587 { 0, } 588 }; 589 590 /** 591 * ich_pata_cable_detect - Probe host controller cable detect info 592 * @ap: Port for which cable detect info is desired 593 * 594 * Read 80c cable indicator from ATA PCI device's PCI config 595 * register. This register is normally set by firmware (BIOS). 596 * 597 * LOCKING: 598 * None (inherited from caller). 599 */ 600 601 static int ich_pata_cable_detect(struct ata_port *ap) 602 { 603 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 604 const struct ich_laptop *lap = &ich_laptop[0]; 605 u8 tmp, mask; 606 607 /* Check for specials - Acer Aspire 5602WLMi */ 608 while (lap->device) { 609 if (lap->device == pdev->device && 610 lap->subvendor == pdev->subsystem_vendor && 611 lap->subdevice == pdev->subsystem_device) { 612 return ATA_CBL_PATA40_SHORT; 613 } 614 lap++; 615 } 616 617 /* check BIOS cable detect results */ 618 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 619 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); 620 if ((tmp & mask) == 0) 621 return ATA_CBL_PATA40; 622 return ATA_CBL_PATA80; 623 } 624 625 /** 626 * piix_pata_prereset - prereset for PATA host controller 627 * @ap: Target port 628 * 629 * LOCKING: 630 * None (inherited from caller). 631 */ 632 static int piix_pata_prereset(struct ata_port *ap) 633 { 634 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 635 636 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 637 return -ENOENT; 638 return ata_std_prereset(ap); 639 } 640 641 static void piix_pata_error_handler(struct ata_port *ap) 642 { 643 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, 644 ata_std_postreset); 645 } 646 647 648 static void piix_sata_error_handler(struct ata_port *ap) 649 { 650 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL, 651 ata_std_postreset); 652 } 653 654 /** 655 * piix_set_piomode - Initialize host controller PATA PIO timings 656 * @ap: Port whose timings we are configuring 657 * @adev: um 658 * 659 * Set PIO mode for device, in host controller PCI config space. 660 * 661 * LOCKING: 662 * None (inherited from caller). 663 */ 664 665 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) 666 { 667 unsigned int pio = adev->pio_mode - XFER_PIO_0; 668 struct pci_dev *dev = to_pci_dev(ap->host->dev); 669 unsigned int is_slave = (adev->devno != 0); 670 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 671 unsigned int slave_port = 0x44; 672 u16 master_data; 673 u8 slave_data; 674 u8 udma_enable; 675 int control = 0; 676 677 /* 678 * See Intel Document 298600-004 for the timing programing rules 679 * for ICH controllers. 680 */ 681 682 static const /* ISP RTC */ 683 u8 timings[][2] = { { 0, 0 }, 684 { 0, 0 }, 685 { 1, 0 }, 686 { 2, 1 }, 687 { 2, 3 }, }; 688 689 if (pio >= 2) 690 control |= 1; /* TIME1 enable */ 691 if (ata_pio_need_iordy(adev)) 692 control |= 2; /* IE enable */ 693 694 /* Intel specifies that the PPE functionality is for disk only */ 695 if (adev->class == ATA_DEV_ATA) 696 control |= 4; /* PPE enable */ 697 698 pci_read_config_word(dev, master_port, &master_data); 699 if (is_slave) { 700 /* Enable SITRE (seperate slave timing register) */ 701 master_data |= 0x4000; 702 /* enable PPE1, IE1 and TIME1 as needed */ 703 master_data |= (control << 4); 704 pci_read_config_byte(dev, slave_port, &slave_data); 705 slave_data &= (ap->port_no ? 0x0f : 0xf0); 706 /* Load the timing nibble for this slave */ 707 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 708 } else { 709 /* Master keeps the bits in a different format */ 710 master_data &= 0xccf8; 711 /* Enable PPE, IE and TIME as appropriate */ 712 master_data |= control; 713 master_data |= 714 (timings[pio][0] << 12) | 715 (timings[pio][1] << 8); 716 } 717 pci_write_config_word(dev, master_port, master_data); 718 if (is_slave) 719 pci_write_config_byte(dev, slave_port, slave_data); 720 721 /* Ensure the UDMA bit is off - it will be turned back on if 722 UDMA is selected */ 723 724 if (ap->udma_mask) { 725 pci_read_config_byte(dev, 0x48, &udma_enable); 726 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 727 pci_write_config_byte(dev, 0x48, udma_enable); 728 } 729 } 730 731 /** 732 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 733 * @ap: Port whose timings we are configuring 734 * @adev: Drive in question 735 * @udma: udma mode, 0 - 6 736 * @isich: set if the chip is an ICH device 737 * 738 * Set UDMA mode for device, in host controller PCI config space. 739 * 740 * LOCKING: 741 * None (inherited from caller). 742 */ 743 744 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich) 745 { 746 struct pci_dev *dev = to_pci_dev(ap->host->dev); 747 u8 master_port = ap->port_no ? 0x42 : 0x40; 748 u16 master_data; 749 u8 speed = adev->dma_mode; 750 int devid = adev->devno + 2 * ap->port_no; 751 u8 udma_enable = 0; 752 753 static const /* ISP RTC */ 754 u8 timings[][2] = { { 0, 0 }, 755 { 0, 0 }, 756 { 1, 0 }, 757 { 2, 1 }, 758 { 2, 3 }, }; 759 760 pci_read_config_word(dev, master_port, &master_data); 761 if (ap->udma_mask) 762 pci_read_config_byte(dev, 0x48, &udma_enable); 763 764 if (speed >= XFER_UDMA_0) { 765 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 766 u16 udma_timing; 767 u16 ideconf; 768 int u_clock, u_speed; 769 770 /* 771 * UDMA is handled by a combination of clock switching and 772 * selection of dividers 773 * 774 * Handy rule: Odd modes are UDMATIMx 01, even are 02 775 * except UDMA0 which is 00 776 */ 777 u_speed = min(2 - (udma & 1), udma); 778 if (udma == 5) 779 u_clock = 0x1000; /* 100Mhz */ 780 else if (udma > 2) 781 u_clock = 1; /* 66Mhz */ 782 else 783 u_clock = 0; /* 33Mhz */ 784 785 udma_enable |= (1 << devid); 786 787 /* Load the CT/RP selection */ 788 pci_read_config_word(dev, 0x4A, &udma_timing); 789 udma_timing &= ~(3 << (4 * devid)); 790 udma_timing |= u_speed << (4 * devid); 791 pci_write_config_word(dev, 0x4A, udma_timing); 792 793 if (isich) { 794 /* Select a 33/66/100Mhz clock */ 795 pci_read_config_word(dev, 0x54, &ideconf); 796 ideconf &= ~(0x1001 << devid); 797 ideconf |= u_clock << devid; 798 /* For ICH or later we should set bit 10 for better 799 performance (WR_PingPong_En) */ 800 pci_write_config_word(dev, 0x54, ideconf); 801 } 802 } else { 803 /* 804 * MWDMA is driven by the PIO timings. We must also enable 805 * IORDY unconditionally along with TIME1. PPE has already 806 * been set when the PIO timing was set. 807 */ 808 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 809 unsigned int control; 810 u8 slave_data; 811 const unsigned int needed_pio[3] = { 812 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 813 }; 814 int pio = needed_pio[mwdma] - XFER_PIO_0; 815 816 control = 3; /* IORDY|TIME1 */ 817 818 /* If the drive MWDMA is faster than it can do PIO then 819 we must force PIO into PIO0 */ 820 821 if (adev->pio_mode < needed_pio[mwdma]) 822 /* Enable DMA timing only */ 823 control |= 8; /* PIO cycles in PIO0 */ 824 825 if (adev->devno) { /* Slave */ 826 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 827 master_data |= control << 4; 828 pci_read_config_byte(dev, 0x44, &slave_data); 829 slave_data &= (0x0F + 0xE1 * ap->port_no); 830 /* Load the matching timing */ 831 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 832 pci_write_config_byte(dev, 0x44, slave_data); 833 } else { /* Master */ 834 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 835 and master timing bits */ 836 master_data |= control; 837 master_data |= 838 (timings[pio][0] << 12) | 839 (timings[pio][1] << 8); 840 } 841 udma_enable &= ~(1 << devid); 842 pci_write_config_word(dev, master_port, master_data); 843 } 844 /* Don't scribble on 0x48 if the controller does not support UDMA */ 845 if (ap->udma_mask) 846 pci_write_config_byte(dev, 0x48, udma_enable); 847 } 848 849 /** 850 * piix_set_dmamode - Initialize host controller PATA DMA timings 851 * @ap: Port whose timings we are configuring 852 * @adev: um 853 * 854 * Set MW/UDMA mode for device, in host controller PCI config space. 855 * 856 * LOCKING: 857 * None (inherited from caller). 858 */ 859 860 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) 861 { 862 do_pata_set_dmamode(ap, adev, 0); 863 } 864 865 /** 866 * ich_set_dmamode - Initialize host controller PATA DMA timings 867 * @ap: Port whose timings we are configuring 868 * @adev: um 869 * 870 * Set MW/UDMA mode for device, in host controller PCI config space. 871 * 872 * LOCKING: 873 * None (inherited from caller). 874 */ 875 876 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev) 877 { 878 do_pata_set_dmamode(ap, adev, 1); 879 } 880 881 #define AHCI_PCI_BAR 5 882 #define AHCI_GLOBAL_CTL 0x04 883 #define AHCI_ENABLE (1 << 31) 884 static int piix_disable_ahci(struct pci_dev *pdev) 885 { 886 void __iomem *mmio; 887 u32 tmp; 888 int rc = 0; 889 890 /* BUG: pci_enable_device has not yet been called. This 891 * works because this device is usually set up by BIOS. 892 */ 893 894 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 895 !pci_resource_len(pdev, AHCI_PCI_BAR)) 896 return 0; 897 898 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 899 if (!mmio) 900 return -ENOMEM; 901 902 tmp = readl(mmio + AHCI_GLOBAL_CTL); 903 if (tmp & AHCI_ENABLE) { 904 tmp &= ~AHCI_ENABLE; 905 writel(tmp, mmio + AHCI_GLOBAL_CTL); 906 907 tmp = readl(mmio + AHCI_GLOBAL_CTL); 908 if (tmp & AHCI_ENABLE) 909 rc = -EIO; 910 } 911 912 pci_iounmap(pdev, mmio); 913 return rc; 914 } 915 916 /** 917 * piix_check_450nx_errata - Check for problem 450NX setup 918 * @ata_dev: the PCI device to check 919 * 920 * Check for the present of 450NX errata #19 and errata #25. If 921 * they are found return an error code so we can turn off DMA 922 */ 923 924 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 925 { 926 struct pci_dev *pdev = NULL; 927 u16 cfg; 928 u8 rev; 929 int no_piix_dma = 0; 930 931 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) 932 { 933 /* Look for 450NX PXB. Check for problem configurations 934 A PCI quirk checks bit 6 already */ 935 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 936 pci_read_config_word(pdev, 0x41, &cfg); 937 /* Only on the original revision: IDE DMA can hang */ 938 if (rev == 0x00) 939 no_piix_dma = 1; 940 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 941 else if (cfg & (1<<14) && rev < 5) 942 no_piix_dma = 2; 943 } 944 if (no_piix_dma) 945 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 946 if (no_piix_dma == 2) 947 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 948 return no_piix_dma; 949 } 950 951 static void __devinit piix_init_pcs(struct pci_dev *pdev, 952 struct ata_port_info *pinfo, 953 const struct piix_map_db *map_db) 954 { 955 u16 pcs, new_pcs; 956 957 pci_read_config_word(pdev, ICH5_PCS, &pcs); 958 959 new_pcs = pcs | map_db->port_enable; 960 961 if (new_pcs != pcs) { 962 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 963 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 964 msleep(150); 965 } 966 } 967 968 static void __devinit piix_init_sata_map(struct pci_dev *pdev, 969 struct ata_port_info *pinfo, 970 const struct piix_map_db *map_db) 971 { 972 struct piix_host_priv *hpriv = pinfo[0].private_data; 973 const unsigned int *map; 974 int i, invalid_map = 0; 975 u8 map_value; 976 977 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 978 979 map = map_db->map[map_value & map_db->mask]; 980 981 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 982 for (i = 0; i < 4; i++) { 983 switch (map[i]) { 984 case RV: 985 invalid_map = 1; 986 printk(" XX"); 987 break; 988 989 case NA: 990 printk(" --"); 991 break; 992 993 case IDE: 994 WARN_ON((i & 1) || map[i + 1] != IDE); 995 pinfo[i / 2] = piix_port_info[ich_pata_100]; 996 pinfo[i / 2].private_data = hpriv; 997 i++; 998 printk(" IDE IDE"); 999 break; 1000 1001 default: 1002 printk(" P%d", map[i]); 1003 if (i & 1) 1004 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1005 break; 1006 } 1007 } 1008 printk(" ]\n"); 1009 1010 if (invalid_map) 1011 dev_printk(KERN_ERR, &pdev->dev, 1012 "invalid MAP value %u\n", map_value); 1013 1014 hpriv->map = map; 1015 } 1016 1017 /** 1018 * piix_init_one - Register PIIX ATA PCI device with kernel services 1019 * @pdev: PCI device to register 1020 * @ent: Entry in piix_pci_tbl matching with @pdev 1021 * 1022 * Called from kernel PCI layer. We probe for combined mode (sigh), 1023 * and then hand over control to libata, for it to do the rest. 1024 * 1025 * LOCKING: 1026 * Inherited from PCI layer (may sleep). 1027 * 1028 * RETURNS: 1029 * Zero on success, or -ERRNO value. 1030 */ 1031 1032 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1033 { 1034 static int printed_version; 1035 struct device *dev = &pdev->dev; 1036 struct ata_port_info port_info[2]; 1037 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] }; 1038 struct piix_host_priv *hpriv; 1039 unsigned long port_flags; 1040 1041 if (!printed_version++) 1042 dev_printk(KERN_DEBUG, &pdev->dev, 1043 "version " DRV_VERSION "\n"); 1044 1045 /* no hotplugging support (FIXME) */ 1046 if (!in_module_init) 1047 return -ENODEV; 1048 1049 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1050 if (!hpriv) 1051 return -ENOMEM; 1052 1053 port_info[0] = piix_port_info[ent->driver_data]; 1054 port_info[1] = piix_port_info[ent->driver_data]; 1055 port_info[0].private_data = hpriv; 1056 port_info[1].private_data = hpriv; 1057 1058 port_flags = port_info[0].flags; 1059 1060 if (port_flags & PIIX_FLAG_AHCI) { 1061 u8 tmp; 1062 pci_read_config_byte(pdev, PIIX_SCC, &tmp); 1063 if (tmp == PIIX_AHCI_DEVICE) { 1064 int rc = piix_disable_ahci(pdev); 1065 if (rc) 1066 return rc; 1067 } 1068 } 1069 1070 /* Initialize SATA map */ 1071 if (port_flags & ATA_FLAG_SATA) { 1072 piix_init_sata_map(pdev, port_info, 1073 piix_map_db_table[ent->driver_data]); 1074 piix_init_pcs(pdev, port_info, 1075 piix_map_db_table[ent->driver_data]); 1076 } 1077 1078 /* On ICH5, some BIOSen disable the interrupt using the 1079 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1080 * On ICH6, this bit has the same effect, but only when 1081 * MSI is disabled (and it is disabled, as we don't use 1082 * message-signalled interrupts currently). 1083 */ 1084 if (port_flags & PIIX_FLAG_CHECKINTR) 1085 pci_intx(pdev, 1); 1086 1087 if (piix_check_450nx_errata(pdev)) { 1088 /* This writes into the master table but it does not 1089 really matter for this errata as we will apply it to 1090 all the PIIX devices on the board */ 1091 port_info[0].mwdma_mask = 0; 1092 port_info[0].udma_mask = 0; 1093 port_info[1].mwdma_mask = 0; 1094 port_info[1].udma_mask = 0; 1095 } 1096 return ata_pci_init_one(pdev, ppinfo, 2); 1097 } 1098 1099 static int __init piix_init(void) 1100 { 1101 int rc; 1102 1103 DPRINTK("pci_register_driver\n"); 1104 rc = pci_register_driver(&piix_pci_driver); 1105 if (rc) 1106 return rc; 1107 1108 in_module_init = 0; 1109 1110 DPRINTK("done\n"); 1111 return 0; 1112 } 1113 1114 static void __exit piix_exit(void) 1115 { 1116 pci_unregister_driver(&piix_pci_driver); 1117 } 1118 1119 module_init(piix_init); 1120 module_exit(piix_exit); 1121