1 /* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The orginal Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * 76 * Should have been BIOS fixed: 77 * 450NX: errata #19 - DMA hangs on old 450NX 78 * 450NX: errata #20 - DMA hangs on old 450NX 79 * 450NX: errata #25 - Corruption with DMA on old 450NX 80 * ICH3 errata #15 - IDE deadlock under high load 81 * (BIOS must set dev 31 fn 0 bit 23) 82 * ICH3 errata #18 - Don't use native mode 83 */ 84 85 #include <linux/kernel.h> 86 #include <linux/module.h> 87 #include <linux/pci.h> 88 #include <linux/init.h> 89 #include <linux/blkdev.h> 90 #include <linux/delay.h> 91 #include <linux/device.h> 92 #include <scsi/scsi_host.h> 93 #include <linux/libata.h> 94 95 #define DRV_NAME "ata_piix" 96 #define DRV_VERSION "2.00ac7" 97 98 enum { 99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 100 ICH5_PMR = 0x90, /* port mapping register */ 101 ICH5_PCS = 0x92, /* port control and status */ 102 PIIX_SCC = 0x0A, /* sub-class code register */ 103 104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */ 105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ 106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 107 108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 110 111 /* combined mode. if set, PATA is channel 0. 112 * if clear, PATA is channel 1. 113 */ 114 PIIX_PORT_ENABLED = (1 << 0), 115 PIIX_PORT_PRESENT = (1 << 4), 116 117 PIIX_80C_PRI = (1 << 5) | (1 << 4), 118 PIIX_80C_SEC = (1 << 7) | (1 << 6), 119 120 /* controller IDs */ 121 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */ 122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */ 123 ich_pata_66 = 2, /* ICH up to 66 Mhz */ 124 ich_pata_100 = 3, /* ICH up to UDMA 100 */ 125 ich_pata_133 = 4, /* ICH up to UDMA 133 */ 126 ich5_sata = 5, 127 ich6_sata = 6, 128 ich6_sata_ahci = 7, 129 ich6m_sata_ahci = 8, 130 ich8_sata_ahci = 9, 131 132 /* constants for mapping table */ 133 P0 = 0, /* port 0 */ 134 P1 = 1, /* port 1 */ 135 P2 = 2, /* port 2 */ 136 P3 = 3, /* port 3 */ 137 IDE = -1, /* IDE */ 138 NA = -2, /* not avaliable */ 139 RV = -3, /* reserved */ 140 141 PIIX_AHCI_DEVICE = 6, 142 }; 143 144 struct piix_map_db { 145 const u32 mask; 146 const u16 port_enable; 147 const int map[][4]; 148 }; 149 150 struct piix_host_priv { 151 const int *map; 152 }; 153 154 static int piix_init_one (struct pci_dev *pdev, 155 const struct pci_device_id *ent); 156 static void piix_host_stop(struct ata_host *host); 157 static void piix_pata_error_handler(struct ata_port *ap); 158 static void ich_pata_error_handler(struct ata_port *ap); 159 static void piix_sata_error_handler(struct ata_port *ap); 160 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); 161 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); 162 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev); 163 164 static unsigned int in_module_init = 1; 165 166 static const struct pci_device_id piix_pci_tbl[] = { 167 #ifdef ATA_ENABLE_PATA 168 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 169 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 170 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 171 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 172 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 173 /* Intel PIIX4 */ 174 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 175 /* Intel PIIX4 */ 176 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 177 /* Intel PIIX */ 178 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 179 /* Intel ICH (i810, i815, i840) UDMA 66*/ 180 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 181 /* Intel ICH0 : UDMA 33*/ 182 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 183 /* Intel ICH2M */ 184 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 185 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 186 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 187 /* Intel ICH3M */ 188 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 189 /* Intel ICH3 (E7500/1) UDMA 100 */ 190 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 191 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 192 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 193 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 194 /* Intel ICH5 */ 195 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, 196 /* C-ICH (i810E2) */ 197 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 198 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 199 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 200 /* ICH6 (and 6) (i915) UDMA 100 */ 201 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 202 /* ICH7/7-R (i945, i975) UDMA 100*/ 203 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, 204 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 205 #endif 206 207 /* NOTE: The following PCI ids must be kept in sync with the 208 * list in drivers/pci/quirks.c. 209 */ 210 211 /* 82801EB (ICH5) */ 212 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 213 /* 82801EB (ICH5) */ 214 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 215 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 216 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 217 /* 6300ESB pretending RAID */ 218 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 219 /* 82801FB/FW (ICH6/ICH6W) */ 220 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 221 /* 82801FR/FRW (ICH6R/ICH6RW) */ 222 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 223 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ 224 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 225 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 226 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 227 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 228 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 229 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 230 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 231 /* SATA Controller 1 IDE (ICH8) */ 232 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 233 /* SATA Controller 2 IDE (ICH8) */ 234 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 235 /* Mobile SATA Controller IDE (ICH8M) */ 236 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 237 /* SATA Controller IDE (ICH9) */ 238 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 239 /* SATA Controller IDE (ICH9) */ 240 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 241 /* SATA Controller IDE (ICH9) */ 242 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 243 /* SATA Controller IDE (ICH9M) */ 244 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 245 /* SATA Controller IDE (ICH9M) */ 246 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 247 /* SATA Controller IDE (ICH9M) */ 248 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 249 250 { } /* terminate list */ 251 }; 252 253 static struct pci_driver piix_pci_driver = { 254 .name = DRV_NAME, 255 .id_table = piix_pci_tbl, 256 .probe = piix_init_one, 257 .remove = ata_pci_remove_one, 258 .suspend = ata_pci_device_suspend, 259 .resume = ata_pci_device_resume, 260 }; 261 262 static struct scsi_host_template piix_sht = { 263 .module = THIS_MODULE, 264 .name = DRV_NAME, 265 .ioctl = ata_scsi_ioctl, 266 .queuecommand = ata_scsi_queuecmd, 267 .can_queue = ATA_DEF_QUEUE, 268 .this_id = ATA_SHT_THIS_ID, 269 .sg_tablesize = LIBATA_MAX_PRD, 270 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 271 .emulated = ATA_SHT_EMULATED, 272 .use_clustering = ATA_SHT_USE_CLUSTERING, 273 .proc_name = DRV_NAME, 274 .dma_boundary = ATA_DMA_BOUNDARY, 275 .slave_configure = ata_scsi_slave_config, 276 .slave_destroy = ata_scsi_slave_destroy, 277 .bios_param = ata_std_bios_param, 278 .resume = ata_scsi_device_resume, 279 .suspend = ata_scsi_device_suspend, 280 }; 281 282 static const struct ata_port_operations piix_pata_ops = { 283 .port_disable = ata_port_disable, 284 .set_piomode = piix_set_piomode, 285 .set_dmamode = piix_set_dmamode, 286 .mode_filter = ata_pci_default_filter, 287 288 .tf_load = ata_tf_load, 289 .tf_read = ata_tf_read, 290 .check_status = ata_check_status, 291 .exec_command = ata_exec_command, 292 .dev_select = ata_std_dev_select, 293 294 .bmdma_setup = ata_bmdma_setup, 295 .bmdma_start = ata_bmdma_start, 296 .bmdma_stop = ata_bmdma_stop, 297 .bmdma_status = ata_bmdma_status, 298 .qc_prep = ata_qc_prep, 299 .qc_issue = ata_qc_issue_prot, 300 .data_xfer = ata_pio_data_xfer, 301 302 .freeze = ata_bmdma_freeze, 303 .thaw = ata_bmdma_thaw, 304 .error_handler = piix_pata_error_handler, 305 .post_internal_cmd = ata_bmdma_post_internal_cmd, 306 307 .irq_handler = ata_interrupt, 308 .irq_clear = ata_bmdma_irq_clear, 309 310 .port_start = ata_port_start, 311 .port_stop = ata_port_stop, 312 .host_stop = piix_host_stop, 313 }; 314 315 static const struct ata_port_operations ich_pata_ops = { 316 .port_disable = ata_port_disable, 317 .set_piomode = piix_set_piomode, 318 .set_dmamode = ich_set_dmamode, 319 .mode_filter = ata_pci_default_filter, 320 321 .tf_load = ata_tf_load, 322 .tf_read = ata_tf_read, 323 .check_status = ata_check_status, 324 .exec_command = ata_exec_command, 325 .dev_select = ata_std_dev_select, 326 327 .bmdma_setup = ata_bmdma_setup, 328 .bmdma_start = ata_bmdma_start, 329 .bmdma_stop = ata_bmdma_stop, 330 .bmdma_status = ata_bmdma_status, 331 .qc_prep = ata_qc_prep, 332 .qc_issue = ata_qc_issue_prot, 333 .data_xfer = ata_pio_data_xfer, 334 335 .freeze = ata_bmdma_freeze, 336 .thaw = ata_bmdma_thaw, 337 .error_handler = ich_pata_error_handler, 338 .post_internal_cmd = ata_bmdma_post_internal_cmd, 339 340 .irq_handler = ata_interrupt, 341 .irq_clear = ata_bmdma_irq_clear, 342 343 .port_start = ata_port_start, 344 .port_stop = ata_port_stop, 345 .host_stop = piix_host_stop, 346 }; 347 348 static const struct ata_port_operations piix_sata_ops = { 349 .port_disable = ata_port_disable, 350 351 .tf_load = ata_tf_load, 352 .tf_read = ata_tf_read, 353 .check_status = ata_check_status, 354 .exec_command = ata_exec_command, 355 .dev_select = ata_std_dev_select, 356 357 .bmdma_setup = ata_bmdma_setup, 358 .bmdma_start = ata_bmdma_start, 359 .bmdma_stop = ata_bmdma_stop, 360 .bmdma_status = ata_bmdma_status, 361 .qc_prep = ata_qc_prep, 362 .qc_issue = ata_qc_issue_prot, 363 .data_xfer = ata_pio_data_xfer, 364 365 .freeze = ata_bmdma_freeze, 366 .thaw = ata_bmdma_thaw, 367 .error_handler = piix_sata_error_handler, 368 .post_internal_cmd = ata_bmdma_post_internal_cmd, 369 370 .irq_handler = ata_interrupt, 371 .irq_clear = ata_bmdma_irq_clear, 372 373 .port_start = ata_port_start, 374 .port_stop = ata_port_stop, 375 .host_stop = piix_host_stop, 376 }; 377 378 static const struct piix_map_db ich5_map_db = { 379 .mask = 0x7, 380 .port_enable = 0x3, 381 .map = { 382 /* PM PS SM SS MAP */ 383 { P0, NA, P1, NA }, /* 000b */ 384 { P1, NA, P0, NA }, /* 001b */ 385 { RV, RV, RV, RV }, 386 { RV, RV, RV, RV }, 387 { P0, P1, IDE, IDE }, /* 100b */ 388 { P1, P0, IDE, IDE }, /* 101b */ 389 { IDE, IDE, P0, P1 }, /* 110b */ 390 { IDE, IDE, P1, P0 }, /* 111b */ 391 }, 392 }; 393 394 static const struct piix_map_db ich6_map_db = { 395 .mask = 0x3, 396 .port_enable = 0xf, 397 .map = { 398 /* PM PS SM SS MAP */ 399 { P0, P2, P1, P3 }, /* 00b */ 400 { IDE, IDE, P1, P3 }, /* 01b */ 401 { P0, P2, IDE, IDE }, /* 10b */ 402 { RV, RV, RV, RV }, 403 }, 404 }; 405 406 static const struct piix_map_db ich6m_map_db = { 407 .mask = 0x3, 408 .port_enable = 0x5, 409 410 /* Map 01b isn't specified in the doc but some notebooks use 411 * it anyway. MAP 01b have been spotted on both ICH6M and 412 * ICH7M. 413 */ 414 .map = { 415 /* PM PS SM SS MAP */ 416 { P0, P2, RV, RV }, /* 00b */ 417 { IDE, IDE, P1, P3 }, /* 01b */ 418 { P0, P2, IDE, IDE }, /* 10b */ 419 { RV, RV, RV, RV }, 420 }, 421 }; 422 423 static const struct piix_map_db ich8_map_db = { 424 .mask = 0x3, 425 .port_enable = 0x3, 426 .map = { 427 /* PM PS SM SS MAP */ 428 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 429 { RV, RV, RV, RV }, 430 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */ 431 { RV, RV, RV, RV }, 432 }, 433 }; 434 435 static const struct piix_map_db *piix_map_db_table[] = { 436 [ich5_sata] = &ich5_map_db, 437 [ich6_sata] = &ich6_map_db, 438 [ich6_sata_ahci] = &ich6_map_db, 439 [ich6m_sata_ahci] = &ich6m_map_db, 440 [ich8_sata_ahci] = &ich8_map_db, 441 }; 442 443 static struct ata_port_info piix_port_info[] = { 444 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */ 445 { 446 .sht = &piix_sht, 447 .flags = PIIX_PATA_FLAGS, 448 .pio_mask = 0x1f, /* pio0-4 */ 449 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 450 .udma_mask = ATA_UDMA_MASK_40C, 451 .port_ops = &piix_pata_ops, 452 }, 453 454 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/ 455 { 456 .sht = &piix_sht, 457 .flags = PIIX_PATA_FLAGS, 458 .pio_mask = 0x1f, /* pio 0-4 */ 459 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 460 .udma_mask = ATA_UDMA2, /* UDMA33 */ 461 .port_ops = &ich_pata_ops, 462 }, 463 /* ich_pata_66: 2 ICH controllers up to 66MHz */ 464 { 465 .sht = &piix_sht, 466 .flags = PIIX_PATA_FLAGS, 467 .pio_mask = 0x1f, /* pio 0-4 */ 468 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ 469 .udma_mask = ATA_UDMA4, 470 .port_ops = &ich_pata_ops, 471 }, 472 473 /* ich_pata_100: 3 */ 474 { 475 .sht = &piix_sht, 476 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 477 .pio_mask = 0x1f, /* pio0-4 */ 478 .mwdma_mask = 0x06, /* mwdma1-2 */ 479 .udma_mask = ATA_UDMA5, /* udma0-5 */ 480 .port_ops = &ich_pata_ops, 481 }, 482 483 /* ich_pata_133: 4 ICH with full UDMA6 */ 484 { 485 .sht = &piix_sht, 486 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 487 .pio_mask = 0x1f, /* pio 0-4 */ 488 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 489 .udma_mask = ATA_UDMA6, /* UDMA133 */ 490 .port_ops = &ich_pata_ops, 491 }, 492 493 /* ich5_sata: 5 */ 494 { 495 .sht = &piix_sht, 496 .flags = PIIX_SATA_FLAGS, 497 .pio_mask = 0x1f, /* pio0-4 */ 498 .mwdma_mask = 0x07, /* mwdma0-2 */ 499 .udma_mask = 0x7f, /* udma0-6 */ 500 .port_ops = &piix_sata_ops, 501 }, 502 503 /* ich6_sata: 6 */ 504 { 505 .sht = &piix_sht, 506 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, 507 .pio_mask = 0x1f, /* pio0-4 */ 508 .mwdma_mask = 0x07, /* mwdma0-2 */ 509 .udma_mask = 0x7f, /* udma0-6 */ 510 .port_ops = &piix_sata_ops, 511 }, 512 513 /* ich6_sata_ahci: 7 */ 514 { 515 .sht = &piix_sht, 516 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 517 PIIX_FLAG_AHCI, 518 .pio_mask = 0x1f, /* pio0-4 */ 519 .mwdma_mask = 0x07, /* mwdma0-2 */ 520 .udma_mask = 0x7f, /* udma0-6 */ 521 .port_ops = &piix_sata_ops, 522 }, 523 524 /* ich6m_sata_ahci: 8 */ 525 { 526 .sht = &piix_sht, 527 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 528 PIIX_FLAG_AHCI, 529 .pio_mask = 0x1f, /* pio0-4 */ 530 .mwdma_mask = 0x07, /* mwdma0-2 */ 531 .udma_mask = 0x7f, /* udma0-6 */ 532 .port_ops = &piix_sata_ops, 533 }, 534 535 /* ich8_sata_ahci: 9 */ 536 { 537 .sht = &piix_sht, 538 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 539 PIIX_FLAG_AHCI, 540 .pio_mask = 0x1f, /* pio0-4 */ 541 .mwdma_mask = 0x07, /* mwdma0-2 */ 542 .udma_mask = 0x7f, /* udma0-6 */ 543 .port_ops = &piix_sata_ops, 544 }, 545 546 }; 547 548 static struct pci_bits piix_enable_bits[] = { 549 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 550 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 551 }; 552 553 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 554 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 555 MODULE_LICENSE("GPL"); 556 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 557 MODULE_VERSION(DRV_VERSION); 558 559 struct ich_laptop { 560 u16 device; 561 u16 subvendor; 562 u16 subdevice; 563 }; 564 565 /* 566 * List of laptops that use short cables rather than 80 wire 567 */ 568 569 static const struct ich_laptop ich_laptop[] = { 570 /* devid, subvendor, subdev */ 571 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 572 /* end marker */ 573 { 0, } 574 }; 575 576 /** 577 * piix_pata_cbl_detect - Probe host controller cable detect info 578 * @ap: Port for which cable detect info is desired 579 * 580 * Read 80c cable indicator from ATA PCI device's PCI config 581 * register. This register is normally set by firmware (BIOS). 582 * 583 * LOCKING: 584 * None (inherited from caller). 585 */ 586 587 static void ich_pata_cbl_detect(struct ata_port *ap) 588 { 589 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 590 const struct ich_laptop *lap = &ich_laptop[0]; 591 u8 tmp, mask; 592 593 /* no 80c support in host controller? */ 594 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0) 595 goto cbl40; 596 597 /* Check for specials - Acer Aspire 5602WLMi */ 598 while (lap->device) { 599 if (lap->device == pdev->device && 600 lap->subvendor == pdev->subsystem_vendor && 601 lap->subdevice == pdev->subsystem_device) { 602 ap->cbl = ATA_CBL_PATA40_SHORT; 603 return; 604 } 605 lap++; 606 } 607 608 /* check BIOS cable detect results */ 609 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 610 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); 611 if ((tmp & mask) == 0) 612 goto cbl40; 613 614 ap->cbl = ATA_CBL_PATA80; 615 return; 616 617 cbl40: 618 ap->cbl = ATA_CBL_PATA40; 619 } 620 621 /** 622 * piix_pata_prereset - prereset for PATA host controller 623 * @ap: Target port 624 * 625 * 626 * LOCKING: 627 * None (inherited from caller). 628 */ 629 static int piix_pata_prereset(struct ata_port *ap) 630 { 631 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 632 633 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 634 return -ENOENT; 635 636 ap->cbl = ATA_CBL_PATA40; 637 return ata_std_prereset(ap); 638 } 639 640 static void piix_pata_error_handler(struct ata_port *ap) 641 { 642 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, 643 ata_std_postreset); 644 } 645 646 647 /** 648 * ich_pata_prereset - prereset for PATA host controller 649 * @ap: Target port 650 * 651 * 652 * LOCKING: 653 * None (inherited from caller). 654 */ 655 static int ich_pata_prereset(struct ata_port *ap) 656 { 657 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 658 659 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) { 660 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n"); 661 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK; 662 return 0; 663 } 664 665 ich_pata_cbl_detect(ap); 666 667 return ata_std_prereset(ap); 668 } 669 670 static void ich_pata_error_handler(struct ata_port *ap) 671 { 672 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL, 673 ata_std_postreset); 674 } 675 676 static void piix_sata_error_handler(struct ata_port *ap) 677 { 678 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL, 679 ata_std_postreset); 680 } 681 682 /** 683 * piix_set_piomode - Initialize host controller PATA PIO timings 684 * @ap: Port whose timings we are configuring 685 * @adev: um 686 * 687 * Set PIO mode for device, in host controller PCI config space. 688 * 689 * LOCKING: 690 * None (inherited from caller). 691 */ 692 693 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) 694 { 695 unsigned int pio = adev->pio_mode - XFER_PIO_0; 696 struct pci_dev *dev = to_pci_dev(ap->host->dev); 697 unsigned int is_slave = (adev->devno != 0); 698 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 699 unsigned int slave_port = 0x44; 700 u16 master_data; 701 u8 slave_data; 702 u8 udma_enable; 703 int control = 0; 704 705 /* 706 * See Intel Document 298600-004 for the timing programing rules 707 * for ICH controllers. 708 */ 709 710 static const /* ISP RTC */ 711 u8 timings[][2] = { { 0, 0 }, 712 { 0, 0 }, 713 { 1, 0 }, 714 { 2, 1 }, 715 { 2, 3 }, }; 716 717 if (pio >= 2) 718 control |= 1; /* TIME1 enable */ 719 if (ata_pio_need_iordy(adev)) 720 control |= 2; /* IE enable */ 721 722 /* Intel specifies that the PPE functionality is for disk only */ 723 if (adev->class == ATA_DEV_ATA) 724 control |= 4; /* PPE enable */ 725 726 pci_read_config_word(dev, master_port, &master_data); 727 if (is_slave) { 728 /* Enable SITRE (seperate slave timing register) */ 729 master_data |= 0x4000; 730 /* enable PPE1, IE1 and TIME1 as needed */ 731 master_data |= (control << 4); 732 pci_read_config_byte(dev, slave_port, &slave_data); 733 slave_data &= (ap->port_no ? 0x0f : 0xf0); 734 /* Load the timing nibble for this slave */ 735 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 736 } else { 737 /* Master keeps the bits in a different format */ 738 master_data &= 0xccf8; 739 /* Enable PPE, IE and TIME as appropriate */ 740 master_data |= control; 741 master_data |= 742 (timings[pio][0] << 12) | 743 (timings[pio][1] << 8); 744 } 745 pci_write_config_word(dev, master_port, master_data); 746 if (is_slave) 747 pci_write_config_byte(dev, slave_port, slave_data); 748 749 /* Ensure the UDMA bit is off - it will be turned back on if 750 UDMA is selected */ 751 752 if (ap->udma_mask) { 753 pci_read_config_byte(dev, 0x48, &udma_enable); 754 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 755 pci_write_config_byte(dev, 0x48, udma_enable); 756 } 757 } 758 759 /** 760 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 761 * @ap: Port whose timings we are configuring 762 * @adev: Drive in question 763 * @udma: udma mode, 0 - 6 764 * @isich: set if the chip is an ICH device 765 * 766 * Set UDMA mode for device, in host controller PCI config space. 767 * 768 * LOCKING: 769 * None (inherited from caller). 770 */ 771 772 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich) 773 { 774 struct pci_dev *dev = to_pci_dev(ap->host->dev); 775 u8 master_port = ap->port_no ? 0x42 : 0x40; 776 u16 master_data; 777 u8 speed = adev->dma_mode; 778 int devid = adev->devno + 2 * ap->port_no; 779 u8 udma_enable; 780 781 static const /* ISP RTC */ 782 u8 timings[][2] = { { 0, 0 }, 783 { 0, 0 }, 784 { 1, 0 }, 785 { 2, 1 }, 786 { 2, 3 }, }; 787 788 pci_read_config_word(dev, master_port, &master_data); 789 pci_read_config_byte(dev, 0x48, &udma_enable); 790 791 if (speed >= XFER_UDMA_0) { 792 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 793 u16 udma_timing; 794 u16 ideconf; 795 int u_clock, u_speed; 796 797 /* 798 * UDMA is handled by a combination of clock switching and 799 * selection of dividers 800 * 801 * Handy rule: Odd modes are UDMATIMx 01, even are 02 802 * except UDMA0 which is 00 803 */ 804 u_speed = min(2 - (udma & 1), udma); 805 if (udma == 5) 806 u_clock = 0x1000; /* 100Mhz */ 807 else if (udma > 2) 808 u_clock = 1; /* 66Mhz */ 809 else 810 u_clock = 0; /* 33Mhz */ 811 812 udma_enable |= (1 << devid); 813 814 /* Load the CT/RP selection */ 815 pci_read_config_word(dev, 0x4A, &udma_timing); 816 udma_timing &= ~(3 << (4 * devid)); 817 udma_timing |= u_speed << (4 * devid); 818 pci_write_config_word(dev, 0x4A, udma_timing); 819 820 if (isich) { 821 /* Select a 33/66/100Mhz clock */ 822 pci_read_config_word(dev, 0x54, &ideconf); 823 ideconf &= ~(0x1001 << devid); 824 ideconf |= u_clock << devid; 825 /* For ICH or later we should set bit 10 for better 826 performance (WR_PingPong_En) */ 827 pci_write_config_word(dev, 0x54, ideconf); 828 } 829 } else { 830 /* 831 * MWDMA is driven by the PIO timings. We must also enable 832 * IORDY unconditionally along with TIME1. PPE has already 833 * been set when the PIO timing was set. 834 */ 835 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 836 unsigned int control; 837 u8 slave_data; 838 const unsigned int needed_pio[3] = { 839 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 840 }; 841 int pio = needed_pio[mwdma] - XFER_PIO_0; 842 843 control = 3; /* IORDY|TIME1 */ 844 845 /* If the drive MWDMA is faster than it can do PIO then 846 we must force PIO into PIO0 */ 847 848 if (adev->pio_mode < needed_pio[mwdma]) 849 /* Enable DMA timing only */ 850 control |= 8; /* PIO cycles in PIO0 */ 851 852 if (adev->devno) { /* Slave */ 853 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 854 master_data |= control << 4; 855 pci_read_config_byte(dev, 0x44, &slave_data); 856 slave_data &= (0x0F + 0xE1 * ap->port_no); 857 /* Load the matching timing */ 858 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 859 pci_write_config_byte(dev, 0x44, slave_data); 860 } else { /* Master */ 861 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 862 and master timing bits */ 863 master_data |= control; 864 master_data |= 865 (timings[pio][0] << 12) | 866 (timings[pio][1] << 8); 867 } 868 udma_enable &= ~(1 << devid); 869 pci_write_config_word(dev, master_port, master_data); 870 } 871 /* Don't scribble on 0x48 if the controller does not support UDMA */ 872 if (ap->udma_mask) 873 pci_write_config_byte(dev, 0x48, udma_enable); 874 } 875 876 /** 877 * piix_set_dmamode - Initialize host controller PATA DMA timings 878 * @ap: Port whose timings we are configuring 879 * @adev: um 880 * 881 * Set MW/UDMA mode for device, in host controller PCI config space. 882 * 883 * LOCKING: 884 * None (inherited from caller). 885 */ 886 887 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) 888 { 889 do_pata_set_dmamode(ap, adev, 0); 890 } 891 892 /** 893 * ich_set_dmamode - Initialize host controller PATA DMA timings 894 * @ap: Port whose timings we are configuring 895 * @adev: um 896 * 897 * Set MW/UDMA mode for device, in host controller PCI config space. 898 * 899 * LOCKING: 900 * None (inherited from caller). 901 */ 902 903 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev) 904 { 905 do_pata_set_dmamode(ap, adev, 1); 906 } 907 908 #define AHCI_PCI_BAR 5 909 #define AHCI_GLOBAL_CTL 0x04 910 #define AHCI_ENABLE (1 << 31) 911 static int piix_disable_ahci(struct pci_dev *pdev) 912 { 913 void __iomem *mmio; 914 u32 tmp; 915 int rc = 0; 916 917 /* BUG: pci_enable_device has not yet been called. This 918 * works because this device is usually set up by BIOS. 919 */ 920 921 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 922 !pci_resource_len(pdev, AHCI_PCI_BAR)) 923 return 0; 924 925 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 926 if (!mmio) 927 return -ENOMEM; 928 929 tmp = readl(mmio + AHCI_GLOBAL_CTL); 930 if (tmp & AHCI_ENABLE) { 931 tmp &= ~AHCI_ENABLE; 932 writel(tmp, mmio + AHCI_GLOBAL_CTL); 933 934 tmp = readl(mmio + AHCI_GLOBAL_CTL); 935 if (tmp & AHCI_ENABLE) 936 rc = -EIO; 937 } 938 939 pci_iounmap(pdev, mmio); 940 return rc; 941 } 942 943 /** 944 * piix_check_450nx_errata - Check for problem 450NX setup 945 * @ata_dev: the PCI device to check 946 * 947 * Check for the present of 450NX errata #19 and errata #25. If 948 * they are found return an error code so we can turn off DMA 949 */ 950 951 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 952 { 953 struct pci_dev *pdev = NULL; 954 u16 cfg; 955 u8 rev; 956 int no_piix_dma = 0; 957 958 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) 959 { 960 /* Look for 450NX PXB. Check for problem configurations 961 A PCI quirk checks bit 6 already */ 962 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 963 pci_read_config_word(pdev, 0x41, &cfg); 964 /* Only on the original revision: IDE DMA can hang */ 965 if (rev == 0x00) 966 no_piix_dma = 1; 967 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 968 else if (cfg & (1<<14) && rev < 5) 969 no_piix_dma = 2; 970 } 971 if (no_piix_dma) 972 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 973 if (no_piix_dma == 2) 974 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 975 return no_piix_dma; 976 } 977 978 static void __devinit piix_init_pcs(struct pci_dev *pdev, 979 struct ata_port_info *pinfo, 980 const struct piix_map_db *map_db) 981 { 982 u16 pcs, new_pcs; 983 984 pci_read_config_word(pdev, ICH5_PCS, &pcs); 985 986 new_pcs = pcs | map_db->port_enable; 987 988 if (new_pcs != pcs) { 989 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 990 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 991 msleep(150); 992 } 993 } 994 995 static void __devinit piix_init_sata_map(struct pci_dev *pdev, 996 struct ata_port_info *pinfo, 997 const struct piix_map_db *map_db) 998 { 999 struct piix_host_priv *hpriv = pinfo[0].private_data; 1000 const unsigned int *map; 1001 int i, invalid_map = 0; 1002 u8 map_value; 1003 1004 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1005 1006 map = map_db->map[map_value & map_db->mask]; 1007 1008 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 1009 for (i = 0; i < 4; i++) { 1010 switch (map[i]) { 1011 case RV: 1012 invalid_map = 1; 1013 printk(" XX"); 1014 break; 1015 1016 case NA: 1017 printk(" --"); 1018 break; 1019 1020 case IDE: 1021 WARN_ON((i & 1) || map[i + 1] != IDE); 1022 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1023 pinfo[i / 2].private_data = hpriv; 1024 i++; 1025 printk(" IDE IDE"); 1026 break; 1027 1028 default: 1029 printk(" P%d", map[i]); 1030 if (i & 1) 1031 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1032 break; 1033 } 1034 } 1035 printk(" ]\n"); 1036 1037 if (invalid_map) 1038 dev_printk(KERN_ERR, &pdev->dev, 1039 "invalid MAP value %u\n", map_value); 1040 1041 hpriv->map = map; 1042 } 1043 1044 /** 1045 * piix_init_one - Register PIIX ATA PCI device with kernel services 1046 * @pdev: PCI device to register 1047 * @ent: Entry in piix_pci_tbl matching with @pdev 1048 * 1049 * Called from kernel PCI layer. We probe for combined mode (sigh), 1050 * and then hand over control to libata, for it to do the rest. 1051 * 1052 * LOCKING: 1053 * Inherited from PCI layer (may sleep). 1054 * 1055 * RETURNS: 1056 * Zero on success, or -ERRNO value. 1057 */ 1058 1059 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1060 { 1061 static int printed_version; 1062 struct ata_port_info port_info[2]; 1063 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] }; 1064 struct piix_host_priv *hpriv; 1065 unsigned long port_flags; 1066 1067 if (!printed_version++) 1068 dev_printk(KERN_DEBUG, &pdev->dev, 1069 "version " DRV_VERSION "\n"); 1070 1071 /* no hotplugging support (FIXME) */ 1072 if (!in_module_init) 1073 return -ENODEV; 1074 1075 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); 1076 if (!hpriv) 1077 return -ENOMEM; 1078 1079 port_info[0] = piix_port_info[ent->driver_data]; 1080 port_info[1] = piix_port_info[ent->driver_data]; 1081 port_info[0].private_data = hpriv; 1082 port_info[1].private_data = hpriv; 1083 1084 port_flags = port_info[0].flags; 1085 1086 if (port_flags & PIIX_FLAG_AHCI) { 1087 u8 tmp; 1088 pci_read_config_byte(pdev, PIIX_SCC, &tmp); 1089 if (tmp == PIIX_AHCI_DEVICE) { 1090 int rc = piix_disable_ahci(pdev); 1091 if (rc) 1092 return rc; 1093 } 1094 } 1095 1096 /* Initialize SATA map */ 1097 if (port_flags & ATA_FLAG_SATA) { 1098 piix_init_sata_map(pdev, port_info, 1099 piix_map_db_table[ent->driver_data]); 1100 piix_init_pcs(pdev, port_info, 1101 piix_map_db_table[ent->driver_data]); 1102 } 1103 1104 /* On ICH5, some BIOSen disable the interrupt using the 1105 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1106 * On ICH6, this bit has the same effect, but only when 1107 * MSI is disabled (and it is disabled, as we don't use 1108 * message-signalled interrupts currently). 1109 */ 1110 if (port_flags & PIIX_FLAG_CHECKINTR) 1111 pci_intx(pdev, 1); 1112 1113 if (piix_check_450nx_errata(pdev)) { 1114 /* This writes into the master table but it does not 1115 really matter for this errata as we will apply it to 1116 all the PIIX devices on the board */ 1117 port_info[0].mwdma_mask = 0; 1118 port_info[0].udma_mask = 0; 1119 port_info[1].mwdma_mask = 0; 1120 port_info[1].udma_mask = 0; 1121 } 1122 return ata_pci_init_one(pdev, ppinfo, 2); 1123 } 1124 1125 static void piix_host_stop(struct ata_host *host) 1126 { 1127 struct piix_host_priv *hpriv = host->private_data; 1128 1129 ata_host_stop(host); 1130 1131 kfree(hpriv); 1132 } 1133 1134 static int __init piix_init(void) 1135 { 1136 int rc; 1137 1138 DPRINTK("pci_register_driver\n"); 1139 rc = pci_register_driver(&piix_pci_driver); 1140 if (rc) 1141 return rc; 1142 1143 in_module_init = 0; 1144 1145 DPRINTK("done\n"); 1146 return 0; 1147 } 1148 1149 static void __exit piix_exit(void) 1150 { 1151 pci_unregister_driver(&piix_pci_driver); 1152 } 1153 1154 module_init(piix_init); 1155 module_exit(piix_exit); 1156