1 /* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The orginal Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * 76 * Should have been BIOS fixed: 77 * 450NX: errata #19 - DMA hangs on old 450NX 78 * 450NX: errata #20 - DMA hangs on old 450NX 79 * 450NX: errata #25 - Corruption with DMA on old 450NX 80 * ICH3 errata #15 - IDE deadlock under high load 81 * (BIOS must set dev 31 fn 0 bit 23) 82 * ICH3 errata #18 - Don't use native mode 83 */ 84 85 #include <linux/kernel.h> 86 #include <linux/module.h> 87 #include <linux/pci.h> 88 #include <linux/init.h> 89 #include <linux/blkdev.h> 90 #include <linux/delay.h> 91 #include <linux/device.h> 92 #include <scsi/scsi_host.h> 93 #include <linux/libata.h> 94 #include <linux/dmi.h> 95 96 #define DRV_NAME "ata_piix" 97 #define DRV_VERSION "2.12" 98 99 enum { 100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 101 ICH5_PMR = 0x90, /* port mapping register */ 102 ICH5_PCS = 0x92, /* port control and status */ 103 PIIX_SCC = 0x0A, /* sub-class code register */ 104 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */ 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ 107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 108 109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 111 112 /* combined mode. if set, PATA is channel 0. 113 * if clear, PATA is channel 1. 114 */ 115 PIIX_PORT_ENABLED = (1 << 0), 116 PIIX_PORT_PRESENT = (1 << 4), 117 118 PIIX_80C_PRI = (1 << 5) | (1 << 4), 119 PIIX_80C_SEC = (1 << 7) | (1 << 6), 120 121 /* controller IDs */ 122 piix_pata_33 = 0, /* PIIX4 at 33Mhz */ 123 ich_pata_33 = 1, /* ICH up to UDMA 33 only */ 124 ich_pata_66 = 2, /* ICH up to 66 Mhz */ 125 ich_pata_100 = 3, /* ICH up to UDMA 100 */ 126 ich5_sata = 5, 127 ich6_sata = 6, 128 ich6_sata_ahci = 7, 129 ich6m_sata_ahci = 8, 130 ich8_sata_ahci = 9, 131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ 132 tolapai_sata_ahci = 11, 133 ich9_2port_sata = 12, 134 135 /* constants for mapping table */ 136 P0 = 0, /* port 0 */ 137 P1 = 1, /* port 1 */ 138 P2 = 2, /* port 2 */ 139 P3 = 3, /* port 3 */ 140 IDE = -1, /* IDE */ 141 NA = -2, /* not avaliable */ 142 RV = -3, /* reserved */ 143 144 PIIX_AHCI_DEVICE = 6, 145 146 /* host->flags bits */ 147 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 148 }; 149 150 struct piix_map_db { 151 const u32 mask; 152 const u16 port_enable; 153 const int map[][4]; 154 }; 155 156 struct piix_host_priv { 157 const int *map; 158 }; 159 160 static int piix_init_one(struct pci_dev *pdev, 161 const struct pci_device_id *ent); 162 static void piix_pata_error_handler(struct ata_port *ap); 163 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); 164 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); 165 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); 166 static int ich_pata_cable_detect(struct ata_port *ap); 167 #ifdef CONFIG_PM 168 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 169 static int piix_pci_device_resume(struct pci_dev *pdev); 170 #endif 171 172 static unsigned int in_module_init = 1; 173 174 static const struct pci_device_id piix_pci_tbl[] = { 175 /* Intel PIIX3 for the 430HX etc */ 176 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 177 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 178 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 179 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 180 /* Intel PIIX4 */ 181 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 182 /* Intel PIIX4 */ 183 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 184 /* Intel PIIX */ 185 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 186 /* Intel ICH (i810, i815, i840) UDMA 66*/ 187 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 188 /* Intel ICH0 : UDMA 33*/ 189 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 190 /* Intel ICH2M */ 191 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 192 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 193 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 194 /* Intel ICH3M */ 195 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 196 /* Intel ICH3 (E7500/1) UDMA 100 */ 197 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 198 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 199 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 200 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 201 /* Intel ICH5 */ 202 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 203 /* C-ICH (i810E2) */ 204 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 205 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 206 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 207 /* ICH6 (and 6) (i915) UDMA 100 */ 208 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 209 /* ICH7/7-R (i945, i975) UDMA 100*/ 210 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 211 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 212 /* ICH8 Mobile PATA Controller */ 213 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 214 215 /* NOTE: The following PCI ids must be kept in sync with the 216 * list in drivers/pci/quirks.c. 217 */ 218 219 /* 82801EB (ICH5) */ 220 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 221 /* 82801EB (ICH5) */ 222 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 223 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 224 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 225 /* 6300ESB pretending RAID */ 226 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 227 /* 82801FB/FW (ICH6/ICH6W) */ 228 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 229 /* 82801FR/FRW (ICH6R/ICH6RW) */ 230 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 231 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ 232 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 233 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 234 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 235 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 236 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, 237 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 238 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, 239 /* SATA Controller 1 IDE (ICH8) */ 240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 241 /* SATA Controller 2 IDE (ICH8) */ 242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, 243 /* Mobile SATA Controller IDE (ICH8M) */ 244 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 245 /* SATA Controller IDE (ICH9) */ 246 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 247 /* SATA Controller IDE (ICH9) */ 248 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, 249 /* SATA Controller IDE (ICH9) */ 250 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, 251 /* SATA Controller IDE (ICH9M) */ 252 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, 253 /* SATA Controller IDE (ICH9M) */ 254 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich9_2port_sata }, 255 /* SATA Controller IDE (ICH9M) */ 256 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, 257 /* SATA Controller IDE (Tolapai) */ 258 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci }, 259 260 { } /* terminate list */ 261 }; 262 263 static struct pci_driver piix_pci_driver = { 264 .name = DRV_NAME, 265 .id_table = piix_pci_tbl, 266 .probe = piix_init_one, 267 .remove = ata_pci_remove_one, 268 #ifdef CONFIG_PM 269 .suspend = piix_pci_device_suspend, 270 .resume = piix_pci_device_resume, 271 #endif 272 }; 273 274 static struct scsi_host_template piix_sht = { 275 .module = THIS_MODULE, 276 .name = DRV_NAME, 277 .ioctl = ata_scsi_ioctl, 278 .queuecommand = ata_scsi_queuecmd, 279 .can_queue = ATA_DEF_QUEUE, 280 .this_id = ATA_SHT_THIS_ID, 281 .sg_tablesize = LIBATA_MAX_PRD, 282 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 283 .emulated = ATA_SHT_EMULATED, 284 .use_clustering = ATA_SHT_USE_CLUSTERING, 285 .proc_name = DRV_NAME, 286 .dma_boundary = ATA_DMA_BOUNDARY, 287 .slave_configure = ata_scsi_slave_config, 288 .slave_destroy = ata_scsi_slave_destroy, 289 .bios_param = ata_std_bios_param, 290 }; 291 292 static const struct ata_port_operations piix_pata_ops = { 293 .set_piomode = piix_set_piomode, 294 .set_dmamode = piix_set_dmamode, 295 .mode_filter = ata_pci_default_filter, 296 297 .tf_load = ata_tf_load, 298 .tf_read = ata_tf_read, 299 .check_status = ata_check_status, 300 .exec_command = ata_exec_command, 301 .dev_select = ata_std_dev_select, 302 303 .bmdma_setup = ata_bmdma_setup, 304 .bmdma_start = ata_bmdma_start, 305 .bmdma_stop = ata_bmdma_stop, 306 .bmdma_status = ata_bmdma_status, 307 .qc_prep = ata_qc_prep, 308 .qc_issue = ata_qc_issue_prot, 309 .data_xfer = ata_data_xfer, 310 311 .freeze = ata_bmdma_freeze, 312 .thaw = ata_bmdma_thaw, 313 .error_handler = piix_pata_error_handler, 314 .post_internal_cmd = ata_bmdma_post_internal_cmd, 315 .cable_detect = ata_cable_40wire, 316 317 .irq_handler = ata_interrupt, 318 .irq_clear = ata_bmdma_irq_clear, 319 .irq_on = ata_irq_on, 320 321 .port_start = ata_port_start, 322 }; 323 324 static const struct ata_port_operations ich_pata_ops = { 325 .set_piomode = piix_set_piomode, 326 .set_dmamode = ich_set_dmamode, 327 .mode_filter = ata_pci_default_filter, 328 329 .tf_load = ata_tf_load, 330 .tf_read = ata_tf_read, 331 .check_status = ata_check_status, 332 .exec_command = ata_exec_command, 333 .dev_select = ata_std_dev_select, 334 335 .bmdma_setup = ata_bmdma_setup, 336 .bmdma_start = ata_bmdma_start, 337 .bmdma_stop = ata_bmdma_stop, 338 .bmdma_status = ata_bmdma_status, 339 .qc_prep = ata_qc_prep, 340 .qc_issue = ata_qc_issue_prot, 341 .data_xfer = ata_data_xfer, 342 343 .freeze = ata_bmdma_freeze, 344 .thaw = ata_bmdma_thaw, 345 .error_handler = piix_pata_error_handler, 346 .post_internal_cmd = ata_bmdma_post_internal_cmd, 347 .cable_detect = ich_pata_cable_detect, 348 349 .irq_handler = ata_interrupt, 350 .irq_clear = ata_bmdma_irq_clear, 351 .irq_on = ata_irq_on, 352 353 .port_start = ata_port_start, 354 }; 355 356 static const struct ata_port_operations piix_sata_ops = { 357 .tf_load = ata_tf_load, 358 .tf_read = ata_tf_read, 359 .check_status = ata_check_status, 360 .exec_command = ata_exec_command, 361 .dev_select = ata_std_dev_select, 362 363 .bmdma_setup = ata_bmdma_setup, 364 .bmdma_start = ata_bmdma_start, 365 .bmdma_stop = ata_bmdma_stop, 366 .bmdma_status = ata_bmdma_status, 367 .qc_prep = ata_qc_prep, 368 .qc_issue = ata_qc_issue_prot, 369 .data_xfer = ata_data_xfer, 370 371 .freeze = ata_bmdma_freeze, 372 .thaw = ata_bmdma_thaw, 373 .error_handler = ata_bmdma_error_handler, 374 .post_internal_cmd = ata_bmdma_post_internal_cmd, 375 376 .irq_handler = ata_interrupt, 377 .irq_clear = ata_bmdma_irq_clear, 378 .irq_on = ata_irq_on, 379 380 .port_start = ata_port_start, 381 }; 382 383 static const struct piix_map_db ich5_map_db = { 384 .mask = 0x7, 385 .port_enable = 0x3, 386 .map = { 387 /* PM PS SM SS MAP */ 388 { P0, NA, P1, NA }, /* 000b */ 389 { P1, NA, P0, NA }, /* 001b */ 390 { RV, RV, RV, RV }, 391 { RV, RV, RV, RV }, 392 { P0, P1, IDE, IDE }, /* 100b */ 393 { P1, P0, IDE, IDE }, /* 101b */ 394 { IDE, IDE, P0, P1 }, /* 110b */ 395 { IDE, IDE, P1, P0 }, /* 111b */ 396 }, 397 }; 398 399 static const struct piix_map_db ich6_map_db = { 400 .mask = 0x3, 401 .port_enable = 0xf, 402 .map = { 403 /* PM PS SM SS MAP */ 404 { P0, P2, P1, P3 }, /* 00b */ 405 { IDE, IDE, P1, P3 }, /* 01b */ 406 { P0, P2, IDE, IDE }, /* 10b */ 407 { RV, RV, RV, RV }, 408 }, 409 }; 410 411 static const struct piix_map_db ich6m_map_db = { 412 .mask = 0x3, 413 .port_enable = 0x5, 414 415 /* Map 01b isn't specified in the doc but some notebooks use 416 * it anyway. MAP 01b have been spotted on both ICH6M and 417 * ICH7M. 418 */ 419 .map = { 420 /* PM PS SM SS MAP */ 421 { P0, P2, NA, NA }, /* 00b */ 422 { IDE, IDE, P1, P3 }, /* 01b */ 423 { P0, P2, IDE, IDE }, /* 10b */ 424 { RV, RV, RV, RV }, 425 }, 426 }; 427 428 static const struct piix_map_db ich8_map_db = { 429 .mask = 0x3, 430 .port_enable = 0x3, 431 .map = { 432 /* PM PS SM SS MAP */ 433 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 434 { RV, RV, RV, RV }, 435 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 436 { RV, RV, RV, RV }, 437 }, 438 }; 439 440 static const struct piix_map_db tolapai_map_db = { 441 .mask = 0x3, 442 .port_enable = 0x3, 443 .map = { 444 /* PM PS SM SS MAP */ 445 { P0, NA, P1, NA }, /* 00b */ 446 { RV, RV, RV, RV }, /* 01b */ 447 { RV, RV, RV, RV }, /* 10b */ 448 { RV, RV, RV, RV }, 449 }, 450 }; 451 452 static const struct piix_map_db ich9_2port_map_db = { 453 .mask = 0x3, 454 .port_enable = 0x3, 455 .map = { 456 /* PM PS SM SS MAP */ 457 { P0, NA, P1, NA }, /* 00b */ 458 { RV, RV, RV, RV }, /* 01b */ 459 { RV, RV, RV, RV }, /* 10b */ 460 { RV, RV, RV, RV }, 461 }, 462 }; 463 464 static const struct piix_map_db *piix_map_db_table[] = { 465 [ich5_sata] = &ich5_map_db, 466 [ich6_sata] = &ich6_map_db, 467 [ich6_sata_ahci] = &ich6_map_db, 468 [ich6m_sata_ahci] = &ich6m_map_db, 469 [ich8_sata_ahci] = &ich8_map_db, 470 [tolapai_sata_ahci] = &tolapai_map_db, 471 [ich9_2port_sata] = &ich9_2port_map_db, 472 }; 473 474 static struct ata_port_info piix_port_info[] = { 475 [piix_pata_33] = /* PIIX4 at 33MHz */ 476 { 477 .sht = &piix_sht, 478 .flags = PIIX_PATA_FLAGS, 479 .pio_mask = 0x1f, /* pio0-4 */ 480 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 481 .udma_mask = ATA_UDMA_MASK_40C, 482 .port_ops = &piix_pata_ops, 483 }, 484 485 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 486 { 487 .sht = &piix_sht, 488 .flags = PIIX_PATA_FLAGS, 489 .pio_mask = 0x1f, /* pio 0-4 */ 490 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 491 .udma_mask = ATA_UDMA2, /* UDMA33 */ 492 .port_ops = &ich_pata_ops, 493 }, 494 495 [ich_pata_66] = /* ICH controllers up to 66MHz */ 496 { 497 .sht = &piix_sht, 498 .flags = PIIX_PATA_FLAGS, 499 .pio_mask = 0x1f, /* pio 0-4 */ 500 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ 501 .udma_mask = ATA_UDMA4, 502 .port_ops = &ich_pata_ops, 503 }, 504 505 [ich_pata_100] = 506 { 507 .sht = &piix_sht, 508 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 509 .pio_mask = 0x1f, /* pio0-4 */ 510 .mwdma_mask = 0x06, /* mwdma1-2 */ 511 .udma_mask = ATA_UDMA5, /* udma0-5 */ 512 .port_ops = &ich_pata_ops, 513 }, 514 515 [ich5_sata] = 516 { 517 .sht = &piix_sht, 518 .flags = PIIX_SATA_FLAGS, 519 .pio_mask = 0x1f, /* pio0-4 */ 520 .mwdma_mask = 0x07, /* mwdma0-2 */ 521 .udma_mask = ATA_UDMA6, 522 .port_ops = &piix_sata_ops, 523 }, 524 525 [ich6_sata] = 526 { 527 .sht = &piix_sht, 528 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, 529 .pio_mask = 0x1f, /* pio0-4 */ 530 .mwdma_mask = 0x07, /* mwdma0-2 */ 531 .udma_mask = ATA_UDMA6, 532 .port_ops = &piix_sata_ops, 533 }, 534 535 [ich6_sata_ahci] = 536 { 537 .sht = &piix_sht, 538 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 539 PIIX_FLAG_AHCI, 540 .pio_mask = 0x1f, /* pio0-4 */ 541 .mwdma_mask = 0x07, /* mwdma0-2 */ 542 .udma_mask = ATA_UDMA6, 543 .port_ops = &piix_sata_ops, 544 }, 545 546 [ich6m_sata_ahci] = 547 { 548 .sht = &piix_sht, 549 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 550 PIIX_FLAG_AHCI, 551 .pio_mask = 0x1f, /* pio0-4 */ 552 .mwdma_mask = 0x07, /* mwdma0-2 */ 553 .udma_mask = ATA_UDMA6, 554 .port_ops = &piix_sata_ops, 555 }, 556 557 [ich8_sata_ahci] = 558 { 559 .sht = &piix_sht, 560 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 561 PIIX_FLAG_AHCI, 562 .pio_mask = 0x1f, /* pio0-4 */ 563 .mwdma_mask = 0x07, /* mwdma0-2 */ 564 .udma_mask = ATA_UDMA6, 565 .port_ops = &piix_sata_ops, 566 }, 567 568 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 569 { 570 .sht = &piix_sht, 571 .flags = PIIX_PATA_FLAGS, 572 .pio_mask = 0x1f, /* pio0-4 */ 573 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 574 .port_ops = &piix_pata_ops, 575 }, 576 577 [tolapai_sata_ahci] = 578 { 579 .sht = &piix_sht, 580 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 581 PIIX_FLAG_AHCI, 582 .pio_mask = 0x1f, /* pio0-4 */ 583 .mwdma_mask = 0x07, /* mwdma0-2 */ 584 .udma_mask = ATA_UDMA6, 585 .port_ops = &piix_sata_ops, 586 }, 587 588 [ich9_2port_sata] = 589 { 590 .sht = &piix_sht, 591 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | 592 PIIX_FLAG_AHCI, 593 .pio_mask = 0x1f, /* pio0-4 */ 594 .mwdma_mask = 0x07, /* mwdma0-2 */ 595 .udma_mask = ATA_UDMA6, 596 .port_ops = &piix_sata_ops, 597 }, 598 }; 599 600 static struct pci_bits piix_enable_bits[] = { 601 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 602 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 603 }; 604 605 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 606 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 607 MODULE_LICENSE("GPL"); 608 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 609 MODULE_VERSION(DRV_VERSION); 610 611 struct ich_laptop { 612 u16 device; 613 u16 subvendor; 614 u16 subdevice; 615 }; 616 617 /* 618 * List of laptops that use short cables rather than 80 wire 619 */ 620 621 static const struct ich_laptop ich_laptop[] = { 622 /* devid, subvendor, subdev */ 623 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 624 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 625 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 626 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 627 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 628 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 629 /* end marker */ 630 { 0, } 631 }; 632 633 /** 634 * ich_pata_cable_detect - Probe host controller cable detect info 635 * @ap: Port for which cable detect info is desired 636 * 637 * Read 80c cable indicator from ATA PCI device's PCI config 638 * register. This register is normally set by firmware (BIOS). 639 * 640 * LOCKING: 641 * None (inherited from caller). 642 */ 643 644 static int ich_pata_cable_detect(struct ata_port *ap) 645 { 646 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 647 const struct ich_laptop *lap = &ich_laptop[0]; 648 u8 tmp, mask; 649 650 /* Check for specials - Acer Aspire 5602WLMi */ 651 while (lap->device) { 652 if (lap->device == pdev->device && 653 lap->subvendor == pdev->subsystem_vendor && 654 lap->subdevice == pdev->subsystem_device) 655 return ATA_CBL_PATA40_SHORT; 656 657 lap++; 658 } 659 660 /* check BIOS cable detect results */ 661 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 662 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); 663 if ((tmp & mask) == 0) 664 return ATA_CBL_PATA40; 665 return ATA_CBL_PATA80; 666 } 667 668 /** 669 * piix_pata_prereset - prereset for PATA host controller 670 * @link: Target link 671 * @deadline: deadline jiffies for the operation 672 * 673 * LOCKING: 674 * None (inherited from caller). 675 */ 676 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 677 { 678 struct ata_port *ap = link->ap; 679 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 680 681 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 682 return -ENOENT; 683 return ata_std_prereset(link, deadline); 684 } 685 686 static void piix_pata_error_handler(struct ata_port *ap) 687 { 688 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, 689 ata_std_postreset); 690 } 691 692 /** 693 * piix_set_piomode - Initialize host controller PATA PIO timings 694 * @ap: Port whose timings we are configuring 695 * @adev: um 696 * 697 * Set PIO mode for device, in host controller PCI config space. 698 * 699 * LOCKING: 700 * None (inherited from caller). 701 */ 702 703 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 704 { 705 unsigned int pio = adev->pio_mode - XFER_PIO_0; 706 struct pci_dev *dev = to_pci_dev(ap->host->dev); 707 unsigned int is_slave = (adev->devno != 0); 708 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 709 unsigned int slave_port = 0x44; 710 u16 master_data; 711 u8 slave_data; 712 u8 udma_enable; 713 int control = 0; 714 715 /* 716 * See Intel Document 298600-004 for the timing programing rules 717 * for ICH controllers. 718 */ 719 720 static const /* ISP RTC */ 721 u8 timings[][2] = { { 0, 0 }, 722 { 0, 0 }, 723 { 1, 0 }, 724 { 2, 1 }, 725 { 2, 3 }, }; 726 727 if (pio >= 2) 728 control |= 1; /* TIME1 enable */ 729 if (ata_pio_need_iordy(adev)) 730 control |= 2; /* IE enable */ 731 732 /* Intel specifies that the PPE functionality is for disk only */ 733 if (adev->class == ATA_DEV_ATA) 734 control |= 4; /* PPE enable */ 735 736 /* PIO configuration clears DTE unconditionally. It will be 737 * programmed in set_dmamode which is guaranteed to be called 738 * after set_piomode if any DMA mode is available. 739 */ 740 pci_read_config_word(dev, master_port, &master_data); 741 if (is_slave) { 742 /* clear TIME1|IE1|PPE1|DTE1 */ 743 master_data &= 0xff0f; 744 /* Enable SITRE (seperate slave timing register) */ 745 master_data |= 0x4000; 746 /* enable PPE1, IE1 and TIME1 as needed */ 747 master_data |= (control << 4); 748 pci_read_config_byte(dev, slave_port, &slave_data); 749 slave_data &= (ap->port_no ? 0x0f : 0xf0); 750 /* Load the timing nibble for this slave */ 751 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 752 << (ap->port_no ? 4 : 0); 753 } else { 754 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 755 master_data &= 0xccf0; 756 /* Enable PPE, IE and TIME as appropriate */ 757 master_data |= control; 758 /* load ISP and RCT */ 759 master_data |= 760 (timings[pio][0] << 12) | 761 (timings[pio][1] << 8); 762 } 763 pci_write_config_word(dev, master_port, master_data); 764 if (is_slave) 765 pci_write_config_byte(dev, slave_port, slave_data); 766 767 /* Ensure the UDMA bit is off - it will be turned back on if 768 UDMA is selected */ 769 770 if (ap->udma_mask) { 771 pci_read_config_byte(dev, 0x48, &udma_enable); 772 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 773 pci_write_config_byte(dev, 0x48, udma_enable); 774 } 775 } 776 777 /** 778 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 779 * @ap: Port whose timings we are configuring 780 * @adev: Drive in question 781 * @udma: udma mode, 0 - 6 782 * @isich: set if the chip is an ICH device 783 * 784 * Set UDMA mode for device, in host controller PCI config space. 785 * 786 * LOCKING: 787 * None (inherited from caller). 788 */ 789 790 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 791 { 792 struct pci_dev *dev = to_pci_dev(ap->host->dev); 793 u8 master_port = ap->port_no ? 0x42 : 0x40; 794 u16 master_data; 795 u8 speed = adev->dma_mode; 796 int devid = adev->devno + 2 * ap->port_no; 797 u8 udma_enable = 0; 798 799 static const /* ISP RTC */ 800 u8 timings[][2] = { { 0, 0 }, 801 { 0, 0 }, 802 { 1, 0 }, 803 { 2, 1 }, 804 { 2, 3 }, }; 805 806 pci_read_config_word(dev, master_port, &master_data); 807 if (ap->udma_mask) 808 pci_read_config_byte(dev, 0x48, &udma_enable); 809 810 if (speed >= XFER_UDMA_0) { 811 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 812 u16 udma_timing; 813 u16 ideconf; 814 int u_clock, u_speed; 815 816 /* 817 * UDMA is handled by a combination of clock switching and 818 * selection of dividers 819 * 820 * Handy rule: Odd modes are UDMATIMx 01, even are 02 821 * except UDMA0 which is 00 822 */ 823 u_speed = min(2 - (udma & 1), udma); 824 if (udma == 5) 825 u_clock = 0x1000; /* 100Mhz */ 826 else if (udma > 2) 827 u_clock = 1; /* 66Mhz */ 828 else 829 u_clock = 0; /* 33Mhz */ 830 831 udma_enable |= (1 << devid); 832 833 /* Load the CT/RP selection */ 834 pci_read_config_word(dev, 0x4A, &udma_timing); 835 udma_timing &= ~(3 << (4 * devid)); 836 udma_timing |= u_speed << (4 * devid); 837 pci_write_config_word(dev, 0x4A, udma_timing); 838 839 if (isich) { 840 /* Select a 33/66/100Mhz clock */ 841 pci_read_config_word(dev, 0x54, &ideconf); 842 ideconf &= ~(0x1001 << devid); 843 ideconf |= u_clock << devid; 844 /* For ICH or later we should set bit 10 for better 845 performance (WR_PingPong_En) */ 846 pci_write_config_word(dev, 0x54, ideconf); 847 } 848 } else { 849 /* 850 * MWDMA is driven by the PIO timings. We must also enable 851 * IORDY unconditionally along with TIME1. PPE has already 852 * been set when the PIO timing was set. 853 */ 854 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 855 unsigned int control; 856 u8 slave_data; 857 const unsigned int needed_pio[3] = { 858 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 859 }; 860 int pio = needed_pio[mwdma] - XFER_PIO_0; 861 862 control = 3; /* IORDY|TIME1 */ 863 864 /* If the drive MWDMA is faster than it can do PIO then 865 we must force PIO into PIO0 */ 866 867 if (adev->pio_mode < needed_pio[mwdma]) 868 /* Enable DMA timing only */ 869 control |= 8; /* PIO cycles in PIO0 */ 870 871 if (adev->devno) { /* Slave */ 872 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 873 master_data |= control << 4; 874 pci_read_config_byte(dev, 0x44, &slave_data); 875 slave_data &= (ap->port_no ? 0x0f : 0xf0); 876 /* Load the matching timing */ 877 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 878 pci_write_config_byte(dev, 0x44, slave_data); 879 } else { /* Master */ 880 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 881 and master timing bits */ 882 master_data |= control; 883 master_data |= 884 (timings[pio][0] << 12) | 885 (timings[pio][1] << 8); 886 } 887 888 if (ap->udma_mask) { 889 udma_enable &= ~(1 << devid); 890 pci_write_config_word(dev, master_port, master_data); 891 } 892 } 893 /* Don't scribble on 0x48 if the controller does not support UDMA */ 894 if (ap->udma_mask) 895 pci_write_config_byte(dev, 0x48, udma_enable); 896 } 897 898 /** 899 * piix_set_dmamode - Initialize host controller PATA DMA timings 900 * @ap: Port whose timings we are configuring 901 * @adev: um 902 * 903 * Set MW/UDMA mode for device, in host controller PCI config space. 904 * 905 * LOCKING: 906 * None (inherited from caller). 907 */ 908 909 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 910 { 911 do_pata_set_dmamode(ap, adev, 0); 912 } 913 914 /** 915 * ich_set_dmamode - Initialize host controller PATA DMA timings 916 * @ap: Port whose timings we are configuring 917 * @adev: um 918 * 919 * Set MW/UDMA mode for device, in host controller PCI config space. 920 * 921 * LOCKING: 922 * None (inherited from caller). 923 */ 924 925 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 926 { 927 do_pata_set_dmamode(ap, adev, 1); 928 } 929 930 #ifdef CONFIG_PM 931 static int piix_broken_suspend(void) 932 { 933 static const struct dmi_system_id sysids[] = { 934 { 935 .ident = "TECRA M3", 936 .matches = { 937 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 938 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 939 }, 940 }, 941 { 942 .ident = "TECRA M5", 943 .matches = { 944 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 945 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 946 }, 947 }, 948 { 949 .ident = "TECRA M7", 950 .matches = { 951 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 952 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 953 }, 954 }, 955 { 956 .ident = "Satellite U200", 957 .matches = { 958 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 959 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 960 }, 961 }, 962 { 963 .ident = "Satellite U205", 964 .matches = { 965 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 966 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 967 }, 968 }, 969 { 970 .ident = "Portege M500", 971 .matches = { 972 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 973 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 974 }, 975 }, 976 977 { } /* terminate list */ 978 }; 979 static const char *oemstrs[] = { 980 "Tecra M3,", 981 }; 982 int i; 983 984 if (dmi_check_system(sysids)) 985 return 1; 986 987 for (i = 0; i < ARRAY_SIZE(oemstrs); i++) 988 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) 989 return 1; 990 991 return 0; 992 } 993 994 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 995 { 996 struct ata_host *host = dev_get_drvdata(&pdev->dev); 997 unsigned long flags; 998 int rc = 0; 999 1000 rc = ata_host_suspend(host, mesg); 1001 if (rc) 1002 return rc; 1003 1004 /* Some braindamaged ACPI suspend implementations expect the 1005 * controller to be awake on entry; otherwise, it burns cpu 1006 * cycles and power trying to do something to the sleeping 1007 * beauty. 1008 */ 1009 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) { 1010 pci_save_state(pdev); 1011 1012 /* mark its power state as "unknown", since we don't 1013 * know if e.g. the BIOS will change its device state 1014 * when we suspend. 1015 */ 1016 if (pdev->current_state == PCI_D0) 1017 pdev->current_state = PCI_UNKNOWN; 1018 1019 /* tell resume that it's waking up from broken suspend */ 1020 spin_lock_irqsave(&host->lock, flags); 1021 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1022 spin_unlock_irqrestore(&host->lock, flags); 1023 } else 1024 ata_pci_device_do_suspend(pdev, mesg); 1025 1026 return 0; 1027 } 1028 1029 static int piix_pci_device_resume(struct pci_dev *pdev) 1030 { 1031 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1032 unsigned long flags; 1033 int rc; 1034 1035 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1036 spin_lock_irqsave(&host->lock, flags); 1037 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1038 spin_unlock_irqrestore(&host->lock, flags); 1039 1040 pci_set_power_state(pdev, PCI_D0); 1041 pci_restore_state(pdev); 1042 1043 /* PCI device wasn't disabled during suspend. Use 1044 * pci_reenable_device() to avoid affecting the enable 1045 * count. 1046 */ 1047 rc = pci_reenable_device(pdev); 1048 if (rc) 1049 dev_printk(KERN_ERR, &pdev->dev, "failed to enable " 1050 "device after resume (%d)\n", rc); 1051 } else 1052 rc = ata_pci_device_do_resume(pdev); 1053 1054 if (rc == 0) 1055 ata_host_resume(host); 1056 1057 return rc; 1058 } 1059 #endif 1060 1061 #define AHCI_PCI_BAR 5 1062 #define AHCI_GLOBAL_CTL 0x04 1063 #define AHCI_ENABLE (1 << 31) 1064 static int piix_disable_ahci(struct pci_dev *pdev) 1065 { 1066 void __iomem *mmio; 1067 u32 tmp; 1068 int rc = 0; 1069 1070 /* BUG: pci_enable_device has not yet been called. This 1071 * works because this device is usually set up by BIOS. 1072 */ 1073 1074 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1075 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1076 return 0; 1077 1078 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1079 if (!mmio) 1080 return -ENOMEM; 1081 1082 tmp = readl(mmio + AHCI_GLOBAL_CTL); 1083 if (tmp & AHCI_ENABLE) { 1084 tmp &= ~AHCI_ENABLE; 1085 writel(tmp, mmio + AHCI_GLOBAL_CTL); 1086 1087 tmp = readl(mmio + AHCI_GLOBAL_CTL); 1088 if (tmp & AHCI_ENABLE) 1089 rc = -EIO; 1090 } 1091 1092 pci_iounmap(pdev, mmio); 1093 return rc; 1094 } 1095 1096 /** 1097 * piix_check_450nx_errata - Check for problem 450NX setup 1098 * @ata_dev: the PCI device to check 1099 * 1100 * Check for the present of 450NX errata #19 and errata #25. If 1101 * they are found return an error code so we can turn off DMA 1102 */ 1103 1104 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 1105 { 1106 struct pci_dev *pdev = NULL; 1107 u16 cfg; 1108 int no_piix_dma = 0; 1109 1110 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1111 /* Look for 450NX PXB. Check for problem configurations 1112 A PCI quirk checks bit 6 already */ 1113 pci_read_config_word(pdev, 0x41, &cfg); 1114 /* Only on the original revision: IDE DMA can hang */ 1115 if (pdev->revision == 0x00) 1116 no_piix_dma = 1; 1117 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1118 else if (cfg & (1<<14) && pdev->revision < 5) 1119 no_piix_dma = 2; 1120 } 1121 if (no_piix_dma) 1122 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 1123 if (no_piix_dma == 2) 1124 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 1125 return no_piix_dma; 1126 } 1127 1128 static void __devinit piix_init_pcs(struct pci_dev *pdev, 1129 struct ata_port_info *pinfo, 1130 const struct piix_map_db *map_db) 1131 { 1132 u16 pcs, new_pcs; 1133 1134 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1135 1136 new_pcs = pcs | map_db->port_enable; 1137 1138 if (new_pcs != pcs) { 1139 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 1140 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1141 msleep(150); 1142 } 1143 } 1144 1145 static void __devinit piix_init_sata_map(struct pci_dev *pdev, 1146 struct ata_port_info *pinfo, 1147 const struct piix_map_db *map_db) 1148 { 1149 struct piix_host_priv *hpriv = pinfo[0].private_data; 1150 const int *map; 1151 int i, invalid_map = 0; 1152 u8 map_value; 1153 1154 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1155 1156 map = map_db->map[map_value & map_db->mask]; 1157 1158 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 1159 for (i = 0; i < 4; i++) { 1160 switch (map[i]) { 1161 case RV: 1162 invalid_map = 1; 1163 printk(" XX"); 1164 break; 1165 1166 case NA: 1167 printk(" --"); 1168 break; 1169 1170 case IDE: 1171 WARN_ON((i & 1) || map[i + 1] != IDE); 1172 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1173 pinfo[i / 2].private_data = hpriv; 1174 i++; 1175 printk(" IDE IDE"); 1176 break; 1177 1178 default: 1179 printk(" P%d", map[i]); 1180 if (i & 1) 1181 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1182 break; 1183 } 1184 } 1185 printk(" ]\n"); 1186 1187 if (invalid_map) 1188 dev_printk(KERN_ERR, &pdev->dev, 1189 "invalid MAP value %u\n", map_value); 1190 1191 hpriv->map = map; 1192 } 1193 1194 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) 1195 { 1196 static const struct dmi_system_id sysids[] = { 1197 { 1198 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1199 * isn't used to boot the system which 1200 * disables the channel. 1201 */ 1202 .ident = "M570U", 1203 .matches = { 1204 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1205 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1206 }, 1207 }, 1208 1209 { } /* terminate list */ 1210 }; 1211 u32 iocfg; 1212 1213 if (!dmi_check_system(sysids)) 1214 return; 1215 1216 /* The datasheet says that bit 18 is NOOP but certain systems 1217 * seem to use it to disable a channel. Clear the bit on the 1218 * affected systems. 1219 */ 1220 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); 1221 if (iocfg & (1 << 18)) { 1222 dev_printk(KERN_INFO, &pdev->dev, 1223 "applying IOCFG bit18 quirk\n"); 1224 iocfg &= ~(1 << 18); 1225 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); 1226 } 1227 } 1228 1229 /** 1230 * piix_init_one - Register PIIX ATA PCI device with kernel services 1231 * @pdev: PCI device to register 1232 * @ent: Entry in piix_pci_tbl matching with @pdev 1233 * 1234 * Called from kernel PCI layer. We probe for combined mode (sigh), 1235 * and then hand over control to libata, for it to do the rest. 1236 * 1237 * LOCKING: 1238 * Inherited from PCI layer (may sleep). 1239 * 1240 * RETURNS: 1241 * Zero on success, or -ERRNO value. 1242 */ 1243 1244 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1245 { 1246 static int printed_version; 1247 struct device *dev = &pdev->dev; 1248 struct ata_port_info port_info[2]; 1249 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1250 struct piix_host_priv *hpriv; 1251 unsigned long port_flags; 1252 1253 if (!printed_version++) 1254 dev_printk(KERN_DEBUG, &pdev->dev, 1255 "version " DRV_VERSION "\n"); 1256 1257 /* no hotplugging support (FIXME) */ 1258 if (!in_module_init) 1259 return -ENODEV; 1260 1261 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1262 if (!hpriv) 1263 return -ENOMEM; 1264 1265 port_info[0] = piix_port_info[ent->driver_data]; 1266 port_info[1] = piix_port_info[ent->driver_data]; 1267 port_info[0].private_data = hpriv; 1268 port_info[1].private_data = hpriv; 1269 1270 port_flags = port_info[0].flags; 1271 1272 if (port_flags & PIIX_FLAG_AHCI) { 1273 u8 tmp; 1274 pci_read_config_byte(pdev, PIIX_SCC, &tmp); 1275 if (tmp == PIIX_AHCI_DEVICE) { 1276 int rc = piix_disable_ahci(pdev); 1277 if (rc) 1278 return rc; 1279 } 1280 } 1281 1282 /* Initialize SATA map */ 1283 if (port_flags & ATA_FLAG_SATA) { 1284 piix_init_sata_map(pdev, port_info, 1285 piix_map_db_table[ent->driver_data]); 1286 piix_init_pcs(pdev, port_info, 1287 piix_map_db_table[ent->driver_data]); 1288 } 1289 1290 /* apply IOCFG bit18 quirk */ 1291 piix_iocfg_bit18_quirk(pdev); 1292 1293 /* On ICH5, some BIOSen disable the interrupt using the 1294 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1295 * On ICH6, this bit has the same effect, but only when 1296 * MSI is disabled (and it is disabled, as we don't use 1297 * message-signalled interrupts currently). 1298 */ 1299 if (port_flags & PIIX_FLAG_CHECKINTR) 1300 pci_intx(pdev, 1); 1301 1302 if (piix_check_450nx_errata(pdev)) { 1303 /* This writes into the master table but it does not 1304 really matter for this errata as we will apply it to 1305 all the PIIX devices on the board */ 1306 port_info[0].mwdma_mask = 0; 1307 port_info[0].udma_mask = 0; 1308 port_info[1].mwdma_mask = 0; 1309 port_info[1].udma_mask = 0; 1310 } 1311 return ata_pci_init_one(pdev, ppi); 1312 } 1313 1314 static int __init piix_init(void) 1315 { 1316 int rc; 1317 1318 DPRINTK("pci_register_driver\n"); 1319 rc = pci_register_driver(&piix_pci_driver); 1320 if (rc) 1321 return rc; 1322 1323 in_module_init = 0; 1324 1325 DPRINTK("done\n"); 1326 return 0; 1327 } 1328 1329 static void __exit piix_exit(void) 1330 { 1331 pci_unregister_driver(&piix_pci_driver); 1332 } 1333 1334 module_init(piix_init); 1335 module_exit(piix_exit); 1336