1 /* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The orginal Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * 76 * Should have been BIOS fixed: 77 * 450NX: errata #19 - DMA hangs on old 450NX 78 * 450NX: errata #20 - DMA hangs on old 450NX 79 * 450NX: errata #25 - Corruption with DMA on old 450NX 80 * ICH3 errata #15 - IDE deadlock under high load 81 * (BIOS must set dev 31 fn 0 bit 23) 82 * ICH3 errata #18 - Don't use native mode 83 */ 84 85 #include <linux/kernel.h> 86 #include <linux/module.h> 87 #include <linux/pci.h> 88 #include <linux/init.h> 89 #include <linux/blkdev.h> 90 #include <linux/delay.h> 91 #include <linux/device.h> 92 #include <scsi/scsi_host.h> 93 #include <linux/libata.h> 94 #include <linux/dmi.h> 95 96 #define DRV_NAME "ata_piix" 97 #define DRV_VERSION "2.12" 98 99 enum { 100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 101 ICH5_PMR = 0x90, /* port mapping register */ 102 ICH5_PCS = 0x92, /* port control and status */ 103 PIIX_SIDPR_BAR = 5, 104 PIIX_SIDPR_LEN = 16, 105 PIIX_SIDPR_IDX = 0, 106 PIIX_SIDPR_DATA = 4, 107 108 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 109 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 110 111 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 112 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 113 114 PIIX_80C_PRI = (1 << 5) | (1 << 4), 115 PIIX_80C_SEC = (1 << 7) | (1 << 6), 116 117 /* constants for mapping table */ 118 P0 = 0, /* port 0 */ 119 P1 = 1, /* port 1 */ 120 P2 = 2, /* port 2 */ 121 P3 = 3, /* port 3 */ 122 IDE = -1, /* IDE */ 123 NA = -2, /* not avaliable */ 124 RV = -3, /* reserved */ 125 126 PIIX_AHCI_DEVICE = 6, 127 128 /* host->flags bits */ 129 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 130 }; 131 132 enum piix_controller_ids { 133 /* controller IDs */ 134 piix_pata_mwdma, /* PIIX3 MWDMA only */ 135 piix_pata_33, /* PIIX4 at 33Mhz */ 136 ich_pata_33, /* ICH up to UDMA 33 only */ 137 ich_pata_66, /* ICH up to 66 Mhz */ 138 ich_pata_100, /* ICH up to UDMA 100 */ 139 ich5_sata, 140 ich6_sata, 141 ich6m_sata, 142 ich8_sata, 143 ich8_2port_sata, 144 ich8m_apple_sata, /* locks up on second port enable */ 145 tolapai_sata, 146 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 147 }; 148 149 struct piix_map_db { 150 const u32 mask; 151 const u16 port_enable; 152 const int map[][4]; 153 }; 154 155 struct piix_host_priv { 156 const int *map; 157 void __iomem *sidpr; 158 }; 159 160 static int piix_init_one(struct pci_dev *pdev, 161 const struct pci_device_id *ent); 162 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); 163 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); 164 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); 165 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); 166 static int ich_pata_cable_detect(struct ata_port *ap); 167 static u8 piix_vmw_bmdma_status(struct ata_port *ap); 168 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val); 169 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val); 170 #ifdef CONFIG_PM 171 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 172 static int piix_pci_device_resume(struct pci_dev *pdev); 173 #endif 174 175 static unsigned int in_module_init = 1; 176 177 static const struct pci_device_id piix_pci_tbl[] = { 178 /* Intel PIIX3 for the 430HX etc */ 179 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 180 /* VMware ICH4 */ 181 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, 182 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 183 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 184 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 185 /* Intel PIIX4 */ 186 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 187 /* Intel PIIX4 */ 188 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 189 /* Intel PIIX */ 190 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 191 /* Intel ICH (i810, i815, i840) UDMA 66*/ 192 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 193 /* Intel ICH0 : UDMA 33*/ 194 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 195 /* Intel ICH2M */ 196 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 197 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 198 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 199 /* Intel ICH3M */ 200 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 201 /* Intel ICH3 (E7500/1) UDMA 100 */ 202 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 203 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 204 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 205 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 206 /* Intel ICH5 */ 207 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 208 /* C-ICH (i810E2) */ 209 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 210 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 211 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 212 /* ICH6 (and 6) (i915) UDMA 100 */ 213 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 214 /* ICH7/7-R (i945, i975) UDMA 100*/ 215 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 216 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 217 /* ICH8 Mobile PATA Controller */ 218 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 219 220 /* NOTE: The following PCI ids must be kept in sync with the 221 * list in drivers/pci/quirks.c. 222 */ 223 224 /* 82801EB (ICH5) */ 225 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 226 /* 82801EB (ICH5) */ 227 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 228 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 229 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 230 /* 6300ESB pretending RAID */ 231 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 232 /* 82801FB/FW (ICH6/ICH6W) */ 233 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 234 /* 82801FR/FRW (ICH6R/ICH6RW) */ 235 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 236 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). 237 * Attach iff the controller is in IDE mode. */ 238 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 239 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, 240 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 241 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 242 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 243 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, 244 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 245 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 246 /* SATA Controller 1 IDE (ICH8) */ 247 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 248 /* SATA Controller 2 IDE (ICH8) */ 249 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 250 /* Mobile SATA Controller IDE (ICH8M), Apple */ 251 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 252 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, 253 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, 254 /* Mobile SATA Controller IDE (ICH8M) */ 255 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 256 /* SATA Controller IDE (ICH9) */ 257 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 258 /* SATA Controller IDE (ICH9) */ 259 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 260 /* SATA Controller IDE (ICH9) */ 261 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 262 /* SATA Controller IDE (ICH9M) */ 263 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 264 /* SATA Controller IDE (ICH9M) */ 265 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 266 /* SATA Controller IDE (ICH9M) */ 267 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 268 /* SATA Controller IDE (Tolapai) */ 269 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, 270 /* SATA Controller IDE (ICH10) */ 271 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 272 /* SATA Controller IDE (ICH10) */ 273 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 274 /* SATA Controller IDE (ICH10) */ 275 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 276 /* SATA Controller IDE (ICH10) */ 277 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 278 279 { } /* terminate list */ 280 }; 281 282 static struct pci_driver piix_pci_driver = { 283 .name = DRV_NAME, 284 .id_table = piix_pci_tbl, 285 .probe = piix_init_one, 286 .remove = ata_pci_remove_one, 287 #ifdef CONFIG_PM 288 .suspend = piix_pci_device_suspend, 289 .resume = piix_pci_device_resume, 290 #endif 291 }; 292 293 static struct scsi_host_template piix_sht = { 294 ATA_BMDMA_SHT(DRV_NAME), 295 }; 296 297 static struct ata_port_operations piix_pata_ops = { 298 .inherits = &ata_bmdma_port_ops, 299 .cable_detect = ata_cable_40wire, 300 .set_piomode = piix_set_piomode, 301 .set_dmamode = piix_set_dmamode, 302 .prereset = piix_pata_prereset, 303 }; 304 305 static struct ata_port_operations piix_vmw_ops = { 306 .inherits = &piix_pata_ops, 307 .bmdma_status = piix_vmw_bmdma_status, 308 }; 309 310 static struct ata_port_operations ich_pata_ops = { 311 .inherits = &piix_pata_ops, 312 .cable_detect = ich_pata_cable_detect, 313 .set_dmamode = ich_set_dmamode, 314 }; 315 316 static struct ata_port_operations piix_sata_ops = { 317 .inherits = &ata_bmdma_port_ops, 318 }; 319 320 static struct ata_port_operations piix_sidpr_sata_ops = { 321 .inherits = &piix_sata_ops, 322 .hardreset = sata_std_hardreset, 323 .scr_read = piix_sidpr_scr_read, 324 .scr_write = piix_sidpr_scr_write, 325 }; 326 327 static const struct piix_map_db ich5_map_db = { 328 .mask = 0x7, 329 .port_enable = 0x3, 330 .map = { 331 /* PM PS SM SS MAP */ 332 { P0, NA, P1, NA }, /* 000b */ 333 { P1, NA, P0, NA }, /* 001b */ 334 { RV, RV, RV, RV }, 335 { RV, RV, RV, RV }, 336 { P0, P1, IDE, IDE }, /* 100b */ 337 { P1, P0, IDE, IDE }, /* 101b */ 338 { IDE, IDE, P0, P1 }, /* 110b */ 339 { IDE, IDE, P1, P0 }, /* 111b */ 340 }, 341 }; 342 343 static const struct piix_map_db ich6_map_db = { 344 .mask = 0x3, 345 .port_enable = 0xf, 346 .map = { 347 /* PM PS SM SS MAP */ 348 { P0, P2, P1, P3 }, /* 00b */ 349 { IDE, IDE, P1, P3 }, /* 01b */ 350 { P0, P2, IDE, IDE }, /* 10b */ 351 { RV, RV, RV, RV }, 352 }, 353 }; 354 355 static const struct piix_map_db ich6m_map_db = { 356 .mask = 0x3, 357 .port_enable = 0x5, 358 359 /* Map 01b isn't specified in the doc but some notebooks use 360 * it anyway. MAP 01b have been spotted on both ICH6M and 361 * ICH7M. 362 */ 363 .map = { 364 /* PM PS SM SS MAP */ 365 { P0, P2, NA, NA }, /* 00b */ 366 { IDE, IDE, P1, P3 }, /* 01b */ 367 { P0, P2, IDE, IDE }, /* 10b */ 368 { RV, RV, RV, RV }, 369 }, 370 }; 371 372 static const struct piix_map_db ich8_map_db = { 373 .mask = 0x3, 374 .port_enable = 0xf, 375 .map = { 376 /* PM PS SM SS MAP */ 377 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 378 { RV, RV, RV, RV }, 379 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 380 { RV, RV, RV, RV }, 381 }, 382 }; 383 384 static const struct piix_map_db ich8_2port_map_db = { 385 .mask = 0x3, 386 .port_enable = 0x3, 387 .map = { 388 /* PM PS SM SS MAP */ 389 { P0, NA, P1, NA }, /* 00b */ 390 { RV, RV, RV, RV }, /* 01b */ 391 { RV, RV, RV, RV }, /* 10b */ 392 { RV, RV, RV, RV }, 393 }, 394 }; 395 396 static const struct piix_map_db ich8m_apple_map_db = { 397 .mask = 0x3, 398 .port_enable = 0x1, 399 .map = { 400 /* PM PS SM SS MAP */ 401 { P0, NA, NA, NA }, /* 00b */ 402 { RV, RV, RV, RV }, 403 { P0, P2, IDE, IDE }, /* 10b */ 404 { RV, RV, RV, RV }, 405 }, 406 }; 407 408 static const struct piix_map_db tolapai_map_db = { 409 .mask = 0x3, 410 .port_enable = 0x3, 411 .map = { 412 /* PM PS SM SS MAP */ 413 { P0, NA, P1, NA }, /* 00b */ 414 { RV, RV, RV, RV }, /* 01b */ 415 { RV, RV, RV, RV }, /* 10b */ 416 { RV, RV, RV, RV }, 417 }, 418 }; 419 420 static const struct piix_map_db *piix_map_db_table[] = { 421 [ich5_sata] = &ich5_map_db, 422 [ich6_sata] = &ich6_map_db, 423 [ich6m_sata] = &ich6m_map_db, 424 [ich8_sata] = &ich8_map_db, 425 [ich8_2port_sata] = &ich8_2port_map_db, 426 [ich8m_apple_sata] = &ich8m_apple_map_db, 427 [tolapai_sata] = &tolapai_map_db, 428 }; 429 430 static struct ata_port_info piix_port_info[] = { 431 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 432 { 433 .flags = PIIX_PATA_FLAGS, 434 .pio_mask = 0x1f, /* pio0-4 */ 435 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 436 .port_ops = &piix_pata_ops, 437 }, 438 439 [piix_pata_33] = /* PIIX4 at 33MHz */ 440 { 441 .flags = PIIX_PATA_FLAGS, 442 .pio_mask = 0x1f, /* pio0-4 */ 443 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 444 .udma_mask = ATA_UDMA_MASK_40C, 445 .port_ops = &piix_pata_ops, 446 }, 447 448 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 449 { 450 .flags = PIIX_PATA_FLAGS, 451 .pio_mask = 0x1f, /* pio 0-4 */ 452 .mwdma_mask = 0x06, /* Check: maybe 0x07 */ 453 .udma_mask = ATA_UDMA2, /* UDMA33 */ 454 .port_ops = &ich_pata_ops, 455 }, 456 457 [ich_pata_66] = /* ICH controllers up to 66MHz */ 458 { 459 .flags = PIIX_PATA_FLAGS, 460 .pio_mask = 0x1f, /* pio 0-4 */ 461 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ 462 .udma_mask = ATA_UDMA4, 463 .port_ops = &ich_pata_ops, 464 }, 465 466 [ich_pata_100] = 467 { 468 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 469 .pio_mask = 0x1f, /* pio0-4 */ 470 .mwdma_mask = 0x06, /* mwdma1-2 */ 471 .udma_mask = ATA_UDMA5, /* udma0-5 */ 472 .port_ops = &ich_pata_ops, 473 }, 474 475 [ich5_sata] = 476 { 477 .flags = PIIX_SATA_FLAGS, 478 .pio_mask = 0x1f, /* pio0-4 */ 479 .mwdma_mask = 0x07, /* mwdma0-2 */ 480 .udma_mask = ATA_UDMA6, 481 .port_ops = &piix_sata_ops, 482 }, 483 484 [ich6_sata] = 485 { 486 .flags = PIIX_SATA_FLAGS, 487 .pio_mask = 0x1f, /* pio0-4 */ 488 .mwdma_mask = 0x07, /* mwdma0-2 */ 489 .udma_mask = ATA_UDMA6, 490 .port_ops = &piix_sata_ops, 491 }, 492 493 [ich6m_sata] = 494 { 495 .flags = PIIX_SATA_FLAGS, 496 .pio_mask = 0x1f, /* pio0-4 */ 497 .mwdma_mask = 0x07, /* mwdma0-2 */ 498 .udma_mask = ATA_UDMA6, 499 .port_ops = &piix_sata_ops, 500 }, 501 502 [ich8_sata] = 503 { 504 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 505 .pio_mask = 0x1f, /* pio0-4 */ 506 .mwdma_mask = 0x07, /* mwdma0-2 */ 507 .udma_mask = ATA_UDMA6, 508 .port_ops = &piix_sata_ops, 509 }, 510 511 [ich8_2port_sata] = 512 { 513 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 514 .pio_mask = 0x1f, /* pio0-4 */ 515 .mwdma_mask = 0x07, /* mwdma0-2 */ 516 .udma_mask = ATA_UDMA6, 517 .port_ops = &piix_sata_ops, 518 }, 519 520 [tolapai_sata] = 521 { 522 .flags = PIIX_SATA_FLAGS, 523 .pio_mask = 0x1f, /* pio0-4 */ 524 .mwdma_mask = 0x07, /* mwdma0-2 */ 525 .udma_mask = ATA_UDMA6, 526 .port_ops = &piix_sata_ops, 527 }, 528 529 [ich8m_apple_sata] = 530 { 531 .flags = PIIX_SATA_FLAGS, 532 .pio_mask = 0x1f, /* pio0-4 */ 533 .mwdma_mask = 0x07, /* mwdma0-2 */ 534 .udma_mask = ATA_UDMA6, 535 .port_ops = &piix_sata_ops, 536 }, 537 538 [piix_pata_vmw] = 539 { 540 .flags = PIIX_PATA_FLAGS, 541 .pio_mask = 0x1f, /* pio0-4 */ 542 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 543 .udma_mask = ATA_UDMA_MASK_40C, 544 .port_ops = &piix_vmw_ops, 545 }, 546 547 }; 548 549 static struct pci_bits piix_enable_bits[] = { 550 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 551 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 552 }; 553 554 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 555 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 556 MODULE_LICENSE("GPL"); 557 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 558 MODULE_VERSION(DRV_VERSION); 559 560 struct ich_laptop { 561 u16 device; 562 u16 subvendor; 563 u16 subdevice; 564 }; 565 566 /* 567 * List of laptops that use short cables rather than 80 wire 568 */ 569 570 static const struct ich_laptop ich_laptop[] = { 571 /* devid, subvendor, subdev */ 572 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 573 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 574 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 575 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 576 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 577 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 578 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ 579 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ 580 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 581 /* end marker */ 582 { 0, } 583 }; 584 585 /** 586 * ich_pata_cable_detect - Probe host controller cable detect info 587 * @ap: Port for which cable detect info is desired 588 * 589 * Read 80c cable indicator from ATA PCI device's PCI config 590 * register. This register is normally set by firmware (BIOS). 591 * 592 * LOCKING: 593 * None (inherited from caller). 594 */ 595 596 static int ich_pata_cable_detect(struct ata_port *ap) 597 { 598 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 599 const struct ich_laptop *lap = &ich_laptop[0]; 600 u8 tmp, mask; 601 602 /* Check for specials - Acer Aspire 5602WLMi */ 603 while (lap->device) { 604 if (lap->device == pdev->device && 605 lap->subvendor == pdev->subsystem_vendor && 606 lap->subdevice == pdev->subsystem_device) 607 return ATA_CBL_PATA40_SHORT; 608 609 lap++; 610 } 611 612 /* check BIOS cable detect results */ 613 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 614 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); 615 if ((tmp & mask) == 0) 616 return ATA_CBL_PATA40; 617 return ATA_CBL_PATA80; 618 } 619 620 /** 621 * piix_pata_prereset - prereset for PATA host controller 622 * @link: Target link 623 * @deadline: deadline jiffies for the operation 624 * 625 * LOCKING: 626 * None (inherited from caller). 627 */ 628 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 629 { 630 struct ata_port *ap = link->ap; 631 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 632 633 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 634 return -ENOENT; 635 return ata_sff_prereset(link, deadline); 636 } 637 638 /** 639 * piix_set_piomode - Initialize host controller PATA PIO timings 640 * @ap: Port whose timings we are configuring 641 * @adev: um 642 * 643 * Set PIO mode for device, in host controller PCI config space. 644 * 645 * LOCKING: 646 * None (inherited from caller). 647 */ 648 649 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 650 { 651 unsigned int pio = adev->pio_mode - XFER_PIO_0; 652 struct pci_dev *dev = to_pci_dev(ap->host->dev); 653 unsigned int is_slave = (adev->devno != 0); 654 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 655 unsigned int slave_port = 0x44; 656 u16 master_data; 657 u8 slave_data; 658 u8 udma_enable; 659 int control = 0; 660 661 /* 662 * See Intel Document 298600-004 for the timing programing rules 663 * for ICH controllers. 664 */ 665 666 static const /* ISP RTC */ 667 u8 timings[][2] = { { 0, 0 }, 668 { 0, 0 }, 669 { 1, 0 }, 670 { 2, 1 }, 671 { 2, 3 }, }; 672 673 if (pio >= 2) 674 control |= 1; /* TIME1 enable */ 675 if (ata_pio_need_iordy(adev)) 676 control |= 2; /* IE enable */ 677 678 /* Intel specifies that the PPE functionality is for disk only */ 679 if (adev->class == ATA_DEV_ATA) 680 control |= 4; /* PPE enable */ 681 682 /* PIO configuration clears DTE unconditionally. It will be 683 * programmed in set_dmamode which is guaranteed to be called 684 * after set_piomode if any DMA mode is available. 685 */ 686 pci_read_config_word(dev, master_port, &master_data); 687 if (is_slave) { 688 /* clear TIME1|IE1|PPE1|DTE1 */ 689 master_data &= 0xff0f; 690 /* Enable SITRE (separate slave timing register) */ 691 master_data |= 0x4000; 692 /* enable PPE1, IE1 and TIME1 as needed */ 693 master_data |= (control << 4); 694 pci_read_config_byte(dev, slave_port, &slave_data); 695 slave_data &= (ap->port_no ? 0x0f : 0xf0); 696 /* Load the timing nibble for this slave */ 697 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 698 << (ap->port_no ? 4 : 0); 699 } else { 700 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 701 master_data &= 0xccf0; 702 /* Enable PPE, IE and TIME as appropriate */ 703 master_data |= control; 704 /* load ISP and RCT */ 705 master_data |= 706 (timings[pio][0] << 12) | 707 (timings[pio][1] << 8); 708 } 709 pci_write_config_word(dev, master_port, master_data); 710 if (is_slave) 711 pci_write_config_byte(dev, slave_port, slave_data); 712 713 /* Ensure the UDMA bit is off - it will be turned back on if 714 UDMA is selected */ 715 716 if (ap->udma_mask) { 717 pci_read_config_byte(dev, 0x48, &udma_enable); 718 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 719 pci_write_config_byte(dev, 0x48, udma_enable); 720 } 721 } 722 723 /** 724 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 725 * @ap: Port whose timings we are configuring 726 * @adev: Drive in question 727 * @udma: udma mode, 0 - 6 728 * @isich: set if the chip is an ICH device 729 * 730 * Set UDMA mode for device, in host controller PCI config space. 731 * 732 * LOCKING: 733 * None (inherited from caller). 734 */ 735 736 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 737 { 738 struct pci_dev *dev = to_pci_dev(ap->host->dev); 739 u8 master_port = ap->port_no ? 0x42 : 0x40; 740 u16 master_data; 741 u8 speed = adev->dma_mode; 742 int devid = adev->devno + 2 * ap->port_no; 743 u8 udma_enable = 0; 744 745 static const /* ISP RTC */ 746 u8 timings[][2] = { { 0, 0 }, 747 { 0, 0 }, 748 { 1, 0 }, 749 { 2, 1 }, 750 { 2, 3 }, }; 751 752 pci_read_config_word(dev, master_port, &master_data); 753 if (ap->udma_mask) 754 pci_read_config_byte(dev, 0x48, &udma_enable); 755 756 if (speed >= XFER_UDMA_0) { 757 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 758 u16 udma_timing; 759 u16 ideconf; 760 int u_clock, u_speed; 761 762 /* 763 * UDMA is handled by a combination of clock switching and 764 * selection of dividers 765 * 766 * Handy rule: Odd modes are UDMATIMx 01, even are 02 767 * except UDMA0 which is 00 768 */ 769 u_speed = min(2 - (udma & 1), udma); 770 if (udma == 5) 771 u_clock = 0x1000; /* 100Mhz */ 772 else if (udma > 2) 773 u_clock = 1; /* 66Mhz */ 774 else 775 u_clock = 0; /* 33Mhz */ 776 777 udma_enable |= (1 << devid); 778 779 /* Load the CT/RP selection */ 780 pci_read_config_word(dev, 0x4A, &udma_timing); 781 udma_timing &= ~(3 << (4 * devid)); 782 udma_timing |= u_speed << (4 * devid); 783 pci_write_config_word(dev, 0x4A, udma_timing); 784 785 if (isich) { 786 /* Select a 33/66/100Mhz clock */ 787 pci_read_config_word(dev, 0x54, &ideconf); 788 ideconf &= ~(0x1001 << devid); 789 ideconf |= u_clock << devid; 790 /* For ICH or later we should set bit 10 for better 791 performance (WR_PingPong_En) */ 792 pci_write_config_word(dev, 0x54, ideconf); 793 } 794 } else { 795 /* 796 * MWDMA is driven by the PIO timings. We must also enable 797 * IORDY unconditionally along with TIME1. PPE has already 798 * been set when the PIO timing was set. 799 */ 800 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 801 unsigned int control; 802 u8 slave_data; 803 const unsigned int needed_pio[3] = { 804 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 805 }; 806 int pio = needed_pio[mwdma] - XFER_PIO_0; 807 808 control = 3; /* IORDY|TIME1 */ 809 810 /* If the drive MWDMA is faster than it can do PIO then 811 we must force PIO into PIO0 */ 812 813 if (adev->pio_mode < needed_pio[mwdma]) 814 /* Enable DMA timing only */ 815 control |= 8; /* PIO cycles in PIO0 */ 816 817 if (adev->devno) { /* Slave */ 818 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 819 master_data |= control << 4; 820 pci_read_config_byte(dev, 0x44, &slave_data); 821 slave_data &= (ap->port_no ? 0x0f : 0xf0); 822 /* Load the matching timing */ 823 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 824 pci_write_config_byte(dev, 0x44, slave_data); 825 } else { /* Master */ 826 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 827 and master timing bits */ 828 master_data |= control; 829 master_data |= 830 (timings[pio][0] << 12) | 831 (timings[pio][1] << 8); 832 } 833 834 if (ap->udma_mask) { 835 udma_enable &= ~(1 << devid); 836 pci_write_config_word(dev, master_port, master_data); 837 } 838 } 839 /* Don't scribble on 0x48 if the controller does not support UDMA */ 840 if (ap->udma_mask) 841 pci_write_config_byte(dev, 0x48, udma_enable); 842 } 843 844 /** 845 * piix_set_dmamode - Initialize host controller PATA DMA timings 846 * @ap: Port whose timings we are configuring 847 * @adev: um 848 * 849 * Set MW/UDMA mode for device, in host controller PCI config space. 850 * 851 * LOCKING: 852 * None (inherited from caller). 853 */ 854 855 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 856 { 857 do_pata_set_dmamode(ap, adev, 0); 858 } 859 860 /** 861 * ich_set_dmamode - Initialize host controller PATA DMA timings 862 * @ap: Port whose timings we are configuring 863 * @adev: um 864 * 865 * Set MW/UDMA mode for device, in host controller PCI config space. 866 * 867 * LOCKING: 868 * None (inherited from caller). 869 */ 870 871 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 872 { 873 do_pata_set_dmamode(ap, adev, 1); 874 } 875 876 /* 877 * Serial ATA Index/Data Pair Superset Registers access 878 * 879 * Beginning from ICH8, there's a sane way to access SCRs using index 880 * and data register pair located at BAR5. This creates an 881 * interesting problem of mapping two SCRs to one port. 882 * 883 * Although they have separate SCRs, the master and slave aren't 884 * independent enough to be treated as separate links - e.g. softreset 885 * resets both. Also, there's no protocol defined for hard resetting 886 * singled device sharing the virtual port (no defined way to acquire 887 * device signature). This is worked around by merging the SCR values 888 * into one sensible value and requesting follow-up SRST after 889 * hardreset. 890 * 891 * SCR merging is perfomed in nibbles which is the unit contents in 892 * SCRs are organized. If two values are equal, the value is used. 893 * When they differ, merge table which lists precedence of possible 894 * values is consulted and the first match or the last entry when 895 * nothing matches is used. When there's no merge table for the 896 * specific nibble, value from the first port is used. 897 */ 898 static const int piix_sidx_map[] = { 899 [SCR_STATUS] = 0, 900 [SCR_ERROR] = 2, 901 [SCR_CONTROL] = 1, 902 }; 903 904 static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg) 905 { 906 struct ata_port *ap = dev->link->ap; 907 struct piix_host_priv *hpriv = ap->host->private_data; 908 909 iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg], 910 hpriv->sidpr + PIIX_SIDPR_IDX); 911 } 912 913 static int piix_sidpr_read(struct ata_device *dev, unsigned int reg) 914 { 915 struct piix_host_priv *hpriv = dev->link->ap->host->private_data; 916 917 piix_sidpr_sel(dev, reg); 918 return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 919 } 920 921 static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val) 922 { 923 struct piix_host_priv *hpriv = dev->link->ap->host->private_data; 924 925 piix_sidpr_sel(dev, reg); 926 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 927 } 928 929 static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl) 930 { 931 u32 val = 0; 932 int i, mi; 933 934 for (i = 0, mi = 0; i < 32 / 4; i++) { 935 u8 c0 = (val0 >> (i * 4)) & 0xf; 936 u8 c1 = (val1 >> (i * 4)) & 0xf; 937 u8 merged = c0; 938 const int *cur; 939 940 /* if no merge preference, assume the first value */ 941 cur = merge_tbl[mi]; 942 if (!cur) 943 goto done; 944 mi++; 945 946 /* if two values equal, use it */ 947 if (c0 == c1) 948 goto done; 949 950 /* choose the first match or the last from the merge table */ 951 while (*cur != -1) { 952 if (c0 == *cur || c1 == *cur) 953 break; 954 cur++; 955 } 956 if (*cur == -1) 957 cur--; 958 merged = *cur; 959 done: 960 val |= merged << (i * 4); 961 } 962 963 return val; 964 } 965 966 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val) 967 { 968 const int * const sstatus_merge_tbl[] = { 969 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 }, 970 /* SPD */ (const int []){ 2, 1, 0, -1 }, 971 /* IPM */ (const int []){ 6, 2, 1, 0, -1 }, 972 NULL, 973 }; 974 const int * const scontrol_merge_tbl[] = { 975 /* DET */ (const int []){ 1, 0, 4, 0, -1 }, 976 /* SPD */ (const int []){ 0, 2, 1, 0, -1 }, 977 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 }, 978 NULL, 979 }; 980 u32 v0, v1; 981 982 if (reg >= ARRAY_SIZE(piix_sidx_map)) 983 return -EINVAL; 984 985 if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) { 986 *val = piix_sidpr_read(&ap->link.device[0], reg); 987 return 0; 988 } 989 990 v0 = piix_sidpr_read(&ap->link.device[0], reg); 991 v1 = piix_sidpr_read(&ap->link.device[1], reg); 992 993 switch (reg) { 994 case SCR_STATUS: 995 *val = piix_merge_scr(v0, v1, sstatus_merge_tbl); 996 break; 997 case SCR_ERROR: 998 *val = v0 | v1; 999 break; 1000 case SCR_CONTROL: 1001 *val = piix_merge_scr(v0, v1, scontrol_merge_tbl); 1002 break; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val) 1009 { 1010 if (reg >= ARRAY_SIZE(piix_sidx_map)) 1011 return -EINVAL; 1012 1013 piix_sidpr_write(&ap->link.device[0], reg, val); 1014 1015 if (ap->flags & ATA_FLAG_SLAVE_POSS) 1016 piix_sidpr_write(&ap->link.device[1], reg, val); 1017 1018 return 0; 1019 } 1020 1021 #ifdef CONFIG_PM 1022 static int piix_broken_suspend(void) 1023 { 1024 static const struct dmi_system_id sysids[] = { 1025 { 1026 .ident = "TECRA M3", 1027 .matches = { 1028 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1029 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 1030 }, 1031 }, 1032 { 1033 .ident = "TECRA M3", 1034 .matches = { 1035 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1036 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 1037 }, 1038 }, 1039 { 1040 .ident = "TECRA M4", 1041 .matches = { 1042 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1043 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), 1044 }, 1045 }, 1046 { 1047 .ident = "TECRA M4", 1048 .matches = { 1049 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1050 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), 1051 }, 1052 }, 1053 { 1054 .ident = "TECRA M5", 1055 .matches = { 1056 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1057 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 1058 }, 1059 }, 1060 { 1061 .ident = "TECRA M6", 1062 .matches = { 1063 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1064 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), 1065 }, 1066 }, 1067 { 1068 .ident = "TECRA M7", 1069 .matches = { 1070 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1071 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 1072 }, 1073 }, 1074 { 1075 .ident = "TECRA A8", 1076 .matches = { 1077 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1078 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 1079 }, 1080 }, 1081 { 1082 .ident = "Satellite R20", 1083 .matches = { 1084 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1085 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), 1086 }, 1087 }, 1088 { 1089 .ident = "Satellite R25", 1090 .matches = { 1091 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1092 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 1093 }, 1094 }, 1095 { 1096 .ident = "Satellite U200", 1097 .matches = { 1098 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1099 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 1100 }, 1101 }, 1102 { 1103 .ident = "Satellite U200", 1104 .matches = { 1105 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1106 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 1107 }, 1108 }, 1109 { 1110 .ident = "Satellite Pro U200", 1111 .matches = { 1112 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1113 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 1114 }, 1115 }, 1116 { 1117 .ident = "Satellite U205", 1118 .matches = { 1119 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1120 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 1121 }, 1122 }, 1123 { 1124 .ident = "SATELLITE U205", 1125 .matches = { 1126 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1127 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 1128 }, 1129 }, 1130 { 1131 .ident = "Portege M500", 1132 .matches = { 1133 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1134 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 1135 }, 1136 }, 1137 1138 { } /* terminate list */ 1139 }; 1140 static const char *oemstrs[] = { 1141 "Tecra M3,", 1142 }; 1143 int i; 1144 1145 if (dmi_check_system(sysids)) 1146 return 1; 1147 1148 for (i = 0; i < ARRAY_SIZE(oemstrs); i++) 1149 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) 1150 return 1; 1151 1152 return 0; 1153 } 1154 1155 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1156 { 1157 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1158 unsigned long flags; 1159 int rc = 0; 1160 1161 rc = ata_host_suspend(host, mesg); 1162 if (rc) 1163 return rc; 1164 1165 /* Some braindamaged ACPI suspend implementations expect the 1166 * controller to be awake on entry; otherwise, it burns cpu 1167 * cycles and power trying to do something to the sleeping 1168 * beauty. 1169 */ 1170 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { 1171 pci_save_state(pdev); 1172 1173 /* mark its power state as "unknown", since we don't 1174 * know if e.g. the BIOS will change its device state 1175 * when we suspend. 1176 */ 1177 if (pdev->current_state == PCI_D0) 1178 pdev->current_state = PCI_UNKNOWN; 1179 1180 /* tell resume that it's waking up from broken suspend */ 1181 spin_lock_irqsave(&host->lock, flags); 1182 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1183 spin_unlock_irqrestore(&host->lock, flags); 1184 } else 1185 ata_pci_device_do_suspend(pdev, mesg); 1186 1187 return 0; 1188 } 1189 1190 static int piix_pci_device_resume(struct pci_dev *pdev) 1191 { 1192 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1193 unsigned long flags; 1194 int rc; 1195 1196 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1197 spin_lock_irqsave(&host->lock, flags); 1198 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1199 spin_unlock_irqrestore(&host->lock, flags); 1200 1201 pci_set_power_state(pdev, PCI_D0); 1202 pci_restore_state(pdev); 1203 1204 /* PCI device wasn't disabled during suspend. Use 1205 * pci_reenable_device() to avoid affecting the enable 1206 * count. 1207 */ 1208 rc = pci_reenable_device(pdev); 1209 if (rc) 1210 dev_printk(KERN_ERR, &pdev->dev, "failed to enable " 1211 "device after resume (%d)\n", rc); 1212 } else 1213 rc = ata_pci_device_do_resume(pdev); 1214 1215 if (rc == 0) 1216 ata_host_resume(host); 1217 1218 return rc; 1219 } 1220 #endif 1221 1222 static u8 piix_vmw_bmdma_status(struct ata_port *ap) 1223 { 1224 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1225 } 1226 1227 #define AHCI_PCI_BAR 5 1228 #define AHCI_GLOBAL_CTL 0x04 1229 #define AHCI_ENABLE (1 << 31) 1230 static int piix_disable_ahci(struct pci_dev *pdev) 1231 { 1232 void __iomem *mmio; 1233 u32 tmp; 1234 int rc = 0; 1235 1236 /* BUG: pci_enable_device has not yet been called. This 1237 * works because this device is usually set up by BIOS. 1238 */ 1239 1240 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1241 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1242 return 0; 1243 1244 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1245 if (!mmio) 1246 return -ENOMEM; 1247 1248 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1249 if (tmp & AHCI_ENABLE) { 1250 tmp &= ~AHCI_ENABLE; 1251 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1252 1253 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1254 if (tmp & AHCI_ENABLE) 1255 rc = -EIO; 1256 } 1257 1258 pci_iounmap(pdev, mmio); 1259 return rc; 1260 } 1261 1262 /** 1263 * piix_check_450nx_errata - Check for problem 450NX setup 1264 * @ata_dev: the PCI device to check 1265 * 1266 * Check for the present of 450NX errata #19 and errata #25. If 1267 * they are found return an error code so we can turn off DMA 1268 */ 1269 1270 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 1271 { 1272 struct pci_dev *pdev = NULL; 1273 u16 cfg; 1274 int no_piix_dma = 0; 1275 1276 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1277 /* Look for 450NX PXB. Check for problem configurations 1278 A PCI quirk checks bit 6 already */ 1279 pci_read_config_word(pdev, 0x41, &cfg); 1280 /* Only on the original revision: IDE DMA can hang */ 1281 if (pdev->revision == 0x00) 1282 no_piix_dma = 1; 1283 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1284 else if (cfg & (1<<14) && pdev->revision < 5) 1285 no_piix_dma = 2; 1286 } 1287 if (no_piix_dma) 1288 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 1289 if (no_piix_dma == 2) 1290 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 1291 return no_piix_dma; 1292 } 1293 1294 static void __devinit piix_init_pcs(struct ata_host *host, 1295 const struct piix_map_db *map_db) 1296 { 1297 struct pci_dev *pdev = to_pci_dev(host->dev); 1298 u16 pcs, new_pcs; 1299 1300 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1301 1302 new_pcs = pcs | map_db->port_enable; 1303 1304 if (new_pcs != pcs) { 1305 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 1306 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1307 msleep(150); 1308 } 1309 } 1310 1311 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, 1312 struct ata_port_info *pinfo, 1313 const struct piix_map_db *map_db) 1314 { 1315 const int *map; 1316 int i, invalid_map = 0; 1317 u8 map_value; 1318 1319 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1320 1321 map = map_db->map[map_value & map_db->mask]; 1322 1323 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 1324 for (i = 0; i < 4; i++) { 1325 switch (map[i]) { 1326 case RV: 1327 invalid_map = 1; 1328 printk(" XX"); 1329 break; 1330 1331 case NA: 1332 printk(" --"); 1333 break; 1334 1335 case IDE: 1336 WARN_ON((i & 1) || map[i + 1] != IDE); 1337 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1338 i++; 1339 printk(" IDE IDE"); 1340 break; 1341 1342 default: 1343 printk(" P%d", map[i]); 1344 if (i & 1) 1345 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1346 break; 1347 } 1348 } 1349 printk(" ]\n"); 1350 1351 if (invalid_map) 1352 dev_printk(KERN_ERR, &pdev->dev, 1353 "invalid MAP value %u\n", map_value); 1354 1355 return map; 1356 } 1357 1358 static void __devinit piix_init_sidpr(struct ata_host *host) 1359 { 1360 struct pci_dev *pdev = to_pci_dev(host->dev); 1361 struct piix_host_priv *hpriv = host->private_data; 1362 struct ata_device *dev0 = &host->ports[0]->link.device[0]; 1363 u32 scontrol; 1364 int i; 1365 1366 /* check for availability */ 1367 for (i = 0; i < 4; i++) 1368 if (hpriv->map[i] == IDE) 1369 return; 1370 1371 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) 1372 return; 1373 1374 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || 1375 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) 1376 return; 1377 1378 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) 1379 return; 1380 1381 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1382 1383 /* SCR access via SIDPR doesn't work on some configurations. 1384 * Give it a test drive by inhibiting power save modes which 1385 * we'll do anyway. 1386 */ 1387 scontrol = piix_sidpr_read(dev0, SCR_CONTROL); 1388 1389 /* if IPM is already 3, SCR access is probably working. Don't 1390 * un-inhibit power save modes as BIOS might have inhibited 1391 * them for a reason. 1392 */ 1393 if ((scontrol & 0xf00) != 0x300) { 1394 scontrol |= 0x300; 1395 piix_sidpr_write(dev0, SCR_CONTROL, scontrol); 1396 scontrol = piix_sidpr_read(dev0, SCR_CONTROL); 1397 1398 if ((scontrol & 0xf00) != 0x300) { 1399 dev_printk(KERN_INFO, host->dev, "SCR access via " 1400 "SIDPR is available but doesn't work\n"); 1401 return; 1402 } 1403 } 1404 1405 host->ports[0]->ops = &piix_sidpr_sata_ops; 1406 host->ports[1]->ops = &piix_sidpr_sata_ops; 1407 } 1408 1409 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) 1410 { 1411 static const struct dmi_system_id sysids[] = { 1412 { 1413 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1414 * isn't used to boot the system which 1415 * disables the channel. 1416 */ 1417 .ident = "M570U", 1418 .matches = { 1419 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1420 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1421 }, 1422 }, 1423 1424 { } /* terminate list */ 1425 }; 1426 u32 iocfg; 1427 1428 if (!dmi_check_system(sysids)) 1429 return; 1430 1431 /* The datasheet says that bit 18 is NOOP but certain systems 1432 * seem to use it to disable a channel. Clear the bit on the 1433 * affected systems. 1434 */ 1435 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); 1436 if (iocfg & (1 << 18)) { 1437 dev_printk(KERN_INFO, &pdev->dev, 1438 "applying IOCFG bit18 quirk\n"); 1439 iocfg &= ~(1 << 18); 1440 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); 1441 } 1442 } 1443 1444 /** 1445 * piix_init_one - Register PIIX ATA PCI device with kernel services 1446 * @pdev: PCI device to register 1447 * @ent: Entry in piix_pci_tbl matching with @pdev 1448 * 1449 * Called from kernel PCI layer. We probe for combined mode (sigh), 1450 * and then hand over control to libata, for it to do the rest. 1451 * 1452 * LOCKING: 1453 * Inherited from PCI layer (may sleep). 1454 * 1455 * RETURNS: 1456 * Zero on success, or -ERRNO value. 1457 */ 1458 1459 static int __devinit piix_init_one(struct pci_dev *pdev, 1460 const struct pci_device_id *ent) 1461 { 1462 static int printed_version; 1463 struct device *dev = &pdev->dev; 1464 struct ata_port_info port_info[2]; 1465 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1466 unsigned long port_flags; 1467 struct ata_host *host; 1468 struct piix_host_priv *hpriv; 1469 int rc; 1470 1471 if (!printed_version++) 1472 dev_printk(KERN_DEBUG, &pdev->dev, 1473 "version " DRV_VERSION "\n"); 1474 1475 /* no hotplugging support (FIXME) */ 1476 if (!in_module_init) 1477 return -ENODEV; 1478 1479 port_info[0] = piix_port_info[ent->driver_data]; 1480 port_info[1] = piix_port_info[ent->driver_data]; 1481 1482 port_flags = port_info[0].flags; 1483 1484 /* enable device and prepare host */ 1485 rc = pcim_enable_device(pdev); 1486 if (rc) 1487 return rc; 1488 1489 /* ICH6R may be driven by either ata_piix or ahci driver 1490 * regardless of BIOS configuration. Make sure AHCI mode is 1491 * off. 1492 */ 1493 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { 1494 int rc = piix_disable_ahci(pdev); 1495 if (rc) 1496 return rc; 1497 } 1498 1499 /* SATA map init can change port_info, do it before prepping host */ 1500 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1501 if (!hpriv) 1502 return -ENOMEM; 1503 1504 if (port_flags & ATA_FLAG_SATA) 1505 hpriv->map = piix_init_sata_map(pdev, port_info, 1506 piix_map_db_table[ent->driver_data]); 1507 1508 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 1509 if (rc) 1510 return rc; 1511 host->private_data = hpriv; 1512 1513 /* initialize controller */ 1514 if (port_flags & ATA_FLAG_SATA) { 1515 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1516 piix_init_sidpr(host); 1517 } 1518 1519 /* apply IOCFG bit18 quirk */ 1520 piix_iocfg_bit18_quirk(pdev); 1521 1522 /* On ICH5, some BIOSen disable the interrupt using the 1523 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1524 * On ICH6, this bit has the same effect, but only when 1525 * MSI is disabled (and it is disabled, as we don't use 1526 * message-signalled interrupts currently). 1527 */ 1528 if (port_flags & PIIX_FLAG_CHECKINTR) 1529 pci_intx(pdev, 1); 1530 1531 if (piix_check_450nx_errata(pdev)) { 1532 /* This writes into the master table but it does not 1533 really matter for this errata as we will apply it to 1534 all the PIIX devices on the board */ 1535 host->ports[0]->mwdma_mask = 0; 1536 host->ports[0]->udma_mask = 0; 1537 host->ports[1]->mwdma_mask = 0; 1538 host->ports[1]->udma_mask = 0; 1539 } 1540 1541 pci_set_master(pdev); 1542 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht); 1543 } 1544 1545 static int __init piix_init(void) 1546 { 1547 int rc; 1548 1549 DPRINTK("pci_register_driver\n"); 1550 rc = pci_register_driver(&piix_pci_driver); 1551 if (rc) 1552 return rc; 1553 1554 in_module_init = 0; 1555 1556 DPRINTK("done\n"); 1557 return 0; 1558 } 1559 1560 static void __exit piix_exit(void) 1561 { 1562 pci_unregister_driver(&piix_pci_driver); 1563 } 1564 1565 module_init(piix_init); 1566 module_exit(piix_exit); 1567