1 /* 2 * ata_piix.c - Intel PATA/SATA controllers 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * 9 * Copyright 2003-2005 Red Hat Inc 10 * Copyright 2003-2005 Jeff Garzik 11 * 12 * 13 * Copyright header from piix.c: 14 * 15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 17 * Copyright (C) 2003 Red Hat Inc 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; see the file COPYING. If not, write to 32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 * 35 * libata documentation is available via 'make {ps|pdf}docs', 36 * as Documentation/DocBook/libata.* 37 * 38 * Hardware documentation available at http://developer.intel.com/ 39 * 40 * Documentation 41 * Publically available from Intel web site. Errata documentation 42 * is also publically available. As an aide to anyone hacking on this 43 * driver the list of errata that are relevant is below, going back to 44 * PIIX4. Older device documentation is now a bit tricky to find. 45 * 46 * The chipsets all follow very much the same design. The orginal Triton 47 * series chipsets do _not_ support independant device timings, but this 48 * is fixed in Triton II. With the odd mobile exception the chips then 49 * change little except in gaining more modes until SATA arrives. This 50 * driver supports only the chips with independant timing (that is those 51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix 52 * for the early chip drivers. 53 * 54 * Errata of note: 55 * 56 * Unfixable 57 * PIIX4 errata #9 - Only on ultra obscure hw 58 * ICH3 errata #13 - Not observed to affect real hw 59 * by Intel 60 * 61 * Things we must deal with 62 * PIIX4 errata #10 - BM IDE hang with non UDMA 63 * (must stop/start dma to recover) 64 * 440MX errata #15 - As PIIX4 errata #10 65 * PIIX4 errata #15 - Must not read control registers 66 * during a PIO transfer 67 * 440MX errata #13 - As PIIX4 errata #15 68 * ICH2 errata #21 - DMA mode 0 doesn't work right 69 * ICH0/1 errata #55 - As ICH2 errata #21 70 * ICH2 spec c #9 - Extra operations needed to handle 71 * drive hotswap [NOT YET SUPPORTED] 72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary 73 * and must be dword aligned 74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 75 * ICH7 errata #16 - MWDMA1 timings are incorrect 76 * 77 * Should have been BIOS fixed: 78 * 450NX: errata #19 - DMA hangs on old 450NX 79 * 450NX: errata #20 - DMA hangs on old 450NX 80 * 450NX: errata #25 - Corruption with DMA on old 450NX 81 * ICH3 errata #15 - IDE deadlock under high load 82 * (BIOS must set dev 31 fn 0 bit 23) 83 * ICH3 errata #18 - Don't use native mode 84 */ 85 86 #include <linux/kernel.h> 87 #include <linux/module.h> 88 #include <linux/pci.h> 89 #include <linux/init.h> 90 #include <linux/blkdev.h> 91 #include <linux/delay.h> 92 #include <linux/device.h> 93 #include <scsi/scsi_host.h> 94 #include <linux/libata.h> 95 #include <linux/dmi.h> 96 97 #define DRV_NAME "ata_piix" 98 #define DRV_VERSION "2.13" 99 100 enum { 101 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ 102 ICH5_PMR = 0x90, /* port mapping register */ 103 ICH5_PCS = 0x92, /* port control and status */ 104 PIIX_SIDPR_BAR = 5, 105 PIIX_SIDPR_LEN = 16, 106 PIIX_SIDPR_IDX = 0, 107 PIIX_SIDPR_DATA = 4, 108 109 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ 110 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ 111 112 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, 113 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, 114 115 PIIX_80C_PRI = (1 << 5) | (1 << 4), 116 PIIX_80C_SEC = (1 << 7) | (1 << 6), 117 118 /* constants for mapping table */ 119 P0 = 0, /* port 0 */ 120 P1 = 1, /* port 1 */ 121 P2 = 2, /* port 2 */ 122 P3 = 3, /* port 3 */ 123 IDE = -1, /* IDE */ 124 NA = -2, /* not avaliable */ 125 RV = -3, /* reserved */ 126 127 PIIX_AHCI_DEVICE = 6, 128 129 /* host->flags bits */ 130 PIIX_HOST_BROKEN_SUSPEND = (1 << 24), 131 }; 132 133 enum piix_controller_ids { 134 /* controller IDs */ 135 piix_pata_mwdma, /* PIIX3 MWDMA only */ 136 piix_pata_33, /* PIIX4 at 33Mhz */ 137 ich_pata_33, /* ICH up to UDMA 33 only */ 138 ich_pata_66, /* ICH up to 66 Mhz */ 139 ich_pata_100, /* ICH up to UDMA 100 */ 140 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/ 141 ich5_sata, 142 ich6_sata, 143 ich6m_sata, 144 ich8_sata, 145 ich8_2port_sata, 146 ich8m_apple_sata, /* locks up on second port enable */ 147 tolapai_sata, 148 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 149 }; 150 151 struct piix_map_db { 152 const u32 mask; 153 const u16 port_enable; 154 const int map[][4]; 155 }; 156 157 struct piix_host_priv { 158 const int *map; 159 u32 saved_iocfg; 160 void __iomem *sidpr; 161 }; 162 163 static int piix_init_one(struct pci_dev *pdev, 164 const struct pci_device_id *ent); 165 static void piix_remove_one(struct pci_dev *pdev); 166 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); 167 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); 168 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); 169 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); 170 static int ich_pata_cable_detect(struct ata_port *ap); 171 static u8 piix_vmw_bmdma_status(struct ata_port *ap); 172 static int piix_sidpr_scr_read(struct ata_link *link, 173 unsigned int reg, u32 *val); 174 static int piix_sidpr_scr_write(struct ata_link *link, 175 unsigned int reg, u32 val); 176 #ifdef CONFIG_PM 177 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 178 static int piix_pci_device_resume(struct pci_dev *pdev); 179 #endif 180 181 static unsigned int in_module_init = 1; 182 183 static const struct pci_device_id piix_pci_tbl[] = { 184 /* Intel PIIX3 for the 430HX etc */ 185 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, 186 /* VMware ICH4 */ 187 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, 188 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 189 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 190 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 191 /* Intel PIIX4 */ 192 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 193 /* Intel PIIX4 */ 194 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 195 /* Intel PIIX */ 196 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 197 /* Intel ICH (i810, i815, i840) UDMA 66*/ 198 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, 199 /* Intel ICH0 : UDMA 33*/ 200 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, 201 /* Intel ICH2M */ 202 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 203 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ 204 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 205 /* Intel ICH3M */ 206 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 207 /* Intel ICH3 (E7500/1) UDMA 100 */ 208 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 209 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ 210 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 211 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 212 /* Intel ICH5 */ 213 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 214 /* C-ICH (i810E2) */ 215 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 216 /* ESB (855GME/875P + 6300ESB) UDMA 100 */ 217 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 218 /* ICH6 (and 6) (i915) UDMA 100 */ 219 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 220 /* ICH7/7-R (i945, i975) UDMA 100*/ 221 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 222 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, 223 /* ICH8 Mobile PATA Controller */ 224 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, 225 226 /* SATA ports */ 227 228 /* 82801EB (ICH5) */ 229 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 230 /* 82801EB (ICH5) */ 231 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 232 /* 6300ESB (ICH5 variant with broken PCS present bits) */ 233 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 234 /* 6300ESB pretending RAID */ 235 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, 236 /* 82801FB/FW (ICH6/ICH6W) */ 237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 238 /* 82801FR/FRW (ICH6R/ICH6RW) */ 239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). 241 * Attach iff the controller is in IDE mode. */ 242 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 243 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, 244 /* 82801GB/GR/GH (ICH7, identical to ICH6) */ 245 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 246 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ 247 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, 248 /* Enterprise Southbridge 2 (631xESB/632xESB) */ 249 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, 250 /* SATA Controller 1 IDE (ICH8) */ 251 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 252 /* SATA Controller 2 IDE (ICH8) */ 253 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 254 /* Mobile SATA Controller IDE (ICH8M), Apple */ 255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, 256 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, 257 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, 258 /* Mobile SATA Controller IDE (ICH8M) */ 259 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 260 /* SATA Controller IDE (ICH9) */ 261 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 262 /* SATA Controller IDE (ICH9) */ 263 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 264 /* SATA Controller IDE (ICH9) */ 265 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 266 /* SATA Controller IDE (ICH9M) */ 267 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 268 /* SATA Controller IDE (ICH9M) */ 269 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 270 /* SATA Controller IDE (ICH9M) */ 271 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 272 /* SATA Controller IDE (Tolapai) */ 273 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, 274 /* SATA Controller IDE (ICH10) */ 275 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 276 /* SATA Controller IDE (ICH10) */ 277 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 278 /* SATA Controller IDE (ICH10) */ 279 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 280 /* SATA Controller IDE (ICH10) */ 281 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 282 /* SATA Controller IDE (PCH) */ 283 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 284 /* SATA Controller IDE (PCH) */ 285 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 286 /* SATA Controller IDE (PCH) */ 287 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 288 /* SATA Controller IDE (PCH) */ 289 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 290 /* SATA Controller IDE (PCH) */ 291 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 292 /* SATA Controller IDE (PCH) */ 293 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, 294 { } /* terminate list */ 295 }; 296 297 static struct pci_driver piix_pci_driver = { 298 .name = DRV_NAME, 299 .id_table = piix_pci_tbl, 300 .probe = piix_init_one, 301 .remove = piix_remove_one, 302 #ifdef CONFIG_PM 303 .suspend = piix_pci_device_suspend, 304 .resume = piix_pci_device_resume, 305 #endif 306 }; 307 308 static struct scsi_host_template piix_sht = { 309 ATA_BMDMA_SHT(DRV_NAME), 310 }; 311 312 static struct ata_port_operations piix_pata_ops = { 313 .inherits = &ata_bmdma32_port_ops, 314 .cable_detect = ata_cable_40wire, 315 .set_piomode = piix_set_piomode, 316 .set_dmamode = piix_set_dmamode, 317 .prereset = piix_pata_prereset, 318 }; 319 320 static struct ata_port_operations piix_vmw_ops = { 321 .inherits = &piix_pata_ops, 322 .bmdma_status = piix_vmw_bmdma_status, 323 }; 324 325 static struct ata_port_operations ich_pata_ops = { 326 .inherits = &piix_pata_ops, 327 .cable_detect = ich_pata_cable_detect, 328 .set_dmamode = ich_set_dmamode, 329 }; 330 331 static struct ata_port_operations piix_sata_ops = { 332 .inherits = &ata_bmdma_port_ops, 333 }; 334 335 static struct ata_port_operations piix_sidpr_sata_ops = { 336 .inherits = &piix_sata_ops, 337 .hardreset = sata_std_hardreset, 338 .scr_read = piix_sidpr_scr_read, 339 .scr_write = piix_sidpr_scr_write, 340 }; 341 342 static const struct piix_map_db ich5_map_db = { 343 .mask = 0x7, 344 .port_enable = 0x3, 345 .map = { 346 /* PM PS SM SS MAP */ 347 { P0, NA, P1, NA }, /* 000b */ 348 { P1, NA, P0, NA }, /* 001b */ 349 { RV, RV, RV, RV }, 350 { RV, RV, RV, RV }, 351 { P0, P1, IDE, IDE }, /* 100b */ 352 { P1, P0, IDE, IDE }, /* 101b */ 353 { IDE, IDE, P0, P1 }, /* 110b */ 354 { IDE, IDE, P1, P0 }, /* 111b */ 355 }, 356 }; 357 358 static const struct piix_map_db ich6_map_db = { 359 .mask = 0x3, 360 .port_enable = 0xf, 361 .map = { 362 /* PM PS SM SS MAP */ 363 { P0, P2, P1, P3 }, /* 00b */ 364 { IDE, IDE, P1, P3 }, /* 01b */ 365 { P0, P2, IDE, IDE }, /* 10b */ 366 { RV, RV, RV, RV }, 367 }, 368 }; 369 370 static const struct piix_map_db ich6m_map_db = { 371 .mask = 0x3, 372 .port_enable = 0x5, 373 374 /* Map 01b isn't specified in the doc but some notebooks use 375 * it anyway. MAP 01b have been spotted on both ICH6M and 376 * ICH7M. 377 */ 378 .map = { 379 /* PM PS SM SS MAP */ 380 { P0, P2, NA, NA }, /* 00b */ 381 { IDE, IDE, P1, P3 }, /* 01b */ 382 { P0, P2, IDE, IDE }, /* 10b */ 383 { RV, RV, RV, RV }, 384 }, 385 }; 386 387 static const struct piix_map_db ich8_map_db = { 388 .mask = 0x3, 389 .port_enable = 0xf, 390 .map = { 391 /* PM PS SM SS MAP */ 392 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ 393 { RV, RV, RV, RV }, 394 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ 395 { RV, RV, RV, RV }, 396 }, 397 }; 398 399 static const struct piix_map_db ich8_2port_map_db = { 400 .mask = 0x3, 401 .port_enable = 0x3, 402 .map = { 403 /* PM PS SM SS MAP */ 404 { P0, NA, P1, NA }, /* 00b */ 405 { RV, RV, RV, RV }, /* 01b */ 406 { RV, RV, RV, RV }, /* 10b */ 407 { RV, RV, RV, RV }, 408 }, 409 }; 410 411 static const struct piix_map_db ich8m_apple_map_db = { 412 .mask = 0x3, 413 .port_enable = 0x1, 414 .map = { 415 /* PM PS SM SS MAP */ 416 { P0, NA, NA, NA }, /* 00b */ 417 { RV, RV, RV, RV }, 418 { P0, P2, IDE, IDE }, /* 10b */ 419 { RV, RV, RV, RV }, 420 }, 421 }; 422 423 static const struct piix_map_db tolapai_map_db = { 424 .mask = 0x3, 425 .port_enable = 0x3, 426 .map = { 427 /* PM PS SM SS MAP */ 428 { P0, NA, P1, NA }, /* 00b */ 429 { RV, RV, RV, RV }, /* 01b */ 430 { RV, RV, RV, RV }, /* 10b */ 431 { RV, RV, RV, RV }, 432 }, 433 }; 434 435 static const struct piix_map_db *piix_map_db_table[] = { 436 [ich5_sata] = &ich5_map_db, 437 [ich6_sata] = &ich6_map_db, 438 [ich6m_sata] = &ich6m_map_db, 439 [ich8_sata] = &ich8_map_db, 440 [ich8_2port_sata] = &ich8_2port_map_db, 441 [ich8m_apple_sata] = &ich8m_apple_map_db, 442 [tolapai_sata] = &tolapai_map_db, 443 }; 444 445 static struct ata_port_info piix_port_info[] = { 446 [piix_pata_mwdma] = /* PIIX3 MWDMA only */ 447 { 448 .flags = PIIX_PATA_FLAGS, 449 .pio_mask = ATA_PIO4, 450 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 451 .port_ops = &piix_pata_ops, 452 }, 453 454 [piix_pata_33] = /* PIIX4 at 33MHz */ 455 { 456 .flags = PIIX_PATA_FLAGS, 457 .pio_mask = ATA_PIO4, 458 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 459 .udma_mask = ATA_UDMA2, 460 .port_ops = &piix_pata_ops, 461 }, 462 463 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ 464 { 465 .flags = PIIX_PATA_FLAGS, 466 .pio_mask = ATA_PIO4, 467 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ 468 .udma_mask = ATA_UDMA2, 469 .port_ops = &ich_pata_ops, 470 }, 471 472 [ich_pata_66] = /* ICH controllers up to 66MHz */ 473 { 474 .flags = PIIX_PATA_FLAGS, 475 .pio_mask = ATA_PIO4, 476 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ 477 .udma_mask = ATA_UDMA4, 478 .port_ops = &ich_pata_ops, 479 }, 480 481 [ich_pata_100] = 482 { 483 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 484 .pio_mask = ATA_PIO4, 485 .mwdma_mask = ATA_MWDMA12_ONLY, 486 .udma_mask = ATA_UDMA5, 487 .port_ops = &ich_pata_ops, 488 }, 489 490 [ich_pata_100_nomwdma1] = 491 { 492 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, 493 .pio_mask = ATA_PIO4, 494 .mwdma_mask = ATA_MWDMA2_ONLY, 495 .udma_mask = ATA_UDMA5, 496 .port_ops = &ich_pata_ops, 497 }, 498 499 [ich5_sata] = 500 { 501 .flags = PIIX_SATA_FLAGS, 502 .pio_mask = ATA_PIO4, 503 .mwdma_mask = ATA_MWDMA2, 504 .udma_mask = ATA_UDMA6, 505 .port_ops = &piix_sata_ops, 506 }, 507 508 [ich6_sata] = 509 { 510 .flags = PIIX_SATA_FLAGS, 511 .pio_mask = ATA_PIO4, 512 .mwdma_mask = ATA_MWDMA2, 513 .udma_mask = ATA_UDMA6, 514 .port_ops = &piix_sata_ops, 515 }, 516 517 [ich6m_sata] = 518 { 519 .flags = PIIX_SATA_FLAGS, 520 .pio_mask = ATA_PIO4, 521 .mwdma_mask = ATA_MWDMA2, 522 .udma_mask = ATA_UDMA6, 523 .port_ops = &piix_sata_ops, 524 }, 525 526 [ich8_sata] = 527 { 528 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 529 .pio_mask = ATA_PIO4, 530 .mwdma_mask = ATA_MWDMA2, 531 .udma_mask = ATA_UDMA6, 532 .port_ops = &piix_sata_ops, 533 }, 534 535 [ich8_2port_sata] = 536 { 537 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, 538 .pio_mask = ATA_PIO4, 539 .mwdma_mask = ATA_MWDMA2, 540 .udma_mask = ATA_UDMA6, 541 .port_ops = &piix_sata_ops, 542 }, 543 544 [tolapai_sata] = 545 { 546 .flags = PIIX_SATA_FLAGS, 547 .pio_mask = ATA_PIO4, 548 .mwdma_mask = ATA_MWDMA2, 549 .udma_mask = ATA_UDMA6, 550 .port_ops = &piix_sata_ops, 551 }, 552 553 [ich8m_apple_sata] = 554 { 555 .flags = PIIX_SATA_FLAGS, 556 .pio_mask = ATA_PIO4, 557 .mwdma_mask = ATA_MWDMA2, 558 .udma_mask = ATA_UDMA6, 559 .port_ops = &piix_sata_ops, 560 }, 561 562 [piix_pata_vmw] = 563 { 564 .flags = PIIX_PATA_FLAGS, 565 .pio_mask = ATA_PIO4, 566 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ 567 .udma_mask = ATA_UDMA2, 568 .port_ops = &piix_vmw_ops, 569 }, 570 571 }; 572 573 static struct pci_bits piix_enable_bits[] = { 574 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ 575 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ 576 }; 577 578 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); 579 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); 580 MODULE_LICENSE("GPL"); 581 MODULE_DEVICE_TABLE(pci, piix_pci_tbl); 582 MODULE_VERSION(DRV_VERSION); 583 584 struct ich_laptop { 585 u16 device; 586 u16 subvendor; 587 u16 subdevice; 588 }; 589 590 /* 591 * List of laptops that use short cables rather than 80 wire 592 */ 593 594 static const struct ich_laptop ich_laptop[] = { 595 /* devid, subvendor, subdev */ 596 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ 597 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ 598 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ 599 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */ 600 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ 601 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ 602 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unkown HP */ 603 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ 604 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */ 605 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ 606 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ 607 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ 608 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ 609 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */ 610 /* end marker */ 611 { 0, } 612 }; 613 614 /** 615 * ich_pata_cable_detect - Probe host controller cable detect info 616 * @ap: Port for which cable detect info is desired 617 * 618 * Read 80c cable indicator from ATA PCI device's PCI config 619 * register. This register is normally set by firmware (BIOS). 620 * 621 * LOCKING: 622 * None (inherited from caller). 623 */ 624 625 static int ich_pata_cable_detect(struct ata_port *ap) 626 { 627 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 628 struct piix_host_priv *hpriv = ap->host->private_data; 629 const struct ich_laptop *lap = &ich_laptop[0]; 630 u8 mask; 631 632 /* Check for specials - Acer Aspire 5602WLMi */ 633 while (lap->device) { 634 if (lap->device == pdev->device && 635 lap->subvendor == pdev->subsystem_vendor && 636 lap->subdevice == pdev->subsystem_device) 637 return ATA_CBL_PATA40_SHORT; 638 639 lap++; 640 } 641 642 /* check BIOS cable detect results */ 643 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; 644 if ((hpriv->saved_iocfg & mask) == 0) 645 return ATA_CBL_PATA40; 646 return ATA_CBL_PATA80; 647 } 648 649 /** 650 * piix_pata_prereset - prereset for PATA host controller 651 * @link: Target link 652 * @deadline: deadline jiffies for the operation 653 * 654 * LOCKING: 655 * None (inherited from caller). 656 */ 657 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) 658 { 659 struct ata_port *ap = link->ap; 660 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 661 662 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) 663 return -ENOENT; 664 return ata_sff_prereset(link, deadline); 665 } 666 667 /** 668 * piix_set_piomode - Initialize host controller PATA PIO timings 669 * @ap: Port whose timings we are configuring 670 * @adev: um 671 * 672 * Set PIO mode for device, in host controller PCI config space. 673 * 674 * LOCKING: 675 * None (inherited from caller). 676 */ 677 678 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) 679 { 680 unsigned int pio = adev->pio_mode - XFER_PIO_0; 681 struct pci_dev *dev = to_pci_dev(ap->host->dev); 682 unsigned int is_slave = (adev->devno != 0); 683 unsigned int master_port= ap->port_no ? 0x42 : 0x40; 684 unsigned int slave_port = 0x44; 685 u16 master_data; 686 u8 slave_data; 687 u8 udma_enable; 688 int control = 0; 689 690 /* 691 * See Intel Document 298600-004 for the timing programing rules 692 * for ICH controllers. 693 */ 694 695 static const /* ISP RTC */ 696 u8 timings[][2] = { { 0, 0 }, 697 { 0, 0 }, 698 { 1, 0 }, 699 { 2, 1 }, 700 { 2, 3 }, }; 701 702 if (pio >= 2) 703 control |= 1; /* TIME1 enable */ 704 if (ata_pio_need_iordy(adev)) 705 control |= 2; /* IE enable */ 706 707 /* Intel specifies that the PPE functionality is for disk only */ 708 if (adev->class == ATA_DEV_ATA) 709 control |= 4; /* PPE enable */ 710 711 /* PIO configuration clears DTE unconditionally. It will be 712 * programmed in set_dmamode which is guaranteed to be called 713 * after set_piomode if any DMA mode is available. 714 */ 715 pci_read_config_word(dev, master_port, &master_data); 716 if (is_slave) { 717 /* clear TIME1|IE1|PPE1|DTE1 */ 718 master_data &= 0xff0f; 719 /* Enable SITRE (separate slave timing register) */ 720 master_data |= 0x4000; 721 /* enable PPE1, IE1 and TIME1 as needed */ 722 master_data |= (control << 4); 723 pci_read_config_byte(dev, slave_port, &slave_data); 724 slave_data &= (ap->port_no ? 0x0f : 0xf0); 725 /* Load the timing nibble for this slave */ 726 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) 727 << (ap->port_no ? 4 : 0); 728 } else { 729 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ 730 master_data &= 0xccf0; 731 /* Enable PPE, IE and TIME as appropriate */ 732 master_data |= control; 733 /* load ISP and RCT */ 734 master_data |= 735 (timings[pio][0] << 12) | 736 (timings[pio][1] << 8); 737 } 738 pci_write_config_word(dev, master_port, master_data); 739 if (is_slave) 740 pci_write_config_byte(dev, slave_port, slave_data); 741 742 /* Ensure the UDMA bit is off - it will be turned back on if 743 UDMA is selected */ 744 745 if (ap->udma_mask) { 746 pci_read_config_byte(dev, 0x48, &udma_enable); 747 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); 748 pci_write_config_byte(dev, 0x48, udma_enable); 749 } 750 } 751 752 /** 753 * do_pata_set_dmamode - Initialize host controller PATA PIO timings 754 * @ap: Port whose timings we are configuring 755 * @adev: Drive in question 756 * @isich: set if the chip is an ICH device 757 * 758 * Set UDMA mode for device, in host controller PCI config space. 759 * 760 * LOCKING: 761 * None (inherited from caller). 762 */ 763 764 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) 765 { 766 struct pci_dev *dev = to_pci_dev(ap->host->dev); 767 u8 master_port = ap->port_no ? 0x42 : 0x40; 768 u16 master_data; 769 u8 speed = adev->dma_mode; 770 int devid = adev->devno + 2 * ap->port_no; 771 u8 udma_enable = 0; 772 773 static const /* ISP RTC */ 774 u8 timings[][2] = { { 0, 0 }, 775 { 0, 0 }, 776 { 1, 0 }, 777 { 2, 1 }, 778 { 2, 3 }, }; 779 780 pci_read_config_word(dev, master_port, &master_data); 781 if (ap->udma_mask) 782 pci_read_config_byte(dev, 0x48, &udma_enable); 783 784 if (speed >= XFER_UDMA_0) { 785 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 786 u16 udma_timing; 787 u16 ideconf; 788 int u_clock, u_speed; 789 790 /* 791 * UDMA is handled by a combination of clock switching and 792 * selection of dividers 793 * 794 * Handy rule: Odd modes are UDMATIMx 01, even are 02 795 * except UDMA0 which is 00 796 */ 797 u_speed = min(2 - (udma & 1), udma); 798 if (udma == 5) 799 u_clock = 0x1000; /* 100Mhz */ 800 else if (udma > 2) 801 u_clock = 1; /* 66Mhz */ 802 else 803 u_clock = 0; /* 33Mhz */ 804 805 udma_enable |= (1 << devid); 806 807 /* Load the CT/RP selection */ 808 pci_read_config_word(dev, 0x4A, &udma_timing); 809 udma_timing &= ~(3 << (4 * devid)); 810 udma_timing |= u_speed << (4 * devid); 811 pci_write_config_word(dev, 0x4A, udma_timing); 812 813 if (isich) { 814 /* Select a 33/66/100Mhz clock */ 815 pci_read_config_word(dev, 0x54, &ideconf); 816 ideconf &= ~(0x1001 << devid); 817 ideconf |= u_clock << devid; 818 /* For ICH or later we should set bit 10 for better 819 performance (WR_PingPong_En) */ 820 pci_write_config_word(dev, 0x54, ideconf); 821 } 822 } else { 823 /* 824 * MWDMA is driven by the PIO timings. We must also enable 825 * IORDY unconditionally along with TIME1. PPE has already 826 * been set when the PIO timing was set. 827 */ 828 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; 829 unsigned int control; 830 u8 slave_data; 831 const unsigned int needed_pio[3] = { 832 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 833 }; 834 int pio = needed_pio[mwdma] - XFER_PIO_0; 835 836 control = 3; /* IORDY|TIME1 */ 837 838 /* If the drive MWDMA is faster than it can do PIO then 839 we must force PIO into PIO0 */ 840 841 if (adev->pio_mode < needed_pio[mwdma]) 842 /* Enable DMA timing only */ 843 control |= 8; /* PIO cycles in PIO0 */ 844 845 if (adev->devno) { /* Slave */ 846 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ 847 master_data |= control << 4; 848 pci_read_config_byte(dev, 0x44, &slave_data); 849 slave_data &= (ap->port_no ? 0x0f : 0xf0); 850 /* Load the matching timing */ 851 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); 852 pci_write_config_byte(dev, 0x44, slave_data); 853 } else { /* Master */ 854 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY 855 and master timing bits */ 856 master_data |= control; 857 master_data |= 858 (timings[pio][0] << 12) | 859 (timings[pio][1] << 8); 860 } 861 862 if (ap->udma_mask) { 863 udma_enable &= ~(1 << devid); 864 pci_write_config_word(dev, master_port, master_data); 865 } 866 } 867 /* Don't scribble on 0x48 if the controller does not support UDMA */ 868 if (ap->udma_mask) 869 pci_write_config_byte(dev, 0x48, udma_enable); 870 } 871 872 /** 873 * piix_set_dmamode - Initialize host controller PATA DMA timings 874 * @ap: Port whose timings we are configuring 875 * @adev: um 876 * 877 * Set MW/UDMA mode for device, in host controller PCI config space. 878 * 879 * LOCKING: 880 * None (inherited from caller). 881 */ 882 883 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) 884 { 885 do_pata_set_dmamode(ap, adev, 0); 886 } 887 888 /** 889 * ich_set_dmamode - Initialize host controller PATA DMA timings 890 * @ap: Port whose timings we are configuring 891 * @adev: um 892 * 893 * Set MW/UDMA mode for device, in host controller PCI config space. 894 * 895 * LOCKING: 896 * None (inherited from caller). 897 */ 898 899 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) 900 { 901 do_pata_set_dmamode(ap, adev, 1); 902 } 903 904 /* 905 * Serial ATA Index/Data Pair Superset Registers access 906 * 907 * Beginning from ICH8, there's a sane way to access SCRs using index 908 * and data register pair located at BAR5 which means that we have 909 * separate SCRs for master and slave. This is handled using libata 910 * slave_link facility. 911 */ 912 static const int piix_sidx_map[] = { 913 [SCR_STATUS] = 0, 914 [SCR_ERROR] = 2, 915 [SCR_CONTROL] = 1, 916 }; 917 918 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) 919 { 920 struct ata_port *ap = link->ap; 921 struct piix_host_priv *hpriv = ap->host->private_data; 922 923 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], 924 hpriv->sidpr + PIIX_SIDPR_IDX); 925 } 926 927 static int piix_sidpr_scr_read(struct ata_link *link, 928 unsigned int reg, u32 *val) 929 { 930 struct piix_host_priv *hpriv = link->ap->host->private_data; 931 932 if (reg >= ARRAY_SIZE(piix_sidx_map)) 933 return -EINVAL; 934 935 piix_sidpr_sel(link, reg); 936 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); 937 return 0; 938 } 939 940 static int piix_sidpr_scr_write(struct ata_link *link, 941 unsigned int reg, u32 val) 942 { 943 struct piix_host_priv *hpriv = link->ap->host->private_data; 944 945 if (reg >= ARRAY_SIZE(piix_sidx_map)) 946 return -EINVAL; 947 948 piix_sidpr_sel(link, reg); 949 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); 950 return 0; 951 } 952 953 #ifdef CONFIG_PM 954 static int piix_broken_suspend(void) 955 { 956 static const struct dmi_system_id sysids[] = { 957 { 958 .ident = "TECRA M3", 959 .matches = { 960 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 961 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), 962 }, 963 }, 964 { 965 .ident = "TECRA M3", 966 .matches = { 967 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 968 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), 969 }, 970 }, 971 { 972 .ident = "TECRA M4", 973 .matches = { 974 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 975 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), 976 }, 977 }, 978 { 979 .ident = "TECRA M4", 980 .matches = { 981 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 982 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), 983 }, 984 }, 985 { 986 .ident = "TECRA M5", 987 .matches = { 988 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 989 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), 990 }, 991 }, 992 { 993 .ident = "TECRA M6", 994 .matches = { 995 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 996 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), 997 }, 998 }, 999 { 1000 .ident = "TECRA M7", 1001 .matches = { 1002 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1003 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), 1004 }, 1005 }, 1006 { 1007 .ident = "TECRA A8", 1008 .matches = { 1009 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1010 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), 1011 }, 1012 }, 1013 { 1014 .ident = "Satellite R20", 1015 .matches = { 1016 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1017 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), 1018 }, 1019 }, 1020 { 1021 .ident = "Satellite R25", 1022 .matches = { 1023 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1024 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), 1025 }, 1026 }, 1027 { 1028 .ident = "Satellite U200", 1029 .matches = { 1030 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1031 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), 1032 }, 1033 }, 1034 { 1035 .ident = "Satellite U200", 1036 .matches = { 1037 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1038 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), 1039 }, 1040 }, 1041 { 1042 .ident = "Satellite Pro U200", 1043 .matches = { 1044 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1045 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), 1046 }, 1047 }, 1048 { 1049 .ident = "Satellite U205", 1050 .matches = { 1051 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1052 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), 1053 }, 1054 }, 1055 { 1056 .ident = "SATELLITE U205", 1057 .matches = { 1058 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1059 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), 1060 }, 1061 }, 1062 { 1063 .ident = "Portege M500", 1064 .matches = { 1065 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 1066 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), 1067 }, 1068 }, 1069 { 1070 .ident = "VGN-BX297XP", 1071 .matches = { 1072 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), 1073 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), 1074 }, 1075 }, 1076 1077 { } /* terminate list */ 1078 }; 1079 static const char *oemstrs[] = { 1080 "Tecra M3,", 1081 }; 1082 int i; 1083 1084 if (dmi_check_system(sysids)) 1085 return 1; 1086 1087 for (i = 0; i < ARRAY_SIZE(oemstrs); i++) 1088 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) 1089 return 1; 1090 1091 /* TECRA M4 sometimes forgets its identify and reports bogus 1092 * DMI information. As the bogus information is a bit 1093 * generic, match as many entries as possible. This manual 1094 * matching is necessary because dmi_system_id.matches is 1095 * limited to four entries. 1096 */ 1097 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && 1098 dmi_match(DMI_PRODUCT_NAME, "000000") && 1099 dmi_match(DMI_PRODUCT_VERSION, "000000") && 1100 dmi_match(DMI_PRODUCT_SERIAL, "000000") && 1101 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && 1102 dmi_match(DMI_BOARD_NAME, "Portable PC") && 1103 dmi_match(DMI_BOARD_VERSION, "Version A0")) 1104 return 1; 1105 1106 return 0; 1107 } 1108 1109 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 1110 { 1111 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1112 unsigned long flags; 1113 int rc = 0; 1114 1115 rc = ata_host_suspend(host, mesg); 1116 if (rc) 1117 return rc; 1118 1119 /* Some braindamaged ACPI suspend implementations expect the 1120 * controller to be awake on entry; otherwise, it burns cpu 1121 * cycles and power trying to do something to the sleeping 1122 * beauty. 1123 */ 1124 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { 1125 pci_save_state(pdev); 1126 1127 /* mark its power state as "unknown", since we don't 1128 * know if e.g. the BIOS will change its device state 1129 * when we suspend. 1130 */ 1131 if (pdev->current_state == PCI_D0) 1132 pdev->current_state = PCI_UNKNOWN; 1133 1134 /* tell resume that it's waking up from broken suspend */ 1135 spin_lock_irqsave(&host->lock, flags); 1136 host->flags |= PIIX_HOST_BROKEN_SUSPEND; 1137 spin_unlock_irqrestore(&host->lock, flags); 1138 } else 1139 ata_pci_device_do_suspend(pdev, mesg); 1140 1141 return 0; 1142 } 1143 1144 static int piix_pci_device_resume(struct pci_dev *pdev) 1145 { 1146 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1147 unsigned long flags; 1148 int rc; 1149 1150 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { 1151 spin_lock_irqsave(&host->lock, flags); 1152 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; 1153 spin_unlock_irqrestore(&host->lock, flags); 1154 1155 pci_set_power_state(pdev, PCI_D0); 1156 pci_restore_state(pdev); 1157 1158 /* PCI device wasn't disabled during suspend. Use 1159 * pci_reenable_device() to avoid affecting the enable 1160 * count. 1161 */ 1162 rc = pci_reenable_device(pdev); 1163 if (rc) 1164 dev_printk(KERN_ERR, &pdev->dev, "failed to enable " 1165 "device after resume (%d)\n", rc); 1166 } else 1167 rc = ata_pci_device_do_resume(pdev); 1168 1169 if (rc == 0) 1170 ata_host_resume(host); 1171 1172 return rc; 1173 } 1174 #endif 1175 1176 static u8 piix_vmw_bmdma_status(struct ata_port *ap) 1177 { 1178 return ata_bmdma_status(ap) & ~ATA_DMA_ERR; 1179 } 1180 1181 #define AHCI_PCI_BAR 5 1182 #define AHCI_GLOBAL_CTL 0x04 1183 #define AHCI_ENABLE (1 << 31) 1184 static int piix_disable_ahci(struct pci_dev *pdev) 1185 { 1186 void __iomem *mmio; 1187 u32 tmp; 1188 int rc = 0; 1189 1190 /* BUG: pci_enable_device has not yet been called. This 1191 * works because this device is usually set up by BIOS. 1192 */ 1193 1194 if (!pci_resource_start(pdev, AHCI_PCI_BAR) || 1195 !pci_resource_len(pdev, AHCI_PCI_BAR)) 1196 return 0; 1197 1198 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); 1199 if (!mmio) 1200 return -ENOMEM; 1201 1202 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1203 if (tmp & AHCI_ENABLE) { 1204 tmp &= ~AHCI_ENABLE; 1205 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); 1206 1207 tmp = ioread32(mmio + AHCI_GLOBAL_CTL); 1208 if (tmp & AHCI_ENABLE) 1209 rc = -EIO; 1210 } 1211 1212 pci_iounmap(pdev, mmio); 1213 return rc; 1214 } 1215 1216 /** 1217 * piix_check_450nx_errata - Check for problem 450NX setup 1218 * @ata_dev: the PCI device to check 1219 * 1220 * Check for the present of 450NX errata #19 and errata #25. If 1221 * they are found return an error code so we can turn off DMA 1222 */ 1223 1224 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) 1225 { 1226 struct pci_dev *pdev = NULL; 1227 u16 cfg; 1228 int no_piix_dma = 0; 1229 1230 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { 1231 /* Look for 450NX PXB. Check for problem configurations 1232 A PCI quirk checks bit 6 already */ 1233 pci_read_config_word(pdev, 0x41, &cfg); 1234 /* Only on the original revision: IDE DMA can hang */ 1235 if (pdev->revision == 0x00) 1236 no_piix_dma = 1; 1237 /* On all revisions below 5 PXB bus lock must be disabled for IDE */ 1238 else if (cfg & (1<<14) && pdev->revision < 5) 1239 no_piix_dma = 2; 1240 } 1241 if (no_piix_dma) 1242 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); 1243 if (no_piix_dma == 2) 1244 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); 1245 return no_piix_dma; 1246 } 1247 1248 static void __devinit piix_init_pcs(struct ata_host *host, 1249 const struct piix_map_db *map_db) 1250 { 1251 struct pci_dev *pdev = to_pci_dev(host->dev); 1252 u16 pcs, new_pcs; 1253 1254 pci_read_config_word(pdev, ICH5_PCS, &pcs); 1255 1256 new_pcs = pcs | map_db->port_enable; 1257 1258 if (new_pcs != pcs) { 1259 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); 1260 pci_write_config_word(pdev, ICH5_PCS, new_pcs); 1261 msleep(150); 1262 } 1263 } 1264 1265 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, 1266 struct ata_port_info *pinfo, 1267 const struct piix_map_db *map_db) 1268 { 1269 const int *map; 1270 int i, invalid_map = 0; 1271 u8 map_value; 1272 1273 pci_read_config_byte(pdev, ICH5_PMR, &map_value); 1274 1275 map = map_db->map[map_value & map_db->mask]; 1276 1277 dev_printk(KERN_INFO, &pdev->dev, "MAP ["); 1278 for (i = 0; i < 4; i++) { 1279 switch (map[i]) { 1280 case RV: 1281 invalid_map = 1; 1282 printk(" XX"); 1283 break; 1284 1285 case NA: 1286 printk(" --"); 1287 break; 1288 1289 case IDE: 1290 WARN_ON((i & 1) || map[i + 1] != IDE); 1291 pinfo[i / 2] = piix_port_info[ich_pata_100]; 1292 i++; 1293 printk(" IDE IDE"); 1294 break; 1295 1296 default: 1297 printk(" P%d", map[i]); 1298 if (i & 1) 1299 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; 1300 break; 1301 } 1302 } 1303 printk(" ]\n"); 1304 1305 if (invalid_map) 1306 dev_printk(KERN_ERR, &pdev->dev, 1307 "invalid MAP value %u\n", map_value); 1308 1309 return map; 1310 } 1311 1312 static bool piix_no_sidpr(struct ata_host *host) 1313 { 1314 struct pci_dev *pdev = to_pci_dev(host->dev); 1315 1316 /* 1317 * Samsung DB-P70 only has three ATA ports exposed and 1318 * curiously the unconnected first port reports link online 1319 * while not responding to SRST protocol causing excessive 1320 * detection delay. 1321 * 1322 * Unfortunately, the system doesn't carry enough DMI 1323 * information to identify the machine but does have subsystem 1324 * vendor and device set. As it's unclear whether the 1325 * subsystem vendor/device is used only for this specific 1326 * board, the port can't be disabled solely with the 1327 * information; however, turning off SIDPR access works around 1328 * the problem. Turn it off. 1329 * 1330 * This problem is reported in bnc#441240. 1331 * 1332 * https://bugzilla.novell.com/show_bug.cgi?id=441420 1333 */ 1334 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && 1335 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && 1336 pdev->subsystem_device == 0xb049) { 1337 dev_printk(KERN_WARNING, host->dev, 1338 "Samsung DB-P70 detected, disabling SIDPR\n"); 1339 return true; 1340 } 1341 1342 return false; 1343 } 1344 1345 static int __devinit piix_init_sidpr(struct ata_host *host) 1346 { 1347 struct pci_dev *pdev = to_pci_dev(host->dev); 1348 struct piix_host_priv *hpriv = host->private_data; 1349 struct ata_link *link0 = &host->ports[0]->link; 1350 u32 scontrol; 1351 int i, rc; 1352 1353 /* check for availability */ 1354 for (i = 0; i < 4; i++) 1355 if (hpriv->map[i] == IDE) 1356 return 0; 1357 1358 /* is it blacklisted? */ 1359 if (piix_no_sidpr(host)) 1360 return 0; 1361 1362 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) 1363 return 0; 1364 1365 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || 1366 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) 1367 return 0; 1368 1369 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) 1370 return 0; 1371 1372 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; 1373 1374 /* SCR access via SIDPR doesn't work on some configurations. 1375 * Give it a test drive by inhibiting power save modes which 1376 * we'll do anyway. 1377 */ 1378 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1379 1380 /* if IPM is already 3, SCR access is probably working. Don't 1381 * un-inhibit power save modes as BIOS might have inhibited 1382 * them for a reason. 1383 */ 1384 if ((scontrol & 0xf00) != 0x300) { 1385 scontrol |= 0x300; 1386 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); 1387 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); 1388 1389 if ((scontrol & 0xf00) != 0x300) { 1390 dev_printk(KERN_INFO, host->dev, "SCR access via " 1391 "SIDPR is available but doesn't work\n"); 1392 return 0; 1393 } 1394 } 1395 1396 /* okay, SCRs available, set ops and ask libata for slave_link */ 1397 for (i = 0; i < 2; i++) { 1398 struct ata_port *ap = host->ports[i]; 1399 1400 ap->ops = &piix_sidpr_sata_ops; 1401 1402 if (ap->flags & ATA_FLAG_SLAVE_POSS) { 1403 rc = ata_slave_link_init(ap); 1404 if (rc) 1405 return rc; 1406 } 1407 } 1408 1409 return 0; 1410 } 1411 1412 static void piix_iocfg_bit18_quirk(struct ata_host *host) 1413 { 1414 static const struct dmi_system_id sysids[] = { 1415 { 1416 /* Clevo M570U sets IOCFG bit 18 if the cdrom 1417 * isn't used to boot the system which 1418 * disables the channel. 1419 */ 1420 .ident = "M570U", 1421 .matches = { 1422 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), 1423 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), 1424 }, 1425 }, 1426 1427 { } /* terminate list */ 1428 }; 1429 struct pci_dev *pdev = to_pci_dev(host->dev); 1430 struct piix_host_priv *hpriv = host->private_data; 1431 1432 if (!dmi_check_system(sysids)) 1433 return; 1434 1435 /* The datasheet says that bit 18 is NOOP but certain systems 1436 * seem to use it to disable a channel. Clear the bit on the 1437 * affected systems. 1438 */ 1439 if (hpriv->saved_iocfg & (1 << 18)) { 1440 dev_printk(KERN_INFO, &pdev->dev, 1441 "applying IOCFG bit18 quirk\n"); 1442 pci_write_config_dword(pdev, PIIX_IOCFG, 1443 hpriv->saved_iocfg & ~(1 << 18)); 1444 } 1445 } 1446 1447 static bool piix_broken_system_poweroff(struct pci_dev *pdev) 1448 { 1449 static const struct dmi_system_id broken_systems[] = { 1450 { 1451 .ident = "HP Compaq 2510p", 1452 .matches = { 1453 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1454 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), 1455 }, 1456 /* PCI slot number of the controller */ 1457 .driver_data = (void *)0x1FUL, 1458 }, 1459 { 1460 .ident = "HP Compaq nc6000", 1461 .matches = { 1462 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1463 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"), 1464 }, 1465 /* PCI slot number of the controller */ 1466 .driver_data = (void *)0x1FUL, 1467 }, 1468 1469 { } /* terminate list */ 1470 }; 1471 const struct dmi_system_id *dmi = dmi_first_match(broken_systems); 1472 1473 if (dmi) { 1474 unsigned long slot = (unsigned long)dmi->driver_data; 1475 /* apply the quirk only to on-board controllers */ 1476 return slot == PCI_SLOT(pdev->devfn); 1477 } 1478 1479 return false; 1480 } 1481 1482 /** 1483 * piix_init_one - Register PIIX ATA PCI device with kernel services 1484 * @pdev: PCI device to register 1485 * @ent: Entry in piix_pci_tbl matching with @pdev 1486 * 1487 * Called from kernel PCI layer. We probe for combined mode (sigh), 1488 * and then hand over control to libata, for it to do the rest. 1489 * 1490 * LOCKING: 1491 * Inherited from PCI layer (may sleep). 1492 * 1493 * RETURNS: 1494 * Zero on success, or -ERRNO value. 1495 */ 1496 1497 static int __devinit piix_init_one(struct pci_dev *pdev, 1498 const struct pci_device_id *ent) 1499 { 1500 static int printed_version; 1501 struct device *dev = &pdev->dev; 1502 struct ata_port_info port_info[2]; 1503 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; 1504 unsigned long port_flags; 1505 struct ata_host *host; 1506 struct piix_host_priv *hpriv; 1507 int rc; 1508 1509 if (!printed_version++) 1510 dev_printk(KERN_DEBUG, &pdev->dev, 1511 "version " DRV_VERSION "\n"); 1512 1513 /* no hotplugging support for later devices (FIXME) */ 1514 if (!in_module_init && ent->driver_data >= ich5_sata) 1515 return -ENODEV; 1516 1517 if (piix_broken_system_poweroff(pdev)) { 1518 piix_port_info[ent->driver_data].flags |= 1519 ATA_FLAG_NO_POWEROFF_SPINDOWN | 1520 ATA_FLAG_NO_HIBERNATE_SPINDOWN; 1521 dev_info(&pdev->dev, "quirky BIOS, skipping spindown " 1522 "on poweroff and hibernation\n"); 1523 } 1524 1525 port_info[0] = piix_port_info[ent->driver_data]; 1526 port_info[1] = piix_port_info[ent->driver_data]; 1527 1528 port_flags = port_info[0].flags; 1529 1530 /* enable device and prepare host */ 1531 rc = pcim_enable_device(pdev); 1532 if (rc) 1533 return rc; 1534 1535 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1536 if (!hpriv) 1537 return -ENOMEM; 1538 1539 /* Save IOCFG, this will be used for cable detection, quirk 1540 * detection and restoration on detach. This is necessary 1541 * because some ACPI implementations mess up cable related 1542 * bits on _STM. Reported on kernel bz#11879. 1543 */ 1544 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); 1545 1546 /* ICH6R may be driven by either ata_piix or ahci driver 1547 * regardless of BIOS configuration. Make sure AHCI mode is 1548 * off. 1549 */ 1550 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { 1551 rc = piix_disable_ahci(pdev); 1552 if (rc) 1553 return rc; 1554 } 1555 1556 /* SATA map init can change port_info, do it before prepping host */ 1557 if (port_flags & ATA_FLAG_SATA) 1558 hpriv->map = piix_init_sata_map(pdev, port_info, 1559 piix_map_db_table[ent->driver_data]); 1560 1561 rc = ata_pci_sff_prepare_host(pdev, ppi, &host); 1562 if (rc) 1563 return rc; 1564 host->private_data = hpriv; 1565 1566 /* initialize controller */ 1567 if (port_flags & ATA_FLAG_SATA) { 1568 piix_init_pcs(host, piix_map_db_table[ent->driver_data]); 1569 rc = piix_init_sidpr(host); 1570 if (rc) 1571 return rc; 1572 } 1573 1574 /* apply IOCFG bit18 quirk */ 1575 piix_iocfg_bit18_quirk(host); 1576 1577 /* On ICH5, some BIOSen disable the interrupt using the 1578 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. 1579 * On ICH6, this bit has the same effect, but only when 1580 * MSI is disabled (and it is disabled, as we don't use 1581 * message-signalled interrupts currently). 1582 */ 1583 if (port_flags & PIIX_FLAG_CHECKINTR) 1584 pci_intx(pdev, 1); 1585 1586 if (piix_check_450nx_errata(pdev)) { 1587 /* This writes into the master table but it does not 1588 really matter for this errata as we will apply it to 1589 all the PIIX devices on the board */ 1590 host->ports[0]->mwdma_mask = 0; 1591 host->ports[0]->udma_mask = 0; 1592 host->ports[1]->mwdma_mask = 0; 1593 host->ports[1]->udma_mask = 0; 1594 } 1595 host->flags |= ATA_HOST_PARALLEL_SCAN; 1596 1597 pci_set_master(pdev); 1598 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht); 1599 } 1600 1601 static void piix_remove_one(struct pci_dev *pdev) 1602 { 1603 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1604 struct piix_host_priv *hpriv = host->private_data; 1605 1606 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); 1607 1608 ata_pci_remove_one(pdev); 1609 } 1610 1611 static int __init piix_init(void) 1612 { 1613 int rc; 1614 1615 DPRINTK("pci_register_driver\n"); 1616 rc = pci_register_driver(&piix_pci_driver); 1617 if (rc) 1618 return rc; 1619 1620 in_module_init = 0; 1621 1622 DPRINTK("done\n"); 1623 return 0; 1624 } 1625 1626 static void __exit piix_exit(void) 1627 { 1628 pci_unregister_driver(&piix_pci_driver); 1629 } 1630 1631 module_init(piix_init); 1632 module_exit(piix_exit); 1633